lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37 #ident "$Id: ixgbe_phy.c,v 1.155 2013/08/14 22:34:03 jtkirshe Exp $"
  38
  39 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
  50 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  51                                           u8 *sff8472_data);
  52
  53 /**
  54  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  55  *  @hw: pointer to the hardware structure
  56  *
  57  *  Initialize the function pointers.
  58  **/
  59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_phy_info *phy = &hw->phy;
  62
  63         DEBUGFUNC("ixgbe_init_phy_ops_generic");
  64
  65         /* PHY */
  66         phy->ops.identify = &ixgbe_identify_phy_generic;
  67         phy->ops.reset = &ixgbe_reset_phy_generic;
  68         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  69         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  70         phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
  71         phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
  72         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  73         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  74         phy->ops.check_link = NULL;
  75         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  76         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  77         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  78         phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
  79         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  80         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  81         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  82         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  83         phy->sfp_type = ixgbe_sfp_type_unknown;
  84         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  85         return IXGBE_SUCCESS;
  86 }
  87
  88 /**
  89  *  ixgbe_identify_phy_generic - Get physical layer module
  90  *  @hw: pointer to hardware structure
  91  *
  92  *  Determines the physical layer module found on the current adapter.
  93  **/
  94 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  95 {
  96         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  97         u32 phy_addr;
  98         u16 ext_ability = 0;
  99
 100         DEBUGFUNC("ixgbe_identify_phy_generic");
 101
 102         if (!hw->phy.phy_semaphore_mask) {
 103                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
 104                                                 IXGBE_STATUS_LAN_ID_1;
 105                 if (hw->phy.lan_id)
 106                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 107                 else
 108                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 109         }
 110
 111         if (hw->phy.type == ixgbe_phy_unknown) {
 112                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 113                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 114                                 hw->phy.addr = phy_addr;
 115                                 ixgbe_get_phy_id(hw);
 116                                 hw->phy.type =
 117                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 118
 119                                 if (hw->phy.type == ixgbe_phy_unknown) {
 120                                         hw->phy.ops.read_reg(hw,
 121                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 122                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 123                                                   &ext_ability);
 124                                         if (ext_ability &
 125                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 126                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 127                                                 hw->phy.type =
 128                                                          ixgbe_phy_cu_unknown;
 129                                         else
 130                                                 hw->phy.type =
 131                                                          ixgbe_phy_generic;
 132                                 }
 133
 134                                 status = IXGBE_SUCCESS;
 135                                 break;
 136                         }
 137                 }
 138
 139                 /* Certain media types do not have a phy so an address will not
 140                  * be found and the code will take this path.  Caller has to
 141                  * decide if it is an error or not.
 142                  */
 143                 if (status != IXGBE_SUCCESS) {
 144                         hw->phy.addr = 0;
 145                 }
 146         } else {
 147                 status = IXGBE_SUCCESS;
 148         }
 149
 150         return status;
 151 }
 152
 153 /**
 154  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 155  * @hw: pointer to the hardware structure
 156  *
 157  * This function checks the MMNGC.MNG_VETO bit to see if there are
 158  * any constraints on link from manageability.  For MAC's that don't
 159  * have this bit just return faluse since the link can not be blocked
 160  * via this method.
 161  **/
 162 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 163 {
 164         u32 mmngc;
 165
 166         DEBUGFUNC("ixgbe_check_reset_blocked");
 167
 168         /* If we don't have this bit, it can't be blocking */
 169         if (hw->mac.type == ixgbe_mac_82598EB)
 170                 return false;
 171
 172         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 173         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 174                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 175                               "MNG_VETO bit detected.\n");
 176                 return true;
 177         }
 178
 179         return false;
 180 }
 181
 182 /**
 183  *  ixgbe_validate_phy_addr - Determines phy address is valid
 184  *  @hw: pointer to hardware structure
 185  *
 186  **/
 187 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 188 {
 189         u16 phy_id = 0;
 190         bool valid = false;
 191
 192         DEBUGFUNC("ixgbe_validate_phy_addr");
 193
 194         hw->phy.addr = phy_addr;
 195         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 196                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 197
 198         if (phy_id != 0xFFFF && phy_id != 0x0)
 199                 valid = true;
 200
 201         return valid;
 202 }
 203
 204 /**
 205  *  ixgbe_get_phy_id - Get the phy type
 206  *  @hw: pointer to hardware structure
 207  *
 208  **/
 209 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 210 {
 211         u32 status;
 212         u16 phy_id_high = 0;
 213         u16 phy_id_low = 0;
 214
 215         DEBUGFUNC("ixgbe_get_phy_id");
 216
 217         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 218                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 219                                       &phy_id_high);
 220
 221         if (status == IXGBE_SUCCESS) {
 222                 hw->phy.id = (u32)(phy_id_high << 16);
 223                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 224                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 225                                               &phy_id_low);
 226                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 227                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 228         }
 229         return status;
 230 }
 231
 232 /**
 233  *  ixgbe_get_phy_type_from_id - Get the phy type
 234  *  @hw: pointer to hardware structure
 235  *
 236  **/
 237 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 238 {
 239         enum ixgbe_phy_type phy_type;
 240
 241         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 242
 243         switch (phy_id) {
 244         case TN1010_PHY_ID:
 245                 phy_type = ixgbe_phy_tn;
 246                 break;
 247         case X540_PHY_ID:
 248                 phy_type = ixgbe_phy_aq;
 249                 break;
 250         case QT2022_PHY_ID:
 251                 phy_type = ixgbe_phy_qt;
 252                 break;
 253         case ATH_PHY_ID:
 254                 phy_type = ixgbe_phy_nl;
 255                 break;
 256         default:
 257                 phy_type = ixgbe_phy_unknown;
 258                 break;
 259         }
 260
 261         DEBUGOUT1("phy type found is %d\n", phy_type);
 262         return phy_type;
 263 }
 264
 265 /**
 266  *  ixgbe_reset_phy_generic - Performs a PHY reset
 267  *  @hw: pointer to hardware structure
 268  **/
 269 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 270 {
 271         u32 i;
 272         u16 ctrl = 0;
 273         s32 status = IXGBE_SUCCESS;
 274
 275         DEBUGFUNC("ixgbe_reset_phy_generic");
 276
 277         if (hw->phy.type == ixgbe_phy_unknown)
 278                 status = ixgbe_identify_phy_generic(hw);
 279
 280         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 281                 goto out;
 282
 283         /* Don't reset PHY if it's shut down due to overtemp. */
 284         if (!hw->phy.reset_if_overtemp &&
 285             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 286                 goto out;
 287
 288         /* Blocked by MNG FW so bail */
 289         if (ixgbe_check_reset_blocked(hw))
 290                 goto out;
 291
 292         /*
 293          * Perform soft PHY reset to the PHY_XS.
 294          * This will cause a soft reset to the PHY
 295          */
 296         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 297                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 298                               IXGBE_MDIO_PHY_XS_RESET);
 299
 300         /*
 301          * Poll for reset bit to self-clear indicating reset is complete.
 302          * Some PHYs could take up to 3 seconds to complete and need about
 303          * 1.7 usec delay after the reset is complete.
 304          */
 305         for (i = 0; i < 30; i++) {
 306                 msec_delay(100);
 307                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 308                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 309                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 310                         usec_delay(2);
 311                         break;
 312                 }
 313         }
 314
 315         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 316                 status = IXGBE_ERR_RESET_FAILED;
 317                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 318                              "PHY reset polling failed to complete.\n");
 319         }
 320
 321 out:
 322         return status;
 323 }
 324
 325 /**
 326  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 327  *  the SWFW lock
 328  *  @hw: pointer to hardware structure
 329  *  @reg_addr: 32 bit address of PHY register to read
 330  *  @phy_data: Pointer to read data from PHY register
 331  **/
 332 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 333                        u16 *phy_data)
 334 {
 335         u32 i, data, command;
 336
 337         /* Setup and write the address cycle command */
 338         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 339                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 340                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 341                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 342
 343         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 344
 345         /*
 346          * Check every 10 usec to see if the address cycle completed.
 347          * The MDI Command bit will clear when the operation is
 348          * complete
 349          */
 350         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 351                 usec_delay(10);
 352
 353                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 354                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 355                                 break;
 356         }
 357
 358
 359         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 360                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 361                 return IXGBE_ERR_PHY;
 362         }
 363
 364         /*
 365          * Address cycle complete, setup and write the read
 366          * command
 367          */
 368         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 369                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 370                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 371                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 372
 373         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 374
 375         /*
 376          * Check every 10 usec to see if the address cycle
 377          * completed. The MDI Command bit will clear when the
 378          * operation is complete
 379          */
 380         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 381                 usec_delay(10);
 382
 383                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 384                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 385                         break;
 386         }
 387
 388         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 389                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 390                 return IXGBE_ERR_PHY;
 391         }
 392
 393         /*
 394          * Read operation is complete.  Get the data
 395          * from MSRWD
 396          */
 397         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 398         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 399         *phy_data = (u16)(data);
 400
 401         return IXGBE_SUCCESS;
 402 }
 403
 404 /**
 405  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 406  *  using the SWFW lock - this function is needed in most cases
 407  *  @hw: pointer to hardware structure
 408  *  @reg_addr: 32 bit address of PHY register to read
 409  *  @phy_data: Pointer to read data from PHY register
 410  **/
 411 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 412                                u32 device_type, u16 *phy_data)
 413 {
 414         s32 status;
 415         u32 gssr = hw->phy.phy_semaphore_mask;
 416
 417         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 418
 419         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 420                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 421                                                 phy_data);
 422                 hw->mac.ops.release_swfw_sync(hw, gssr);
 423         } else {
 424                 status = IXGBE_ERR_SWFW_SYNC;
 425         }
 426
 427         return status;
 428 }
 429
 430 /**
 431  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 432  *  without SWFW lock
 433  *  @hw: pointer to hardware structure
 434  *  @reg_addr: 32 bit PHY register to write
 435  *  @device_type: 5 bit device type
 436  *  @phy_data: Data to write to the PHY register
 437  **/
 438 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 439                                 u32 device_type, u16 phy_data)
 440 {
 441         u32 i, command;
 442
 443         /* Put the data in the MDI single read and write data register*/
 444         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 445
 446         /* Setup and write the address cycle command */
 447         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 448                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 449                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 450                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 451
 452         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 453
 454         /*
 455          * Check every 10 usec to see if the address cycle completed.
 456          * The MDI Command bit will clear when the operation is
 457          * complete
 458          */
 459         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 460                 usec_delay(10);
 461
 462                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 463                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 464                         break;
 465         }
 466
 467         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 468                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 469                 return IXGBE_ERR_PHY;
 470         }
 471
 472         /*
 473          * Address cycle complete, setup and write the write
 474          * command
 475          */
 476         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 477                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 478                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 479                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 480
 481         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 482
 483         /*
 484          * Check every 10 usec to see if the address cycle
 485          * completed. The MDI Command bit will clear when the
 486          * operation is complete
 487          */
 488         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 489                 usec_delay(10);
 490
 491                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 492                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 493                         break;
 494         }
 495
 496         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 497                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 498                 return IXGBE_ERR_PHY;
 499         }
 500
 501         return IXGBE_SUCCESS;
 502 }
 503
 504 /**
 505  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 506  *  using SWFW lock- this function is needed in most cases
 507  *  @hw: pointer to hardware structure
 508  *  @reg_addr: 32 bit PHY register to write
 509  *  @device_type: 5 bit device type
 510  *  @phy_data: Data to write to the PHY register
 511  **/
 512 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 513                                 u32 device_type, u16 phy_data)
 514 {
 515         s32 status;
 516         u32 gssr = hw->phy.phy_semaphore_mask;
 517
 518         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 519
 520         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 521                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 522                                                  phy_data);
 523                 hw->mac.ops.release_swfw_sync(hw, gssr);
 524         } else {
 525                 status = IXGBE_ERR_SWFW_SYNC;
 526         }
 527
 528         return status;
 529 }
 530
 531 /**
 532  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 533  *  @hw: pointer to hardware structure
 534  *
 535  *  Restart auto-negotiation and PHY and waits for completion.
 536  **/
 537 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 538 {
 539         s32 status = IXGBE_SUCCESS;
 540         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 541         bool autoneg = false;
 542         ixgbe_link_speed speed;
 543
 544         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 545
 546         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 547
 548         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 549                 /* Set or unset auto-negotiation 10G advertisement */
 550                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 551                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 552                                      &autoneg_reg);
 553
 554                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 555                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 556                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 557
 558                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 559                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 560                                       autoneg_reg);
 561         }
 562
 563         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 564                 /* Set or unset auto-negotiation 1G advertisement */
 565                 hw->phy.ops.read_reg(hw,
 566                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 567                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 568                                      &autoneg_reg);
 569
 570                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 571                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 572                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 573
 574                 hw->phy.ops.write_reg(hw,
 575                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 576                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 577                                       autoneg_reg);
 578         }
 579
 580         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 581                 /* Set or unset auto-negotiation 100M advertisement */
 582                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 583                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 584                                      &autoneg_reg);
 585
 586                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 587                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 588                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 589                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 590
 591                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 592                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 593                                       autoneg_reg);
 594         }
 595
 596         /* Blocked by MNG FW so don't reset PHY */
 597         if (ixgbe_check_reset_blocked(hw))
 598                 return status;
 599
 600         /* Restart PHY auto-negotiation. */
 601         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 602                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 603
 604         autoneg_reg |= IXGBE_MII_RESTART;
 605
 606         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 607                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 608
 609         return status;
 610 }
 611
 612 /**
 613  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 614  *  @hw: pointer to hardware structure
 615  *  @speed: new link speed
 616  **/
 617 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 618                                        ixgbe_link_speed speed,
 619                                        bool autoneg_wait_to_complete)
 620 {
 621         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 622
 623         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 624
 625         /*
 626          * Clear autoneg_advertised and set new values based on input link
 627          * speed.
 628          */
 629         hw->phy.autoneg_advertised = 0;
 630
 631         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 632                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 633
 634         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 635                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 636
 637         if (speed & IXGBE_LINK_SPEED_100_FULL)
 638                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 639
 640         /* Setup link based on the new speed settings */
 641         hw->phy.ops.setup_link(hw);
 642
 643         return IXGBE_SUCCESS;
 644 }
 645
 646 /**
 647  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 648  *  @hw: pointer to hardware structure
 649  *  @speed: pointer to link speed
 650  *  @autoneg: boolean auto-negotiation value
 651  *
 652  *  Determines the link capabilities by reading the AUTOC register.
 653  **/
 654 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 655                                                ixgbe_link_speed *speed,
 656                                                bool *autoneg)
 657 {
 658         s32 status;
 659         u16 speed_ability;
 660
 661         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 662
 663         *speed = 0;
 664         *autoneg = true;
 665
 666         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 667                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 668                                       &speed_ability);
 669
 670         if (status == IXGBE_SUCCESS) {
 671                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 672                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 673                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 674                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 675                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 676                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 677         }
 678
 679         return status;
 680 }
 681
 682 /**
 683  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 684  *  @hw: pointer to hardware structure
 685  *
 686  *  Reads the VS1 register to determine if link is up and the current speed for
 687  *  the PHY.
 688  **/
 689 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 690                              bool *link_up)
 691 {
 692         s32 status = IXGBE_SUCCESS;
 693         u32 time_out;
 694         u32 max_time_out = 10;
 695         u16 phy_link = 0;
 696         u16 phy_speed = 0;
 697         u16 phy_data = 0;
 698
 699         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 700
 701         /* Initialize speed and link to default case */
 702         *link_up = false;
 703         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 704
 705         /*
 706          * Check current speed and link status of the PHY register.
 707          * This is a vendor specific register and may have to
 708          * be changed for other copper PHYs.
 709          */
 710         for (time_out = 0; time_out < max_time_out; time_out++) {
 711                 usec_delay(10);
 712                 status = hw->phy.ops.read_reg(hw,
 713                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 714                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 715                                         &phy_data);
 716                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 717                 phy_speed = phy_data &
 718                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 719                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 720                         *link_up = true;
 721                         if (phy_speed ==
 722                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 723                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 724                         break;
 725                 }
 726         }
 727
 728         return status;
 729 }
 730
 731 /**
 732  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
 733  *      @hw: pointer to hardware structure
 734  *
 735  *      Restart auto-negotiation and PHY and waits for completion.
 736  **/
 737 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 738 {
 739         s32 status = IXGBE_SUCCESS;
 740         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 741         bool autoneg = false;
 742         ixgbe_link_speed speed;
 743
 744         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 745
 746         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 747
 748         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 749                 /* Set or unset auto-negotiation 10G advertisement */
 750                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 751                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 752                                      &autoneg_reg);
 753
 754                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 755                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 756                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 757
 758                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 759                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 760                                       autoneg_reg);
 761         }
 762
 763         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 764                 /* Set or unset auto-negotiation 1G advertisement */
 765                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 766                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 767                                      &autoneg_reg);
 768
 769                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 770                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 771                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 772
 773                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 774                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 775                                       autoneg_reg);
 776         }
 777
 778         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 779                 /* Set or unset auto-negotiation 100M advertisement */
 780                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 781                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 782                                      &autoneg_reg);
 783
 784                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 785                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 786                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 787
 788                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 789                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 790                                       autoneg_reg);
 791         }
 792
 793         /* Blocked by MNG FW so don't reset PHY */
 794         if (ixgbe_check_reset_blocked(hw))
 795                 return status;
 796
 797         /* Restart PHY auto-negotiation. */
 798         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 799                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 800
 801         autoneg_reg |= IXGBE_MII_RESTART;
 802
 803         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 804                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 805
 806         return status;
 807 }
 808
 809 /**
 810  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 811  *  @hw: pointer to hardware structure
 812  *  @firmware_version: pointer to the PHY Firmware Version
 813  **/
 814 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 815                                        u16 *firmware_version)
 816 {
 817         s32 status;
 818
 819         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 820
 821         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 822                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 823                                       firmware_version);
 824
 825         return status;
 826 }
 827
 828 /**
 829  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 830  *  @hw: pointer to hardware structure
 831  *  @firmware_version: pointer to the PHY Firmware Version
 832  **/
 833 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 834                                            u16 *firmware_version)
 835 {
 836         s32 status;
 837
 838         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 839
 840         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 841                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 842                                       firmware_version);
 843
 844         return status;
 845 }
 846
 847 /**
 848  *  ixgbe_reset_phy_nl - Performs a PHY reset
 849  *  @hw: pointer to hardware structure
 850  **/
 851 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 852 {
 853         u16 phy_offset, control, eword, edata, block_crc;
 854         bool end_data = false;
 855         u16 list_offset, data_offset;
 856         u16 phy_data = 0;
 857         s32 ret_val = IXGBE_SUCCESS;
 858         u32 i;
 859
 860         DEBUGFUNC("ixgbe_reset_phy_nl");
 861
 862         /* Blocked by MNG FW so bail */
 863         if (ixgbe_check_reset_blocked(hw))
 864                 goto out;
 865
 866         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 867                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 868
 869         /* reset the PHY and poll for completion */
 870         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 871                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 872                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 873
 874         for (i = 0; i < 100; i++) {
 875                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 876                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 877                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 878                         break;
 879                 msec_delay(10);
 880         }
 881
 882         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 883                 DEBUGOUT("PHY reset did not complete.\n");
 884                 ret_val = IXGBE_ERR_PHY;
 885                 goto out;
 886         }
 887
 888         /* Get init offsets */
 889         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 890                                                       &data_offset);
 891         if (ret_val != IXGBE_SUCCESS)
 892                 goto out;
 893
 894         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 895         data_offset++;
 896         while (!end_data) {
 897                 /*
 898                  * Read control word from PHY init contents offset
 899                  */
 900                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 901                 if (ret_val)
 902                         goto err_eeprom;
 903                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 904                            IXGBE_CONTROL_SHIFT_NL;
 905                 edata = eword & IXGBE_DATA_MASK_NL;
 906                 switch (control) {
 907                 case IXGBE_DELAY_NL:
 908                         data_offset++;
 909                         DEBUGOUT1("DELAY: %d MS\n", edata);
 910                         msec_delay(edata);
 911                         break;
 912                 case IXGBE_DATA_NL:
 913                         DEBUGOUT("DATA:\n");
 914                         data_offset++;
 915                         ret_val = hw->eeprom.ops.read(hw, data_offset,
 916                                                       &phy_offset);
 917                         if (ret_val)
 918                                 goto err_eeprom;
 919                         data_offset++;
 920                         for (i = 0; i < edata; i++) {
 921                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 922                                                               &eword);
 923                                 if (ret_val)
 924                                         goto err_eeprom;
 925                                 hw->phy.ops.write_reg(hw, phy_offset,
 926                                                       IXGBE_TWINAX_DEV, eword);
 927                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
 928                                           phy_offset);
 929                                 data_offset++;
 930                                 phy_offset++;
 931                         }
 932                         break;
 933                 case IXGBE_CONTROL_NL:
 934                         data_offset++;
 935                         DEBUGOUT("CONTROL:\n");
 936                         if (edata == IXGBE_CONTROL_EOL_NL) {
 937                                 DEBUGOUT("EOL\n");
 938                                 end_data = true;
 939                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 940                                 DEBUGOUT("SOL\n");
 941                         } else {
 942                                 DEBUGOUT("Bad control value\n");
 943                                 ret_val = IXGBE_ERR_PHY;
 944                                 goto out;
 945                         }
 946                         break;
 947                 default:
 948                         DEBUGOUT("Bad control type\n");
 949                         ret_val = IXGBE_ERR_PHY;
 950                         goto out;
 951                 }
 952         }
 953
 954 out:
 955         return ret_val;
 956
 957 err_eeprom:
 958         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 959                       "eeprom read at offset %d failed", data_offset);
 960         return IXGBE_ERR_PHY;
 961 }
 962
 963 /**
 964  *  ixgbe_identify_module_generic - Identifies module type
 965  *  @hw: pointer to hardware structure
 966  *
 967  *  Determines HW type and calls appropriate function.
 968  **/
 969 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 970 {
 971         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 972
 973         DEBUGFUNC("ixgbe_identify_module_generic");
 974
 975         switch (hw->mac.ops.get_media_type(hw)) {
 976         case ixgbe_media_type_fiber:
 977                 status = ixgbe_identify_sfp_module_generic(hw);
 978                 break;
 979
 980         case ixgbe_media_type_fiber_qsfp:
 981                 status = ixgbe_identify_qsfp_module_generic(hw);
 982                 break;
 983
 984         default:
 985                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 986                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 987                 break;
 988         }
 989
 990         return status;
 991 }
 992
 993 /**
 994  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 995  *  @hw: pointer to hardware structure
 996  *
 997  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 998  **/
 999 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1000 {
1001         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1002         u32 vendor_oui = 0;
1003         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1004         u8 identifier = 0;
1005         u8 comp_codes_1g = 0;
1006         u8 comp_codes_10g = 0;
1007         u8 oui_bytes[3] = {0, 0, 0};
1008         u8 cable_tech = 0;
1009         u8 cable_spec = 0;
1010         u16 enforce_sfp = 0;
1011
1012         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1013
1014         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1015                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1016                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1017                 goto out;
1018         }
1019
1020         status = hw->phy.ops.read_i2c_eeprom(hw,
1021                                              IXGBE_SFF_IDENTIFIER,
1022                                              &identifier);
1023
1024         if (status != IXGBE_SUCCESS)
1025                 goto err_read_i2c_eeprom;
1026
1027         /* LAN ID is needed for sfp_type determination */
1028         hw->mac.ops.set_lan_id(hw);
1029
1030         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1031                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1032                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1033         } else {
1034                 status = hw->phy.ops.read_i2c_eeprom(hw,
1035                                                      IXGBE_SFF_1GBE_COMP_CODES,
1036                                                      &comp_codes_1g);
1037
1038                 if (status != IXGBE_SUCCESS)
1039                         goto err_read_i2c_eeprom;
1040
1041                 status = hw->phy.ops.read_i2c_eeprom(hw,
1042                                                      IXGBE_SFF_10GBE_COMP_CODES,
1043                                                      &comp_codes_10g);
1044
1045                 if (status != IXGBE_SUCCESS)
1046                         goto err_read_i2c_eeprom;
1047                 status = hw->phy.ops.read_i2c_eeprom(hw,
1048                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1049                                                      &cable_tech);
1050
1051                 if (status != IXGBE_SUCCESS)
1052                         goto err_read_i2c_eeprom;
1053
1054                  /* ID Module
1055                   * =========
1056                   * 0   SFP_DA_CU
1057                   * 1   SFP_SR
1058                   * 2   SFP_LR
1059                   * 3   SFP_DA_CORE0 - 82599-specific
1060                   * 4   SFP_DA_CORE1 - 82599-specific
1061                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1062                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1063                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1064                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1065                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1066                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1067                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1068                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1069                   */
1070                 if (hw->mac.type == ixgbe_mac_82598EB) {
1071                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1072                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1073                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1074                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1075                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1076                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1077                         else
1078                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1079                 } else {
1080                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1081                                 if (hw->bus.lan_id == 0)
1082                                         hw->phy.sfp_type =
1083                                                      ixgbe_sfp_type_da_cu_core0;
1084                                 else
1085                                         hw->phy.sfp_type =
1086                                                      ixgbe_sfp_type_da_cu_core1;
1087                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1088                                 hw->phy.ops.read_i2c_eeprom(
1089                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1090                                                 &cable_spec);
1091                                 if (cable_spec &
1092                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1093                                         if (hw->bus.lan_id == 0)
1094                                                 hw->phy.sfp_type =
1095                                                 ixgbe_sfp_type_da_act_lmt_core0;
1096                                         else
1097                                                 hw->phy.sfp_type =
1098                                                 ixgbe_sfp_type_da_act_lmt_core1;
1099                                 } else {
1100                                         hw->phy.sfp_type =
1101                                                         ixgbe_sfp_type_unknown;
1102                                 }
1103                         } else if (comp_codes_10g &
1104                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1105                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1106                                 if (hw->bus.lan_id == 0)
1107                                         hw->phy.sfp_type =
1108                                                       ixgbe_sfp_type_srlr_core0;
1109                                 else
1110                                         hw->phy.sfp_type =
1111                                                       ixgbe_sfp_type_srlr_core1;
1112                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1113                                 if (hw->bus.lan_id == 0)
1114                                         hw->phy.sfp_type =
1115                                                 ixgbe_sfp_type_1g_cu_core0;
1116                                 else
1117                                         hw->phy.sfp_type =
1118                                                 ixgbe_sfp_type_1g_cu_core1;
1119                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1120                                 if (hw->bus.lan_id == 0)
1121                                         hw->phy.sfp_type =
1122                                                 ixgbe_sfp_type_1g_sx_core0;
1123                                 else
1124                                         hw->phy.sfp_type =
1125                                                 ixgbe_sfp_type_1g_sx_core1;
1126                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1127                                 if (hw->bus.lan_id == 0)
1128                                         hw->phy.sfp_type =
1129                                                 ixgbe_sfp_type_1g_lx_core0;
1130                                 else
1131                                         hw->phy.sfp_type =
1132                                                 ixgbe_sfp_type_1g_lx_core1;
1133                         } else {
1134                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1135                         }
1136                 }
1137
1138                 if (hw->phy.sfp_type != stored_sfp_type)
1139                         hw->phy.sfp_setup_needed = true;
1140
1141                 /* Determine if the SFP+ PHY is dual speed or not. */
1142                 hw->phy.multispeed_fiber = false;
1143                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1144                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1145                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1146                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1147                         hw->phy.multispeed_fiber = true;
1148
1149                 /* Determine PHY vendor */
1150                 if (hw->phy.type != ixgbe_phy_nl) {
1151                         hw->phy.id = identifier;
1152                         status = hw->phy.ops.read_i2c_eeprom(hw,
1153                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1154                                                     &oui_bytes[0]);
1155
1156                         if (status != IXGBE_SUCCESS)
1157                                 goto err_read_i2c_eeprom;
1158
1159                         status = hw->phy.ops.read_i2c_eeprom(hw,
1160                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1161                                                     &oui_bytes[1]);
1162
1163                         if (status != IXGBE_SUCCESS)
1164                                 goto err_read_i2c_eeprom;
1165
1166                         status = hw->phy.ops.read_i2c_eeprom(hw,
1167                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1168                                                     &oui_bytes[2]);
1169
1170                         if (status != IXGBE_SUCCESS)
1171                                 goto err_read_i2c_eeprom;
1172
1173                         vendor_oui =
1174                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1175                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1176                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1177
1178                         switch (vendor_oui) {
1179                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1180                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1181                                         hw->phy.type =
1182                                                     ixgbe_phy_sfp_passive_tyco;
1183                                 break;
1184                         case IXGBE_SFF_VENDOR_OUI_FTL:
1185                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1186                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1187                                 else
1188                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1189                                 break;
1190                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1191                                 hw->phy.type = ixgbe_phy_sfp_avago;
1192                                 break;
1193                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1194                                 hw->phy.type = ixgbe_phy_sfp_intel;
1195                                 break;
1196                         default:
1197                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1198                                         hw->phy.type =
1199                                                  ixgbe_phy_sfp_passive_unknown;
1200                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1201                                         hw->phy.type =
1202                                                 ixgbe_phy_sfp_active_unknown;
1203                                 else
1204                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1205                                 break;
1206                         }
1207                 }
1208
1209                 /* Allow any DA cable vendor */
1210                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1211                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1212                         status = IXGBE_SUCCESS;
1213                         goto out;
1214                 }
1215
1216                 /* Verify supported 1G SFP modules */
1217                 if (comp_codes_10g == 0 &&
1218                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1219                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1220                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1221                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1222                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1223                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1224                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1225                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1226                         goto out;
1227                 }
1228
1229                 /* Anything else 82598-based is supported */
1230                 if (hw->mac.type == ixgbe_mac_82598EB) {
1231                         status = IXGBE_SUCCESS;
1232                         goto out;
1233                 }
1234
1235                 ixgbe_get_device_caps(hw, &enforce_sfp);
1236                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1237                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1238                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1239                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1240                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1241                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1242                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1243                         /* Make sure we're a supported PHY type */
1244                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1245                                 status = IXGBE_SUCCESS;
1246                         } else {
1247                                 if (hw->allow_unsupported_sfp == true) {
1248                                         EWARN(hw, "WARNING: Intel (R) Network "
1249                                               "Connections are quality tested "
1250                                               "using Intel (R) Ethernet Optics."
1251                                               " Using untested modules is not "
1252                                               "supported and may cause unstable"
1253                                               " operation or damage to the "
1254                                               "module or the adapter. Intel "
1255                                               "Corporation is not responsible "
1256                                               "for any harm caused by using "
1257                                               "untested modules.\n", status);
1258                                         status = IXGBE_SUCCESS;
1259                                 } else {
1260                                         DEBUGOUT("SFP+ module not supported\n");
1261                                         hw->phy.type =
1262                                                 ixgbe_phy_sfp_unsupported;
1263                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1264                                 }
1265                         }
1266                 } else {
1267                         status = IXGBE_SUCCESS;
1268                 }
1269         }
1270
1271 out:
1272         return status;
1273
1274 err_read_i2c_eeprom:
1275         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1276         if (hw->phy.type != ixgbe_phy_nl) {
1277                 hw->phy.id = 0;
1278                 hw->phy.type = ixgbe_phy_unknown;
1279         }
1280         return IXGBE_ERR_SFP_NOT_PRESENT;
1281 }
1282
1283 /**
1284  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1285  *  @hw: pointer to hardware structure
1286  *
1287  *  Determines physical layer capabilities of the current SFP.
1288  */
1289 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1290 {
1291         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1292         u8 comp_codes_10g = 0;
1293         u8 comp_codes_1g = 0;
1294
1295         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1296
1297         hw->phy.ops.identify_sfp(hw);
1298         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1299                 return physical_layer;
1300
1301         switch (hw->phy.type) {
1302         case ixgbe_phy_sfp_passive_tyco:
1303         case ixgbe_phy_sfp_passive_unknown:
1304         case ixgbe_phy_qsfp_passive_unknown:
1305                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1306                 break;
1307         case ixgbe_phy_sfp_ftl_active:
1308         case ixgbe_phy_sfp_active_unknown:
1309         case ixgbe_phy_qsfp_active_unknown:
1310                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1311                 break;
1312         case ixgbe_phy_sfp_avago:
1313         case ixgbe_phy_sfp_ftl:
1314         case ixgbe_phy_sfp_intel:
1315         case ixgbe_phy_sfp_unknown:
1316                 hw->phy.ops.read_i2c_eeprom(hw,
1317                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1318                 hw->phy.ops.read_i2c_eeprom(hw,
1319                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1320                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1321                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1322                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1323                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1324                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1325                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1326                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1327                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1328                 break;
1329         case ixgbe_phy_qsfp_intel:
1330         case ixgbe_phy_qsfp_unknown:
1331                 hw->phy.ops.read_i2c_eeprom(hw,
1332                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1333                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1334                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1335                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1336                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1337                 break;
1338         default:
1339                 break;
1340         }
1341
1342         return physical_layer;
1343 }
1344
1345 /**
1346  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1347  *  @hw: pointer to hardware structure
1348  *
1349  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1350  **/
1351 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1352 {
1353         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1354         u32 vendor_oui = 0;
1355         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1356         u8 identifier = 0;
1357         u8 comp_codes_1g = 0;
1358         u8 comp_codes_10g = 0;
1359         u8 oui_bytes[3] = {0, 0, 0};
1360         u16 enforce_sfp = 0;
1361         u8 connector = 0;
1362         u8 cable_length = 0;
1363         u8 device_tech = 0;
1364         bool active_cable = false;
1365
1366         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1367
1368         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1369                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1370                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1371                 goto out;
1372         }
1373
1374         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1375                                              &identifier);
1376
1377         if (status != IXGBE_SUCCESS)
1378                 goto err_read_i2c_eeprom;
1379
1380         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1381                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1382                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1383                 goto out;
1384         }
1385
1386         hw->phy.id = identifier;
1387
1388         /* LAN ID is needed for sfp_type determination */
1389         hw->mac.ops.set_lan_id(hw);
1390
1391         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1392                                              &comp_codes_10g);
1393
1394         if (status != IXGBE_SUCCESS)
1395                 goto err_read_i2c_eeprom;
1396
1397         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1398                                              &comp_codes_1g);
1399
1400         if (status != IXGBE_SUCCESS)
1401                 goto err_read_i2c_eeprom;
1402
1403         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1404                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1405                 if (hw->bus.lan_id == 0)
1406                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1407                 else
1408                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1409         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1410                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1411                 if (hw->bus.lan_id == 0)
1412                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1413                 else
1414                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1415         } else {
1416                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1417                         active_cable = true;
1418
1419                 if (!active_cable) {
1420                         /* check for active DA cables that pre-date
1421                          * SFF-8436 v3.6 */
1422                         hw->phy.ops.read_i2c_eeprom(hw,
1423                                         IXGBE_SFF_QSFP_CONNECTOR,
1424                                         &connector);
1425
1426                         hw->phy.ops.read_i2c_eeprom(hw,
1427                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1428                                         &cable_length);
1429
1430                         hw->phy.ops.read_i2c_eeprom(hw,
1431                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1432                                         &device_tech);
1433
1434                         if ((connector ==
1435                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1436                             (cable_length > 0) &&
1437                             ((device_tech >> 4) ==
1438                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1439                                 active_cable = true;
1440                 }
1441
1442                 if (active_cable) {
1443                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1444                         if (hw->bus.lan_id == 0)
1445                                 hw->phy.sfp_type =
1446                                                 ixgbe_sfp_type_da_act_lmt_core0;
1447                         else
1448                                 hw->phy.sfp_type =
1449                                                 ixgbe_sfp_type_da_act_lmt_core1;
1450                 } else {
1451                         /* unsupported module type */
1452                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1453                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1454                         goto out;
1455                 }
1456         }
1457
1458         if (hw->phy.sfp_type != stored_sfp_type)
1459                 hw->phy.sfp_setup_needed = true;
1460
1461         /* Determine if the QSFP+ PHY is dual speed or not. */
1462         hw->phy.multispeed_fiber = false;
1463         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1464            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1465            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1466            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1467                 hw->phy.multispeed_fiber = true;
1468
1469         /* Determine PHY vendor for optical modules */
1470         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1471                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1472                 status = hw->phy.ops.read_i2c_eeprom(hw,
1473                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1474                                             &oui_bytes[0]);
1475
1476                 if (status != IXGBE_SUCCESS)
1477                         goto err_read_i2c_eeprom;
1478
1479                 status = hw->phy.ops.read_i2c_eeprom(hw,
1480                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1481                                             &oui_bytes[1]);
1482
1483                 if (status != IXGBE_SUCCESS)
1484                         goto err_read_i2c_eeprom;
1485
1486                 status = hw->phy.ops.read_i2c_eeprom(hw,
1487                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1488                                             &oui_bytes[2]);
1489
1490                 if (status != IXGBE_SUCCESS)
1491                         goto err_read_i2c_eeprom;
1492
1493                 vendor_oui =
1494                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1495                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1496                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1497
1498                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1499                         hw->phy.type = ixgbe_phy_qsfp_intel;
1500                 else
1501                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1502
1503                 ixgbe_get_device_caps(hw, &enforce_sfp);
1504                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1505                         /* Make sure we're a supported PHY type */
1506                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1507                                 status = IXGBE_SUCCESS;
1508                         } else {
1509                                 if (hw->allow_unsupported_sfp == true) {
1510                                         EWARN(hw, "WARNING: Intel (R) Network "
1511                                               "Connections are quality tested "
1512                                               "using Intel (R) Ethernet Optics."
1513                                               " Using untested modules is not "
1514                                               "supported and may cause unstable"
1515                                               " operation or damage to the "
1516                                               "module or the adapter. Intel "
1517                                               "Corporation is not responsible "
1518                                               "for any harm caused by using "
1519                                               "untested modules.\n", status);
1520                                         status = IXGBE_SUCCESS;
1521                                 } else {
1522                                         DEBUGOUT("QSFP module not supported\n");
1523                                         hw->phy.type =
1524                                                 ixgbe_phy_sfp_unsupported;
1525                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1526                                 }
1527                         }
1528                 } else {
1529                         status = IXGBE_SUCCESS;
1530                 }
1531         }
1532
1533 out:
1534         return status;
1535
1536 err_read_i2c_eeprom:
1537         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1538         hw->phy.id = 0;
1539         hw->phy.type = ixgbe_phy_unknown;
1540
1541         return IXGBE_ERR_SFP_NOT_PRESENT;
1542 }
1543
1544
1545 /**
1546  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1547  *  @hw: pointer to hardware structure
1548  *  @list_offset: offset to the SFP ID list
1549  *  @data_offset: offset to the SFP data block
1550  *
1551  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1552  *  so it returns the offsets to the phy init sequence block.
1553  **/
1554 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1555                                         u16 *list_offset,
1556                                         u16 *data_offset)
1557 {
1558         u16 sfp_id;
1559         u16 sfp_type = hw->phy.sfp_type;
1560
1561         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1562
1563         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1564                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1565
1566         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1567                 return IXGBE_ERR_SFP_NOT_PRESENT;
1568
1569         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1570             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1571                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1572
1573         /*
1574          * Limiting active cables and 1G Phys must be initialized as
1575          * SR modules
1576          */
1577         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1578             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1579             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1580             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1581                 sfp_type = ixgbe_sfp_type_srlr_core0;
1582         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1583                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1584                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1585                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1586                 sfp_type = ixgbe_sfp_type_srlr_core1;
1587
1588         /* Read offset to PHY init contents */
1589         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1590                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1591                               "eeprom read at offset %d failed",
1592                               IXGBE_PHY_INIT_OFFSET_NL);
1593                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1594         }
1595
1596         if ((!*list_offset) || (*list_offset == 0xFFFF))
1597                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1598
1599         /* Shift offset to first ID word */
1600         (*list_offset)++;
1601
1602         /*
1603          * Find the matching SFP ID in the EEPROM
1604          * and program the init sequence
1605          */
1606         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1607                 goto err_phy;
1608
1609         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1610                 if (sfp_id == sfp_type) {
1611                         (*list_offset)++;
1612                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1613                                 goto err_phy;
1614                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1615                                 DEBUGOUT("SFP+ module not supported\n");
1616                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1617                         } else {
1618                                 break;
1619                         }
1620                 } else {
1621                         (*list_offset) += 2;
1622                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1623                                 goto err_phy;
1624                 }
1625         }
1626
1627         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1628                 DEBUGOUT("No matching SFP+ module found\n");
1629                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1630         }
1631
1632         return IXGBE_SUCCESS;
1633
1634 err_phy:
1635         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1636                       "eeprom read at offset %d failed", *list_offset);
1637         return IXGBE_ERR_PHY;
1638 }
1639
1640 /**
1641  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1642  *  @hw: pointer to hardware structure
1643  *  @byte_offset: EEPROM byte offset to read
1644  *  @eeprom_data: value read
1645  *
1646  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1647  **/
1648 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1649                                   u8 *eeprom_data)
1650 {
1651         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1652
1653         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1654                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1655                                          eeprom_data);
1656 }
1657
1658 /**
1659  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1660  *  @hw: pointer to hardware structure
1661  *  @byte_offset: byte offset at address 0xA2
1662  *  @eeprom_data: value read
1663  *
1664  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1665  **/
1666 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1667                                           u8 *sff8472_data)
1668 {
1669         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1670                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1671                                          sff8472_data);
1672 }
1673
1674 /**
1675  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1676  *  @hw: pointer to hardware structure
1677  *  @byte_offset: EEPROM byte offset to write
1678  *  @eeprom_data: value to write
1679  *
1680  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1681  **/
1682 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1683                                    u8 eeprom_data)
1684 {
1685         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1686
1687         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1688                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1689                                           eeprom_data);
1690 }
1691
1692 /**
1693  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1694  *  @hw: pointer to hardware structure
1695  *  @byte_offset: byte offset to read
1696  *  @data: value read
1697  *
1698  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1699  *  a specified device address.
1700  **/
1701 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1702                                 u8 dev_addr, u8 *data)
1703 {
1704         s32 status;
1705         u32 max_retry = 10;
1706         u32 retry = 0;
1707         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1708         bool nack = 1;
1709         *data = 0;
1710
1711         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1712
1713         do {
1714                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1715                         return IXGBE_ERR_SWFW_SYNC;
1716
1717                 ixgbe_i2c_start(hw);
1718
1719                 /* Device Address and write indication */
1720                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1721                 if (status != IXGBE_SUCCESS)
1722                         goto fail;
1723
1724                 status = ixgbe_get_i2c_ack(hw);
1725                 if (status != IXGBE_SUCCESS)
1726                         goto fail;
1727
1728                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1729                 if (status != IXGBE_SUCCESS)
1730                         goto fail;
1731
1732                 status = ixgbe_get_i2c_ack(hw);
1733                 if (status != IXGBE_SUCCESS)
1734                         goto fail;
1735
1736                 ixgbe_i2c_start(hw);
1737
1738                 /* Device Address and read indication */
1739                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1740                 if (status != IXGBE_SUCCESS)
1741                         goto fail;
1742
1743                 status = ixgbe_get_i2c_ack(hw);
1744                 if (status != IXGBE_SUCCESS)
1745                         goto fail;
1746
1747                 status = ixgbe_clock_in_i2c_byte(hw, data);
1748                 if (status != IXGBE_SUCCESS)
1749                         goto fail;
1750
1751                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1752                 if (status != IXGBE_SUCCESS)
1753                         goto fail;
1754
1755                 ixgbe_i2c_stop(hw);
1756                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1757                 return IXGBE_SUCCESS;
1758
1759 fail:
1760                 ixgbe_i2c_bus_clear(hw);
1761                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1762                 msec_delay(100);
1763                 retry++;
1764                 if (retry < max_retry)
1765                         DEBUGOUT("I2C byte read error - Retrying.\n");
1766                 else
1767                         DEBUGOUT("I2C byte read error.\n");
1768
1769         } while (retry < max_retry);
1770
1771         return status;
1772 }
1773
1774 /**
1775  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1776  *  @hw: pointer to hardware structure
1777  *  @byte_offset: byte offset to write
1778  *  @data: value to write
1779  *
1780  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1781  *  a specified device address.
1782  **/
1783 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1784                                  u8 dev_addr, u8 data)
1785 {
1786         s32 status = IXGBE_SUCCESS;
1787         u32 max_retry = 1;
1788         u32 retry = 0;
1789         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1790
1791         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1792
1793         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1794                 status = IXGBE_ERR_SWFW_SYNC;
1795                 goto write_byte_out;
1796         }
1797
1798         do {
1799                 ixgbe_i2c_start(hw);
1800
1801                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1802                 if (status != IXGBE_SUCCESS)
1803                         goto fail;
1804
1805                 status = ixgbe_get_i2c_ack(hw);
1806                 if (status != IXGBE_SUCCESS)
1807                         goto fail;
1808
1809                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1810                 if (status != IXGBE_SUCCESS)
1811                         goto fail;
1812
1813                 status = ixgbe_get_i2c_ack(hw);
1814                 if (status != IXGBE_SUCCESS)
1815                         goto fail;
1816
1817                 status = ixgbe_clock_out_i2c_byte(hw, data);
1818                 if (status != IXGBE_SUCCESS)
1819                         goto fail;
1820
1821                 status = ixgbe_get_i2c_ack(hw);
1822                 if (status != IXGBE_SUCCESS)
1823                         goto fail;
1824
1825                 ixgbe_i2c_stop(hw);
1826                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1827                 return IXGBE_SUCCESS;
1828
1829 fail:
1830                 ixgbe_i2c_bus_clear(hw);
1831                 retry++;
1832                 if (retry < max_retry)
1833                         DEBUGOUT("I2C byte write error - Retrying.\n");
1834                 else
1835                         DEBUGOUT("I2C byte write error.\n");
1836         } while (retry < max_retry);
1837
1838         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1839
1840 write_byte_out:
1841         return status;
1842 }
1843
1844 /**
1845  *  ixgbe_i2c_start - Sets I2C start condition
1846  *  @hw: pointer to hardware structure
1847  *
1848  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1849  **/
1850 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
1851 {
1852         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1853
1854         DEBUGFUNC("ixgbe_i2c_start");
1855
1856         /* Start condition must begin with data and clock high */
1857         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1858         ixgbe_raise_i2c_clk(hw, &i2cctl);
1859
1860         /* Setup time for start condition (4.7us) */
1861         usec_delay(IXGBE_I2C_T_SU_STA);
1862
1863         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1864
1865         /* Hold time for start condition (4us) */
1866         usec_delay(IXGBE_I2C_T_HD_STA);
1867
1868         ixgbe_lower_i2c_clk(hw, &i2cctl);
1869
1870         /* Minimum low period of clock is 4.7 us */
1871         usec_delay(IXGBE_I2C_T_LOW);
1872
1873 }
1874
1875 /**
1876  *  ixgbe_i2c_stop - Sets I2C stop condition
1877  *  @hw: pointer to hardware structure
1878  *
1879  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1880  **/
1881 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1882 {
1883         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1884
1885         DEBUGFUNC("ixgbe_i2c_stop");
1886
1887         /* Stop condition must begin with data low and clock high */
1888         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1889         ixgbe_raise_i2c_clk(hw, &i2cctl);
1890
1891         /* Setup time for stop condition (4us) */
1892         usec_delay(IXGBE_I2C_T_SU_STO);
1893
1894         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1895
1896         /* bus free time between stop and start (4.7us)*/
1897         usec_delay(IXGBE_I2C_T_BUF);
1898 }
1899
1900 /**
1901  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1902  *  @hw: pointer to hardware structure
1903  *  @data: data byte to clock in
1904  *
1905  *  Clocks in one byte data via I2C data/clock
1906  **/
1907 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1908 {
1909         s32 i;
1910         bool bit = 0;
1911
1912         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1913
1914         for (i = 7; i >= 0; i--) {
1915                 ixgbe_clock_in_i2c_bit(hw, &bit);
1916                 *data |= bit << i;
1917         }
1918
1919         return IXGBE_SUCCESS;
1920 }
1921
1922 /**
1923  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1924  *  @hw: pointer to hardware structure
1925  *  @data: data byte clocked out
1926  *
1927  *  Clocks out one byte data via I2C data/clock
1928  **/
1929 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1930 {
1931         s32 status = IXGBE_SUCCESS;
1932         s32 i;
1933         u32 i2cctl;
1934         bool bit;
1935
1936         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1937
1938         for (i = 7; i >= 0; i--) {
1939                 bit = (data >> i) & 0x1;
1940                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1941
1942                 if (status != IXGBE_SUCCESS)
1943                         break;
1944         }
1945
1946         /* Release SDA line (set high) */
1947         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1948         i2cctl |= IXGBE_I2C_DATA_OUT;
1949         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1950         IXGBE_WRITE_FLUSH(hw);
1951
1952         return status;
1953 }
1954
1955 /**
1956  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1957  *  @hw: pointer to hardware structure
1958  *
1959  *  Clocks in/out one bit via I2C data/clock
1960  **/
1961 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1962 {
1963         s32 status = IXGBE_SUCCESS;
1964         u32 i = 0;
1965         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1966         u32 timeout = 10;
1967         bool ack = 1;
1968
1969         DEBUGFUNC("ixgbe_get_i2c_ack");
1970
1971         ixgbe_raise_i2c_clk(hw, &i2cctl);
1972
1973
1974         /* Minimum high period of clock is 4us */
1975         usec_delay(IXGBE_I2C_T_HIGH);
1976
1977         /* Poll for ACK.  Note that ACK in I2C spec is
1978          * transition from 1 to 0 */
1979         for (i = 0; i < timeout; i++) {
1980                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1981                 ack = ixgbe_get_i2c_data(&i2cctl);
1982
1983                 usec_delay(1);
1984                 if (!ack)
1985                         break;
1986         }
1987
1988         if (ack == 1) {
1989                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1990                              "I2C ack was not received.\n");
1991                 status = IXGBE_ERR_I2C;
1992         }
1993
1994         ixgbe_lower_i2c_clk(hw, &i2cctl);
1995
1996         /* Minimum low period of clock is 4.7 us */
1997         usec_delay(IXGBE_I2C_T_LOW);
1998
1999         return status;
2000 }
2001
2002 /**
2003  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2004  *  @hw: pointer to hardware structure
2005  *  @data: read data value
2006  *
2007  *  Clocks in one bit via I2C data/clock
2008  **/
2009 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2010 {
2011         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2012
2013         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2014
2015         ixgbe_raise_i2c_clk(hw, &i2cctl);
2016
2017         /* Minimum high period of clock is 4us */
2018         usec_delay(IXGBE_I2C_T_HIGH);
2019
2020         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2021         *data = ixgbe_get_i2c_data(&i2cctl);
2022
2023         ixgbe_lower_i2c_clk(hw, &i2cctl);
2024
2025         /* Minimum low period of clock is 4.7 us */
2026         usec_delay(IXGBE_I2C_T_LOW);
2027
2028         return IXGBE_SUCCESS;
2029 }
2030
2031 /**
2032  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2033  *  @hw: pointer to hardware structure
2034  *  @data: data value to write
2035  *
2036  *  Clocks out one bit via I2C data/clock
2037  **/
2038 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2039 {
2040         s32 status;
2041         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2042
2043         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2044
2045         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2046         if (status == IXGBE_SUCCESS) {
2047                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2048
2049                 /* Minimum high period of clock is 4us */
2050                 usec_delay(IXGBE_I2C_T_HIGH);
2051
2052                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2053
2054                 /* Minimum low period of clock is 4.7 us.
2055                  * This also takes care of the data hold time.
2056                  */
2057                 usec_delay(IXGBE_I2C_T_LOW);
2058         } else {
2059                 status = IXGBE_ERR_I2C;
2060                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2061                              "I2C data was not set to %X\n", data);
2062         }
2063
2064         return status;
2065 }
2066
2067 /**
2068  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2069  *  @hw: pointer to hardware structure
2070  *  @i2cctl: Current value of I2CCTL register
2071  *
2072  *  Raises the I2C clock line '0'->'1'
2073  **/
2074 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2075 {
2076         u32 i = 0;
2077         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2078         u32 i2cctl_r = 0;
2079
2080         DEBUGFUNC("ixgbe_raise_i2c_clk");
2081
2082         for (i = 0; i < timeout; i++) {
2083                 *i2cctl |= IXGBE_I2C_CLK_OUT;
2084
2085                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
2086                 IXGBE_WRITE_FLUSH(hw);
2087                 /* SCL rise time (1000ns) */
2088                 usec_delay(IXGBE_I2C_T_RISE);
2089
2090                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2091                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
2092                         break;
2093         }
2094 }
2095
2096 /**
2097  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2098  *  @hw: pointer to hardware structure
2099  *  @i2cctl: Current value of I2CCTL register
2100  *
2101  *  Lowers the I2C clock line '1'->'0'
2102  **/
2103 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2104 {
2105
2106         DEBUGFUNC("ixgbe_lower_i2c_clk");
2107
2108         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
2109
2110         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
2111         IXGBE_WRITE_FLUSH(hw);
2112
2113         /* SCL fall time (300ns) */
2114         usec_delay(IXGBE_I2C_T_FALL);
2115 }
2116
2117 /**
2118  *  ixgbe_set_i2c_data - Sets the I2C data bit
2119  *  @hw: pointer to hardware structure
2120  *  @i2cctl: Current value of I2CCTL register
2121  *  @data: I2C data value (0 or 1) to set
2122  *
2123  *  Sets the I2C data bit
2124  **/
2125 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2126 {
2127         s32 status = IXGBE_SUCCESS;
2128
2129         DEBUGFUNC("ixgbe_set_i2c_data");
2130
2131         if (data)
2132                 *i2cctl |= IXGBE_I2C_DATA_OUT;
2133         else
2134                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
2135
2136         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
2137         IXGBE_WRITE_FLUSH(hw);
2138
2139         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2140         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2141
2142         /* Verify data was set correctly */
2143         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2144         if (data != ixgbe_get_i2c_data(i2cctl)) {
2145                 status = IXGBE_ERR_I2C;
2146                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2147                              "Error - I2C data was not set to %X.\n",
2148                              data);
2149         }
2150
2151         return status;
2152 }
2153
2154 /**
2155  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2156  *  @hw: pointer to hardware structure
2157  *  @i2cctl: Current value of I2CCTL register
2158  *
2159  *  Returns the I2C data bit value
2160  **/
2161 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
2162 {
2163         bool data;
2164
2165         DEBUGFUNC("ixgbe_get_i2c_data");
2166
2167         if (*i2cctl & IXGBE_I2C_DATA_IN)
2168                 data = 1;
2169         else
2170                 data = 0;
2171
2172         return data;
2173 }
2174
2175 /**
2176  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2177  *  @hw: pointer to hardware structure
2178  *
2179  *  Clears the I2C bus by sending nine clock pulses.
2180  *  Used when data line is stuck low.
2181  **/
2182 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2183 {
2184         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2185         u32 i;
2186
2187         DEBUGFUNC("ixgbe_i2c_bus_clear");
2188
2189         ixgbe_i2c_start(hw);
2190
2191         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2192
2193         for (i = 0; i < 9; i++) {
2194                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2195
2196                 /* Min high period of clock is 4us */
2197                 usec_delay(IXGBE_I2C_T_HIGH);
2198
2199                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2200
2201                 /* Min low period of clock is 4.7us*/
2202                 usec_delay(IXGBE_I2C_T_LOW);
2203         }
2204
2205         ixgbe_i2c_start(hw);
2206
2207         /* Put the i2c bus back to default state */
2208         ixgbe_i2c_stop(hw);
2209 }
2210
2211 /**
2212  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2213  *  @hw: pointer to hardware structure
2214  *
2215  *  Checks if the LASI temp alarm status was triggered due to overtemp
2216  **/
2217 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2218 {
2219         s32 status = IXGBE_SUCCESS;
2220         u16 phy_data = 0;
2221
2222         DEBUGFUNC("ixgbe_tn_check_overtemp");
2223
2224         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2225                 goto out;
2226
2227         /* Check that the LASI temp alarm status was triggered */
2228         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2229                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2230
2231         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2232                 goto out;
2233
2234         status = IXGBE_ERR_OVERTEMP;
2235         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2236 out:
2237         return status;
2238 }