1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37 #ident "$Id: ixgbe_phy.c,v 1.155 2013/08/14 22:34:03 jtkirshe Exp $"
39 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
50 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
54 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
55 * @hw: pointer to the hardware structure
57 * Initialize the function pointers.
59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
61 struct ixgbe_phy_info *phy = &hw->phy;
63 DEBUGFUNC("ixgbe_init_phy_ops_generic");
66 phy->ops.identify = &ixgbe_identify_phy_generic;
67 phy->ops.reset = &ixgbe_reset_phy_generic;
68 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
69 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
70 phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
71 phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
72 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
73 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
74 phy->ops.check_link = NULL;
75 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
76 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
77 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
78 phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
79 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
80 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
81 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
82 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
83 phy->sfp_type = ixgbe_sfp_type_unknown;
84 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
89 * ixgbe_identify_phy_generic - Get physical layer module
90 * @hw: pointer to hardware structure
92 * Determines the physical layer module found on the current adapter.
94 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
96 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
100 DEBUGFUNC("ixgbe_identify_phy_generic");
102 if (!hw->phy.phy_semaphore_mask) {
103 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
104 IXGBE_STATUS_LAN_ID_1;
106 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
108 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
111 if (hw->phy.type == ixgbe_phy_unknown) {
112 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
113 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
114 hw->phy.addr = phy_addr;
115 ixgbe_get_phy_id(hw);
117 ixgbe_get_phy_type_from_id(hw->phy.id);
119 if (hw->phy.type == ixgbe_phy_unknown) {
120 hw->phy.ops.read_reg(hw,
121 IXGBE_MDIO_PHY_EXT_ABILITY,
122 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
125 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
126 IXGBE_MDIO_PHY_1000BASET_ABILITY))
128 ixgbe_phy_cu_unknown;
134 status = IXGBE_SUCCESS;
139 /* Certain media types do not have a phy so an address will not
140 * be found and the code will take this path. Caller has to
141 * decide if it is an error or not.
143 if (status != IXGBE_SUCCESS) {
147 status = IXGBE_SUCCESS;
154 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
155 * @hw: pointer to the hardware structure
157 * This function checks the MMNGC.MNG_VETO bit to see if there are
158 * any constraints on link from manageability. For MAC's that don't
159 * have this bit just return faluse since the link can not be blocked
162 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
166 DEBUGFUNC("ixgbe_check_reset_blocked");
168 /* If we don't have this bit, it can't be blocking */
169 if (hw->mac.type == ixgbe_mac_82598EB)
172 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
173 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
174 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
175 "MNG_VETO bit detected.\n");
183 * ixgbe_validate_phy_addr - Determines phy address is valid
184 * @hw: pointer to hardware structure
187 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
192 DEBUGFUNC("ixgbe_validate_phy_addr");
194 hw->phy.addr = phy_addr;
195 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
196 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
198 if (phy_id != 0xFFFF && phy_id != 0x0)
205 * ixgbe_get_phy_id - Get the phy type
206 * @hw: pointer to hardware structure
209 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
215 DEBUGFUNC("ixgbe_get_phy_id");
217 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
218 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
221 if (status == IXGBE_SUCCESS) {
222 hw->phy.id = (u32)(phy_id_high << 16);
223 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
224 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
226 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
227 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
233 * ixgbe_get_phy_type_from_id - Get the phy type
234 * @hw: pointer to hardware structure
237 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
239 enum ixgbe_phy_type phy_type;
241 DEBUGFUNC("ixgbe_get_phy_type_from_id");
245 phy_type = ixgbe_phy_tn;
248 phy_type = ixgbe_phy_aq;
251 phy_type = ixgbe_phy_qt;
254 phy_type = ixgbe_phy_nl;
257 phy_type = ixgbe_phy_unknown;
261 DEBUGOUT1("phy type found is %d\n", phy_type);
266 * ixgbe_reset_phy_generic - Performs a PHY reset
267 * @hw: pointer to hardware structure
269 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
273 s32 status = IXGBE_SUCCESS;
275 DEBUGFUNC("ixgbe_reset_phy_generic");
277 if (hw->phy.type == ixgbe_phy_unknown)
278 status = ixgbe_identify_phy_generic(hw);
280 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
283 /* Don't reset PHY if it's shut down due to overtemp. */
284 if (!hw->phy.reset_if_overtemp &&
285 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
288 /* Blocked by MNG FW so bail */
289 if (ixgbe_check_reset_blocked(hw))
293 * Perform soft PHY reset to the PHY_XS.
294 * This will cause a soft reset to the PHY
296 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
297 IXGBE_MDIO_PHY_XS_DEV_TYPE,
298 IXGBE_MDIO_PHY_XS_RESET);
301 * Poll for reset bit to self-clear indicating reset is complete.
302 * Some PHYs could take up to 3 seconds to complete and need about
303 * 1.7 usec delay after the reset is complete.
305 for (i = 0; i < 30; i++) {
307 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
308 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
309 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
315 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
316 status = IXGBE_ERR_RESET_FAILED;
317 ERROR_REPORT1(IXGBE_ERROR_POLLING,
318 "PHY reset polling failed to complete.\n");
326 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
328 * @hw: pointer to hardware structure
329 * @reg_addr: 32 bit address of PHY register to read
330 * @phy_data: Pointer to read data from PHY register
332 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
335 u32 i, data, command;
337 /* Setup and write the address cycle command */
338 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
339 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
340 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
341 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
343 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
346 * Check every 10 usec to see if the address cycle completed.
347 * The MDI Command bit will clear when the operation is
350 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
353 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
354 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
359 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
360 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
361 return IXGBE_ERR_PHY;
365 * Address cycle complete, setup and write the read
368 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
369 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
370 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
371 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
373 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
376 * Check every 10 usec to see if the address cycle
377 * completed. The MDI Command bit will clear when the
378 * operation is complete
380 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
383 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
384 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
388 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
389 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
390 return IXGBE_ERR_PHY;
394 * Read operation is complete. Get the data
397 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
398 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
399 *phy_data = (u16)(data);
401 return IXGBE_SUCCESS;
405 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
406 * using the SWFW lock - this function is needed in most cases
407 * @hw: pointer to hardware structure
408 * @reg_addr: 32 bit address of PHY register to read
409 * @phy_data: Pointer to read data from PHY register
411 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
412 u32 device_type, u16 *phy_data)
415 u32 gssr = hw->phy.phy_semaphore_mask;
417 DEBUGFUNC("ixgbe_read_phy_reg_generic");
419 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
420 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
422 hw->mac.ops.release_swfw_sync(hw, gssr);
424 status = IXGBE_ERR_SWFW_SYNC;
431 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
433 * @hw: pointer to hardware structure
434 * @reg_addr: 32 bit PHY register to write
435 * @device_type: 5 bit device type
436 * @phy_data: Data to write to the PHY register
438 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
439 u32 device_type, u16 phy_data)
443 /* Put the data in the MDI single read and write data register*/
444 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
446 /* Setup and write the address cycle command */
447 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
448 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
449 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
450 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
452 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
455 * Check every 10 usec to see if the address cycle completed.
456 * The MDI Command bit will clear when the operation is
459 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
462 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
463 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
467 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
468 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
469 return IXGBE_ERR_PHY;
473 * Address cycle complete, setup and write the write
476 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
477 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
478 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
479 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
481 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
484 * Check every 10 usec to see if the address cycle
485 * completed. The MDI Command bit will clear when the
486 * operation is complete
488 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
491 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
492 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
496 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
497 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
498 return IXGBE_ERR_PHY;
501 return IXGBE_SUCCESS;
505 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
506 * using SWFW lock- this function is needed in most cases
507 * @hw: pointer to hardware structure
508 * @reg_addr: 32 bit PHY register to write
509 * @device_type: 5 bit device type
510 * @phy_data: Data to write to the PHY register
512 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
513 u32 device_type, u16 phy_data)
516 u32 gssr = hw->phy.phy_semaphore_mask;
518 DEBUGFUNC("ixgbe_write_phy_reg_generic");
520 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
521 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
523 hw->mac.ops.release_swfw_sync(hw, gssr);
525 status = IXGBE_ERR_SWFW_SYNC;
532 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
533 * @hw: pointer to hardware structure
535 * Restart auto-negotiation and PHY and waits for completion.
537 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
539 s32 status = IXGBE_SUCCESS;
540 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
541 bool autoneg = false;
542 ixgbe_link_speed speed;
544 DEBUGFUNC("ixgbe_setup_phy_link_generic");
546 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
548 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
549 /* Set or unset auto-negotiation 10G advertisement */
550 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
551 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
554 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
555 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
556 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
558 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
559 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
563 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
564 /* Set or unset auto-negotiation 1G advertisement */
565 hw->phy.ops.read_reg(hw,
566 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
567 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
570 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
571 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
572 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
574 hw->phy.ops.write_reg(hw,
575 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
576 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
580 if (speed & IXGBE_LINK_SPEED_100_FULL) {
581 /* Set or unset auto-negotiation 100M advertisement */
582 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
583 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
586 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
587 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
588 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
589 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
591 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
592 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
596 /* Blocked by MNG FW so don't reset PHY */
597 if (ixgbe_check_reset_blocked(hw))
600 /* Restart PHY auto-negotiation. */
601 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
602 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
604 autoneg_reg |= IXGBE_MII_RESTART;
606 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
607 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
613 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
614 * @hw: pointer to hardware structure
615 * @speed: new link speed
617 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
618 ixgbe_link_speed speed,
619 bool autoneg_wait_to_complete)
621 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
623 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
626 * Clear autoneg_advertised and set new values based on input link
629 hw->phy.autoneg_advertised = 0;
631 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
632 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
634 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
635 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
637 if (speed & IXGBE_LINK_SPEED_100_FULL)
638 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
640 /* Setup link based on the new speed settings */
641 hw->phy.ops.setup_link(hw);
643 return IXGBE_SUCCESS;
647 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
648 * @hw: pointer to hardware structure
649 * @speed: pointer to link speed
650 * @autoneg: boolean auto-negotiation value
652 * Determines the link capabilities by reading the AUTOC register.
654 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
655 ixgbe_link_speed *speed,
661 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
666 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
667 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
670 if (status == IXGBE_SUCCESS) {
671 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
672 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
673 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
674 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
675 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
676 *speed |= IXGBE_LINK_SPEED_100_FULL;
683 * ixgbe_check_phy_link_tnx - Determine link and speed status
684 * @hw: pointer to hardware structure
686 * Reads the VS1 register to determine if link is up and the current speed for
689 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
692 s32 status = IXGBE_SUCCESS;
694 u32 max_time_out = 10;
699 DEBUGFUNC("ixgbe_check_phy_link_tnx");
701 /* Initialize speed and link to default case */
703 *speed = IXGBE_LINK_SPEED_10GB_FULL;
706 * Check current speed and link status of the PHY register.
707 * This is a vendor specific register and may have to
708 * be changed for other copper PHYs.
710 for (time_out = 0; time_out < max_time_out; time_out++) {
712 status = hw->phy.ops.read_reg(hw,
713 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
714 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
716 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
717 phy_speed = phy_data &
718 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
719 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
722 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
723 *speed = IXGBE_LINK_SPEED_1GB_FULL;
732 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
733 * @hw: pointer to hardware structure
735 * Restart auto-negotiation and PHY and waits for completion.
737 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
739 s32 status = IXGBE_SUCCESS;
740 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
741 bool autoneg = false;
742 ixgbe_link_speed speed;
744 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
746 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
748 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
749 /* Set or unset auto-negotiation 10G advertisement */
750 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
751 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
754 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
755 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
756 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
758 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
759 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
763 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
764 /* Set or unset auto-negotiation 1G advertisement */
765 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
766 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
769 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
770 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
771 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
773 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
774 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
778 if (speed & IXGBE_LINK_SPEED_100_FULL) {
779 /* Set or unset auto-negotiation 100M advertisement */
780 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
781 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
784 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
785 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
786 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
788 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
789 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
793 /* Blocked by MNG FW so don't reset PHY */
794 if (ixgbe_check_reset_blocked(hw))
797 /* Restart PHY auto-negotiation. */
798 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
799 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
801 autoneg_reg |= IXGBE_MII_RESTART;
803 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
804 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
810 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
811 * @hw: pointer to hardware structure
812 * @firmware_version: pointer to the PHY Firmware Version
814 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
815 u16 *firmware_version)
819 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
821 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
822 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
829 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
830 * @hw: pointer to hardware structure
831 * @firmware_version: pointer to the PHY Firmware Version
833 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
834 u16 *firmware_version)
838 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
840 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
841 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
848 * ixgbe_reset_phy_nl - Performs a PHY reset
849 * @hw: pointer to hardware structure
851 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
853 u16 phy_offset, control, eword, edata, block_crc;
854 bool end_data = false;
855 u16 list_offset, data_offset;
857 s32 ret_val = IXGBE_SUCCESS;
860 DEBUGFUNC("ixgbe_reset_phy_nl");
862 /* Blocked by MNG FW so bail */
863 if (ixgbe_check_reset_blocked(hw))
866 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
867 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
869 /* reset the PHY and poll for completion */
870 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
871 IXGBE_MDIO_PHY_XS_DEV_TYPE,
872 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
874 for (i = 0; i < 100; i++) {
875 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
876 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
877 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
882 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
883 DEBUGOUT("PHY reset did not complete.\n");
884 ret_val = IXGBE_ERR_PHY;
888 /* Get init offsets */
889 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
891 if (ret_val != IXGBE_SUCCESS)
894 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
898 * Read control word from PHY init contents offset
900 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
903 control = (eword & IXGBE_CONTROL_MASK_NL) >>
904 IXGBE_CONTROL_SHIFT_NL;
905 edata = eword & IXGBE_DATA_MASK_NL;
909 DEBUGOUT1("DELAY: %d MS\n", edata);
915 ret_val = hw->eeprom.ops.read(hw, data_offset,
920 for (i = 0; i < edata; i++) {
921 ret_val = hw->eeprom.ops.read(hw, data_offset,
925 hw->phy.ops.write_reg(hw, phy_offset,
926 IXGBE_TWINAX_DEV, eword);
927 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
933 case IXGBE_CONTROL_NL:
935 DEBUGOUT("CONTROL:\n");
936 if (edata == IXGBE_CONTROL_EOL_NL) {
939 } else if (edata == IXGBE_CONTROL_SOL_NL) {
942 DEBUGOUT("Bad control value\n");
943 ret_val = IXGBE_ERR_PHY;
948 DEBUGOUT("Bad control type\n");
949 ret_val = IXGBE_ERR_PHY;
958 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
959 "eeprom read at offset %d failed", data_offset);
960 return IXGBE_ERR_PHY;
964 * ixgbe_identify_module_generic - Identifies module type
965 * @hw: pointer to hardware structure
967 * Determines HW type and calls appropriate function.
969 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
971 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
973 DEBUGFUNC("ixgbe_identify_module_generic");
975 switch (hw->mac.ops.get_media_type(hw)) {
976 case ixgbe_media_type_fiber:
977 status = ixgbe_identify_sfp_module_generic(hw);
982 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
983 status = IXGBE_ERR_SFP_NOT_PRESENT;
991 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
992 * @hw: pointer to hardware structure
994 * Searches for and identifies the SFP module and assigns appropriate PHY type.
996 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
998 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1000 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1002 u8 comp_codes_1g = 0;
1003 u8 comp_codes_10g = 0;
1004 u8 oui_bytes[3] = {0, 0, 0};
1007 u16 enforce_sfp = 0;
1009 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1011 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1012 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1013 status = IXGBE_ERR_SFP_NOT_PRESENT;
1017 status = hw->phy.ops.read_i2c_eeprom(hw,
1018 IXGBE_SFF_IDENTIFIER,
1021 if (status != IXGBE_SUCCESS)
1022 goto err_read_i2c_eeprom;
1024 /* LAN ID is needed for sfp_type determination */
1025 hw->mac.ops.set_lan_id(hw);
1027 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1028 hw->phy.type = ixgbe_phy_sfp_unsupported;
1029 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1031 status = hw->phy.ops.read_i2c_eeprom(hw,
1032 IXGBE_SFF_1GBE_COMP_CODES,
1035 if (status != IXGBE_SUCCESS)
1036 goto err_read_i2c_eeprom;
1038 status = hw->phy.ops.read_i2c_eeprom(hw,
1039 IXGBE_SFF_10GBE_COMP_CODES,
1042 if (status != IXGBE_SUCCESS)
1043 goto err_read_i2c_eeprom;
1044 status = hw->phy.ops.read_i2c_eeprom(hw,
1045 IXGBE_SFF_CABLE_TECHNOLOGY,
1048 if (status != IXGBE_SUCCESS)
1049 goto err_read_i2c_eeprom;
1056 * 3 SFP_DA_CORE0 - 82599-specific
1057 * 4 SFP_DA_CORE1 - 82599-specific
1058 * 5 SFP_SR/LR_CORE0 - 82599-specific
1059 * 6 SFP_SR/LR_CORE1 - 82599-specific
1060 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1061 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1062 * 9 SFP_1g_cu_CORE0 - 82599-specific
1063 * 10 SFP_1g_cu_CORE1 - 82599-specific
1064 * 11 SFP_1g_sx_CORE0 - 82599-specific
1065 * 12 SFP_1g_sx_CORE1 - 82599-specific
1067 if (hw->mac.type == ixgbe_mac_82598EB) {
1068 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1069 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1070 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1071 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1072 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1073 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1075 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1076 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1077 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1078 if (hw->bus.lan_id == 0)
1080 ixgbe_sfp_type_da_cu_core0;
1083 ixgbe_sfp_type_da_cu_core1;
1084 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1085 hw->phy.ops.read_i2c_eeprom(
1086 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1089 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1090 if (hw->bus.lan_id == 0)
1092 ixgbe_sfp_type_da_act_lmt_core0;
1095 ixgbe_sfp_type_da_act_lmt_core1;
1098 ixgbe_sfp_type_unknown;
1100 } else if (comp_codes_10g &
1101 (IXGBE_SFF_10GBASESR_CAPABLE |
1102 IXGBE_SFF_10GBASELR_CAPABLE)) {
1103 if (hw->bus.lan_id == 0)
1105 ixgbe_sfp_type_srlr_core0;
1108 ixgbe_sfp_type_srlr_core1;
1109 #ifdef SUPPORT_10GBASE_ER
1110 } else if (comp_codes_10g &
1111 IXGBE_SFF_10GBASEER_CAPABLE) {
1112 if (hw->bus.lan_id == 0)
1114 ixgbe_sfp_type_er_core0;
1117 ixgbe_sfp_type_er_core1;
1118 #endif /* SUPPORT_10GBASE_ER */
1119 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1120 if (hw->bus.lan_id == 0)
1122 ixgbe_sfp_type_1g_cu_core0;
1125 ixgbe_sfp_type_1g_cu_core1;
1126 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1127 if (hw->bus.lan_id == 0)
1129 ixgbe_sfp_type_1g_sx_core0;
1132 ixgbe_sfp_type_1g_sx_core1;
1133 #ifdef SUPPORT_1000BASE_LX
1134 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1135 if (hw->bus.lan_id == 0)
1137 ixgbe_sfp_type_1g_lx_core0;
1140 ixgbe_sfp_type_1g_lx_core1;
1141 #endif /* SUPPORT_1000BASE_LX */
1143 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1147 if (hw->phy.sfp_type != stored_sfp_type)
1148 hw->phy.sfp_setup_needed = true;
1150 /* Determine if the SFP+ PHY is dual speed or not. */
1151 hw->phy.multispeed_fiber = false;
1152 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1153 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1154 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1155 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1156 hw->phy.multispeed_fiber = true;
1158 /* Determine PHY vendor */
1159 if (hw->phy.type != ixgbe_phy_nl) {
1160 hw->phy.id = identifier;
1161 status = hw->phy.ops.read_i2c_eeprom(hw,
1162 IXGBE_SFF_VENDOR_OUI_BYTE0,
1165 if (status != IXGBE_SUCCESS)
1166 goto err_read_i2c_eeprom;
1168 status = hw->phy.ops.read_i2c_eeprom(hw,
1169 IXGBE_SFF_VENDOR_OUI_BYTE1,
1172 if (status != IXGBE_SUCCESS)
1173 goto err_read_i2c_eeprom;
1175 status = hw->phy.ops.read_i2c_eeprom(hw,
1176 IXGBE_SFF_VENDOR_OUI_BYTE2,
1179 if (status != IXGBE_SUCCESS)
1180 goto err_read_i2c_eeprom;
1183 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1184 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1185 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1187 switch (vendor_oui) {
1188 case IXGBE_SFF_VENDOR_OUI_TYCO:
1189 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1191 ixgbe_phy_sfp_passive_tyco;
1193 case IXGBE_SFF_VENDOR_OUI_FTL:
1194 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1195 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1197 hw->phy.type = ixgbe_phy_sfp_ftl;
1199 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1200 hw->phy.type = ixgbe_phy_sfp_avago;
1202 case IXGBE_SFF_VENDOR_OUI_INTEL:
1203 hw->phy.type = ixgbe_phy_sfp_intel;
1206 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1208 ixgbe_phy_sfp_passive_unknown;
1209 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1211 ixgbe_phy_sfp_active_unknown;
1213 hw->phy.type = ixgbe_phy_sfp_unknown;
1218 /* Allow any DA cable vendor */
1219 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1220 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1221 status = IXGBE_SUCCESS;
1225 /* Verify supported 1G SFP modules */
1226 if (comp_codes_10g == 0 &&
1227 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1228 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1229 #ifdef SUPPORT_1000BASE_LX
1230 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1231 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1233 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1234 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1235 hw->phy.type = ixgbe_phy_sfp_unsupported;
1236 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1240 /* Anything else 82598-based is supported */
1241 if (hw->mac.type == ixgbe_mac_82598EB) {
1242 status = IXGBE_SUCCESS;
1246 ixgbe_get_device_caps(hw, &enforce_sfp);
1247 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1248 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1249 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1250 #ifdef SUPPORT_1000BASE_LX
1251 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1252 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1254 #ifdef SUPPORT_10GBASE_ER
1255 hw->phy.sfp_type == ixgbe_sfp_type_er_core0 ||
1256 hw->phy.sfp_type == ixgbe_sfp_type_er_core1 ||
1258 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1259 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1260 /* Make sure we're a supported PHY type */
1261 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1262 status = IXGBE_SUCCESS;
1264 if (hw->allow_unsupported_sfp == true) {
1265 EWARN(hw, "WARNING: Intel (R) Network "
1266 "Connections are quality tested "
1267 "using Intel (R) Ethernet Optics."
1268 " Using untested modules is not "
1269 "supported and may cause unstable"
1270 " operation or damage to the "
1271 "module or the adapter. Intel "
1272 "Corporation is not responsible "
1273 "for any harm caused by using "
1274 "untested modules.\n", status);
1275 status = IXGBE_SUCCESS;
1277 DEBUGOUT("SFP+ module not supported\n");
1279 ixgbe_phy_sfp_unsupported;
1280 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1284 status = IXGBE_SUCCESS;
1291 err_read_i2c_eeprom:
1292 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1293 if (hw->phy.type != ixgbe_phy_nl) {
1295 hw->phy.type = ixgbe_phy_unknown;
1297 return IXGBE_ERR_SFP_NOT_PRESENT;
1303 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1304 * @hw: pointer to hardware structure
1305 * @list_offset: offset to the SFP ID list
1306 * @data_offset: offset to the SFP data block
1308 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1309 * so it returns the offsets to the phy init sequence block.
1311 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1316 u16 sfp_type = hw->phy.sfp_type;
1318 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1320 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1321 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1323 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1324 return IXGBE_ERR_SFP_NOT_PRESENT;
1326 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1327 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1328 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1331 * Limiting active cables and 1G Phys must be initialized as
1334 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1335 #ifdef SUPPORT_10GBASE_ER
1336 sfp_type == ixgbe_sfp_type_er_core0 ||
1337 #endif /* SUPPORT_10GBASE_ER */
1338 #ifdef SUPPORT_1000BASE_LX
1339 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1340 #endif /* SUPPORT_1000BASE_LX */
1341 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1342 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1343 sfp_type = ixgbe_sfp_type_srlr_core0;
1344 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1345 #ifdef SUPPORT_10GBASE_ER
1346 sfp_type == ixgbe_sfp_type_er_core1 ||
1347 #endif /* SUPPORT_10GBASE_ER */
1348 #ifdef SUPPORT_1000BASE_LX
1349 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1350 #endif /* SUPPORT_1000BASE_LX */
1351 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1352 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1353 sfp_type = ixgbe_sfp_type_srlr_core1;
1355 /* Read offset to PHY init contents */
1356 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1357 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1358 "eeprom read at offset %d failed",
1359 IXGBE_PHY_INIT_OFFSET_NL);
1360 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1363 if ((!*list_offset) || (*list_offset == 0xFFFF))
1364 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1366 /* Shift offset to first ID word */
1370 * Find the matching SFP ID in the EEPROM
1371 * and program the init sequence
1373 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1376 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1377 if (sfp_id == sfp_type) {
1379 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1381 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1382 DEBUGOUT("SFP+ module not supported\n");
1383 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1388 (*list_offset) += 2;
1389 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1394 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1395 DEBUGOUT("No matching SFP+ module found\n");
1396 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1399 return IXGBE_SUCCESS;
1402 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1403 "eeprom read at offset %d failed", *list_offset);
1404 return IXGBE_ERR_PHY;
1408 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1409 * @hw: pointer to hardware structure
1410 * @byte_offset: EEPROM byte offset to read
1411 * @eeprom_data: value read
1413 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1415 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1418 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1420 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1421 IXGBE_I2C_EEPROM_DEV_ADDR,
1426 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1427 * @hw: pointer to hardware structure
1428 * @byte_offset: byte offset at address 0xA2
1429 * @eeprom_data: value read
1431 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1433 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1436 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1437 IXGBE_I2C_EEPROM_DEV_ADDR2,
1442 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1443 * @hw: pointer to hardware structure
1444 * @byte_offset: EEPROM byte offset to write
1445 * @eeprom_data: value to write
1447 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1449 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1452 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1454 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1455 IXGBE_I2C_EEPROM_DEV_ADDR,
1460 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1461 * @hw: pointer to hardware structure
1462 * @byte_offset: byte offset to read
1465 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1466 * a specified device address.
1468 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1469 u8 dev_addr, u8 *data)
1474 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1478 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1481 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1482 return IXGBE_ERR_SWFW_SYNC;
1484 ixgbe_i2c_start(hw);
1486 /* Device Address and write indication */
1487 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1488 if (status != IXGBE_SUCCESS)
1491 status = ixgbe_get_i2c_ack(hw);
1492 if (status != IXGBE_SUCCESS)
1495 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1496 if (status != IXGBE_SUCCESS)
1499 status = ixgbe_get_i2c_ack(hw);
1500 if (status != IXGBE_SUCCESS)
1503 ixgbe_i2c_start(hw);
1505 /* Device Address and read indication */
1506 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1507 if (status != IXGBE_SUCCESS)
1510 status = ixgbe_get_i2c_ack(hw);
1511 if (status != IXGBE_SUCCESS)
1514 status = ixgbe_clock_in_i2c_byte(hw, data);
1515 if (status != IXGBE_SUCCESS)
1518 status = ixgbe_clock_out_i2c_bit(hw, nack);
1519 if (status != IXGBE_SUCCESS)
1523 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1524 return IXGBE_SUCCESS;
1527 ixgbe_i2c_bus_clear(hw);
1528 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1531 if (retry < max_retry)
1532 DEBUGOUT("I2C byte read error - Retrying.\n");
1534 DEBUGOUT("I2C byte read error.\n");
1536 } while (retry < max_retry);
1542 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1543 * @hw: pointer to hardware structure
1544 * @byte_offset: byte offset to write
1545 * @data: value to write
1547 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1548 * a specified device address.
1550 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1551 u8 dev_addr, u8 data)
1553 s32 status = IXGBE_SUCCESS;
1556 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1558 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1560 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1561 status = IXGBE_ERR_SWFW_SYNC;
1562 goto write_byte_out;
1566 ixgbe_i2c_start(hw);
1568 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1569 if (status != IXGBE_SUCCESS)
1572 status = ixgbe_get_i2c_ack(hw);
1573 if (status != IXGBE_SUCCESS)
1576 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1577 if (status != IXGBE_SUCCESS)
1580 status = ixgbe_get_i2c_ack(hw);
1581 if (status != IXGBE_SUCCESS)
1584 status = ixgbe_clock_out_i2c_byte(hw, data);
1585 if (status != IXGBE_SUCCESS)
1588 status = ixgbe_get_i2c_ack(hw);
1589 if (status != IXGBE_SUCCESS)
1593 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1594 return IXGBE_SUCCESS;
1597 ixgbe_i2c_bus_clear(hw);
1599 if (retry < max_retry)
1600 DEBUGOUT("I2C byte write error - Retrying.\n");
1602 DEBUGOUT("I2C byte write error.\n");
1603 } while (retry < max_retry);
1605 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1612 * ixgbe_i2c_start - Sets I2C start condition
1613 * @hw: pointer to hardware structure
1615 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1617 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
1619 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1621 DEBUGFUNC("ixgbe_i2c_start");
1623 /* Start condition must begin with data and clock high */
1624 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1625 ixgbe_raise_i2c_clk(hw, &i2cctl);
1627 /* Setup time for start condition (4.7us) */
1628 usec_delay(IXGBE_I2C_T_SU_STA);
1630 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1632 /* Hold time for start condition (4us) */
1633 usec_delay(IXGBE_I2C_T_HD_STA);
1635 ixgbe_lower_i2c_clk(hw, &i2cctl);
1637 /* Minimum low period of clock is 4.7 us */
1638 usec_delay(IXGBE_I2C_T_LOW);
1643 * ixgbe_i2c_stop - Sets I2C stop condition
1644 * @hw: pointer to hardware structure
1646 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1648 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1650 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1652 DEBUGFUNC("ixgbe_i2c_stop");
1654 /* Stop condition must begin with data low and clock high */
1655 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1656 ixgbe_raise_i2c_clk(hw, &i2cctl);
1658 /* Setup time for stop condition (4us) */
1659 usec_delay(IXGBE_I2C_T_SU_STO);
1661 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1663 /* bus free time between stop and start (4.7us)*/
1664 usec_delay(IXGBE_I2C_T_BUF);
1668 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1669 * @hw: pointer to hardware structure
1670 * @data: data byte to clock in
1672 * Clocks in one byte data via I2C data/clock
1674 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1679 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1681 for (i = 7; i >= 0; i--) {
1682 ixgbe_clock_in_i2c_bit(hw, &bit);
1686 return IXGBE_SUCCESS;
1690 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1691 * @hw: pointer to hardware structure
1692 * @data: data byte clocked out
1694 * Clocks out one byte data via I2C data/clock
1696 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1698 s32 status = IXGBE_SUCCESS;
1703 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1705 for (i = 7; i >= 0; i--) {
1706 bit = (data >> i) & 0x1;
1707 status = ixgbe_clock_out_i2c_bit(hw, bit);
1709 if (status != IXGBE_SUCCESS)
1713 /* Release SDA line (set high) */
1714 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1715 i2cctl |= IXGBE_I2C_DATA_OUT;
1716 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1717 IXGBE_WRITE_FLUSH(hw);
1723 * ixgbe_get_i2c_ack - Polls for I2C ACK
1724 * @hw: pointer to hardware structure
1726 * Clocks in/out one bit via I2C data/clock
1728 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1730 s32 status = IXGBE_SUCCESS;
1732 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1736 DEBUGFUNC("ixgbe_get_i2c_ack");
1738 ixgbe_raise_i2c_clk(hw, &i2cctl);
1741 /* Minimum high period of clock is 4us */
1742 usec_delay(IXGBE_I2C_T_HIGH);
1744 /* Poll for ACK. Note that ACK in I2C spec is
1745 * transition from 1 to 0 */
1746 for (i = 0; i < timeout; i++) {
1747 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1748 ack = ixgbe_get_i2c_data(&i2cctl);
1756 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1757 "I2C ack was not received.\n");
1758 status = IXGBE_ERR_I2C;
1761 ixgbe_lower_i2c_clk(hw, &i2cctl);
1763 /* Minimum low period of clock is 4.7 us */
1764 usec_delay(IXGBE_I2C_T_LOW);
1770 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1771 * @hw: pointer to hardware structure
1772 * @data: read data value
1774 * Clocks in one bit via I2C data/clock
1776 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1778 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1780 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1782 ixgbe_raise_i2c_clk(hw, &i2cctl);
1784 /* Minimum high period of clock is 4us */
1785 usec_delay(IXGBE_I2C_T_HIGH);
1787 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1788 *data = ixgbe_get_i2c_data(&i2cctl);
1790 ixgbe_lower_i2c_clk(hw, &i2cctl);
1792 /* Minimum low period of clock is 4.7 us */
1793 usec_delay(IXGBE_I2C_T_LOW);
1795 return IXGBE_SUCCESS;
1799 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1800 * @hw: pointer to hardware structure
1801 * @data: data value to write
1803 * Clocks out one bit via I2C data/clock
1805 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1808 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1810 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1812 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1813 if (status == IXGBE_SUCCESS) {
1814 ixgbe_raise_i2c_clk(hw, &i2cctl);
1816 /* Minimum high period of clock is 4us */
1817 usec_delay(IXGBE_I2C_T_HIGH);
1819 ixgbe_lower_i2c_clk(hw, &i2cctl);
1821 /* Minimum low period of clock is 4.7 us.
1822 * This also takes care of the data hold time.
1824 usec_delay(IXGBE_I2C_T_LOW);
1826 status = IXGBE_ERR_I2C;
1827 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1828 "I2C data was not set to %X\n", data);
1835 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1836 * @hw: pointer to hardware structure
1837 * @i2cctl: Current value of I2CCTL register
1839 * Raises the I2C clock line '0'->'1'
1841 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1844 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1847 DEBUGFUNC("ixgbe_raise_i2c_clk");
1849 for (i = 0; i < timeout; i++) {
1850 *i2cctl |= IXGBE_I2C_CLK_OUT;
1852 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1853 IXGBE_WRITE_FLUSH(hw);
1854 /* SCL rise time (1000ns) */
1855 usec_delay(IXGBE_I2C_T_RISE);
1857 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1858 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1864 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1865 * @hw: pointer to hardware structure
1866 * @i2cctl: Current value of I2CCTL register
1868 * Lowers the I2C clock line '1'->'0'
1870 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1873 DEBUGFUNC("ixgbe_lower_i2c_clk");
1875 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1877 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1878 IXGBE_WRITE_FLUSH(hw);
1880 /* SCL fall time (300ns) */
1881 usec_delay(IXGBE_I2C_T_FALL);
1885 * ixgbe_set_i2c_data - Sets the I2C data bit
1886 * @hw: pointer to hardware structure
1887 * @i2cctl: Current value of I2CCTL register
1888 * @data: I2C data value (0 or 1) to set
1890 * Sets the I2C data bit
1892 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1894 s32 status = IXGBE_SUCCESS;
1896 DEBUGFUNC("ixgbe_set_i2c_data");
1899 *i2cctl |= IXGBE_I2C_DATA_OUT;
1901 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1903 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1904 IXGBE_WRITE_FLUSH(hw);
1906 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1907 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1909 /* Verify data was set correctly */
1910 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1911 if (data != ixgbe_get_i2c_data(i2cctl)) {
1912 status = IXGBE_ERR_I2C;
1913 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1914 "Error - I2C data was not set to %X.\n",
1922 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1923 * @hw: pointer to hardware structure
1924 * @i2cctl: Current value of I2CCTL register
1926 * Returns the I2C data bit value
1928 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
1932 DEBUGFUNC("ixgbe_get_i2c_data");
1934 if (*i2cctl & IXGBE_I2C_DATA_IN)
1943 * ixgbe_i2c_bus_clear - Clears the I2C bus
1944 * @hw: pointer to hardware structure
1946 * Clears the I2C bus by sending nine clock pulses.
1947 * Used when data line is stuck low.
1949 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1951 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1954 DEBUGFUNC("ixgbe_i2c_bus_clear");
1956 ixgbe_i2c_start(hw);
1958 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1960 for (i = 0; i < 9; i++) {
1961 ixgbe_raise_i2c_clk(hw, &i2cctl);
1963 /* Min high period of clock is 4us */
1964 usec_delay(IXGBE_I2C_T_HIGH);
1966 ixgbe_lower_i2c_clk(hw, &i2cctl);
1968 /* Min low period of clock is 4.7us*/
1969 usec_delay(IXGBE_I2C_T_LOW);
1972 ixgbe_i2c_start(hw);
1974 /* Put the i2c bus back to default state */
1979 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1980 * @hw: pointer to hardware structure
1982 * Checks if the LASI temp alarm status was triggered due to overtemp
1984 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1986 s32 status = IXGBE_SUCCESS;
1989 DEBUGFUNC("ixgbe_tn_check_overtemp");
1991 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1994 /* Check that the LASI temp alarm status was triggered */
1995 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1996 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1998 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2001 status = IXGBE_ERR_OVERTEMP;
2002 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");