lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37 #ident "$Id: ixgbe_phy.c,v 1.139 2012/05/24 23:36:12 jtkirshe Exp $"
  38
  39 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
  50
  51 /**
  52  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  53  *  @hw: pointer to the hardware structure
  54  *
  55  *  Initialize the function pointers.
  56  **/
  57 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  58 {
  59         struct ixgbe_phy_info *phy = &hw->phy;
  60
  61         DEBUGFUNC("ixgbe_init_phy_ops_generic");
  62
  63         /* PHY */
  64         phy->ops.identify = &ixgbe_identify_phy_generic;
  65         phy->ops.reset = &ixgbe_reset_phy_generic;
  66         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  67         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  68         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  69         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  70         phy->ops.check_link = NULL;
  71         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  72         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  73         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  74         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  75         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  76         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  77         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  78         phy->sfp_type = ixgbe_sfp_type_unknown;
  79         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  80         return IXGBE_SUCCESS;
  81 }
  82
  83 /**
  84  *  ixgbe_identify_phy_generic - Get physical layer module
  85  *  @hw: pointer to hardware structure
  86  *
  87  *  Determines the physical layer module found on the current adapter.
  88  **/
  89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  90 {
  91         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  92         u32 phy_addr;
  93         u16 ext_ability = 0;
  94
  95         DEBUGFUNC("ixgbe_identify_phy_generic");
  96
  97         if (hw->phy.type == ixgbe_phy_unknown) {
  98                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  99                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 100                                 hw->phy.addr = phy_addr;
 101                                 ixgbe_get_phy_id(hw);
 102                                 hw->phy.type =
 103                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 104
 105                                 if (hw->phy.type == ixgbe_phy_unknown) {
 106                                         hw->phy.ops.read_reg(hw,
 107                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 108                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 109                                                   &ext_ability);
 110                                         if (ext_ability &
 111                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 112                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 113                                                 hw->phy.type =
 114                                                          ixgbe_phy_cu_unknown;
 115                                         else
 116                                                 hw->phy.type =
 117                                                          ixgbe_phy_generic;
 118                                 }
 119
 120                                 status = IXGBE_SUCCESS;
 121                                 break;
 122                         }
 123                 }
 124
 125                 /* Certain media types do not have a phy so an address will not
 126                  * be found and the code will take this path.  Caller has to
 127                  * decide if it is an error or not.
 128                  */
 129                 if (status != IXGBE_SUCCESS) {
 130                         hw->phy.addr = 0;
 131                 }
 132         } else {
 133                 status = IXGBE_SUCCESS;
 134         }
 135
 136         return status;
 137 }
 138
 139 /**
 140  *  ixgbe_validate_phy_addr - Determines phy address is valid
 141  *  @hw: pointer to hardware structure
 142  *
 143  **/
 144 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 145 {
 146         u16 phy_id = 0;
 147         bool valid = false;
 148
 149         DEBUGFUNC("ixgbe_validate_phy_addr");
 150
 151         hw->phy.addr = phy_addr;
 152         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 153                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 154
 155         if (phy_id != 0xFFFF && phy_id != 0x0)
 156                 valid = true;
 157
 158         return valid;
 159 }
 160
 161 /**
 162  *  ixgbe_get_phy_id - Get the phy type
 163  *  @hw: pointer to hardware structure
 164  *
 165  **/
 166 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 167 {
 168         u32 status;
 169         u16 phy_id_high = 0;
 170         u16 phy_id_low = 0;
 171
 172         DEBUGFUNC("ixgbe_get_phy_id");
 173
 174         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 175                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 176                                       &phy_id_high);
 177
 178         if (status == IXGBE_SUCCESS) {
 179                 hw->phy.id = (u32)(phy_id_high << 16);
 180                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 181                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 182                                               &phy_id_low);
 183                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 184                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 185         }
 186         return status;
 187 }
 188
 189 /**
 190  *  ixgbe_get_phy_type_from_id - Get the phy type
 191  *  @hw: pointer to hardware structure
 192  *
 193  **/
 194 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 195 {
 196         enum ixgbe_phy_type phy_type;
 197
 198         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 199
 200         switch (phy_id) {
 201         case TN1010_PHY_ID:
 202                 phy_type = ixgbe_phy_tn;
 203                 break;
 204         case X540_PHY_ID:
 205                 phy_type = ixgbe_phy_aq;
 206                 break;
 207         case QT2022_PHY_ID:
 208                 phy_type = ixgbe_phy_qt;
 209                 break;
 210         case ATH_PHY_ID:
 211                 phy_type = ixgbe_phy_nl;
 212                 break;
 213         default:
 214                 phy_type = ixgbe_phy_unknown;
 215                 break;
 216         }
 217
 218         DEBUGOUT1("phy type found is %d\n", phy_type);
 219         return phy_type;
 220 }
 221
 222 /**
 223  *  ixgbe_reset_phy_generic - Performs a PHY reset
 224  *  @hw: pointer to hardware structure
 225  **/
 226 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 227 {
 228         u32 i;
 229         u16 ctrl = 0;
 230         s32 status = IXGBE_SUCCESS;
 231
 232         DEBUGFUNC("ixgbe_reset_phy_generic");
 233
 234         if (hw->phy.type == ixgbe_phy_unknown)
 235                 status = ixgbe_identify_phy_generic(hw);
 236
 237         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 238                 goto out;
 239
 240         /* Don't reset PHY if it's shut down due to overtemp. */
 241         if (!hw->phy.reset_if_overtemp &&
 242             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 243                 goto out;
 244
 245         /*
 246          * Perform soft PHY reset to the PHY_XS.
 247          * This will cause a soft reset to the PHY
 248          */
 249         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 250                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 251                               IXGBE_MDIO_PHY_XS_RESET);
 252
 253         /*
 254          * Poll for reset bit to self-clear indicating reset is complete.
 255          * Some PHYs could take up to 3 seconds to complete and need about
 256          * 1.7 usec delay after the reset is complete.
 257          */
 258         for (i = 0; i < 30; i++) {
 259                 msec_delay(100);
 260                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 261                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 262                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 263                         usec_delay(2);
 264                         break;
 265                 }
 266         }
 267
 268         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 269                 status = IXGBE_ERR_RESET_FAILED;
 270                 DEBUGOUT("PHY reset polling failed to complete.\n");
 271         }
 272
 273 out:
 274         return status;
 275 }
 276
 277 /**
 278  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 279  *  @hw: pointer to hardware structure
 280  *  @reg_addr: 32 bit address of PHY register to read
 281  *  @phy_data: Pointer to read data from PHY register
 282  **/
 283 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 284                                u32 device_type, u16 *phy_data)
 285 {
 286         u32 command;
 287         u32 i;
 288         u32 data;
 289         s32 status = IXGBE_SUCCESS;
 290         u16 gssr;
 291
 292         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 293
 294         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 295                 gssr = IXGBE_GSSR_PHY1_SM;
 296         else
 297                 gssr = IXGBE_GSSR_PHY0_SM;
 298
 299         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
 300                 status = IXGBE_ERR_SWFW_SYNC;
 301
 302         if (status == IXGBE_SUCCESS) {
 303                 /* Setup and write the address cycle command */
 304                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 305                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 306                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 307                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 308
 309                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 310
 311                 /*
 312                  * Check every 10 usec to see if the address cycle completed.
 313                  * The MDI Command bit will clear when the operation is
 314                  * complete
 315                  */
 316                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 317                         usec_delay(10);
 318
 319                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 320
 321                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 322                                 break;
 323                 }
 324
 325                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 326                         DEBUGOUT("PHY address command did not complete.\n");
 327                         status = IXGBE_ERR_PHY;
 328                 }
 329
 330                 if (status == IXGBE_SUCCESS) {
 331                         /*
 332                          * Address cycle complete, setup and write the read
 333                          * command
 334                          */
 335                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 336                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 337                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 338                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 339
 340                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 341
 342                         /*
 343                          * Check every 10 usec to see if the address cycle
 344                          * completed. The MDI Command bit will clear when the
 345                          * operation is complete
 346                          */
 347                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 348                                 usec_delay(10);
 349
 350                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 351
 352                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 353                                         break;
 354                         }
 355
 356                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 357                                 DEBUGOUT("PHY read command didn't complete\n");
 358                                 status = IXGBE_ERR_PHY;
 359                         } else {
 360                                 /*
 361                                  * Read operation is complete.  Get the data
 362                                  * from MSRWD
 363                                  */
 364                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 365                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 366                                 *phy_data = (u16)(data);
 367                         }
 368                 }
 369
 370                 hw->mac.ops.release_swfw_sync(hw, gssr);
 371         }
 372
 373         return status;
 374 }
 375
 376 /**
 377  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 378  *  @hw: pointer to hardware structure
 379  *  @reg_addr: 32 bit PHY register to write
 380  *  @device_type: 5 bit device type
 381  *  @phy_data: Data to write to the PHY register
 382  **/
 383 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 384                                 u32 device_type, u16 phy_data)
 385 {
 386         u32 command;
 387         u32 i;
 388         s32 status = IXGBE_SUCCESS;
 389         u16 gssr;
 390
 391         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 392
 393         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 394                 gssr = IXGBE_GSSR_PHY1_SM;
 395         else
 396                 gssr = IXGBE_GSSR_PHY0_SM;
 397
 398         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
 399                 status = IXGBE_ERR_SWFW_SYNC;
 400
 401         if (status == IXGBE_SUCCESS) {
 402                 /* Put the data in the MDI single read and write data register*/
 403                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 404
 405                 /* Setup and write the address cycle command */
 406                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 407                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 408                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 409                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 410
 411                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 412
 413                 /*
 414                  * Check every 10 usec to see if the address cycle completed.
 415                  * The MDI Command bit will clear when the operation is
 416                  * complete
 417                  */
 418                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 419                         usec_delay(10);
 420
 421                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 422
 423                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 424                                 break;
 425                 }
 426
 427                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 428                         DEBUGOUT("PHY address cmd didn't complete\n");
 429                         status = IXGBE_ERR_PHY;
 430                 }
 431
 432                 if (status == IXGBE_SUCCESS) {
 433                         /*
 434                          * Address cycle complete, setup and write the write
 435                          * command
 436                          */
 437                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 438                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 439                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 440                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 441
 442                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 443
 444                         /*
 445                          * Check every 10 usec to see if the address cycle
 446                          * completed. The MDI Command bit will clear when the
 447                          * operation is complete
 448                          */
 449                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 450                                 usec_delay(10);
 451
 452                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 453
 454                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 455                                         break;
 456                         }
 457
 458                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 459                                 DEBUGOUT("PHY address cmd didn't complete\n");
 460                                 status = IXGBE_ERR_PHY;
 461                         }
 462                 }
 463
 464                 hw->mac.ops.release_swfw_sync(hw, gssr);
 465         }
 466
 467         return status;
 468 }
 469
 470 /**
 471  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 472  *  @hw: pointer to hardware structure
 473  *
 474  *  Restart autonegotiation and PHY and waits for completion.
 475  **/
 476 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 477 {
 478         s32 status = IXGBE_SUCCESS;
 479         u32 time_out;
 480         u32 max_time_out = 10;
 481         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 482         bool autoneg = false;
 483         ixgbe_link_speed speed;
 484
 485         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 486
 487         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 488
 489         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 490                 /* Set or unset auto-negotiation 10G advertisement */
 491                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 492                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 493                                      &autoneg_reg);
 494
 495                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 496                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 497                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 498
 499                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 500                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 501                                       autoneg_reg);
 502         }
 503
 504         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 505                 /* Set or unset auto-negotiation 1G advertisement */
 506                 hw->phy.ops.read_reg(hw,
 507                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 508                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 509                                      &autoneg_reg);
 510
 511                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 512                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 513                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 514
 515                 hw->phy.ops.write_reg(hw,
 516                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 517                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 518                                       autoneg_reg);
 519         }
 520
 521         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 522                 /* Set or unset auto-negotiation 100M advertisement */
 523                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 524                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 525                                      &autoneg_reg);
 526
 527                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 528                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 529                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 530                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 531
 532                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 533                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 534                                       autoneg_reg);
 535         }
 536
 537         /* Restart PHY autonegotiation and wait for completion */
 538         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 539                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 540
 541         autoneg_reg |= IXGBE_MII_RESTART;
 542
 543         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 544                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 545
 546         /* Wait for autonegotiation to finish */
 547         for (time_out = 0; time_out < max_time_out; time_out++) {
 548                 usec_delay(10);
 549                 /* Restart PHY autonegotiation and wait for completion */
 550                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 551                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 552                                               &autoneg_reg);
 553
 554                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 555                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 556                         break;
 557         }
 558
 559         if (time_out == max_time_out) {
 560                 status = IXGBE_ERR_LINK_SETUP;
 561                 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
 562         }
 563
 564         return status;
 565 }
 566
 567 /**
 568  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 569  *  @hw: pointer to hardware structure
 570  *  @speed: new link speed
 571  *  @autoneg: true if autonegotiation enabled
 572  **/
 573 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 574                                        ixgbe_link_speed speed,
 575                                        bool autoneg,
 576                                        bool autoneg_wait_to_complete)
 577 {
 578         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 579
 580         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 581
 582         /*
 583          * Clear autoneg_advertised and set new values based on input link
 584          * speed.
 585          */
 586         hw->phy.autoneg_advertised = 0;
 587
 588         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 589                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 590
 591         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 592                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 593
 594         if (speed & IXGBE_LINK_SPEED_100_FULL)
 595                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 596
 597         /* Setup link based on the new speed settings */
 598         hw->phy.ops.setup_link(hw);
 599
 600         return IXGBE_SUCCESS;
 601 }
 602
 603 /**
 604  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 605  *  @hw: pointer to hardware structure
 606  *  @speed: pointer to link speed
 607  *  @autoneg: boolean auto-negotiation value
 608  *
 609  *  Determines the link capabilities by reading the AUTOC register.
 610  **/
 611 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 612                                                ixgbe_link_speed *speed,
 613                                                bool *autoneg)
 614 {
 615         s32 status;
 616         u16 speed_ability;
 617
 618         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 619
 620         *speed = 0;
 621         *autoneg = true;
 622
 623         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 624                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 625                                       &speed_ability);
 626
 627         if (status == IXGBE_SUCCESS) {
 628                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 629                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 630                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 631                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 632                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 633                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 634         }
 635
 636         return status;
 637 }
 638
 639 /**
 640  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 641  *  @hw: pointer to hardware structure
 642  *
 643  *  Reads the VS1 register to determine if link is up and the current speed for
 644  *  the PHY.
 645  **/
 646 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 647                              bool *link_up)
 648 {
 649         s32 status = IXGBE_SUCCESS;
 650         u32 time_out;
 651         u32 max_time_out = 10;
 652         u16 phy_link = 0;
 653         u16 phy_speed = 0;
 654         u16 phy_data = 0;
 655
 656         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 657
 658         /* Initialize speed and link to default case */
 659         *link_up = false;
 660         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 661
 662         /*
 663          * Check current speed and link status of the PHY register.
 664          * This is a vendor specific register and may have to
 665          * be changed for other copper PHYs.
 666          */
 667         for (time_out = 0; time_out < max_time_out; time_out++) {
 668                 usec_delay(10);
 669                 status = hw->phy.ops.read_reg(hw,
 670                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 671                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 672                                         &phy_data);
 673                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 674                 phy_speed = phy_data &
 675                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 676                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 677                         *link_up = true;
 678                         if (phy_speed ==
 679                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 680                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 681                         break;
 682                 }
 683         }
 684
 685         return status;
 686 }
 687
 688 /**
 689  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 690  *      @hw: pointer to hardware structure
 691  *
 692  *      Restart autonegotiation and PHY and waits for completion.
 693  **/
 694 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 695 {
 696         s32 status = IXGBE_SUCCESS;
 697         u32 time_out;
 698         u32 max_time_out = 10;
 699         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 700         bool autoneg = false;
 701         ixgbe_link_speed speed;
 702
 703         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 704
 705         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 706
 707         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 708                 /* Set or unset auto-negotiation 10G advertisement */
 709                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 710                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 711                                      &autoneg_reg);
 712
 713                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 714                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 715                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 716
 717                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 718                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 719                                       autoneg_reg);
 720         }
 721
 722         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 723                 /* Set or unset auto-negotiation 1G advertisement */
 724                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 725                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 726                                      &autoneg_reg);
 727
 728                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 729                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 730                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 731
 732                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 733                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 734                                       autoneg_reg);
 735         }
 736
 737         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 738                 /* Set or unset auto-negotiation 100M advertisement */
 739                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 740                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 741                                      &autoneg_reg);
 742
 743                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 744                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 745                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 746
 747                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 748                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 749                                       autoneg_reg);
 750         }
 751
 752         /* Restart PHY autonegotiation and wait for completion */
 753         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 754                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 755
 756         autoneg_reg |= IXGBE_MII_RESTART;
 757
 758         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 759                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 760
 761         /* Wait for autonegotiation to finish */
 762         for (time_out = 0; time_out < max_time_out; time_out++) {
 763                 usec_delay(10);
 764                 /* Restart PHY autonegotiation and wait for completion */
 765                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 766                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 767                                               &autoneg_reg);
 768
 769                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 770                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 771                         break;
 772         }
 773
 774         if (time_out == max_time_out) {
 775                 status = IXGBE_ERR_LINK_SETUP;
 776                 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
 777         }
 778
 779         return status;
 780 }
 781
 782 /**
 783  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 784  *  @hw: pointer to hardware structure
 785  *  @firmware_version: pointer to the PHY Firmware Version
 786  **/
 787 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 788                                        u16 *firmware_version)
 789 {
 790         s32 status;
 791
 792         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 793
 794         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 795                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 796                                       firmware_version);
 797
 798         return status;
 799 }
 800
 801 /**
 802  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 803  *  @hw: pointer to hardware structure
 804  *  @firmware_version: pointer to the PHY Firmware Version
 805  **/
 806 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 807                                            u16 *firmware_version)
 808 {
 809         s32 status;
 810
 811         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 812
 813         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 814                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 815                                       firmware_version);
 816
 817         return status;
 818 }
 819
 820 /**
 821  *  ixgbe_reset_phy_nl - Performs a PHY reset
 822  *  @hw: pointer to hardware structure
 823  **/
 824 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 825 {
 826         u16 phy_offset, control, eword, edata, block_crc;
 827         bool end_data = false;
 828         u16 list_offset, data_offset;
 829         u16 phy_data = 0;
 830         s32 ret_val = IXGBE_SUCCESS;
 831         u32 i;
 832
 833         DEBUGFUNC("ixgbe_reset_phy_nl");
 834
 835         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 836                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 837
 838         /* reset the PHY and poll for completion */
 839         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 840                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 841                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 842
 843         for (i = 0; i < 100; i++) {
 844                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 845                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 846                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 847                         break;
 848                 msec_delay(10);
 849         }
 850
 851         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 852                 DEBUGOUT("PHY reset did not complete.\n");
 853                 ret_val = IXGBE_ERR_PHY;
 854                 goto out;
 855         }
 856
 857         /* Get init offsets */
 858         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 859                                                       &data_offset);
 860         if (ret_val != IXGBE_SUCCESS)
 861                 goto out;
 862
 863         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 864         data_offset++;
 865         while (!end_data) {
 866                 /*
 867                  * Read control word from PHY init contents offset
 868                  */
 869                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 870                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 871                            IXGBE_CONTROL_SHIFT_NL;
 872                 edata = eword & IXGBE_DATA_MASK_NL;
 873                 switch (control) {
 874                 case IXGBE_DELAY_NL:
 875                         data_offset++;
 876                         DEBUGOUT1("DELAY: %d MS\n", edata);
 877                         msec_delay(edata);
 878                         break;
 879                 case IXGBE_DATA_NL:
 880                         DEBUGOUT("DATA:\n");
 881                         data_offset++;
 882                         hw->eeprom.ops.read(hw, data_offset++,
 883                                             &phy_offset);
 884                         for (i = 0; i < edata; i++) {
 885                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 886                                 hw->phy.ops.write_reg(hw, phy_offset,
 887                                                       IXGBE_TWINAX_DEV, eword);
 888                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
 889                                           phy_offset);
 890                                 data_offset++;
 891                                 phy_offset++;
 892                         }
 893                         break;
 894                 case IXGBE_CONTROL_NL:
 895                         data_offset++;
 896                         DEBUGOUT("CONTROL:\n");
 897                         if (edata == IXGBE_CONTROL_EOL_NL) {
 898                                 DEBUGOUT("EOL\n");
 899                                 end_data = true;
 900                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 901                                 DEBUGOUT("SOL\n");
 902                         } else {
 903                                 DEBUGOUT("Bad control value\n");
 904                                 ret_val = IXGBE_ERR_PHY;
 905                                 goto out;
 906                         }
 907                         break;
 908                 default:
 909                         DEBUGOUT("Bad control type\n");
 910                         ret_val = IXGBE_ERR_PHY;
 911                         goto out;
 912                 }
 913         }
 914
 915 out:
 916         return ret_val;
 917 }
 918
 919 /**
 920  *  ixgbe_identify_module_generic - Identifies module type
 921  *  @hw: pointer to hardware structure
 922  *
 923  *  Determines HW type and calls appropriate function.
 924  **/
 925 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 926 {
 927         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 928
 929         DEBUGFUNC("ixgbe_identify_module_generic");
 930
 931         switch (hw->mac.ops.get_media_type(hw)) {
 932         case ixgbe_media_type_fiber:
 933                 status = ixgbe_identify_sfp_module_generic(hw);
 934                 break;
 935
 936
 937         default:
 938                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 939                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 940                 break;
 941         }
 942
 943         return status;
 944 }
 945
 946 /**
 947  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 948  *  @hw: pointer to hardware structure
 949  *
 950  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 951  **/
 952 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 953 {
 954         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 955         u32 vendor_oui = 0;
 956         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 957         u8 identifier = 0;
 958         u8 comp_codes_1g = 0;
 959         u8 comp_codes_10g = 0;
 960         u8 oui_bytes[3] = {0, 0, 0};
 961         u8 cable_tech = 0;
 962         u8 cable_spec = 0;
 963         u16 enforce_sfp = 0;
 964
 965         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
 966
 967         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 968                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 969                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 970                 goto out;
 971         }
 972
 973         status = hw->phy.ops.read_i2c_eeprom(hw,
 974                                              IXGBE_SFF_IDENTIFIER,
 975                                              &identifier);
 976
 977         if (status == IXGBE_ERR_SWFW_SYNC ||
 978             status == IXGBE_ERR_I2C ||
 979             status == IXGBE_ERR_SFP_NOT_PRESENT)
 980                 goto err_read_i2c_eeprom;
 981
 982         /* LAN ID is needed for sfp_type determination */
 983         hw->mac.ops.set_lan_id(hw);
 984
 985         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 986                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 987                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 988         } else {
 989                 status = hw->phy.ops.read_i2c_eeprom(hw,
 990                                                      IXGBE_SFF_1GBE_COMP_CODES,
 991                                                      &comp_codes_1g);
 992
 993                 if (status == IXGBE_ERR_SWFW_SYNC ||
 994                     status == IXGBE_ERR_I2C ||
 995                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 996                         goto err_read_i2c_eeprom;
 997
 998                 status = hw->phy.ops.read_i2c_eeprom(hw,
 999                                                      IXGBE_SFF_10GBE_COMP_CODES,
1000                                                      &comp_codes_10g);
1001
1002                 if (status == IXGBE_ERR_SWFW_SYNC ||
1003                     status == IXGBE_ERR_I2C ||
1004                     status == IXGBE_ERR_SFP_NOT_PRESENT)
1005                         goto err_read_i2c_eeprom;
1006                 status = hw->phy.ops.read_i2c_eeprom(hw,
1007                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1008                                                      &cable_tech);
1009
1010                 if (status == IXGBE_ERR_SWFW_SYNC ||
1011                     status == IXGBE_ERR_I2C ||
1012                     status == IXGBE_ERR_SFP_NOT_PRESENT)
1013                         goto err_read_i2c_eeprom;
1014
1015                  /* ID Module
1016                   * =========
1017                   * 0   SFP_DA_CU
1018                   * 1   SFP_SR
1019                   * 2   SFP_LR
1020                   * 3   SFP_DA_CORE0 - 82599-specific
1021                   * 4   SFP_DA_CORE1 - 82599-specific
1022                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1023                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1024                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1025                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1026                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1027                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1028                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1029                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1030                   */
1031                 if (hw->mac.type == ixgbe_mac_82598EB) {
1032                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1033                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1034                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1035                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1036                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1037                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1038                         else
1039                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1040                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1041                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1042                                 if (hw->bus.lan_id == 0)
1043                                         hw->phy.sfp_type =
1044                                                      ixgbe_sfp_type_da_cu_core0;
1045                                 else
1046                                         hw->phy.sfp_type =
1047                                                      ixgbe_sfp_type_da_cu_core1;
1048                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1049                                 hw->phy.ops.read_i2c_eeprom(
1050                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1051                                                 &cable_spec);
1052                                 if (cable_spec &
1053                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1054                                         if (hw->bus.lan_id == 0)
1055                                                 hw->phy.sfp_type =
1056                                                 ixgbe_sfp_type_da_act_lmt_core0;
1057                                         else
1058                                                 hw->phy.sfp_type =
1059                                                 ixgbe_sfp_type_da_act_lmt_core1;
1060                                 } else {
1061                                         hw->phy.sfp_type =
1062                                                         ixgbe_sfp_type_unknown;
1063                                 }
1064                         } else if (comp_codes_10g &
1065                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1066                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1067                                 if (hw->bus.lan_id == 0)
1068                                         hw->phy.sfp_type =
1069                                                       ixgbe_sfp_type_srlr_core0;
1070                                 else
1071                                         hw->phy.sfp_type =
1072                                                       ixgbe_sfp_type_srlr_core1;
1073                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1074                                 if (hw->bus.lan_id == 0)
1075                                         hw->phy.sfp_type =
1076                                                 ixgbe_sfp_type_1g_cu_core0;
1077                                 else
1078                                         hw->phy.sfp_type =
1079                                                 ixgbe_sfp_type_1g_cu_core1;
1080                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1081                                 if (hw->bus.lan_id == 0)
1082                                         hw->phy.sfp_type =
1083                                                 ixgbe_sfp_type_1g_sx_core0;
1084                                 else
1085                                         hw->phy.sfp_type =
1086                                                 ixgbe_sfp_type_1g_sx_core1;
1087                         } else {
1088                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1089                         }
1090                 }
1091
1092                 if (hw->phy.sfp_type != stored_sfp_type)
1093                         hw->phy.sfp_setup_needed = true;
1094
1095                 /* Determine if the SFP+ PHY is dual speed or not. */
1096                 hw->phy.multispeed_fiber = false;
1097                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1098                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1099                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1100                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1101                         hw->phy.multispeed_fiber = true;
1102
1103                 /* Determine PHY vendor */
1104                 if (hw->phy.type != ixgbe_phy_nl) {
1105                         hw->phy.id = identifier;
1106                         status = hw->phy.ops.read_i2c_eeprom(hw,
1107                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1108                                                     &oui_bytes[0]);
1109
1110                         if (status == IXGBE_ERR_SWFW_SYNC ||
1111                             status == IXGBE_ERR_I2C ||
1112                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1113                                 goto err_read_i2c_eeprom;
1114
1115                         status = hw->phy.ops.read_i2c_eeprom(hw,
1116                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1117                                                     &oui_bytes[1]);
1118
1119                         if (status == IXGBE_ERR_SWFW_SYNC ||
1120                             status == IXGBE_ERR_I2C ||
1121                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1122                                 goto err_read_i2c_eeprom;
1123
1124                         status = hw->phy.ops.read_i2c_eeprom(hw,
1125                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1126                                                     &oui_bytes[2]);
1127
1128                         if (status == IXGBE_ERR_SWFW_SYNC ||
1129                             status == IXGBE_ERR_I2C ||
1130                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1131                                 goto err_read_i2c_eeprom;
1132
1133                         vendor_oui =
1134                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1135                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1136                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1137
1138                         switch (vendor_oui) {
1139                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1140                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1141                                         hw->phy.type =
1142                                                     ixgbe_phy_sfp_passive_tyco;
1143                                 break;
1144                         case IXGBE_SFF_VENDOR_OUI_FTL:
1145                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1146                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1147                                 else
1148                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1149                                 break;
1150                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1151                                 hw->phy.type = ixgbe_phy_sfp_avago;
1152                                 break;
1153                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1154                                 hw->phy.type = ixgbe_phy_sfp_intel;
1155                                 break;
1156                         default:
1157                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1158                                         hw->phy.type =
1159                                                  ixgbe_phy_sfp_passive_unknown;
1160                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1161                                         hw->phy.type =
1162                                                 ixgbe_phy_sfp_active_unknown;
1163                                 else
1164                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1165                                 break;
1166                         }
1167                 }
1168
1169                 /* Allow any DA cable vendor */
1170                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1171                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1172                         status = IXGBE_SUCCESS;
1173                         goto out;
1174                 }
1175
1176                 /* Verify supported 1G SFP modules */
1177                 if (comp_codes_10g == 0 &&
1178                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1179                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1180                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0  ||
1181                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1182                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1183                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1184                         goto out;
1185                 }
1186
1187                 /* Anything else 82598-based is supported */
1188                 if (hw->mac.type == ixgbe_mac_82598EB) {
1189                         status = IXGBE_SUCCESS;
1190                         goto out;
1191                 }
1192
1193                 ixgbe_get_device_caps(hw, &enforce_sfp);
1194                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1195                     !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1196                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1197                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0)  ||
1198                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1199                         /* Make sure we're a supported PHY type */
1200                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1201                                 status = IXGBE_SUCCESS;
1202                         } else {
1203                                 if (hw->allow_unsupported_sfp == true) {
1204                                         EWARN(hw, "WARNING: Intel (R) Network "
1205                                               "Connections are quality tested "
1206                                               "using Intel (R) Ethernet Optics."
1207                                               " Using untested modules is not "
1208                                               "supported and may cause unstable"
1209                                               " operation or damage to the "
1210                                               "module or the adapter. Intel "
1211                                               "Corporation is not responsible "
1212                                               "for any harm caused by using "
1213                                               "untested modules.\n", status);
1214                                         status = IXGBE_SUCCESS;
1215                                 } else {
1216                                         DEBUGOUT("SFP+ module not supported\n");
1217                                         hw->phy.type =
1218                                                 ixgbe_phy_sfp_unsupported;
1219                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1220                                 }
1221                         }
1222                 } else {
1223                         status = IXGBE_SUCCESS;
1224                 }
1225         }
1226
1227 out:
1228         return status;
1229
1230 err_read_i2c_eeprom:
1231         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1232         if (hw->phy.type != ixgbe_phy_nl) {
1233                 hw->phy.id = 0;
1234                 hw->phy.type = ixgbe_phy_unknown;
1235         }
1236         return IXGBE_ERR_SFP_NOT_PRESENT;
1237 }
1238
1239
1240
1241 /**
1242  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1243  *  @hw: pointer to hardware structure
1244  *  @list_offset: offset to the SFP ID list
1245  *  @data_offset: offset to the SFP data block
1246  *
1247  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1248  *  so it returns the offsets to the phy init sequence block.
1249  **/
1250 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1251                                         u16 *list_offset,
1252                                         u16 *data_offset)
1253 {
1254         u16 sfp_id;
1255         u16 sfp_type = hw->phy.sfp_type;
1256
1257         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1258
1259         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1260                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1261
1262         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1263                 return IXGBE_ERR_SFP_NOT_PRESENT;
1264
1265         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1266             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1267                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1268
1269         /*
1270          * Limiting active cables and 1G Phys must be initialized as
1271          * SR modules
1272          */
1273         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1274             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1275             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1276                 sfp_type = ixgbe_sfp_type_srlr_core0;
1277         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1278                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1279                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1280                 sfp_type = ixgbe_sfp_type_srlr_core1;
1281
1282         /* Read offset to PHY init contents */
1283         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1284
1285         if ((!*list_offset) || (*list_offset == 0xFFFF))
1286                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1287
1288         /* Shift offset to first ID word */
1289         (*list_offset)++;
1290
1291         /*
1292          * Find the matching SFP ID in the EEPROM
1293          * and program the init sequence
1294          */
1295         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1296
1297         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1298                 if (sfp_id == sfp_type) {
1299                         (*list_offset)++;
1300                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
1301                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1302                                 DEBUGOUT("SFP+ module not supported\n");
1303                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1304                         } else {
1305                                 break;
1306                         }
1307                 } else {
1308                         (*list_offset) += 2;
1309                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1310                                 return IXGBE_ERR_PHY;
1311                 }
1312         }
1313
1314         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1315                 DEBUGOUT("No matching SFP+ module found\n");
1316                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1317         }
1318
1319         return IXGBE_SUCCESS;
1320 }
1321
1322 /**
1323  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1324  *  @hw: pointer to hardware structure
1325  *  @byte_offset: EEPROM byte offset to read
1326  *  @eeprom_data: value read
1327  *
1328  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1329  **/
1330 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1331                                   u8 *eeprom_data)
1332 {
1333         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1334
1335         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1336                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1337                                          eeprom_data);
1338 }
1339
1340 /**
1341  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1342  *  @hw: pointer to hardware structure
1343  *  @byte_offset: EEPROM byte offset to write
1344  *  @eeprom_data: value to write
1345  *
1346  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1347  **/
1348 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1349                                    u8 eeprom_data)
1350 {
1351         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1352
1353         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1354                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1355                                           eeprom_data);
1356 }
1357
1358 /**
1359  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1360  *  @hw: pointer to hardware structure
1361  *  @byte_offset: byte offset to read
1362  *  @data: value read
1363  *
1364  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1365  *  a specified device address.
1366  **/
1367 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1368                                 u8 dev_addr, u8 *data)
1369 {
1370         s32 status = IXGBE_SUCCESS;
1371         u32 max_retry = 10;
1372         u32 retry = 0;
1373         u16 swfw_mask = 0;
1374         bool nack = 1;
1375         *data = 0;
1376
1377         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1378
1379         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1380                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1381         else
1382                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1383
1384         do {
1385                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1386                     != IXGBE_SUCCESS) {
1387                         status = IXGBE_ERR_SWFW_SYNC;
1388                         goto read_byte_out;
1389                 }
1390
1391                 ixgbe_i2c_start(hw);
1392
1393                 /* Device Address and write indication */
1394                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1395                 if (status != IXGBE_SUCCESS)
1396                         goto fail;
1397
1398                 status = ixgbe_get_i2c_ack(hw);
1399                 if (status != IXGBE_SUCCESS)
1400                         goto fail;
1401
1402                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1403                 if (status != IXGBE_SUCCESS)
1404                         goto fail;
1405
1406                 status = ixgbe_get_i2c_ack(hw);
1407                 if (status != IXGBE_SUCCESS)
1408                         goto fail;
1409
1410                 ixgbe_i2c_start(hw);
1411
1412                 /* Device Address and read indication */
1413                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1414                 if (status != IXGBE_SUCCESS)
1415                         goto fail;
1416
1417                 status = ixgbe_get_i2c_ack(hw);
1418                 if (status != IXGBE_SUCCESS)
1419                         goto fail;
1420
1421                 status = ixgbe_clock_in_i2c_byte(hw, data);
1422                 if (status != IXGBE_SUCCESS)
1423                         goto fail;
1424
1425                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1426                 if (status != IXGBE_SUCCESS)
1427                         goto fail;
1428
1429                 ixgbe_i2c_stop(hw);
1430                 break;
1431
1432 fail:
1433                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1434                 msec_delay(100);
1435                 ixgbe_i2c_bus_clear(hw);
1436                 retry++;
1437                 if (retry < max_retry)
1438                         DEBUGOUT("I2C byte read error - Retrying.\n");
1439                 else
1440                         DEBUGOUT("I2C byte read error.\n");
1441
1442         } while (retry < max_retry);
1443
1444         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1445
1446 read_byte_out:
1447         return status;
1448 }
1449
1450 /**
1451  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1452  *  @hw: pointer to hardware structure
1453  *  @byte_offset: byte offset to write
1454  *  @data: value to write
1455  *
1456  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1457  *  a specified device address.
1458  **/
1459 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1460                                  u8 dev_addr, u8 data)
1461 {
1462         s32 status = IXGBE_SUCCESS;
1463         u32 max_retry = 1;
1464         u32 retry = 0;
1465         u16 swfw_mask = 0;
1466
1467         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1468
1469         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1470                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1471         else
1472                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1473
1474         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1475                 status = IXGBE_ERR_SWFW_SYNC;
1476                 goto write_byte_out;
1477         }
1478
1479         do {
1480                 ixgbe_i2c_start(hw);
1481
1482                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1483                 if (status != IXGBE_SUCCESS)
1484                         goto fail;
1485
1486                 status = ixgbe_get_i2c_ack(hw);
1487                 if (status != IXGBE_SUCCESS)
1488                         goto fail;
1489
1490                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1491                 if (status != IXGBE_SUCCESS)
1492                         goto fail;
1493
1494                 status = ixgbe_get_i2c_ack(hw);
1495                 if (status != IXGBE_SUCCESS)
1496                         goto fail;
1497
1498                 status = ixgbe_clock_out_i2c_byte(hw, data);
1499                 if (status != IXGBE_SUCCESS)
1500                         goto fail;
1501
1502                 status = ixgbe_get_i2c_ack(hw);
1503                 if (status != IXGBE_SUCCESS)
1504                         goto fail;
1505
1506                 ixgbe_i2c_stop(hw);
1507                 break;
1508
1509 fail:
1510                 ixgbe_i2c_bus_clear(hw);
1511                 retry++;
1512                 if (retry < max_retry)
1513                         DEBUGOUT("I2C byte write error - Retrying.\n");
1514                 else
1515                         DEBUGOUT("I2C byte write error.\n");
1516         } while (retry < max_retry);
1517
1518         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1519
1520 write_byte_out:
1521         return status;
1522 }
1523
1524 /**
1525  *  ixgbe_i2c_start - Sets I2C start condition
1526  *  @hw: pointer to hardware structure
1527  *
1528  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1529  **/
1530 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
1531 {
1532         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1533
1534         DEBUGFUNC("ixgbe_i2c_start");
1535
1536         /* Start condition must begin with data and clock high */
1537         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1538         ixgbe_raise_i2c_clk(hw, &i2cctl);
1539
1540         /* Setup time for start condition (4.7us) */
1541         usec_delay(IXGBE_I2C_T_SU_STA);
1542
1543         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1544
1545         /* Hold time for start condition (4us) */
1546         usec_delay(IXGBE_I2C_T_HD_STA);
1547
1548         ixgbe_lower_i2c_clk(hw, &i2cctl);
1549
1550         /* Minimum low period of clock is 4.7 us */
1551         usec_delay(IXGBE_I2C_T_LOW);
1552
1553 }
1554
1555 /**
1556  *  ixgbe_i2c_stop - Sets I2C stop condition
1557  *  @hw: pointer to hardware structure
1558  *
1559  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1560  **/
1561 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1562 {
1563         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1564
1565         DEBUGFUNC("ixgbe_i2c_stop");
1566
1567         /* Stop condition must begin with data low and clock high */
1568         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1569         ixgbe_raise_i2c_clk(hw, &i2cctl);
1570
1571         /* Setup time for stop condition (4us) */
1572         usec_delay(IXGBE_I2C_T_SU_STO);
1573
1574         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1575
1576         /* bus free time between stop and start (4.7us)*/
1577         usec_delay(IXGBE_I2C_T_BUF);
1578 }
1579
1580 /**
1581  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1582  *  @hw: pointer to hardware structure
1583  *  @data: data byte to clock in
1584  *
1585  *  Clocks in one byte data via I2C data/clock
1586  **/
1587 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1588 {
1589         s32 i;
1590         bool bit = 0;
1591
1592         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1593
1594         for (i = 7; i >= 0; i--) {
1595                 ixgbe_clock_in_i2c_bit(hw, &bit);
1596                 *data |= bit << i;
1597         }
1598
1599         return IXGBE_SUCCESS;
1600 }
1601
1602 /**
1603  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1604  *  @hw: pointer to hardware structure
1605  *  @data: data byte clocked out
1606  *
1607  *  Clocks out one byte data via I2C data/clock
1608  **/
1609 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1610 {
1611         s32 status = IXGBE_SUCCESS;
1612         s32 i;
1613         u32 i2cctl;
1614         bool bit;
1615
1616         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1617
1618         for (i = 7; i >= 0; i--) {
1619                 bit = (data >> i) & 0x1;
1620                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1621
1622                 if (status != IXGBE_SUCCESS)
1623                         break;
1624         }
1625
1626         /* Release SDA line (set high) */
1627         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1628         i2cctl |= IXGBE_I2C_DATA_OUT;
1629         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1630         IXGBE_WRITE_FLUSH(hw);
1631
1632         return status;
1633 }
1634
1635 /**
1636  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1637  *  @hw: pointer to hardware structure
1638  *
1639  *  Clocks in/out one bit via I2C data/clock
1640  **/
1641 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1642 {
1643         s32 status = IXGBE_SUCCESS;
1644         u32 i = 0;
1645         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1646         u32 timeout = 10;
1647         bool ack = 1;
1648
1649         DEBUGFUNC("ixgbe_get_i2c_ack");
1650
1651         ixgbe_raise_i2c_clk(hw, &i2cctl);
1652
1653
1654         /* Minimum high period of clock is 4us */
1655         usec_delay(IXGBE_I2C_T_HIGH);
1656
1657         /* Poll for ACK.  Note that ACK in I2C spec is
1658          * transition from 1 to 0 */
1659         for (i = 0; i < timeout; i++) {
1660                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1661                 ack = ixgbe_get_i2c_data(&i2cctl);
1662
1663                 usec_delay(1);
1664                 if (ack == 0)
1665                         break;
1666         }
1667
1668         if (ack == 1) {
1669                 DEBUGOUT("I2C ack was not received.\n");
1670                 status = IXGBE_ERR_I2C;
1671         }
1672
1673         ixgbe_lower_i2c_clk(hw, &i2cctl);
1674
1675         /* Minimum low period of clock is 4.7 us */
1676         usec_delay(IXGBE_I2C_T_LOW);
1677
1678         return status;
1679 }
1680
1681 /**
1682  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1683  *  @hw: pointer to hardware structure
1684  *  @data: read data value
1685  *
1686  *  Clocks in one bit via I2C data/clock
1687  **/
1688 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1689 {
1690         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1691
1692         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1693
1694         ixgbe_raise_i2c_clk(hw, &i2cctl);
1695
1696         /* Minimum high period of clock is 4us */
1697         usec_delay(IXGBE_I2C_T_HIGH);
1698
1699         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1700         *data = ixgbe_get_i2c_data(&i2cctl);
1701
1702         ixgbe_lower_i2c_clk(hw, &i2cctl);
1703
1704         /* Minimum low period of clock is 4.7 us */
1705         usec_delay(IXGBE_I2C_T_LOW);
1706
1707         return IXGBE_SUCCESS;
1708 }
1709
1710 /**
1711  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1712  *  @hw: pointer to hardware structure
1713  *  @data: data value to write
1714  *
1715  *  Clocks out one bit via I2C data/clock
1716  **/
1717 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1718 {
1719         s32 status;
1720         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1721
1722         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1723
1724         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1725         if (status == IXGBE_SUCCESS) {
1726                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1727
1728                 /* Minimum high period of clock is 4us */
1729                 usec_delay(IXGBE_I2C_T_HIGH);
1730
1731                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1732
1733                 /* Minimum low period of clock is 4.7 us.
1734                  * This also takes care of the data hold time.
1735                  */
1736                 usec_delay(IXGBE_I2C_T_LOW);
1737         } else {
1738                 status = IXGBE_ERR_I2C;
1739                 DEBUGOUT1("I2C data was not set to %X\n", data);
1740         }
1741
1742         return status;
1743 }
1744 /**
1745  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1746  *  @hw: pointer to hardware structure
1747  *  @i2cctl: Current value of I2CCTL register
1748  *
1749  *  Raises the I2C clock line '0'->'1'
1750  **/
1751 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1752 {
1753         u32 i = 0;
1754         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1755         u32 i2cctl_r = 0;
1756
1757         DEBUGFUNC("ixgbe_raise_i2c_clk");
1758
1759         for (i = 0; i < timeout; i++) {
1760                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1761
1762                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1763                 IXGBE_WRITE_FLUSH(hw);
1764                 /* SCL rise time (1000ns) */
1765                 usec_delay(IXGBE_I2C_T_RISE);
1766
1767                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1768                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1769                         break;
1770         }
1771 }
1772
1773 /**
1774  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1775  *  @hw: pointer to hardware structure
1776  *  @i2cctl: Current value of I2CCTL register
1777  *
1778  *  Lowers the I2C clock line '1'->'0'
1779  **/
1780 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1781 {
1782
1783         DEBUGFUNC("ixgbe_lower_i2c_clk");
1784
1785         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1786
1787         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1788         IXGBE_WRITE_FLUSH(hw);
1789
1790         /* SCL fall time (300ns) */
1791         usec_delay(IXGBE_I2C_T_FALL);
1792 }
1793
1794 /**
1795  *  ixgbe_set_i2c_data - Sets the I2C data bit
1796  *  @hw: pointer to hardware structure
1797  *  @i2cctl: Current value of I2CCTL register
1798  *  @data: I2C data value (0 or 1) to set
1799  *
1800  *  Sets the I2C data bit
1801  **/
1802 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1803 {
1804         s32 status = IXGBE_SUCCESS;
1805
1806         DEBUGFUNC("ixgbe_set_i2c_data");
1807
1808         if (data)
1809                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1810         else
1811                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1812
1813         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1814         IXGBE_WRITE_FLUSH(hw);
1815
1816         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1817         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1818
1819         /* Verify data was set correctly */
1820         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1821         if (data != ixgbe_get_i2c_data(i2cctl)) {
1822                 status = IXGBE_ERR_I2C;
1823                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1824         }
1825
1826         return status;
1827 }
1828
1829 /**
1830  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1831  *  @hw: pointer to hardware structure
1832  *  @i2cctl: Current value of I2CCTL register
1833  *
1834  *  Returns the I2C data bit value
1835  **/
1836 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
1837 {
1838         bool data;
1839
1840         DEBUGFUNC("ixgbe_get_i2c_data");
1841
1842         if (*i2cctl & IXGBE_I2C_DATA_IN)
1843                 data = 1;
1844         else
1845                 data = 0;
1846
1847         return data;
1848 }
1849
1850 /**
1851  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1852  *  @hw: pointer to hardware structure
1853  *
1854  *  Clears the I2C bus by sending nine clock pulses.
1855  *  Used when data line is stuck low.
1856  **/
1857 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1858 {
1859         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1860         u32 i;
1861
1862         DEBUGFUNC("ixgbe_i2c_bus_clear");
1863
1864         ixgbe_i2c_start(hw);
1865
1866         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1867
1868         for (i = 0; i < 9; i++) {
1869                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1870
1871                 /* Min high period of clock is 4us */
1872                 usec_delay(IXGBE_I2C_T_HIGH);
1873
1874                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1875
1876                 /* Min low period of clock is 4.7us*/
1877                 usec_delay(IXGBE_I2C_T_LOW);
1878         }
1879
1880         ixgbe_i2c_start(hw);
1881
1882         /* Put the i2c bus back to default state */
1883         ixgbe_i2c_stop(hw);
1884 }
1885
1886 /**
1887  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1888  *  @hw: pointer to hardware structure
1889  *
1890  *  Checks if the LASI temp alarm status was triggered due to overtemp
1891  **/
1892 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1893 {
1894         s32 status = IXGBE_SUCCESS;
1895         u16 phy_data = 0;
1896
1897         DEBUGFUNC("ixgbe_tn_check_overtemp");
1898
1899         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1900                 goto out;
1901
1902         /* Check that the LASI temp alarm status was triggered */
1903         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1904                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1905
1906         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1907                 goto out;
1908
1909         status = IXGBE_ERR_OVERTEMP;
1910 out:
1911         return status;
1912 }