lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37 #ident "$Id: ixgbe_phy.c,v 1.155 2013/08/14 22:34:03 jtkirshe Exp $"
  38
  39 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
  50 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  51                                           u8 *sff8472_data);
  52
  53 /**
  54  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  55  *  @hw: pointer to the hardware structure
  56  *
  57  *  Initialize the function pointers.
  58  **/
  59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_phy_info *phy = &hw->phy;
  62
  63         DEBUGFUNC("ixgbe_init_phy_ops_generic");
  64
  65         /* PHY */
  66         phy->ops.identify = &ixgbe_identify_phy_generic;
  67         phy->ops.reset = &ixgbe_reset_phy_generic;
  68         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  69         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  70         phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
  71         phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
  72         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  73         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  74         phy->ops.check_link = NULL;
  75         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  76         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  77         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  78         phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
  79         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  80         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  81         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  82         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  83         phy->sfp_type = ixgbe_sfp_type_unknown;
  84         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  85         return IXGBE_SUCCESS;
  86 }
  87
  88 /**
  89  *  ixgbe_identify_phy_generic - Get physical layer module
  90  *  @hw: pointer to hardware structure
  91  *
  92  *  Determines the physical layer module found on the current adapter.
  93  **/
  94 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  95 {
  96         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  97         u32 phy_addr;
  98         u16 ext_ability = 0;
  99
 100         DEBUGFUNC("ixgbe_identify_phy_generic");
 101
 102         if (!hw->phy.phy_semaphore_mask) {
 103                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
 104                                                 IXGBE_STATUS_LAN_ID_1;
 105                 if (hw->phy.lan_id)
 106                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 107                 else
 108                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 109         }
 110
 111         if (hw->phy.type == ixgbe_phy_unknown) {
 112                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 113                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 114                                 hw->phy.addr = phy_addr;
 115                                 ixgbe_get_phy_id(hw);
 116                                 hw->phy.type =
 117                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 118
 119                                 if (hw->phy.type == ixgbe_phy_unknown) {
 120                                         hw->phy.ops.read_reg(hw,
 121                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 122                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 123                                                   &ext_ability);
 124                                         if (ext_ability &
 125                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 126                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 127                                                 hw->phy.type =
 128                                                          ixgbe_phy_cu_unknown;
 129                                         else
 130                                                 hw->phy.type =
 131                                                          ixgbe_phy_generic;
 132                                 }
 133
 134                                 status = IXGBE_SUCCESS;
 135                                 break;
 136                         }
 137                 }
 138
 139                 /* Certain media types do not have a phy so an address will not
 140                  * be found and the code will take this path.  Caller has to
 141                  * decide if it is an error or not.
 142                  */
 143                 if (status != IXGBE_SUCCESS) {
 144                         hw->phy.addr = 0;
 145                 }
 146         } else {
 147                 status = IXGBE_SUCCESS;
 148         }
 149
 150         return status;
 151 }
 152
 153 /**
 154  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 155  * @hw: pointer to the hardware structure
 156  *
 157  * This function checks the MMNGC.MNG_VETO bit to see if there are
 158  * any constraints on link from manageability.  For MAC's that don't
 159  * have this bit just return faluse since the link can not be blocked
 160  * via this method.
 161  **/
 162 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 163 {
 164         u32 mmngc;
 165
 166         DEBUGFUNC("ixgbe_check_reset_blocked");
 167
 168         /* If we don't have this bit, it can't be blocking */
 169         if (hw->mac.type == ixgbe_mac_82598EB)
 170                 return false;
 171
 172         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 173         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 174                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 175                               "MNG_VETO bit detected.\n");
 176                 return true;
 177         }
 178
 179         return false;
 180 }
 181
 182 /**
 183  *  ixgbe_validate_phy_addr - Determines phy address is valid
 184  *  @hw: pointer to hardware structure
 185  *
 186  **/
 187 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 188 {
 189         u16 phy_id = 0;
 190         bool valid = false;
 191
 192         DEBUGFUNC("ixgbe_validate_phy_addr");
 193
 194         hw->phy.addr = phy_addr;
 195         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 196                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 197
 198         if (phy_id != 0xFFFF && phy_id != 0x0)
 199                 valid = true;
 200
 201         return valid;
 202 }
 203
 204 /**
 205  *  ixgbe_get_phy_id - Get the phy type
 206  *  @hw: pointer to hardware structure
 207  *
 208  **/
 209 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 210 {
 211         u32 status;
 212         u16 phy_id_high = 0;
 213         u16 phy_id_low = 0;
 214
 215         DEBUGFUNC("ixgbe_get_phy_id");
 216
 217         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 218                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 219                                       &phy_id_high);
 220
 221         if (status == IXGBE_SUCCESS) {
 222                 hw->phy.id = (u32)(phy_id_high << 16);
 223                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 224                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 225                                               &phy_id_low);
 226                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 227                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 228         }
 229         return status;
 230 }
 231
 232 /**
 233  *  ixgbe_get_phy_type_from_id - Get the phy type
 234  *  @hw: pointer to hardware structure
 235  *
 236  **/
 237 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 238 {
 239         enum ixgbe_phy_type phy_type;
 240
 241         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 242
 243         switch (phy_id) {
 244         case TN1010_PHY_ID:
 245                 phy_type = ixgbe_phy_tn;
 246                 break;
 247         case X540_PHY_ID:
 248                 phy_type = ixgbe_phy_aq;
 249                 break;
 250         case QT2022_PHY_ID:
 251                 phy_type = ixgbe_phy_qt;
 252                 break;
 253         case ATH_PHY_ID:
 254                 phy_type = ixgbe_phy_nl;
 255                 break;
 256         default:
 257                 phy_type = ixgbe_phy_unknown;
 258                 break;
 259         }
 260
 261         DEBUGOUT1("phy type found is %d\n", phy_type);
 262         return phy_type;
 263 }
 264
 265 /**
 266  *  ixgbe_reset_phy_generic - Performs a PHY reset
 267  *  @hw: pointer to hardware structure
 268  **/
 269 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 270 {
 271         u32 i;
 272         u16 ctrl = 0;
 273         s32 status = IXGBE_SUCCESS;
 274
 275         DEBUGFUNC("ixgbe_reset_phy_generic");
 276
 277         if (hw->phy.type == ixgbe_phy_unknown)
 278                 status = ixgbe_identify_phy_generic(hw);
 279
 280         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 281                 goto out;
 282
 283         /* Don't reset PHY if it's shut down due to overtemp. */
 284         if (!hw->phy.reset_if_overtemp &&
 285             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 286                 goto out;
 287
 288         /* Blocked by MNG FW so bail */
 289         if (ixgbe_check_reset_blocked(hw))
 290                 goto out;
 291
 292         /*
 293          * Perform soft PHY reset to the PHY_XS.
 294          * This will cause a soft reset to the PHY
 295          */
 296         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 297                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 298                               IXGBE_MDIO_PHY_XS_RESET);
 299
 300         /*
 301          * Poll for reset bit to self-clear indicating reset is complete.
 302          * Some PHYs could take up to 3 seconds to complete and need about
 303          * 1.7 usec delay after the reset is complete.
 304          */
 305         for (i = 0; i < 30; i++) {
 306                 msec_delay(100);
 307                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 308                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 309                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 310                         usec_delay(2);
 311                         break;
 312                 }
 313         }
 314
 315         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 316                 status = IXGBE_ERR_RESET_FAILED;
 317                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 318                              "PHY reset polling failed to complete.\n");
 319         }
 320
 321 out:
 322         return status;
 323 }
 324
 325 /**
 326  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 327  *  the SWFW lock
 328  *  @hw: pointer to hardware structure
 329  *  @reg_addr: 32 bit address of PHY register to read
 330  *  @phy_data: Pointer to read data from PHY register
 331  **/
 332 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 333                        u16 *phy_data)
 334 {
 335         u32 i, data, command;
 336
 337         /* Setup and write the address cycle command */
 338         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 339                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 340                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 341                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 342
 343         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 344
 345         /*
 346          * Check every 10 usec to see if the address cycle completed.
 347          * The MDI Command bit will clear when the operation is
 348          * complete
 349          */
 350         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 351                 usec_delay(10);
 352
 353                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 354                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 355                                 break;
 356         }
 357
 358
 359         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 360                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 361                 return IXGBE_ERR_PHY;
 362         }
 363
 364         /*
 365          * Address cycle complete, setup and write the read
 366          * command
 367          */
 368         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 369                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 370                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 371                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 372
 373         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 374
 375         /*
 376          * Check every 10 usec to see if the address cycle
 377          * completed. The MDI Command bit will clear when the
 378          * operation is complete
 379          */
 380         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 381                 usec_delay(10);
 382
 383                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 384                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 385                         break;
 386         }
 387
 388         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 389                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 390                 return IXGBE_ERR_PHY;
 391         }
 392
 393         /*
 394          * Read operation is complete.  Get the data
 395          * from MSRWD
 396          */
 397         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 398         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 399         *phy_data = (u16)(data);
 400
 401         return IXGBE_SUCCESS;
 402 }
 403
 404 /**
 405  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 406  *  using the SWFW lock - this function is needed in most cases
 407  *  @hw: pointer to hardware structure
 408  *  @reg_addr: 32 bit address of PHY register to read
 409  *  @phy_data: Pointer to read data from PHY register
 410  **/
 411 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 412                                u32 device_type, u16 *phy_data)
 413 {
 414         s32 status;
 415         u32 gssr = hw->phy.phy_semaphore_mask;
 416
 417         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 418
 419         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 420                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 421                                                 phy_data);
 422                 hw->mac.ops.release_swfw_sync(hw, gssr);
 423         } else {
 424                 status = IXGBE_ERR_SWFW_SYNC;
 425         }
 426
 427         return status;
 428 }
 429
 430 /**
 431  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 432  *  without SWFW lock
 433  *  @hw: pointer to hardware structure
 434  *  @reg_addr: 32 bit PHY register to write
 435  *  @device_type: 5 bit device type
 436  *  @phy_data: Data to write to the PHY register
 437  **/
 438 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 439                                 u32 device_type, u16 phy_data)
 440 {
 441         u32 i, command;
 442
 443         /* Put the data in the MDI single read and write data register*/
 444         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 445
 446         /* Setup and write the address cycle command */
 447         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 448                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 449                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 450                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 451
 452         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 453
 454         /*
 455          * Check every 10 usec to see if the address cycle completed.
 456          * The MDI Command bit will clear when the operation is
 457          * complete
 458          */
 459         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 460                 usec_delay(10);
 461
 462                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 463                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 464                         break;
 465         }
 466
 467         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 468                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 469                 return IXGBE_ERR_PHY;
 470         }
 471
 472         /*
 473          * Address cycle complete, setup and write the write
 474          * command
 475          */
 476         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 477                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 478                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 479                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 480
 481         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 482
 483         /*
 484          * Check every 10 usec to see if the address cycle
 485          * completed. The MDI Command bit will clear when the
 486          * operation is complete
 487          */
 488         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 489                 usec_delay(10);
 490
 491                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 492                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 493                         break;
 494         }
 495
 496         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 497                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 498                 return IXGBE_ERR_PHY;
 499         }
 500
 501         return IXGBE_SUCCESS;
 502 }
 503
 504 /**
 505  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 506  *  using SWFW lock- this function is needed in most cases
 507  *  @hw: pointer to hardware structure
 508  *  @reg_addr: 32 bit PHY register to write
 509  *  @device_type: 5 bit device type
 510  *  @phy_data: Data to write to the PHY register
 511  **/
 512 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 513                                 u32 device_type, u16 phy_data)
 514 {
 515         s32 status;
 516         u32 gssr = hw->phy.phy_semaphore_mask;
 517
 518         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 519
 520         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 521                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 522                                                  phy_data);
 523                 hw->mac.ops.release_swfw_sync(hw, gssr);
 524         } else {
 525                 status = IXGBE_ERR_SWFW_SYNC;
 526         }
 527
 528         return status;
 529 }
 530
 531 /**
 532  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 533  *  @hw: pointer to hardware structure
 534  *
 535  *  Restart auto-negotiation and PHY and waits for completion.
 536  **/
 537 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 538 {
 539         s32 status = IXGBE_SUCCESS;
 540         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 541         bool autoneg = false;
 542         ixgbe_link_speed speed;
 543
 544         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 545
 546         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 547
 548         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 549                 /* Set or unset auto-negotiation 10G advertisement */
 550                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 551                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 552                                      &autoneg_reg);
 553
 554                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 555                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 556                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 557
 558                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 559                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 560                                       autoneg_reg);
 561         }
 562
 563         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 564                 /* Set or unset auto-negotiation 1G advertisement */
 565                 hw->phy.ops.read_reg(hw,
 566                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 567                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 568                                      &autoneg_reg);
 569
 570                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 571                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 572                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 573
 574                 hw->phy.ops.write_reg(hw,
 575                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 576                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 577                                       autoneg_reg);
 578         }
 579
 580         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 581                 /* Set or unset auto-negotiation 100M advertisement */
 582                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 583                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 584                                      &autoneg_reg);
 585
 586                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 587                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 588                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 589                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 590
 591                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 592                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 593                                       autoneg_reg);
 594         }
 595
 596         /* Blocked by MNG FW so don't reset PHY */
 597         if (ixgbe_check_reset_blocked(hw))
 598                 return status;
 599
 600         /* Restart PHY auto-negotiation. */
 601         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 602                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 603
 604         autoneg_reg |= IXGBE_MII_RESTART;
 605
 606         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 607                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 608
 609         return status;
 610 }
 611
 612 /**
 613  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 614  *  @hw: pointer to hardware structure
 615  *  @speed: new link speed
 616  **/
 617 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 618                                        ixgbe_link_speed speed,
 619                                        bool autoneg_wait_to_complete)
 620 {
 621         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 622
 623         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 624
 625         /*
 626          * Clear autoneg_advertised and set new values based on input link
 627          * speed.
 628          */
 629         hw->phy.autoneg_advertised = 0;
 630
 631         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 632                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 633
 634         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 635                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 636
 637         if (speed & IXGBE_LINK_SPEED_100_FULL)
 638                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 639
 640         /* Setup link based on the new speed settings */
 641         hw->phy.ops.setup_link(hw);
 642
 643         return IXGBE_SUCCESS;
 644 }
 645
 646 /**
 647  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 648  *  @hw: pointer to hardware structure
 649  *  @speed: pointer to link speed
 650  *  @autoneg: boolean auto-negotiation value
 651  *
 652  *  Determines the link capabilities by reading the AUTOC register.
 653  **/
 654 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 655                                                ixgbe_link_speed *speed,
 656                                                bool *autoneg)
 657 {
 658         s32 status;
 659         u16 speed_ability;
 660
 661         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 662
 663         *speed = 0;
 664         *autoneg = true;
 665
 666         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 667                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 668                                       &speed_ability);
 669
 670         if (status == IXGBE_SUCCESS) {
 671                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 672                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 673                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 674                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 675                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 676                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 677         }
 678
 679         return status;
 680 }
 681
 682 /**
 683  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 684  *  @hw: pointer to hardware structure
 685  *
 686  *  Reads the VS1 register to determine if link is up and the current speed for
 687  *  the PHY.
 688  **/
 689 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 690                              bool *link_up)
 691 {
 692         s32 status = IXGBE_SUCCESS;
 693         u32 time_out;
 694         u32 max_time_out = 10;
 695         u16 phy_link = 0;
 696         u16 phy_speed = 0;
 697         u16 phy_data = 0;
 698
 699         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 700
 701         /* Initialize speed and link to default case */
 702         *link_up = false;
 703         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 704
 705         /*
 706          * Check current speed and link status of the PHY register.
 707          * This is a vendor specific register and may have to
 708          * be changed for other copper PHYs.
 709          */
 710         for (time_out = 0; time_out < max_time_out; time_out++) {
 711                 usec_delay(10);
 712                 status = hw->phy.ops.read_reg(hw,
 713                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 714                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 715                                         &phy_data);
 716                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 717                 phy_speed = phy_data &
 718                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 719                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 720                         *link_up = true;
 721                         if (phy_speed ==
 722                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 723                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 724                         break;
 725                 }
 726         }
 727
 728         return status;
 729 }
 730
 731 /**
 732  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
 733  *      @hw: pointer to hardware structure
 734  *
 735  *      Restart auto-negotiation and PHY and waits for completion.
 736  **/
 737 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 738 {
 739         s32 status = IXGBE_SUCCESS;
 740         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 741         bool autoneg = false;
 742         ixgbe_link_speed speed;
 743
 744         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 745
 746         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 747
 748         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 749                 /* Set or unset auto-negotiation 10G advertisement */
 750                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 751                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 752                                      &autoneg_reg);
 753
 754                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 755                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 756                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 757
 758                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 759                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 760                                       autoneg_reg);
 761         }
 762
 763         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 764                 /* Set or unset auto-negotiation 1G advertisement */
 765                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 766                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 767                                      &autoneg_reg);
 768
 769                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 770                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 771                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 772
 773                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 774                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 775                                       autoneg_reg);
 776         }
 777
 778         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 779                 /* Set or unset auto-negotiation 100M advertisement */
 780                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 781                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 782                                      &autoneg_reg);
 783
 784                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 785                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 786                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 787
 788                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 789                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 790                                       autoneg_reg);
 791         }
 792
 793         /* Blocked by MNG FW so don't reset PHY */
 794         if (ixgbe_check_reset_blocked(hw))
 795                 return status;
 796
 797         /* Restart PHY auto-negotiation. */
 798         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 799                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 800
 801         autoneg_reg |= IXGBE_MII_RESTART;
 802
 803         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 804                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 805
 806         return status;
 807 }
 808
 809 /**
 810  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 811  *  @hw: pointer to hardware structure
 812  *  @firmware_version: pointer to the PHY Firmware Version
 813  **/
 814 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 815                                        u16 *firmware_version)
 816 {
 817         s32 status;
 818
 819         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 820
 821         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 822                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 823                                       firmware_version);
 824
 825         return status;
 826 }
 827
 828 /**
 829  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 830  *  @hw: pointer to hardware structure
 831  *  @firmware_version: pointer to the PHY Firmware Version
 832  **/
 833 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 834                                            u16 *firmware_version)
 835 {
 836         s32 status;
 837
 838         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 839
 840         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 841                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 842                                       firmware_version);
 843
 844         return status;
 845 }
 846
 847 /**
 848  *  ixgbe_reset_phy_nl - Performs a PHY reset
 849  *  @hw: pointer to hardware structure
 850  **/
 851 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 852 {
 853         u16 phy_offset, control, eword, edata, block_crc;
 854         bool end_data = false;
 855         u16 list_offset, data_offset;
 856         u16 phy_data = 0;
 857         s32 ret_val = IXGBE_SUCCESS;
 858         u32 i;
 859
 860         DEBUGFUNC("ixgbe_reset_phy_nl");
 861
 862         /* Blocked by MNG FW so bail */
 863         if (ixgbe_check_reset_blocked(hw))
 864                 goto out;
 865
 866         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 867                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 868
 869         /* reset the PHY and poll for completion */
 870         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 871                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 872                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 873
 874         for (i = 0; i < 100; i++) {
 875                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 876                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 877                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 878                         break;
 879                 msec_delay(10);
 880         }
 881
 882         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 883                 DEBUGOUT("PHY reset did not complete.\n");
 884                 ret_val = IXGBE_ERR_PHY;
 885                 goto out;
 886         }
 887
 888         /* Get init offsets */
 889         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 890                                                       &data_offset);
 891         if (ret_val != IXGBE_SUCCESS)
 892                 goto out;
 893
 894         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 895         data_offset++;
 896         while (!end_data) {
 897                 /*
 898                  * Read control word from PHY init contents offset
 899                  */
 900                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 901                 if (ret_val)
 902                         goto err_eeprom;
 903                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 904                            IXGBE_CONTROL_SHIFT_NL;
 905                 edata = eword & IXGBE_DATA_MASK_NL;
 906                 switch (control) {
 907                 case IXGBE_DELAY_NL:
 908                         data_offset++;
 909                         DEBUGOUT1("DELAY: %d MS\n", edata);
 910                         msec_delay(edata);
 911                         break;
 912                 case IXGBE_DATA_NL:
 913                         DEBUGOUT("DATA:\n");
 914                         data_offset++;
 915                         ret_val = hw->eeprom.ops.read(hw, data_offset,
 916                                                       &phy_offset);
 917                         if (ret_val)
 918                                 goto err_eeprom;
 919                         data_offset++;
 920                         for (i = 0; i < edata; i++) {
 921                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 922                                                               &eword);
 923                                 if (ret_val)
 924                                         goto err_eeprom;
 925                                 hw->phy.ops.write_reg(hw, phy_offset,
 926                                                       IXGBE_TWINAX_DEV, eword);
 927                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
 928                                           phy_offset);
 929                                 data_offset++;
 930                                 phy_offset++;
 931                         }
 932                         break;
 933                 case IXGBE_CONTROL_NL:
 934                         data_offset++;
 935                         DEBUGOUT("CONTROL:\n");
 936                         if (edata == IXGBE_CONTROL_EOL_NL) {
 937                                 DEBUGOUT("EOL\n");
 938                                 end_data = true;
 939                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 940                                 DEBUGOUT("SOL\n");
 941                         } else {
 942                                 DEBUGOUT("Bad control value\n");
 943                                 ret_val = IXGBE_ERR_PHY;
 944                                 goto out;
 945                         }
 946                         break;
 947                 default:
 948                         DEBUGOUT("Bad control type\n");
 949                         ret_val = IXGBE_ERR_PHY;
 950                         goto out;
 951                 }
 952         }
 953
 954 out:
 955         return ret_val;
 956
 957 err_eeprom:
 958         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 959                       "eeprom read at offset %d failed", data_offset);
 960         return IXGBE_ERR_PHY;
 961 }
 962
 963 /**
 964  *  ixgbe_identify_module_generic - Identifies module type
 965  *  @hw: pointer to hardware structure
 966  *
 967  *  Determines HW type and calls appropriate function.
 968  **/
 969 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 970 {
 971         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 972
 973         DEBUGFUNC("ixgbe_identify_module_generic");
 974
 975         switch (hw->mac.ops.get_media_type(hw)) {
 976         case ixgbe_media_type_fiber:
 977                 status = ixgbe_identify_sfp_module_generic(hw);
 978                 break;
 979
 980
 981         default:
 982                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 983                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 984                 break;
 985         }
 986
 987         return status;
 988 }
 989
 990 /**
 991  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 992  *  @hw: pointer to hardware structure
 993  *
 994  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 995  **/
 996 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 997 {
 998         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 999         u32 vendor_oui = 0;
1000         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1001         u8 identifier = 0;
1002         u8 comp_codes_1g = 0;
1003         u8 comp_codes_10g = 0;
1004         u8 oui_bytes[3] = {0, 0, 0};
1005         u8 cable_tech = 0;
1006         u8 cable_spec = 0;
1007         u16 enforce_sfp = 0;
1008
1009         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1010
1011         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1012                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1013                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1014                 goto out;
1015         }
1016
1017         status = hw->phy.ops.read_i2c_eeprom(hw,
1018                                              IXGBE_SFF_IDENTIFIER,
1019                                              &identifier);
1020
1021         if (status != IXGBE_SUCCESS)
1022                 goto err_read_i2c_eeprom;
1023
1024         /* LAN ID is needed for sfp_type determination */
1025         hw->mac.ops.set_lan_id(hw);
1026
1027         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1028                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1029                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1030         } else {
1031                 status = hw->phy.ops.read_i2c_eeprom(hw,
1032                                                      IXGBE_SFF_1GBE_COMP_CODES,
1033                                                      &comp_codes_1g);
1034
1035                 if (status != IXGBE_SUCCESS)
1036                         goto err_read_i2c_eeprom;
1037
1038                 status = hw->phy.ops.read_i2c_eeprom(hw,
1039                                                      IXGBE_SFF_10GBE_COMP_CODES,
1040                                                      &comp_codes_10g);
1041
1042                 if (status != IXGBE_SUCCESS)
1043                         goto err_read_i2c_eeprom;
1044                 status = hw->phy.ops.read_i2c_eeprom(hw,
1045                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1046                                                      &cable_tech);
1047
1048                 if (status != IXGBE_SUCCESS)
1049                         goto err_read_i2c_eeprom;
1050
1051                  /* ID Module
1052                   * =========
1053                   * 0   SFP_DA_CU
1054                   * 1   SFP_SR
1055                   * 2   SFP_LR
1056                   * 3   SFP_DA_CORE0 - 82599-specific
1057                   * 4   SFP_DA_CORE1 - 82599-specific
1058                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1059                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1060                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1061                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1062                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1063                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1064                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1065                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1066                   */
1067                 if (hw->mac.type == ixgbe_mac_82598EB) {
1068                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1069                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1070                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1071                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1072                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1073                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1074                         else
1075                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1076                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1077                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1078                                 if (hw->bus.lan_id == 0)
1079                                         hw->phy.sfp_type =
1080                                                      ixgbe_sfp_type_da_cu_core0;
1081                                 else
1082                                         hw->phy.sfp_type =
1083                                                      ixgbe_sfp_type_da_cu_core1;
1084                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1085                                 hw->phy.ops.read_i2c_eeprom(
1086                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1087                                                 &cable_spec);
1088                                 if (cable_spec &
1089                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1090                                         if (hw->bus.lan_id == 0)
1091                                                 hw->phy.sfp_type =
1092                                                 ixgbe_sfp_type_da_act_lmt_core0;
1093                                         else
1094                                                 hw->phy.sfp_type =
1095                                                 ixgbe_sfp_type_da_act_lmt_core1;
1096                                 } else {
1097                                         hw->phy.sfp_type =
1098                                                         ixgbe_sfp_type_unknown;
1099                                 }
1100                         } else if (comp_codes_10g &
1101                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1102                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1103                                 if (hw->bus.lan_id == 0)
1104                                         hw->phy.sfp_type =
1105                                                       ixgbe_sfp_type_srlr_core0;
1106                                 else
1107                                         hw->phy.sfp_type =
1108                                                       ixgbe_sfp_type_srlr_core1;
1109 #ifdef SUPPORT_10GBASE_ER
1110                         } else if (comp_codes_10g &
1111                                    IXGBE_SFF_10GBASEER_CAPABLE) {
1112                                 if (hw->bus.lan_id == 0)
1113                                         hw->phy.sfp_type =
1114                                                         ixgbe_sfp_type_er_core0;
1115                                 else
1116                                         hw->phy.sfp_type =
1117                                                         ixgbe_sfp_type_er_core1;
1118 #endif /* SUPPORT_10GBASE_ER */
1119                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1120                                 if (hw->bus.lan_id == 0)
1121                                         hw->phy.sfp_type =
1122                                                 ixgbe_sfp_type_1g_cu_core0;
1123                                 else
1124                                         hw->phy.sfp_type =
1125                                                 ixgbe_sfp_type_1g_cu_core1;
1126                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1127                                 if (hw->bus.lan_id == 0)
1128                                         hw->phy.sfp_type =
1129                                                 ixgbe_sfp_type_1g_sx_core0;
1130                                 else
1131                                         hw->phy.sfp_type =
1132                                                 ixgbe_sfp_type_1g_sx_core1;
1133 #ifdef SUPPORT_1000BASE_LX
1134                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1135                                 if (hw->bus.lan_id == 0)
1136                                         hw->phy.sfp_type =
1137                                                 ixgbe_sfp_type_1g_lx_core0;
1138                                 else
1139                                         hw->phy.sfp_type =
1140                                                 ixgbe_sfp_type_1g_lx_core1;
1141 #endif /* SUPPORT_1000BASE_LX */
1142                         } else {
1143                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1144                         }
1145                 }
1146
1147                 if (hw->phy.sfp_type != stored_sfp_type)
1148                         hw->phy.sfp_setup_needed = true;
1149
1150                 /* Determine if the SFP+ PHY is dual speed or not. */
1151                 hw->phy.multispeed_fiber = false;
1152                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1153                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1154                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1155                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1156                         hw->phy.multispeed_fiber = true;
1157
1158                 /* Determine PHY vendor */
1159                 if (hw->phy.type != ixgbe_phy_nl) {
1160                         hw->phy.id = identifier;
1161                         status = hw->phy.ops.read_i2c_eeprom(hw,
1162                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1163                                                     &oui_bytes[0]);
1164
1165                         if (status != IXGBE_SUCCESS)
1166                                 goto err_read_i2c_eeprom;
1167
1168                         status = hw->phy.ops.read_i2c_eeprom(hw,
1169                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1170                                                     &oui_bytes[1]);
1171
1172                         if (status != IXGBE_SUCCESS)
1173                                 goto err_read_i2c_eeprom;
1174
1175                         status = hw->phy.ops.read_i2c_eeprom(hw,
1176                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1177                                                     &oui_bytes[2]);
1178
1179                         if (status != IXGBE_SUCCESS)
1180                                 goto err_read_i2c_eeprom;
1181
1182                         vendor_oui =
1183                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1184                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1185                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1186
1187                         switch (vendor_oui) {
1188                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1189                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1190                                         hw->phy.type =
1191                                                     ixgbe_phy_sfp_passive_tyco;
1192                                 break;
1193                         case IXGBE_SFF_VENDOR_OUI_FTL:
1194                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1195                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1196                                 else
1197                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1198                                 break;
1199                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1200                                 hw->phy.type = ixgbe_phy_sfp_avago;
1201                                 break;
1202                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1203                                 hw->phy.type = ixgbe_phy_sfp_intel;
1204                                 break;
1205                         default:
1206                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1207                                         hw->phy.type =
1208                                                  ixgbe_phy_sfp_passive_unknown;
1209                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1210                                         hw->phy.type =
1211                                                 ixgbe_phy_sfp_active_unknown;
1212                                 else
1213                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1214                                 break;
1215                         }
1216                 }
1217
1218                 /* Allow any DA cable vendor */
1219                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1220                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1221                         status = IXGBE_SUCCESS;
1222                         goto out;
1223                 }
1224
1225                 /* Verify supported 1G SFP modules */
1226                 if (comp_codes_10g == 0 &&
1227                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1228                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1229 #ifdef SUPPORT_1000BASE_LX
1230                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1231                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1232 #endif
1233                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1234                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1235                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1236                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1237                         goto out;
1238                 }
1239
1240                 /* Anything else 82598-based is supported */
1241                 if (hw->mac.type == ixgbe_mac_82598EB) {
1242                         status = IXGBE_SUCCESS;
1243                         goto out;
1244                 }
1245
1246                 ixgbe_get_device_caps(hw, &enforce_sfp);
1247                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1248                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1249                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1250 #ifdef SUPPORT_1000BASE_LX
1251                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1252                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1253 #endif
1254 #ifdef SUPPORT_10GBASE_ER
1255                       hw->phy.sfp_type == ixgbe_sfp_type_er_core0 ||
1256                       hw->phy.sfp_type == ixgbe_sfp_type_er_core1 ||
1257 #endif
1258                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1259                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1260                         /* Make sure we're a supported PHY type */
1261                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1262                                 status = IXGBE_SUCCESS;
1263                         } else {
1264                                 if (hw->allow_unsupported_sfp == true) {
1265                                         EWARN(hw, "WARNING: Intel (R) Network "
1266                                               "Connections are quality tested "
1267                                               "using Intel (R) Ethernet Optics."
1268                                               " Using untested modules is not "
1269                                               "supported and may cause unstable"
1270                                               " operation or damage to the "
1271                                               "module or the adapter. Intel "
1272                                               "Corporation is not responsible "
1273                                               "for any harm caused by using "
1274                                               "untested modules.\n", status);
1275                                         status = IXGBE_SUCCESS;
1276                                 } else {
1277                                         DEBUGOUT("SFP+ module not supported\n");
1278                                         hw->phy.type =
1279                                                 ixgbe_phy_sfp_unsupported;
1280                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1281                                 }
1282                         }
1283                 } else {
1284                         status = IXGBE_SUCCESS;
1285                 }
1286         }
1287
1288 out:
1289         return status;
1290
1291 err_read_i2c_eeprom:
1292         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1293         if (hw->phy.type != ixgbe_phy_nl) {
1294                 hw->phy.id = 0;
1295                 hw->phy.type = ixgbe_phy_unknown;
1296         }
1297         return IXGBE_ERR_SFP_NOT_PRESENT;
1298 }
1299
1300 /**
1301  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1302  *  @hw: pointer to hardware structure
1303  *
1304  *  Determines physical layer capabilities of the current SFP.
1305  */
1306 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1307 {
1308         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1309         u8 comp_codes_10g = 0;
1310         u8 comp_codes_1g = 0;
1311
1312         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1313
1314         hw->phy.ops.identify_sfp(hw);
1315         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1316                 return physical_layer;
1317
1318         switch (hw->phy.type) {
1319         case ixgbe_phy_sfp_passive_tyco:
1320         case ixgbe_phy_sfp_passive_unknown:
1321                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1322                 break;
1323         case ixgbe_phy_sfp_ftl_active:
1324         case ixgbe_phy_sfp_active_unknown:
1325                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1326                 break;
1327         case ixgbe_phy_sfp_avago:
1328         case ixgbe_phy_sfp_ftl:
1329         case ixgbe_phy_sfp_intel:
1330         case ixgbe_phy_sfp_unknown:
1331                 hw->phy.ops.read_i2c_eeprom(hw,
1332                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1333                 hw->phy.ops.read_i2c_eeprom(hw,
1334                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1335                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1336                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1337                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1338                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1339                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1340                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1341                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1342                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1343                 break;
1344         default:
1345                 break;
1346         }
1347
1348         return physical_layer;
1349 }
1350
1351
1352 /**
1353  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1354  *  @hw: pointer to hardware structure
1355  *  @list_offset: offset to the SFP ID list
1356  *  @data_offset: offset to the SFP data block
1357  *
1358  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1359  *  so it returns the offsets to the phy init sequence block.
1360  **/
1361 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1362                                         u16 *list_offset,
1363                                         u16 *data_offset)
1364 {
1365         u16 sfp_id;
1366         u16 sfp_type = hw->phy.sfp_type;
1367
1368         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1369
1370         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1371                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1372
1373         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1374                 return IXGBE_ERR_SFP_NOT_PRESENT;
1375
1376         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1377             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1378                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1379
1380         /*
1381          * Limiting active cables and 1G Phys must be initialized as
1382          * SR modules
1383          */
1384         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1385 #ifdef SUPPORT_10GBASE_ER
1386             sfp_type == ixgbe_sfp_type_er_core0 ||
1387 #endif /* SUPPORT_10GBASE_ER */
1388 #ifdef SUPPORT_1000BASE_LX
1389             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1390 #endif /* SUPPORT_1000BASE_LX */
1391             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1392             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1393                 sfp_type = ixgbe_sfp_type_srlr_core0;
1394         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1395 #ifdef SUPPORT_10GBASE_ER
1396                  sfp_type == ixgbe_sfp_type_er_core1 ||
1397 #endif /* SUPPORT_10GBASE_ER */
1398 #ifdef SUPPORT_1000BASE_LX
1399                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1400 #endif /* SUPPORT_1000BASE_LX */
1401                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1402                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1403                 sfp_type = ixgbe_sfp_type_srlr_core1;
1404
1405         /* Read offset to PHY init contents */
1406         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1407                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1408                               "eeprom read at offset %d failed",
1409                               IXGBE_PHY_INIT_OFFSET_NL);
1410                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1411         }
1412
1413         if ((!*list_offset) || (*list_offset == 0xFFFF))
1414                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1415
1416         /* Shift offset to first ID word */
1417         (*list_offset)++;
1418
1419         /*
1420          * Find the matching SFP ID in the EEPROM
1421          * and program the init sequence
1422          */
1423         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1424                 goto err_phy;
1425
1426         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1427                 if (sfp_id == sfp_type) {
1428                         (*list_offset)++;
1429                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1430                                 goto err_phy;
1431                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1432                                 DEBUGOUT("SFP+ module not supported\n");
1433                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1434                         } else {
1435                                 break;
1436                         }
1437                 } else {
1438                         (*list_offset) += 2;
1439                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1440                                 goto err_phy;
1441                 }
1442         }
1443
1444         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1445                 DEBUGOUT("No matching SFP+ module found\n");
1446                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1447         }
1448
1449         return IXGBE_SUCCESS;
1450
1451 err_phy:
1452         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1453                       "eeprom read at offset %d failed", *list_offset);
1454         return IXGBE_ERR_PHY;
1455 }
1456
1457 /**
1458  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1459  *  @hw: pointer to hardware structure
1460  *  @byte_offset: EEPROM byte offset to read
1461  *  @eeprom_data: value read
1462  *
1463  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1464  **/
1465 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1466                                   u8 *eeprom_data)
1467 {
1468         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1469
1470         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1471                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1472                                          eeprom_data);
1473 }
1474
1475 /**
1476  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1477  *  @hw: pointer to hardware structure
1478  *  @byte_offset: byte offset at address 0xA2
1479  *  @eeprom_data: value read
1480  *
1481  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1482  **/
1483 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1484                                           u8 *sff8472_data)
1485 {
1486         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1487                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1488                                          sff8472_data);
1489 }
1490
1491 /**
1492  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1493  *  @hw: pointer to hardware structure
1494  *  @byte_offset: EEPROM byte offset to write
1495  *  @eeprom_data: value to write
1496  *
1497  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1498  **/
1499 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1500                                    u8 eeprom_data)
1501 {
1502         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1503
1504         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1505                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1506                                           eeprom_data);
1507 }
1508
1509 /**
1510  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1511  *  @hw: pointer to hardware structure
1512  *  @byte_offset: byte offset to read
1513  *  @data: value read
1514  *
1515  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1516  *  a specified device address.
1517  **/
1518 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1519                                 u8 dev_addr, u8 *data)
1520 {
1521         s32 status;
1522         u32 max_retry = 10;
1523         u32 retry = 0;
1524         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1525         bool nack = 1;
1526         *data = 0;
1527
1528         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1529
1530         do {
1531                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1532                         return IXGBE_ERR_SWFW_SYNC;
1533
1534                 ixgbe_i2c_start(hw);
1535
1536                 /* Device Address and write indication */
1537                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1538                 if (status != IXGBE_SUCCESS)
1539                         goto fail;
1540
1541                 status = ixgbe_get_i2c_ack(hw);
1542                 if (status != IXGBE_SUCCESS)
1543                         goto fail;
1544
1545                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1546                 if (status != IXGBE_SUCCESS)
1547                         goto fail;
1548
1549                 status = ixgbe_get_i2c_ack(hw);
1550                 if (status != IXGBE_SUCCESS)
1551                         goto fail;
1552
1553                 ixgbe_i2c_start(hw);
1554
1555                 /* Device Address and read indication */
1556                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1557                 if (status != IXGBE_SUCCESS)
1558                         goto fail;
1559
1560                 status = ixgbe_get_i2c_ack(hw);
1561                 if (status != IXGBE_SUCCESS)
1562                         goto fail;
1563
1564                 status = ixgbe_clock_in_i2c_byte(hw, data);
1565                 if (status != IXGBE_SUCCESS)
1566                         goto fail;
1567
1568                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1569                 if (status != IXGBE_SUCCESS)
1570                         goto fail;
1571
1572                 ixgbe_i2c_stop(hw);
1573                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1574                 return IXGBE_SUCCESS;
1575
1576 fail:
1577                 ixgbe_i2c_bus_clear(hw);
1578                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1579                 msec_delay(100);
1580                 retry++;
1581                 if (retry < max_retry)
1582                         DEBUGOUT("I2C byte read error - Retrying.\n");
1583                 else
1584                         DEBUGOUT("I2C byte read error.\n");
1585
1586         } while (retry < max_retry);
1587
1588         return status;
1589 }
1590
1591 /**
1592  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1593  *  @hw: pointer to hardware structure
1594  *  @byte_offset: byte offset to write
1595  *  @data: value to write
1596  *
1597  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1598  *  a specified device address.
1599  **/
1600 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1601                                  u8 dev_addr, u8 data)
1602 {
1603         s32 status = IXGBE_SUCCESS;
1604         u32 max_retry = 1;
1605         u32 retry = 0;
1606         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1607
1608         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1609
1610         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1611                 status = IXGBE_ERR_SWFW_SYNC;
1612                 goto write_byte_out;
1613         }
1614
1615         do {
1616                 ixgbe_i2c_start(hw);
1617
1618                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1619                 if (status != IXGBE_SUCCESS)
1620                         goto fail;
1621
1622                 status = ixgbe_get_i2c_ack(hw);
1623                 if (status != IXGBE_SUCCESS)
1624                         goto fail;
1625
1626                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1627                 if (status != IXGBE_SUCCESS)
1628                         goto fail;
1629
1630                 status = ixgbe_get_i2c_ack(hw);
1631                 if (status != IXGBE_SUCCESS)
1632                         goto fail;
1633
1634                 status = ixgbe_clock_out_i2c_byte(hw, data);
1635                 if (status != IXGBE_SUCCESS)
1636                         goto fail;
1637
1638                 status = ixgbe_get_i2c_ack(hw);
1639                 if (status != IXGBE_SUCCESS)
1640                         goto fail;
1641
1642                 ixgbe_i2c_stop(hw);
1643                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1644                 return IXGBE_SUCCESS;
1645
1646 fail:
1647                 ixgbe_i2c_bus_clear(hw);
1648                 retry++;
1649                 if (retry < max_retry)
1650                         DEBUGOUT("I2C byte write error - Retrying.\n");
1651                 else
1652                         DEBUGOUT("I2C byte write error.\n");
1653         } while (retry < max_retry);
1654
1655         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1656
1657 write_byte_out:
1658         return status;
1659 }
1660
1661 /**
1662  *  ixgbe_i2c_start - Sets I2C start condition
1663  *  @hw: pointer to hardware structure
1664  *
1665  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1666  **/
1667 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
1668 {
1669         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1670
1671         DEBUGFUNC("ixgbe_i2c_start");
1672
1673         /* Start condition must begin with data and clock high */
1674         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1675         ixgbe_raise_i2c_clk(hw, &i2cctl);
1676
1677         /* Setup time for start condition (4.7us) */
1678         usec_delay(IXGBE_I2C_T_SU_STA);
1679
1680         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1681
1682         /* Hold time for start condition (4us) */
1683         usec_delay(IXGBE_I2C_T_HD_STA);
1684
1685         ixgbe_lower_i2c_clk(hw, &i2cctl);
1686
1687         /* Minimum low period of clock is 4.7 us */
1688         usec_delay(IXGBE_I2C_T_LOW);
1689
1690 }
1691
1692 /**
1693  *  ixgbe_i2c_stop - Sets I2C stop condition
1694  *  @hw: pointer to hardware structure
1695  *
1696  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1697  **/
1698 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1699 {
1700         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1701
1702         DEBUGFUNC("ixgbe_i2c_stop");
1703
1704         /* Stop condition must begin with data low and clock high */
1705         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1706         ixgbe_raise_i2c_clk(hw, &i2cctl);
1707
1708         /* Setup time for stop condition (4us) */
1709         usec_delay(IXGBE_I2C_T_SU_STO);
1710
1711         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1712
1713         /* bus free time between stop and start (4.7us)*/
1714         usec_delay(IXGBE_I2C_T_BUF);
1715 }
1716
1717 /**
1718  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1719  *  @hw: pointer to hardware structure
1720  *  @data: data byte to clock in
1721  *
1722  *  Clocks in one byte data via I2C data/clock
1723  **/
1724 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1725 {
1726         s32 i;
1727         bool bit = 0;
1728
1729         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1730
1731         for (i = 7; i >= 0; i--) {
1732                 ixgbe_clock_in_i2c_bit(hw, &bit);
1733                 *data |= bit << i;
1734         }
1735
1736         return IXGBE_SUCCESS;
1737 }
1738
1739 /**
1740  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1741  *  @hw: pointer to hardware structure
1742  *  @data: data byte clocked out
1743  *
1744  *  Clocks out one byte data via I2C data/clock
1745  **/
1746 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1747 {
1748         s32 status = IXGBE_SUCCESS;
1749         s32 i;
1750         u32 i2cctl;
1751         bool bit;
1752
1753         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1754
1755         for (i = 7; i >= 0; i--) {
1756                 bit = (data >> i) & 0x1;
1757                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1758
1759                 if (status != IXGBE_SUCCESS)
1760                         break;
1761         }
1762
1763         /* Release SDA line (set high) */
1764         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1765         i2cctl |= IXGBE_I2C_DATA_OUT;
1766         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1767         IXGBE_WRITE_FLUSH(hw);
1768
1769         return status;
1770 }
1771
1772 /**
1773  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1774  *  @hw: pointer to hardware structure
1775  *
1776  *  Clocks in/out one bit via I2C data/clock
1777  **/
1778 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1779 {
1780         s32 status = IXGBE_SUCCESS;
1781         u32 i = 0;
1782         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1783         u32 timeout = 10;
1784         bool ack = 1;
1785
1786         DEBUGFUNC("ixgbe_get_i2c_ack");
1787
1788         ixgbe_raise_i2c_clk(hw, &i2cctl);
1789
1790
1791         /* Minimum high period of clock is 4us */
1792         usec_delay(IXGBE_I2C_T_HIGH);
1793
1794         /* Poll for ACK.  Note that ACK in I2C spec is
1795          * transition from 1 to 0 */
1796         for (i = 0; i < timeout; i++) {
1797                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1798                 ack = ixgbe_get_i2c_data(&i2cctl);
1799
1800                 usec_delay(1);
1801                 if (!ack)
1802                         break;
1803         }
1804
1805         if (ack == 1) {
1806                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1807                              "I2C ack was not received.\n");
1808                 status = IXGBE_ERR_I2C;
1809         }
1810
1811         ixgbe_lower_i2c_clk(hw, &i2cctl);
1812
1813         /* Minimum low period of clock is 4.7 us */
1814         usec_delay(IXGBE_I2C_T_LOW);
1815
1816         return status;
1817 }
1818
1819 /**
1820  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1821  *  @hw: pointer to hardware structure
1822  *  @data: read data value
1823  *
1824  *  Clocks in one bit via I2C data/clock
1825  **/
1826 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1827 {
1828         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1829
1830         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1831
1832         ixgbe_raise_i2c_clk(hw, &i2cctl);
1833
1834         /* Minimum high period of clock is 4us */
1835         usec_delay(IXGBE_I2C_T_HIGH);
1836
1837         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1838         *data = ixgbe_get_i2c_data(&i2cctl);
1839
1840         ixgbe_lower_i2c_clk(hw, &i2cctl);
1841
1842         /* Minimum low period of clock is 4.7 us */
1843         usec_delay(IXGBE_I2C_T_LOW);
1844
1845         return IXGBE_SUCCESS;
1846 }
1847
1848 /**
1849  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1850  *  @hw: pointer to hardware structure
1851  *  @data: data value to write
1852  *
1853  *  Clocks out one bit via I2C data/clock
1854  **/
1855 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1856 {
1857         s32 status;
1858         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1859
1860         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1861
1862         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1863         if (status == IXGBE_SUCCESS) {
1864                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1865
1866                 /* Minimum high period of clock is 4us */
1867                 usec_delay(IXGBE_I2C_T_HIGH);
1868
1869                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1870
1871                 /* Minimum low period of clock is 4.7 us.
1872                  * This also takes care of the data hold time.
1873                  */
1874                 usec_delay(IXGBE_I2C_T_LOW);
1875         } else {
1876                 status = IXGBE_ERR_I2C;
1877                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1878                              "I2C data was not set to %X\n", data);
1879         }
1880
1881         return status;
1882 }
1883
1884 /**
1885  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1886  *  @hw: pointer to hardware structure
1887  *  @i2cctl: Current value of I2CCTL register
1888  *
1889  *  Raises the I2C clock line '0'->'1'
1890  **/
1891 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1892 {
1893         u32 i = 0;
1894         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1895         u32 i2cctl_r = 0;
1896
1897         DEBUGFUNC("ixgbe_raise_i2c_clk");
1898
1899         for (i = 0; i < timeout; i++) {
1900                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1901
1902                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1903                 IXGBE_WRITE_FLUSH(hw);
1904                 /* SCL rise time (1000ns) */
1905                 usec_delay(IXGBE_I2C_T_RISE);
1906
1907                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1908                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1909                         break;
1910         }
1911 }
1912
1913 /**
1914  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1915  *  @hw: pointer to hardware structure
1916  *  @i2cctl: Current value of I2CCTL register
1917  *
1918  *  Lowers the I2C clock line '1'->'0'
1919  **/
1920 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1921 {
1922
1923         DEBUGFUNC("ixgbe_lower_i2c_clk");
1924
1925         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1926
1927         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1928         IXGBE_WRITE_FLUSH(hw);
1929
1930         /* SCL fall time (300ns) */
1931         usec_delay(IXGBE_I2C_T_FALL);
1932 }
1933
1934 /**
1935  *  ixgbe_set_i2c_data - Sets the I2C data bit
1936  *  @hw: pointer to hardware structure
1937  *  @i2cctl: Current value of I2CCTL register
1938  *  @data: I2C data value (0 or 1) to set
1939  *
1940  *  Sets the I2C data bit
1941  **/
1942 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1943 {
1944         s32 status = IXGBE_SUCCESS;
1945
1946         DEBUGFUNC("ixgbe_set_i2c_data");
1947
1948         if (data)
1949                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1950         else
1951                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1952
1953         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1954         IXGBE_WRITE_FLUSH(hw);
1955
1956         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1957         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1958
1959         /* Verify data was set correctly */
1960         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1961         if (data != ixgbe_get_i2c_data(i2cctl)) {
1962                 status = IXGBE_ERR_I2C;
1963                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1964                              "Error - I2C data was not set to %X.\n",
1965                              data);
1966         }
1967
1968         return status;
1969 }
1970
1971 /**
1972  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1973  *  @hw: pointer to hardware structure
1974  *  @i2cctl: Current value of I2CCTL register
1975  *
1976  *  Returns the I2C data bit value
1977  **/
1978 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
1979 {
1980         bool data;
1981
1982         DEBUGFUNC("ixgbe_get_i2c_data");
1983
1984         if (*i2cctl & IXGBE_I2C_DATA_IN)
1985                 data = 1;
1986         else
1987                 data = 0;
1988
1989         return data;
1990 }
1991
1992 /**
1993  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1994  *  @hw: pointer to hardware structure
1995  *
1996  *  Clears the I2C bus by sending nine clock pulses.
1997  *  Used when data line is stuck low.
1998  **/
1999 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2000 {
2001         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2002         u32 i;
2003
2004         DEBUGFUNC("ixgbe_i2c_bus_clear");
2005
2006         ixgbe_i2c_start(hw);
2007
2008         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2009
2010         for (i = 0; i < 9; i++) {
2011                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2012
2013                 /* Min high period of clock is 4us */
2014                 usec_delay(IXGBE_I2C_T_HIGH);
2015
2016                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2017
2018                 /* Min low period of clock is 4.7us*/
2019                 usec_delay(IXGBE_I2C_T_LOW);
2020         }
2021
2022         ixgbe_i2c_start(hw);
2023
2024         /* Put the i2c bus back to default state */
2025         ixgbe_i2c_stop(hw);
2026 }
2027
2028 /**
2029  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2030  *  @hw: pointer to hardware structure
2031  *
2032  *  Checks if the LASI temp alarm status was triggered due to overtemp
2033  **/
2034 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2035 {
2036         s32 status = IXGBE_SUCCESS;
2037         u16 phy_data = 0;
2038
2039         DEBUGFUNC("ixgbe_tn_check_overtemp");
2040
2041         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2042                 goto out;
2043
2044         /* Check that the LASI temp alarm status was triggered */
2045         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2046                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2047
2048         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2049                 goto out;
2050
2051         status = IXGBE_ERR_OVERTEMP;
2052         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2053 out:
2054         return status;
2055 }