lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37 #ident "$Id: ixgbe_phy.c,v 1.155 2013/08/14 22:34:03 jtkirshe Exp $"
  38
  39 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
  50 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  51                                           u8 *sff8472_data);
  52
  53 /**
  54  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  55  *  @hw: pointer to the hardware structure
  56  *
  57  *  Initialize the function pointers.
  58  **/
  59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_phy_info *phy = &hw->phy;
  62
  63         DEBUGFUNC("ixgbe_init_phy_ops_generic");
  64
  65         /* PHY */
  66         phy->ops.identify = &ixgbe_identify_phy_generic;
  67         phy->ops.reset = &ixgbe_reset_phy_generic;
  68         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  69         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  70         phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
  71         phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
  72         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  73         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  74         phy->ops.check_link = NULL;
  75         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  76         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  77         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  78         phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
  79         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  80         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  81         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  82         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  83         phy->sfp_type = ixgbe_sfp_type_unknown;
  84         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  85         return IXGBE_SUCCESS;
  86 }
  87
  88 /**
  89  *  ixgbe_identify_phy_generic - Get physical layer module
  90  *  @hw: pointer to hardware structure
  91  *
  92  *  Determines the physical layer module found on the current adapter.
  93  **/
  94 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  95 {
  96         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  97         u32 phy_addr;
  98         u16 ext_ability = 0;
  99
 100         DEBUGFUNC("ixgbe_identify_phy_generic");
 101
 102         if (!hw->phy.phy_semaphore_mask) {
 103                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
 104                                                 IXGBE_STATUS_LAN_ID_1;
 105                 if (hw->phy.lan_id)
 106                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 107                 else
 108                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 109         }
 110
 111         if (hw->phy.type == ixgbe_phy_unknown) {
 112                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 113                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 114                                 hw->phy.addr = phy_addr;
 115                                 ixgbe_get_phy_id(hw);
 116                                 hw->phy.type =
 117                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 118
 119                                 if (hw->phy.type == ixgbe_phy_unknown) {
 120                                         hw->phy.ops.read_reg(hw,
 121                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 122                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 123                                                   &ext_ability);
 124                                         if (ext_ability &
 125                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 126                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 127                                                 hw->phy.type =
 128                                                          ixgbe_phy_cu_unknown;
 129                                         else
 130                                                 hw->phy.type =
 131                                                          ixgbe_phy_generic;
 132                                 }
 133
 134                                 status = IXGBE_SUCCESS;
 135                                 break;
 136                         }
 137                 }
 138
 139                 /* Certain media types do not have a phy so an address will not
 140                  * be found and the code will take this path.  Caller has to
 141                  * decide if it is an error or not.
 142                  */
 143                 if (status != IXGBE_SUCCESS) {
 144                         hw->phy.addr = 0;
 145                 }
 146         } else {
 147                 status = IXGBE_SUCCESS;
 148         }
 149
 150         return status;
 151 }
 152
 153 /**
 154  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 155  * @hw: pointer to the hardware structure
 156  *
 157  * This function checks the MMNGC.MNG_VETO bit to see if there are
 158  * any constraints on link from manageability.  For MAC's that don't
 159  * have this bit just return faluse since the link can not be blocked
 160  * via this method.
 161  **/
 162 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 163 {
 164         u32 mmngc;
 165
 166         DEBUGFUNC("ixgbe_check_reset_blocked");
 167
 168         /* If we don't have this bit, it can't be blocking */
 169         if (hw->mac.type == ixgbe_mac_82598EB)
 170                 return false;
 171
 172         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 173         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 174                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 175                               "MNG_VETO bit detected.\n");
 176                 return true;
 177         }
 178
 179         return false;
 180 }
 181
 182 /**
 183  *  ixgbe_validate_phy_addr - Determines phy address is valid
 184  *  @hw: pointer to hardware structure
 185  *
 186  **/
 187 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 188 {
 189         u16 phy_id = 0;
 190         bool valid = false;
 191
 192         DEBUGFUNC("ixgbe_validate_phy_addr");
 193
 194         hw->phy.addr = phy_addr;
 195         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 196                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 197
 198         if (phy_id != 0xFFFF && phy_id != 0x0)
 199                 valid = true;
 200
 201         return valid;
 202 }
 203
 204 /**
 205  *  ixgbe_get_phy_id - Get the phy type
 206  *  @hw: pointer to hardware structure
 207  *
 208  **/
 209 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 210 {
 211         u32 status;
 212         u16 phy_id_high = 0;
 213         u16 phy_id_low = 0;
 214
 215         DEBUGFUNC("ixgbe_get_phy_id");
 216
 217         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 218                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 219                                       &phy_id_high);
 220
 221         if (status == IXGBE_SUCCESS) {
 222                 hw->phy.id = (u32)(phy_id_high << 16);
 223                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 224                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 225                                               &phy_id_low);
 226                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 227                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 228         }
 229         return status;
 230 }
 231
 232 /**
 233  *  ixgbe_get_phy_type_from_id - Get the phy type
 234  *  @hw: pointer to hardware structure
 235  *
 236  **/
 237 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 238 {
 239         enum ixgbe_phy_type phy_type;
 240
 241         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 242
 243         switch (phy_id) {
 244         case TN1010_PHY_ID:
 245                 phy_type = ixgbe_phy_tn;
 246                 break;
 247         case X540_PHY_ID:
 248                 phy_type = ixgbe_phy_aq;
 249                 break;
 250         case QT2022_PHY_ID:
 251                 phy_type = ixgbe_phy_qt;
 252                 break;
 253         case ATH_PHY_ID:
 254                 phy_type = ixgbe_phy_nl;
 255                 break;
 256         default:
 257                 phy_type = ixgbe_phy_unknown;
 258                 break;
 259         }
 260
 261         DEBUGOUT1("phy type found is %d\n", phy_type);
 262         return phy_type;
 263 }
 264
 265 /**
 266  *  ixgbe_reset_phy_generic - Performs a PHY reset
 267  *  @hw: pointer to hardware structure
 268  **/
 269 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 270 {
 271         u32 i;
 272         u16 ctrl = 0;
 273         s32 status = IXGBE_SUCCESS;
 274
 275         DEBUGFUNC("ixgbe_reset_phy_generic");
 276
 277         if (hw->phy.type == ixgbe_phy_unknown)
 278                 status = ixgbe_identify_phy_generic(hw);
 279
 280         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 281                 goto out;
 282
 283         /* Don't reset PHY if it's shut down due to overtemp. */
 284         if (!hw->phy.reset_if_overtemp &&
 285             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 286                 goto out;
 287
 288         /* Blocked by MNG FW so bail */
 289         if (ixgbe_check_reset_blocked(hw))
 290                 goto out;
 291
 292         /*
 293          * Perform soft PHY reset to the PHY_XS.
 294          * This will cause a soft reset to the PHY
 295          */
 296         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 297                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 298                               IXGBE_MDIO_PHY_XS_RESET);
 299
 300         /*
 301          * Poll for reset bit to self-clear indicating reset is complete.
 302          * Some PHYs could take up to 3 seconds to complete and need about
 303          * 1.7 usec delay after the reset is complete.
 304          */
 305         for (i = 0; i < 30; i++) {
 306                 msec_delay(100);
 307                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 308                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 309                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 310                         usec_delay(2);
 311                         break;
 312                 }
 313         }
 314
 315         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 316                 status = IXGBE_ERR_RESET_FAILED;
 317                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 318                              "PHY reset polling failed to complete.\n");
 319         }
 320
 321 out:
 322         return status;
 323 }
 324
 325 /**
 326  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 327  *  the SWFW lock
 328  *  @hw: pointer to hardware structure
 329  *  @reg_addr: 32 bit address of PHY register to read
 330  *  @phy_data: Pointer to read data from PHY register
 331  **/
 332 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 333                        u16 *phy_data)
 334 {
 335         u32 i, data, command;
 336
 337         /* Setup and write the address cycle command */
 338         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 339                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 340                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 341                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 342
 343         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 344
 345         /*
 346          * Check every 10 usec to see if the address cycle completed.
 347          * The MDI Command bit will clear when the operation is
 348          * complete
 349          */
 350         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 351                 usec_delay(10);
 352
 353                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 354                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 355                                 break;
 356         }
 357
 358
 359         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 360                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 361                 return IXGBE_ERR_PHY;
 362         }
 363
 364         /*
 365          * Address cycle complete, setup and write the read
 366          * command
 367          */
 368         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 369                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 370                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 371                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 372
 373         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 374
 375         /*
 376          * Check every 10 usec to see if the address cycle
 377          * completed. The MDI Command bit will clear when the
 378          * operation is complete
 379          */
 380         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 381                 usec_delay(10);
 382
 383                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 384                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 385                         break;
 386         }
 387
 388         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 389                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 390                 return IXGBE_ERR_PHY;
 391         }
 392
 393         /*
 394          * Read operation is complete.  Get the data
 395          * from MSRWD
 396          */
 397         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 398         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 399         *phy_data = (u16)(data);
 400
 401         return IXGBE_SUCCESS;
 402 }
 403
 404 /**
 405  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 406  *  using the SWFW lock - this function is needed in most cases
 407  *  @hw: pointer to hardware structure
 408  *  @reg_addr: 32 bit address of PHY register to read
 409  *  @phy_data: Pointer to read data from PHY register
 410  **/
 411 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 412                                u32 device_type, u16 *phy_data)
 413 {
 414         s32 status;
 415         u32 gssr = hw->phy.phy_semaphore_mask;
 416
 417         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 418
 419         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 420                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 421                                                 phy_data);
 422                 hw->mac.ops.release_swfw_sync(hw, gssr);
 423         } else {
 424                 status = IXGBE_ERR_SWFW_SYNC;
 425         }
 426
 427         return status;
 428 }
 429
 430 /**
 431  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 432  *  without SWFW lock
 433  *  @hw: pointer to hardware structure
 434  *  @reg_addr: 32 bit PHY register to write
 435  *  @device_type: 5 bit device type
 436  *  @phy_data: Data to write to the PHY register
 437  **/
 438 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 439                                 u32 device_type, u16 phy_data)
 440 {
 441         u32 i, command;
 442
 443         /* Put the data in the MDI single read and write data register*/
 444         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 445
 446         /* Setup and write the address cycle command */
 447         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 448                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 449                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 450                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 451
 452         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 453
 454         /*
 455          * Check every 10 usec to see if the address cycle completed.
 456          * The MDI Command bit will clear when the operation is
 457          * complete
 458          */
 459         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 460                 usec_delay(10);
 461
 462                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 463                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 464                         break;
 465         }
 466
 467         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 468                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 469                 return IXGBE_ERR_PHY;
 470         }
 471
 472         /*
 473          * Address cycle complete, setup and write the write
 474          * command
 475          */
 476         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 477                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 478                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 479                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 480
 481         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 482
 483         /*
 484          * Check every 10 usec to see if the address cycle
 485          * completed. The MDI Command bit will clear when the
 486          * operation is complete
 487          */
 488         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 489                 usec_delay(10);
 490
 491                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 492                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 493                         break;
 494         }
 495
 496         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 497                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 498                 return IXGBE_ERR_PHY;
 499         }
 500
 501         return IXGBE_SUCCESS;
 502 }
 503
 504 /**
 505  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 506  *  using SWFW lock- this function is needed in most cases
 507  *  @hw: pointer to hardware structure
 508  *  @reg_addr: 32 bit PHY register to write
 509  *  @device_type: 5 bit device type
 510  *  @phy_data: Data to write to the PHY register
 511  **/
 512 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 513                                 u32 device_type, u16 phy_data)
 514 {
 515         s32 status;
 516         u32 gssr = hw->phy.phy_semaphore_mask;
 517
 518         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 519
 520         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 521                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 522                                                  phy_data);
 523                 hw->mac.ops.release_swfw_sync(hw, gssr);
 524         } else {
 525                 status = IXGBE_ERR_SWFW_SYNC;
 526         }
 527
 528         return status;
 529 }
 530
 531 /**
 532  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 533  *  @hw: pointer to hardware structure
 534  *
 535  *  Restart auto-negotiation and PHY and waits for completion.
 536  **/
 537 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 538 {
 539         s32 status = IXGBE_SUCCESS;
 540         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 541         bool autoneg = false;
 542         ixgbe_link_speed speed;
 543
 544         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 545
 546         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 547
 548         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 549                 /* Set or unset auto-negotiation 10G advertisement */
 550                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 551                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 552                                      &autoneg_reg);
 553
 554                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 555                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 556                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 557
 558                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 559                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 560                                       autoneg_reg);
 561         }
 562
 563         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 564                 /* Set or unset auto-negotiation 1G advertisement */
 565                 hw->phy.ops.read_reg(hw,
 566                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 567                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 568                                      &autoneg_reg);
 569
 570                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 571                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 572                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 573
 574                 hw->phy.ops.write_reg(hw,
 575                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 576                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 577                                       autoneg_reg);
 578         }
 579
 580         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 581                 /* Set or unset auto-negotiation 100M advertisement */
 582                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 583                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 584                                      &autoneg_reg);
 585
 586                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 587                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 588                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 589                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 590
 591                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 592                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 593                                       autoneg_reg);
 594         }
 595
 596         /* Blocked by MNG FW so don't reset PHY */
 597         if (ixgbe_check_reset_blocked(hw))
 598                 return status;
 599
 600         /* Restart PHY auto-negotiation. */
 601         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 602                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 603
 604         autoneg_reg |= IXGBE_MII_RESTART;
 605
 606         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 607                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 608
 609         return status;
 610 }
 611
 612 /**
 613  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 614  *  @hw: pointer to hardware structure
 615  *  @speed: new link speed
 616  **/
 617 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 618                                        ixgbe_link_speed speed,
 619                                        bool autoneg_wait_to_complete)
 620 {
 621         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 622
 623         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 624
 625         /*
 626          * Clear autoneg_advertised and set new values based on input link
 627          * speed.
 628          */
 629         hw->phy.autoneg_advertised = 0;
 630
 631         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 632                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 633
 634         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 635                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 636
 637         if (speed & IXGBE_LINK_SPEED_100_FULL)
 638                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 639
 640         /* Setup link based on the new speed settings */
 641         hw->phy.ops.setup_link(hw);
 642
 643         return IXGBE_SUCCESS;
 644 }
 645
 646 /**
 647  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 648  *  @hw: pointer to hardware structure
 649  *  @speed: pointer to link speed
 650  *  @autoneg: boolean auto-negotiation value
 651  *
 652  *  Determines the link capabilities by reading the AUTOC register.
 653  **/
 654 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 655                                                ixgbe_link_speed *speed,
 656                                                bool *autoneg)
 657 {
 658         s32 status;
 659         u16 speed_ability;
 660
 661         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 662
 663         *speed = 0;
 664         *autoneg = true;
 665
 666         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 667                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 668                                       &speed_ability);
 669
 670         if (status == IXGBE_SUCCESS) {
 671                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 672                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 673                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 674                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 675                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 676                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 677         }
 678
 679         return status;
 680 }
 681
 682 /**
 683  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 684  *  @hw: pointer to hardware structure
 685  *
 686  *  Reads the VS1 register to determine if link is up and the current speed for
 687  *  the PHY.
 688  **/
 689 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 690                              bool *link_up)
 691 {
 692         s32 status = IXGBE_SUCCESS;
 693         u32 time_out;
 694         u32 max_time_out = 10;
 695         u16 phy_link = 0;
 696         u16 phy_speed = 0;
 697         u16 phy_data = 0;
 698
 699         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 700
 701         /* Initialize speed and link to default case */
 702         *link_up = false;
 703         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 704
 705         /*
 706          * Check current speed and link status of the PHY register.
 707          * This is a vendor specific register and may have to
 708          * be changed for other copper PHYs.
 709          */
 710         for (time_out = 0; time_out < max_time_out; time_out++) {
 711                 usec_delay(10);
 712                 status = hw->phy.ops.read_reg(hw,
 713                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 714                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 715                                         &phy_data);
 716                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 717                 phy_speed = phy_data &
 718                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 719                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 720                         *link_up = true;
 721                         if (phy_speed ==
 722                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 723                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 724                         break;
 725                 }
 726         }
 727
 728         return status;
 729 }
 730
 731 /**
 732  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
 733  *      @hw: pointer to hardware structure
 734  *
 735  *      Restart auto-negotiation and PHY and waits for completion.
 736  **/
 737 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 738 {
 739         s32 status = IXGBE_SUCCESS;
 740         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 741         bool autoneg = false;
 742         ixgbe_link_speed speed;
 743
 744         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 745
 746         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 747
 748         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 749                 /* Set or unset auto-negotiation 10G advertisement */
 750                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 751                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 752                                      &autoneg_reg);
 753
 754                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 755                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 756                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 757
 758                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 759                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 760                                       autoneg_reg);
 761         }
 762
 763         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 764                 /* Set or unset auto-negotiation 1G advertisement */
 765                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 766                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 767                                      &autoneg_reg);
 768
 769                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 770                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 771                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 772
 773                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 774                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 775                                       autoneg_reg);
 776         }
 777
 778         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 779                 /* Set or unset auto-negotiation 100M advertisement */
 780                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 781                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 782                                      &autoneg_reg);
 783
 784                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 785                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 786                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 787
 788                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 789                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 790                                       autoneg_reg);
 791         }
 792
 793         /* Blocked by MNG FW so don't reset PHY */
 794         if (ixgbe_check_reset_blocked(hw))
 795                 return status;
 796
 797         /* Restart PHY auto-negotiation. */
 798         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 799                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 800
 801         autoneg_reg |= IXGBE_MII_RESTART;
 802
 803         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 804                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 805
 806         return status;
 807 }
 808
 809 /**
 810  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 811  *  @hw: pointer to hardware structure
 812  *  @firmware_version: pointer to the PHY Firmware Version
 813  **/
 814 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 815                                        u16 *firmware_version)
 816 {
 817         s32 status;
 818
 819         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 820
 821         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 822                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 823                                       firmware_version);
 824
 825         return status;
 826 }
 827
 828 /**
 829  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 830  *  @hw: pointer to hardware structure
 831  *  @firmware_version: pointer to the PHY Firmware Version
 832  **/
 833 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 834                                            u16 *firmware_version)
 835 {
 836         s32 status;
 837
 838         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 839
 840         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 841                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 842                                       firmware_version);
 843
 844         return status;
 845 }
 846
 847 /**
 848  *  ixgbe_reset_phy_nl - Performs a PHY reset
 849  *  @hw: pointer to hardware structure
 850  **/
 851 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 852 {
 853         u16 phy_offset, control, eword, edata, block_crc;
 854         bool end_data = false;
 855         u16 list_offset, data_offset;
 856         u16 phy_data = 0;
 857         s32 ret_val = IXGBE_SUCCESS;
 858         u32 i;
 859
 860         DEBUGFUNC("ixgbe_reset_phy_nl");
 861
 862         /* Blocked by MNG FW so bail */
 863         if (ixgbe_check_reset_blocked(hw))
 864                 goto out;
 865
 866         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 867                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 868
 869         /* reset the PHY and poll for completion */
 870         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 871                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 872                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 873
 874         for (i = 0; i < 100; i++) {
 875                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 876                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 877                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 878                         break;
 879                 msec_delay(10);
 880         }
 881
 882         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 883                 DEBUGOUT("PHY reset did not complete.\n");
 884                 ret_val = IXGBE_ERR_PHY;
 885                 goto out;
 886         }
 887
 888         /* Get init offsets */
 889         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 890                                                       &data_offset);
 891         if (ret_val != IXGBE_SUCCESS)
 892                 goto out;
 893
 894         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 895         data_offset++;
 896         while (!end_data) {
 897                 /*
 898                  * Read control word from PHY init contents offset
 899                  */
 900                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 901                 if (ret_val)
 902                         goto err_eeprom;
 903                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 904                            IXGBE_CONTROL_SHIFT_NL;
 905                 edata = eword & IXGBE_DATA_MASK_NL;
 906                 switch (control) {
 907                 case IXGBE_DELAY_NL:
 908                         data_offset++;
 909                         DEBUGOUT1("DELAY: %d MS\n", edata);
 910                         msec_delay(edata);
 911                         break;
 912                 case IXGBE_DATA_NL:
 913                         DEBUGOUT("DATA:\n");
 914                         data_offset++;
 915                         ret_val = hw->eeprom.ops.read(hw, data_offset,
 916                                                       &phy_offset);
 917                         if (ret_val)
 918                                 goto err_eeprom;
 919                         data_offset++;
 920                         for (i = 0; i < edata; i++) {
 921                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 922                                                               &eword);
 923                                 if (ret_val)
 924                                         goto err_eeprom;
 925                                 hw->phy.ops.write_reg(hw, phy_offset,
 926                                                       IXGBE_TWINAX_DEV, eword);
 927                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
 928                                           phy_offset);
 929                                 data_offset++;
 930                                 phy_offset++;
 931                         }
 932                         break;
 933                 case IXGBE_CONTROL_NL:
 934                         data_offset++;
 935                         DEBUGOUT("CONTROL:\n");
 936                         if (edata == IXGBE_CONTROL_EOL_NL) {
 937                                 DEBUGOUT("EOL\n");
 938                                 end_data = true;
 939                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 940                                 DEBUGOUT("SOL\n");
 941                         } else {
 942                                 DEBUGOUT("Bad control value\n");
 943                                 ret_val = IXGBE_ERR_PHY;
 944                                 goto out;
 945                         }
 946                         break;
 947                 default:
 948                         DEBUGOUT("Bad control type\n");
 949                         ret_val = IXGBE_ERR_PHY;
 950                         goto out;
 951                 }
 952         }
 953
 954 out:
 955         return ret_val;
 956
 957 err_eeprom:
 958         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 959                       "eeprom read at offset %d failed", data_offset);
 960         return IXGBE_ERR_PHY;
 961 }
 962
 963 /**
 964  *  ixgbe_identify_module_generic - Identifies module type
 965  *  @hw: pointer to hardware structure
 966  *
 967  *  Determines HW type and calls appropriate function.
 968  **/
 969 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 970 {
 971         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 972
 973         DEBUGFUNC("ixgbe_identify_module_generic");
 974
 975         switch (hw->mac.ops.get_media_type(hw)) {
 976         case ixgbe_media_type_fiber:
 977                 status = ixgbe_identify_sfp_module_generic(hw);
 978                 break;
 979
 980         case ixgbe_media_type_fiber_qsfp:
 981                 status = ixgbe_identify_qsfp_module_generic(hw);
 982                 break;
 983
 984         default:
 985                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 986                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 987                 break;
 988         }
 989
 990         return status;
 991 }
 992
 993 /**
 994  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 995  *  @hw: pointer to hardware structure
 996  *
 997  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 998  **/
 999 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1000 {
1001         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1002         u32 vendor_oui = 0;
1003         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1004         u8 identifier = 0;
1005         u8 comp_codes_1g = 0;
1006         u8 comp_codes_10g = 0;
1007         u8 oui_bytes[3] = {0, 0, 0};
1008         u8 cable_tech = 0;
1009         u8 cable_spec = 0;
1010         u16 enforce_sfp = 0;
1011
1012         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1013
1014         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1015                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1016                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1017                 goto out;
1018         }
1019
1020         status = hw->phy.ops.read_i2c_eeprom(hw,
1021                                              IXGBE_SFF_IDENTIFIER,
1022                                              &identifier);
1023
1024         if (status != IXGBE_SUCCESS)
1025                 goto err_read_i2c_eeprom;
1026
1027         /* LAN ID is needed for sfp_type determination */
1028         hw->mac.ops.set_lan_id(hw);
1029
1030         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1031                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1032                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1033         } else {
1034                 status = hw->phy.ops.read_i2c_eeprom(hw,
1035                                                      IXGBE_SFF_1GBE_COMP_CODES,
1036                                                      &comp_codes_1g);
1037
1038                 if (status != IXGBE_SUCCESS)
1039                         goto err_read_i2c_eeprom;
1040
1041                 status = hw->phy.ops.read_i2c_eeprom(hw,
1042                                                      IXGBE_SFF_10GBE_COMP_CODES,
1043                                                      &comp_codes_10g);
1044
1045                 if (status != IXGBE_SUCCESS)
1046                         goto err_read_i2c_eeprom;
1047                 status = hw->phy.ops.read_i2c_eeprom(hw,
1048                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1049                                                      &cable_tech);
1050
1051                 if (status != IXGBE_SUCCESS)
1052                         goto err_read_i2c_eeprom;
1053
1054                  /* ID Module
1055                   * =========
1056                   * 0   SFP_DA_CU
1057                   * 1   SFP_SR
1058                   * 2   SFP_LR
1059                   * 3   SFP_DA_CORE0 - 82599-specific
1060                   * 4   SFP_DA_CORE1 - 82599-specific
1061                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1062                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1063                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1064                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1065                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1066                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1067                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1068                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1069                   */
1070                 if (hw->mac.type == ixgbe_mac_82598EB) {
1071                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1072                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1073                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1074                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1075                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1076                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1077                         else
1078                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1079                 } else {
1080                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1081                                 if (hw->bus.lan_id == 0)
1082                                         hw->phy.sfp_type =
1083                                                      ixgbe_sfp_type_da_cu_core0;
1084                                 else
1085                                         hw->phy.sfp_type =
1086                                                      ixgbe_sfp_type_da_cu_core1;
1087                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1088                                 hw->phy.ops.read_i2c_eeprom(
1089                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1090                                                 &cable_spec);
1091                                 if (cable_spec &
1092                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1093                                         if (hw->bus.lan_id == 0)
1094                                                 hw->phy.sfp_type =
1095                                                 ixgbe_sfp_type_da_act_lmt_core0;
1096                                         else
1097                                                 hw->phy.sfp_type =
1098                                                 ixgbe_sfp_type_da_act_lmt_core1;
1099                                 } else {
1100                                         hw->phy.sfp_type =
1101                                                         ixgbe_sfp_type_unknown;
1102                                 }
1103                         } else if (comp_codes_10g &
1104                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1105                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1106                                 if (hw->bus.lan_id == 0)
1107                                         hw->phy.sfp_type =
1108                                                       ixgbe_sfp_type_srlr_core0;
1109                                 else
1110                                         hw->phy.sfp_type =
1111                                                       ixgbe_sfp_type_srlr_core1;
1112 #ifdef SUPPORT_10GBASE_ER
1113                         } else if (comp_codes_10g &
1114                                    IXGBE_SFF_10GBASEER_CAPABLE) {
1115                                 if (hw->bus.lan_id == 0)
1116                                         hw->phy.sfp_type =
1117                                                         ixgbe_sfp_type_er_core0;
1118                                 else
1119                                         hw->phy.sfp_type =
1120                                                         ixgbe_sfp_type_er_core1;
1121 #endif /* SUPPORT_10GBASE_ER */
1122                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1123                                 if (hw->bus.lan_id == 0)
1124                                         hw->phy.sfp_type =
1125                                                 ixgbe_sfp_type_1g_cu_core0;
1126                                 else
1127                                         hw->phy.sfp_type =
1128                                                 ixgbe_sfp_type_1g_cu_core1;
1129                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1130                                 if (hw->bus.lan_id == 0)
1131                                         hw->phy.sfp_type =
1132                                                 ixgbe_sfp_type_1g_sx_core0;
1133                                 else
1134                                         hw->phy.sfp_type =
1135                                                 ixgbe_sfp_type_1g_sx_core1;
1136 #ifdef SUPPORT_1000BASE_LX
1137                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1138                                 if (hw->bus.lan_id == 0)
1139                                         hw->phy.sfp_type =
1140                                                 ixgbe_sfp_type_1g_lx_core0;
1141                                 else
1142                                         hw->phy.sfp_type =
1143                                                 ixgbe_sfp_type_1g_lx_core1;
1144 #endif /* SUPPORT_1000BASE_LX */
1145                         } else {
1146                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1147                         }
1148                 }
1149
1150                 if (hw->phy.sfp_type != stored_sfp_type)
1151                         hw->phy.sfp_setup_needed = true;
1152
1153                 /* Determine if the SFP+ PHY is dual speed or not. */
1154                 hw->phy.multispeed_fiber = false;
1155                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1156                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1157                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1158                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1159                         hw->phy.multispeed_fiber = true;
1160
1161                 /* Determine PHY vendor */
1162                 if (hw->phy.type != ixgbe_phy_nl) {
1163                         hw->phy.id = identifier;
1164                         status = hw->phy.ops.read_i2c_eeprom(hw,
1165                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1166                                                     &oui_bytes[0]);
1167
1168                         if (status != IXGBE_SUCCESS)
1169                                 goto err_read_i2c_eeprom;
1170
1171                         status = hw->phy.ops.read_i2c_eeprom(hw,
1172                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1173                                                     &oui_bytes[1]);
1174
1175                         if (status != IXGBE_SUCCESS)
1176                                 goto err_read_i2c_eeprom;
1177
1178                         status = hw->phy.ops.read_i2c_eeprom(hw,
1179                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1180                                                     &oui_bytes[2]);
1181
1182                         if (status != IXGBE_SUCCESS)
1183                                 goto err_read_i2c_eeprom;
1184
1185                         vendor_oui =
1186                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1187                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1188                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1189
1190                         switch (vendor_oui) {
1191                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1192                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1193                                         hw->phy.type =
1194                                                     ixgbe_phy_sfp_passive_tyco;
1195                                 break;
1196                         case IXGBE_SFF_VENDOR_OUI_FTL:
1197                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1198                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1199                                 else
1200                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1201                                 break;
1202                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1203                                 hw->phy.type = ixgbe_phy_sfp_avago;
1204                                 break;
1205                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1206                                 hw->phy.type = ixgbe_phy_sfp_intel;
1207                                 break;
1208                         default:
1209                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1210                                         hw->phy.type =
1211                                                  ixgbe_phy_sfp_passive_unknown;
1212                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1213                                         hw->phy.type =
1214                                                 ixgbe_phy_sfp_active_unknown;
1215                                 else
1216                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1217                                 break;
1218                         }
1219                 }
1220
1221                 /* Allow any DA cable vendor */
1222                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1223                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1224                         status = IXGBE_SUCCESS;
1225                         goto out;
1226                 }
1227
1228                 /* Verify supported 1G SFP modules */
1229                 if (comp_codes_10g == 0 &&
1230                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1231                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1232 #ifdef SUPPORT_1000BASE_LX
1233                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1234                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1235 #endif
1236                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1237                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1238                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1239                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1240                         goto out;
1241                 }
1242
1243                 /* Anything else 82598-based is supported */
1244                 if (hw->mac.type == ixgbe_mac_82598EB) {
1245                         status = IXGBE_SUCCESS;
1246                         goto out;
1247                 }
1248
1249                 ixgbe_get_device_caps(hw, &enforce_sfp);
1250                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1251                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1252                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1253 #ifdef SUPPORT_1000BASE_LX
1254                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1255                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1256 #endif
1257 #ifdef SUPPORT_10GBASE_ER
1258                       hw->phy.sfp_type == ixgbe_sfp_type_er_core0 ||
1259                       hw->phy.sfp_type == ixgbe_sfp_type_er_core1 ||
1260 #endif
1261                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1262                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1263                         /* Make sure we're a supported PHY type */
1264                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1265                                 status = IXGBE_SUCCESS;
1266                         } else {
1267                                 if (hw->allow_unsupported_sfp == true) {
1268                                         EWARN(hw, "WARNING: Intel (R) Network "
1269                                               "Connections are quality tested "
1270                                               "using Intel (R) Ethernet Optics."
1271                                               " Using untested modules is not "
1272                                               "supported and may cause unstable"
1273                                               " operation or damage to the "
1274                                               "module or the adapter. Intel "
1275                                               "Corporation is not responsible "
1276                                               "for any harm caused by using "
1277                                               "untested modules.\n", status);
1278                                         status = IXGBE_SUCCESS;
1279                                 } else {
1280                                         DEBUGOUT("SFP+ module not supported\n");
1281                                         hw->phy.type =
1282                                                 ixgbe_phy_sfp_unsupported;
1283                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1284                                 }
1285                         }
1286                 } else {
1287                         status = IXGBE_SUCCESS;
1288                 }
1289         }
1290
1291 out:
1292         return status;
1293
1294 err_read_i2c_eeprom:
1295         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1296         if (hw->phy.type != ixgbe_phy_nl) {
1297                 hw->phy.id = 0;
1298                 hw->phy.type = ixgbe_phy_unknown;
1299         }
1300         return IXGBE_ERR_SFP_NOT_PRESENT;
1301 }
1302
1303 /**
1304  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1305  *  @hw: pointer to hardware structure
1306  *
1307  *  Determines physical layer capabilities of the current SFP.
1308  */
1309 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1310 {
1311         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1312         u8 comp_codes_10g = 0;
1313         u8 comp_codes_1g = 0;
1314
1315         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1316
1317         hw->phy.ops.identify_sfp(hw);
1318         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1319                 return physical_layer;
1320
1321         switch (hw->phy.type) {
1322         case ixgbe_phy_sfp_passive_tyco:
1323         case ixgbe_phy_sfp_passive_unknown:
1324         case ixgbe_phy_qsfp_passive_unknown:
1325                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1326                 break;
1327         case ixgbe_phy_sfp_ftl_active:
1328         case ixgbe_phy_sfp_active_unknown:
1329         case ixgbe_phy_qsfp_active_unknown:
1330                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1331                 break;
1332         case ixgbe_phy_sfp_avago:
1333         case ixgbe_phy_sfp_ftl:
1334         case ixgbe_phy_sfp_intel:
1335         case ixgbe_phy_sfp_unknown:
1336                 hw->phy.ops.read_i2c_eeprom(hw,
1337                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1338                 hw->phy.ops.read_i2c_eeprom(hw,
1339                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1340                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1341                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1342                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1343                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1344                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1345                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1346                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1347                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1348                 break;
1349         case ixgbe_phy_qsfp_intel:
1350         case ixgbe_phy_qsfp_unknown:
1351                 hw->phy.ops.read_i2c_eeprom(hw,
1352                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1353                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1354                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1355                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1356                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1357                 break;
1358         default:
1359                 break;
1360         }
1361
1362         return physical_layer;
1363 }
1364
1365 /**
1366  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1367  *  @hw: pointer to hardware structure
1368  *
1369  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1370  **/
1371 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1372 {
1373         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1374         u32 vendor_oui = 0;
1375         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1376         u8 identifier = 0;
1377         u8 comp_codes_1g = 0;
1378         u8 comp_codes_10g = 0;
1379         u8 oui_bytes[3] = {0, 0, 0};
1380         u16 enforce_sfp = 0;
1381         u8 connector = 0;
1382         u8 cable_length = 0;
1383         u8 device_tech = 0;
1384         bool active_cable = false;
1385
1386         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1387
1388         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1389                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1390                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1391                 goto out;
1392         }
1393
1394         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1395                                              &identifier);
1396
1397         if (status != IXGBE_SUCCESS)
1398                 goto err_read_i2c_eeprom;
1399
1400         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1401                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1402                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1403                 goto out;
1404         }
1405
1406         hw->phy.id = identifier;
1407
1408         /* LAN ID is needed for sfp_type determination */
1409         hw->mac.ops.set_lan_id(hw);
1410
1411         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1412                                              &comp_codes_10g);
1413
1414         if (status != IXGBE_SUCCESS)
1415                 goto err_read_i2c_eeprom;
1416
1417         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1418                                              &comp_codes_1g);
1419
1420         if (status != IXGBE_SUCCESS)
1421                 goto err_read_i2c_eeprom;
1422
1423         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1424                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1425                 if (hw->bus.lan_id == 0)
1426                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1427                 else
1428                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1429         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1430                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1431                 if (hw->bus.lan_id == 0)
1432                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1433                 else
1434                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1435         } else {
1436                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1437                         active_cable = true;
1438
1439                 if (!active_cable) {
1440                         /* check for active DA cables that pre-date
1441                          * SFF-8436 v3.6 */
1442                         hw->phy.ops.read_i2c_eeprom(hw,
1443                                         IXGBE_SFF_QSFP_CONNECTOR,
1444                                         &connector);
1445
1446                         hw->phy.ops.read_i2c_eeprom(hw,
1447                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1448                                         &cable_length);
1449
1450                         hw->phy.ops.read_i2c_eeprom(hw,
1451                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1452                                         &device_tech);
1453
1454                         if ((connector ==
1455                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1456                             (cable_length > 0) &&
1457                             ((device_tech >> 4) ==
1458                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1459                                 active_cable = true;
1460                 }
1461
1462                 if (active_cable) {
1463                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1464                         if (hw->bus.lan_id == 0)
1465                                 hw->phy.sfp_type =
1466                                                 ixgbe_sfp_type_da_act_lmt_core0;
1467                         else
1468                                 hw->phy.sfp_type =
1469                                                 ixgbe_sfp_type_da_act_lmt_core1;
1470                 } else {
1471                         /* unsupported module type */
1472                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1473                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1474                         goto out;
1475                 }
1476         }
1477
1478         if (hw->phy.sfp_type != stored_sfp_type)
1479                 hw->phy.sfp_setup_needed = true;
1480
1481         /* Determine if the QSFP+ PHY is dual speed or not. */
1482         hw->phy.multispeed_fiber = false;
1483         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1484            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1485            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1486            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1487                 hw->phy.multispeed_fiber = true;
1488
1489         /* Determine PHY vendor for optical modules */
1490         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1491                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1492                 status = hw->phy.ops.read_i2c_eeprom(hw,
1493                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1494                                             &oui_bytes[0]);
1495
1496                 if (status != IXGBE_SUCCESS)
1497                         goto err_read_i2c_eeprom;
1498
1499                 status = hw->phy.ops.read_i2c_eeprom(hw,
1500                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1501                                             &oui_bytes[1]);
1502
1503                 if (status != IXGBE_SUCCESS)
1504                         goto err_read_i2c_eeprom;
1505
1506                 status = hw->phy.ops.read_i2c_eeprom(hw,
1507                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1508                                             &oui_bytes[2]);
1509
1510                 if (status != IXGBE_SUCCESS)
1511                         goto err_read_i2c_eeprom;
1512
1513                 vendor_oui =
1514                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1515                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1516                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1517
1518                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1519                         hw->phy.type = ixgbe_phy_qsfp_intel;
1520                 else
1521                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1522
1523                 ixgbe_get_device_caps(hw, &enforce_sfp);
1524                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1525                         /* Make sure we're a supported PHY type */
1526                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1527                                 status = IXGBE_SUCCESS;
1528                         } else {
1529                                 if (hw->allow_unsupported_sfp == true) {
1530                                         EWARN(hw, "WARNING: Intel (R) Network "
1531                                               "Connections are quality tested "
1532                                               "using Intel (R) Ethernet Optics."
1533                                               " Using untested modules is not "
1534                                               "supported and may cause unstable"
1535                                               " operation or damage to the "
1536                                               "module or the adapter. Intel "
1537                                               "Corporation is not responsible "
1538                                               "for any harm caused by using "
1539                                               "untested modules.\n", status);
1540                                         status = IXGBE_SUCCESS;
1541                                 } else {
1542                                         DEBUGOUT("QSFP module not supported\n");
1543                                         hw->phy.type =
1544                                                 ixgbe_phy_sfp_unsupported;
1545                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1546                                 }
1547                         }
1548                 } else {
1549                         status = IXGBE_SUCCESS;
1550                 }
1551         }
1552
1553 out:
1554         return status;
1555
1556 err_read_i2c_eeprom:
1557         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1558         hw->phy.id = 0;
1559         hw->phy.type = ixgbe_phy_unknown;
1560
1561         return IXGBE_ERR_SFP_NOT_PRESENT;
1562 }
1563
1564
1565 /**
1566  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1567  *  @hw: pointer to hardware structure
1568  *  @list_offset: offset to the SFP ID list
1569  *  @data_offset: offset to the SFP data block
1570  *
1571  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1572  *  so it returns the offsets to the phy init sequence block.
1573  **/
1574 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1575                                         u16 *list_offset,
1576                                         u16 *data_offset)
1577 {
1578         u16 sfp_id;
1579         u16 sfp_type = hw->phy.sfp_type;
1580
1581         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1582
1583         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1584                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1585
1586         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1587                 return IXGBE_ERR_SFP_NOT_PRESENT;
1588
1589         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1590             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1591                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1592
1593         /*
1594          * Limiting active cables and 1G Phys must be initialized as
1595          * SR modules
1596          */
1597         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1598 #ifdef SUPPORT_10GBASE_ER
1599             sfp_type == ixgbe_sfp_type_er_core0 ||
1600 #endif /* SUPPORT_10GBASE_ER */
1601 #ifdef SUPPORT_1000BASE_LX
1602             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1603 #endif /* SUPPORT_1000BASE_LX */
1604             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1605             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1606                 sfp_type = ixgbe_sfp_type_srlr_core0;
1607         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1608 #ifdef SUPPORT_10GBASE_ER
1609                  sfp_type == ixgbe_sfp_type_er_core1 ||
1610 #endif /* SUPPORT_10GBASE_ER */
1611 #ifdef SUPPORT_1000BASE_LX
1612                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1613 #endif /* SUPPORT_1000BASE_LX */
1614                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1615                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1616                 sfp_type = ixgbe_sfp_type_srlr_core1;
1617
1618         /* Read offset to PHY init contents */
1619         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1620                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1621                               "eeprom read at offset %d failed",
1622                               IXGBE_PHY_INIT_OFFSET_NL);
1623                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1624         }
1625
1626         if ((!*list_offset) || (*list_offset == 0xFFFF))
1627                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1628
1629         /* Shift offset to first ID word */
1630         (*list_offset)++;
1631
1632         /*
1633          * Find the matching SFP ID in the EEPROM
1634          * and program the init sequence
1635          */
1636         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1637                 goto err_phy;
1638
1639         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1640                 if (sfp_id == sfp_type) {
1641                         (*list_offset)++;
1642                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1643                                 goto err_phy;
1644                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1645                                 DEBUGOUT("SFP+ module not supported\n");
1646                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1647                         } else {
1648                                 break;
1649                         }
1650                 } else {
1651                         (*list_offset) += 2;
1652                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1653                                 goto err_phy;
1654                 }
1655         }
1656
1657         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1658                 DEBUGOUT("No matching SFP+ module found\n");
1659                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1660         }
1661
1662         return IXGBE_SUCCESS;
1663
1664 err_phy:
1665         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1666                       "eeprom read at offset %d failed", *list_offset);
1667         return IXGBE_ERR_PHY;
1668 }
1669
1670 /**
1671  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1672  *  @hw: pointer to hardware structure
1673  *  @byte_offset: EEPROM byte offset to read
1674  *  @eeprom_data: value read
1675  *
1676  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1677  **/
1678 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1679                                   u8 *eeprom_data)
1680 {
1681         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1682
1683         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1684                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1685                                          eeprom_data);
1686 }
1687
1688 /**
1689  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1690  *  @hw: pointer to hardware structure
1691  *  @byte_offset: byte offset at address 0xA2
1692  *  @eeprom_data: value read
1693  *
1694  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1695  **/
1696 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1697                                           u8 *sff8472_data)
1698 {
1699         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1700                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1701                                          sff8472_data);
1702 }
1703
1704 /**
1705  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1706  *  @hw: pointer to hardware structure
1707  *  @byte_offset: EEPROM byte offset to write
1708  *  @eeprom_data: value to write
1709  *
1710  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1711  **/
1712 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1713                                    u8 eeprom_data)
1714 {
1715         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1716
1717         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1718                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1719                                           eeprom_data);
1720 }
1721
1722 /**
1723  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1724  *  @hw: pointer to hardware structure
1725  *  @byte_offset: byte offset to read
1726  *  @data: value read
1727  *
1728  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1729  *  a specified device address.
1730  **/
1731 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1732                                 u8 dev_addr, u8 *data)
1733 {
1734         s32 status;
1735         u32 max_retry = 10;
1736         u32 retry = 0;
1737         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1738         bool nack = 1;
1739         *data = 0;
1740
1741         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1742
1743         do {
1744                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1745                         return IXGBE_ERR_SWFW_SYNC;
1746
1747                 ixgbe_i2c_start(hw);
1748
1749                 /* Device Address and write indication */
1750                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1751                 if (status != IXGBE_SUCCESS)
1752                         goto fail;
1753
1754                 status = ixgbe_get_i2c_ack(hw);
1755                 if (status != IXGBE_SUCCESS)
1756                         goto fail;
1757
1758                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1759                 if (status != IXGBE_SUCCESS)
1760                         goto fail;
1761
1762                 status = ixgbe_get_i2c_ack(hw);
1763                 if (status != IXGBE_SUCCESS)
1764                         goto fail;
1765
1766                 ixgbe_i2c_start(hw);
1767
1768                 /* Device Address and read indication */
1769                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1770                 if (status != IXGBE_SUCCESS)
1771                         goto fail;
1772
1773                 status = ixgbe_get_i2c_ack(hw);
1774                 if (status != IXGBE_SUCCESS)
1775                         goto fail;
1776
1777                 status = ixgbe_clock_in_i2c_byte(hw, data);
1778                 if (status != IXGBE_SUCCESS)
1779                         goto fail;
1780
1781                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1782                 if (status != IXGBE_SUCCESS)
1783                         goto fail;
1784
1785                 ixgbe_i2c_stop(hw);
1786                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1787                 return IXGBE_SUCCESS;
1788
1789 fail:
1790                 ixgbe_i2c_bus_clear(hw);
1791                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1792                 msec_delay(100);
1793                 retry++;
1794                 if (retry < max_retry)
1795                         DEBUGOUT("I2C byte read error - Retrying.\n");
1796                 else
1797                         DEBUGOUT("I2C byte read error.\n");
1798
1799         } while (retry < max_retry);
1800
1801         return status;
1802 }
1803
1804 /**
1805  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1806  *  @hw: pointer to hardware structure
1807  *  @byte_offset: byte offset to write
1808  *  @data: value to write
1809  *
1810  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1811  *  a specified device address.
1812  **/
1813 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1814                                  u8 dev_addr, u8 data)
1815 {
1816         s32 status = IXGBE_SUCCESS;
1817         u32 max_retry = 1;
1818         u32 retry = 0;
1819         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1820
1821         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1822
1823         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1824                 status = IXGBE_ERR_SWFW_SYNC;
1825                 goto write_byte_out;
1826         }
1827
1828         do {
1829                 ixgbe_i2c_start(hw);
1830
1831                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1832                 if (status != IXGBE_SUCCESS)
1833                         goto fail;
1834
1835                 status = ixgbe_get_i2c_ack(hw);
1836                 if (status != IXGBE_SUCCESS)
1837                         goto fail;
1838
1839                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1840                 if (status != IXGBE_SUCCESS)
1841                         goto fail;
1842
1843                 status = ixgbe_get_i2c_ack(hw);
1844                 if (status != IXGBE_SUCCESS)
1845                         goto fail;
1846
1847                 status = ixgbe_clock_out_i2c_byte(hw, data);
1848                 if (status != IXGBE_SUCCESS)
1849                         goto fail;
1850
1851                 status = ixgbe_get_i2c_ack(hw);
1852                 if (status != IXGBE_SUCCESS)
1853                         goto fail;
1854
1855                 ixgbe_i2c_stop(hw);
1856                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1857                 return IXGBE_SUCCESS;
1858
1859 fail:
1860                 ixgbe_i2c_bus_clear(hw);
1861                 retry++;
1862                 if (retry < max_retry)
1863                         DEBUGOUT("I2C byte write error - Retrying.\n");
1864                 else
1865                         DEBUGOUT("I2C byte write error.\n");
1866         } while (retry < max_retry);
1867
1868         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1869
1870 write_byte_out:
1871         return status;
1872 }
1873
1874 /**
1875  *  ixgbe_i2c_start - Sets I2C start condition
1876  *  @hw: pointer to hardware structure
1877  *
1878  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1879  **/
1880 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
1881 {
1882         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1883
1884         DEBUGFUNC("ixgbe_i2c_start");
1885
1886         /* Start condition must begin with data and clock high */
1887         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1888         ixgbe_raise_i2c_clk(hw, &i2cctl);
1889
1890         /* Setup time for start condition (4.7us) */
1891         usec_delay(IXGBE_I2C_T_SU_STA);
1892
1893         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1894
1895         /* Hold time for start condition (4us) */
1896         usec_delay(IXGBE_I2C_T_HD_STA);
1897
1898         ixgbe_lower_i2c_clk(hw, &i2cctl);
1899
1900         /* Minimum low period of clock is 4.7 us */
1901         usec_delay(IXGBE_I2C_T_LOW);
1902
1903 }
1904
1905 /**
1906  *  ixgbe_i2c_stop - Sets I2C stop condition
1907  *  @hw: pointer to hardware structure
1908  *
1909  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1910  **/
1911 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1912 {
1913         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1914
1915         DEBUGFUNC("ixgbe_i2c_stop");
1916
1917         /* Stop condition must begin with data low and clock high */
1918         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1919         ixgbe_raise_i2c_clk(hw, &i2cctl);
1920
1921         /* Setup time for stop condition (4us) */
1922         usec_delay(IXGBE_I2C_T_SU_STO);
1923
1924         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1925
1926         /* bus free time between stop and start (4.7us)*/
1927         usec_delay(IXGBE_I2C_T_BUF);
1928 }
1929
1930 /**
1931  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1932  *  @hw: pointer to hardware structure
1933  *  @data: data byte to clock in
1934  *
1935  *  Clocks in one byte data via I2C data/clock
1936  **/
1937 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1938 {
1939         s32 i;
1940         bool bit = 0;
1941
1942         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1943
1944         for (i = 7; i >= 0; i--) {
1945                 ixgbe_clock_in_i2c_bit(hw, &bit);
1946                 *data |= bit << i;
1947         }
1948
1949         return IXGBE_SUCCESS;
1950 }
1951
1952 /**
1953  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1954  *  @hw: pointer to hardware structure
1955  *  @data: data byte clocked out
1956  *
1957  *  Clocks out one byte data via I2C data/clock
1958  **/
1959 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1960 {
1961         s32 status = IXGBE_SUCCESS;
1962         s32 i;
1963         u32 i2cctl;
1964         bool bit;
1965
1966         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1967
1968         for (i = 7; i >= 0; i--) {
1969                 bit = (data >> i) & 0x1;
1970                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1971
1972                 if (status != IXGBE_SUCCESS)
1973                         break;
1974         }
1975
1976         /* Release SDA line (set high) */
1977         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1978         i2cctl |= IXGBE_I2C_DATA_OUT;
1979         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1980         IXGBE_WRITE_FLUSH(hw);
1981
1982         return status;
1983 }
1984
1985 /**
1986  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1987  *  @hw: pointer to hardware structure
1988  *
1989  *  Clocks in/out one bit via I2C data/clock
1990  **/
1991 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1992 {
1993         s32 status = IXGBE_SUCCESS;
1994         u32 i = 0;
1995         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1996         u32 timeout = 10;
1997         bool ack = 1;
1998
1999         DEBUGFUNC("ixgbe_get_i2c_ack");
2000
2001         ixgbe_raise_i2c_clk(hw, &i2cctl);
2002
2003
2004         /* Minimum high period of clock is 4us */
2005         usec_delay(IXGBE_I2C_T_HIGH);
2006
2007         /* Poll for ACK.  Note that ACK in I2C spec is
2008          * transition from 1 to 0 */
2009         for (i = 0; i < timeout; i++) {
2010                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2011                 ack = ixgbe_get_i2c_data(&i2cctl);
2012
2013                 usec_delay(1);
2014                 if (!ack)
2015                         break;
2016         }
2017
2018         if (ack == 1) {
2019                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2020                              "I2C ack was not received.\n");
2021                 status = IXGBE_ERR_I2C;
2022         }
2023
2024         ixgbe_lower_i2c_clk(hw, &i2cctl);
2025
2026         /* Minimum low period of clock is 4.7 us */
2027         usec_delay(IXGBE_I2C_T_LOW);
2028
2029         return status;
2030 }
2031
2032 /**
2033  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2034  *  @hw: pointer to hardware structure
2035  *  @data: read data value
2036  *
2037  *  Clocks in one bit via I2C data/clock
2038  **/
2039 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2040 {
2041         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2042
2043         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2044
2045         ixgbe_raise_i2c_clk(hw, &i2cctl);
2046
2047         /* Minimum high period of clock is 4us */
2048         usec_delay(IXGBE_I2C_T_HIGH);
2049
2050         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2051         *data = ixgbe_get_i2c_data(&i2cctl);
2052
2053         ixgbe_lower_i2c_clk(hw, &i2cctl);
2054
2055         /* Minimum low period of clock is 4.7 us */
2056         usec_delay(IXGBE_I2C_T_LOW);
2057
2058         return IXGBE_SUCCESS;
2059 }
2060
2061 /**
2062  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2063  *  @hw: pointer to hardware structure
2064  *  @data: data value to write
2065  *
2066  *  Clocks out one bit via I2C data/clock
2067  **/
2068 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2069 {
2070         s32 status;
2071         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2072
2073         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2074
2075         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2076         if (status == IXGBE_SUCCESS) {
2077                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2078
2079                 /* Minimum high period of clock is 4us */
2080                 usec_delay(IXGBE_I2C_T_HIGH);
2081
2082                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2083
2084                 /* Minimum low period of clock is 4.7 us.
2085                  * This also takes care of the data hold time.
2086                  */
2087                 usec_delay(IXGBE_I2C_T_LOW);
2088         } else {
2089                 status = IXGBE_ERR_I2C;
2090                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2091                              "I2C data was not set to %X\n", data);
2092         }
2093
2094         return status;
2095 }
2096
2097 /**
2098  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2099  *  @hw: pointer to hardware structure
2100  *  @i2cctl: Current value of I2CCTL register
2101  *
2102  *  Raises the I2C clock line '0'->'1'
2103  **/
2104 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2105 {
2106         u32 i = 0;
2107         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2108         u32 i2cctl_r = 0;
2109
2110         DEBUGFUNC("ixgbe_raise_i2c_clk");
2111
2112         for (i = 0; i < timeout; i++) {
2113                 *i2cctl |= IXGBE_I2C_CLK_OUT;
2114
2115                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
2116                 IXGBE_WRITE_FLUSH(hw);
2117                 /* SCL rise time (1000ns) */
2118                 usec_delay(IXGBE_I2C_T_RISE);
2119
2120                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2121                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
2122                         break;
2123         }
2124 }
2125
2126 /**
2127  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2128  *  @hw: pointer to hardware structure
2129  *  @i2cctl: Current value of I2CCTL register
2130  *
2131  *  Lowers the I2C clock line '1'->'0'
2132  **/
2133 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2134 {
2135
2136         DEBUGFUNC("ixgbe_lower_i2c_clk");
2137
2138         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
2139
2140         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
2141         IXGBE_WRITE_FLUSH(hw);
2142
2143         /* SCL fall time (300ns) */
2144         usec_delay(IXGBE_I2C_T_FALL);
2145 }
2146
2147 /**
2148  *  ixgbe_set_i2c_data - Sets the I2C data bit
2149  *  @hw: pointer to hardware structure
2150  *  @i2cctl: Current value of I2CCTL register
2151  *  @data: I2C data value (0 or 1) to set
2152  *
2153  *  Sets the I2C data bit
2154  **/
2155 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2156 {
2157         s32 status = IXGBE_SUCCESS;
2158
2159         DEBUGFUNC("ixgbe_set_i2c_data");
2160
2161         if (data)
2162                 *i2cctl |= IXGBE_I2C_DATA_OUT;
2163         else
2164                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
2165
2166         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
2167         IXGBE_WRITE_FLUSH(hw);
2168
2169         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2170         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2171
2172         /* Verify data was set correctly */
2173         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2174         if (data != ixgbe_get_i2c_data(i2cctl)) {
2175                 status = IXGBE_ERR_I2C;
2176                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2177                              "Error - I2C data was not set to %X.\n",
2178                              data);
2179         }
2180
2181         return status;
2182 }
2183
2184 /**
2185  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2186  *  @hw: pointer to hardware structure
2187  *  @i2cctl: Current value of I2CCTL register
2188  *
2189  *  Returns the I2C data bit value
2190  **/
2191 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
2192 {
2193         bool data;
2194
2195         DEBUGFUNC("ixgbe_get_i2c_data");
2196
2197         if (*i2cctl & IXGBE_I2C_DATA_IN)
2198                 data = 1;
2199         else
2200                 data = 0;
2201
2202         return data;
2203 }
2204
2205 /**
2206  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2207  *  @hw: pointer to hardware structure
2208  *
2209  *  Clears the I2C bus by sending nine clock pulses.
2210  *  Used when data line is stuck low.
2211  **/
2212 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2213 {
2214         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2215         u32 i;
2216
2217         DEBUGFUNC("ixgbe_i2c_bus_clear");
2218
2219         ixgbe_i2c_start(hw);
2220
2221         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2222
2223         for (i = 0; i < 9; i++) {
2224                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2225
2226                 /* Min high period of clock is 4us */
2227                 usec_delay(IXGBE_I2C_T_HIGH);
2228
2229                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2230
2231                 /* Min low period of clock is 4.7us*/
2232                 usec_delay(IXGBE_I2C_T_LOW);
2233         }
2234
2235         ixgbe_i2c_start(hw);
2236
2237         /* Put the i2c bus back to default state */
2238         ixgbe_i2c_stop(hw);
2239 }
2240
2241 /**
2242  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2243  *  @hw: pointer to hardware structure
2244  *
2245  *  Checks if the LASI temp alarm status was triggered due to overtemp
2246  **/
2247 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2248 {
2249         s32 status = IXGBE_SUCCESS;
2250         u16 phy_data = 0;
2251
2252         DEBUGFUNC("ixgbe_tn_check_overtemp");
2253
2254         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2255                 goto out;
2256
2257         /* Check that the LASI temp alarm status was triggered */
2258         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2259                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2260
2261         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2262                 goto out;
2263
2264         status = IXGBE_ERR_OVERTEMP;
2265         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2266 out:
2267         return status;
2268 }