ixgbe/base: rework locking
[dpdk.git] / lib / librte_pmd_ixgbe / ixgbe / ixgbe_phy.h
1 /*******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9  1. Redistributions of source code must retain the above copyright notice,
10     this list of conditions and the following disclaimer.
11
12  2. Redistributions in binary form must reproduce the above copyright
13     notice, this list of conditions and the following disclaimer in the
14     documentation and/or other materials provided with the distribution.
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16  3. Neither the name of the Intel Corporation nor the names of its
17     contributors may be used to endorse or promote products derived from
18     this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ***************************************************************************/
33
34 #ifndef _IXGBE_PHY_H_
35 #define _IXGBE_PHY_H_
36
37 #include "ixgbe_type.h"
38 #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
39
40 /* EEPROM byte offsets */
41 #define IXGBE_SFF_IDENTIFIER            0x0
42 #define IXGBE_SFF_IDENTIFIER_SFP        0x3
43 #define IXGBE_SFF_VENDOR_OUI_BYTE0      0x25
44 #define IXGBE_SFF_VENDOR_OUI_BYTE1      0x26
45 #define IXGBE_SFF_VENDOR_OUI_BYTE2      0x27
46 #define IXGBE_SFF_1GBE_COMP_CODES       0x6
47 #define IXGBE_SFF_10GBE_COMP_CODES      0x3
48 #define IXGBE_SFF_CABLE_TECHNOLOGY      0x8
49 #define IXGBE_SFF_CABLE_SPEC_COMP       0x3C
50
51 /* Bitmasks */
52 #define IXGBE_SFF_DA_PASSIVE_CABLE      0x4
53 #define IXGBE_SFF_DA_ACTIVE_CABLE       0x8
54 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING       0x4
55 #define IXGBE_SFF_1GBASESX_CAPABLE      0x1
56 #define IXGBE_SFF_1GBASELX_CAPABLE      0x2
57 #define IXGBE_SFF_1GBASET_CAPABLE       0x8
58 #define IXGBE_SFF_10GBASESR_CAPABLE     0x10
59 #define IXGBE_SFF_10GBASELR_CAPABLE     0x20
60 #ifdef SUPPORT_10GBASE_ER
61 #define IXGBE_SFF_10GBASEER_CAPABLE    0x80
62 #endif /* SUPPORT_10GBASE_ER */
63 #define IXGBE_SFF_ADDRESSING_MODE       0x4
64 #define IXGBE_I2C_EEPROM_READ_MASK      0x100
65 #define IXGBE_I2C_EEPROM_STATUS_MASK    0x3
66 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION    0x0
67 #define IXGBE_I2C_EEPROM_STATUS_PASS    0x1
68 #define IXGBE_I2C_EEPROM_STATUS_FAIL    0x2
69 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS     0x3
70
71 /* Flow control defines */
72 #define IXGBE_TAF_SYM_PAUSE             0x400
73 #define IXGBE_TAF_ASM_PAUSE             0x800
74
75 /* Bit-shift macros */
76 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT        24
77 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT        16
78 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT        8
79
80 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
81 #define IXGBE_SFF_VENDOR_OUI_TYCO       0x00407600
82 #define IXGBE_SFF_VENDOR_OUI_FTL        0x00906500
83 #define IXGBE_SFF_VENDOR_OUI_AVAGO      0x00176A00
84 #define IXGBE_SFF_VENDOR_OUI_INTEL      0x001B2100
85
86 /* I2C SDA and SCL timing parameters for standard mode */
87 #define IXGBE_I2C_T_HD_STA      4
88 #define IXGBE_I2C_T_LOW         5
89 #define IXGBE_I2C_T_HIGH        4
90 #define IXGBE_I2C_T_SU_STA      5
91 #define IXGBE_I2C_T_HD_DATA     5
92 #define IXGBE_I2C_T_SU_DATA     1
93 #define IXGBE_I2C_T_RISE        1
94 #define IXGBE_I2C_T_FALL        1
95 #define IXGBE_I2C_T_SU_STO      4
96 #define IXGBE_I2C_T_BUF         5
97
98 #define IXGBE_TN_LASI_STATUS_REG        0x9005
99 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
100
101 #ident "$Id: ixgbe_phy.h,v 1.48 2012/01/04 01:49:02 jtkirshe Exp $"
102
103 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
104 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
105 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
106 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
107 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
108 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
109 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
110                                u32 device_type, u16 *phy_data);
111 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
112                                 u32 device_type, u16 phy_data);
113 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
114 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
115                                        ixgbe_link_speed speed,
116                                        bool autoneg_wait_to_complete);
117 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
118                                                ixgbe_link_speed *speed,
119                                                bool *autoneg);
120 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
121
122 /* PHY specific */
123 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
124                              ixgbe_link_speed *speed,
125                              bool *link_up);
126 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
127 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
128                                        u16 *firmware_version);
129 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
130                                            u16 *firmware_version);
131
132 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
133 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
134 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
135 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
136                                         u16 *list_offset,
137                                         u16 *data_offset);
138 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
139 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
140                                 u8 dev_addr, u8 *data);
141 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
142                                  u8 dev_addr, u8 data);
143 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
144                                   u8 *eeprom_data);
145 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
146                                    u8 eeprom_data);
147 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
148 #endif /* _IXGBE_PHY_H_ */