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3 Copyright (c) 2001-2014, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ***************************************************************************/
37 #include "ixgbe_type.h"
38 #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
39 #define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
40 #define IXGBE_I2C_EEPROM_BANK_LEN 0xFF
42 /* EEPROM byte offsets */
43 #define IXGBE_SFF_IDENTIFIER 0x0
44 #define IXGBE_SFF_IDENTIFIER_SFP 0x3
45 #define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
46 #define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
47 #define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
48 #define IXGBE_SFF_1GBE_COMP_CODES 0x6
49 #define IXGBE_SFF_10GBE_COMP_CODES 0x3
50 #define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
51 #define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
52 #define IXGBE_SFF_SFF_8472_SWAP 0x5C
53 #define IXGBE_SFF_SFF_8472_COMP 0x5E
54 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD
55 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
56 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
57 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
58 #define IXGBE_SFF_QSFP_CONNECTOR 0x82
59 #define IXGBE_SFF_QSFP_10GBE_COMP 0x83
60 #define IXGBE_SFF_QSFP_1GBE_COMP 0x86
61 #define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92
62 #define IXGBE_SFF_QSFP_DEVICE_TECH 0x93
65 #define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
66 #define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
67 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
68 #define IXGBE_SFF_1GBASESX_CAPABLE 0x1
69 #define IXGBE_SFF_1GBASELX_CAPABLE 0x2
70 #define IXGBE_SFF_1GBASET_CAPABLE 0x8
71 #define IXGBE_SFF_10GBASESR_CAPABLE 0x10
72 #define IXGBE_SFF_10GBASELR_CAPABLE 0x20
73 #ifdef SUPPORT_10GBASE_ER
74 #define IXGBE_SFF_10GBASEER_CAPABLE 0x80
75 #endif /* SUPPORT_10GBASE_ER */
76 #define IXGBE_SFF_ADDRESSING_MODE 0x4
77 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1
78 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
79 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23
80 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0
81 #define IXGBE_I2C_EEPROM_READ_MASK 0x100
82 #define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
83 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
84 #define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
85 #define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
86 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
88 /* Flow control defines */
89 #define IXGBE_TAF_SYM_PAUSE 0x400
90 #define IXGBE_TAF_ASM_PAUSE 0x800
92 /* Bit-shift macros */
93 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
94 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
95 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
97 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
98 #define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
99 #define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
100 #define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
101 #define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
103 /* I2C SDA and SCL timing parameters for standard mode */
104 #define IXGBE_I2C_T_HD_STA 4
105 #define IXGBE_I2C_T_LOW 5
106 #define IXGBE_I2C_T_HIGH 4
107 #define IXGBE_I2C_T_SU_STA 5
108 #define IXGBE_I2C_T_HD_DATA 5
109 #define IXGBE_I2C_T_SU_DATA 1
110 #define IXGBE_I2C_T_RISE 1
111 #define IXGBE_I2C_T_FALL 1
112 #define IXGBE_I2C_T_SU_STO 4
113 #define IXGBE_I2C_T_BUF 5
115 #define IXGBE_TN_LASI_STATUS_REG 0x9005
116 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
118 /* SFP+ SFF-8472 Compliance */
119 #define IXGBE_SFF_SFF_8472_UNSUP 0x00
121 #ident "$Id: ixgbe_phy.h,v 1.56 2013/09/05 23:59:49 jtkirshe Exp $"
123 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
124 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
125 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
126 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
127 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
128 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
129 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
131 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
133 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
134 u32 device_type, u16 *phy_data);
135 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
136 u32 device_type, u16 phy_data);
137 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
138 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
139 ixgbe_link_speed speed,
140 bool autoneg_wait_to_complete);
141 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
142 ixgbe_link_speed *speed,
144 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
147 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
148 ixgbe_link_speed *speed,
150 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
151 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
152 u16 *firmware_version);
153 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
154 u16 *firmware_version);
156 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
157 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
158 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
159 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);
160 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
161 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
164 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
165 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
166 u8 dev_addr, u8 *data);
167 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
168 u8 dev_addr, u8 data);
169 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
171 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
173 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
174 #endif /* _IXGBE_PHY_H_ */