1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #ifndef _IXGBE_TYPE_H_
36 #define _IXGBE_TYPE_H_
38 #include "ixgbe_osdep.h"
42 #define IXGBE_INTEL_VENDOR_ID 0x8086
45 #define IXGBE_DEV_ID_82598 0x10B6
46 #define IXGBE_DEV_ID_82598_BX 0x1508
47 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
48 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
49 #define IXGBE_DEV_ID_82598AT 0x10C8
50 #define IXGBE_DEV_ID_82598AT2 0x150B
51 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
52 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
53 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
54 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
55 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
56 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
57 #define IXGBE_DEV_ID_82599_KX4 0x10F7
58 #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
59 #define IXGBE_DEV_ID_82599_KR 0x1517
60 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
61 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
62 #define IXGBE_DEV_ID_82599_CX4 0x10F9
63 #define IXGBE_DEV_ID_82599_SFP 0x10FB
64 #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
65 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
66 #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
67 #define IXGBE_DEV_ID_82599_SFP_EM 0x1507
68 #define IXGBE_DEV_ID_82599EN_SFP 0x1557
69 #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
70 #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
71 #define IXGBE_DEV_ID_82599_VF 0x10ED
72 #define IXGBE_DEV_ID_X540_VF 0x1515
73 #define IXGBE_DEV_ID_X540T 0x1528
75 /* General Registers */
76 #define IXGBE_CTRL 0x00000
77 #define IXGBE_STATUS 0x00008
78 #define IXGBE_CTRL_EXT 0x00018
79 #define IXGBE_ESDP 0x00020
80 #define IXGBE_EODSDP 0x00028
81 #define IXGBE_I2CCTL 0x00028
82 #define IXGBE_PHY_GPIO 0x00028
83 #define IXGBE_MAC_GPIO 0x00030
84 #define IXGBE_PHYINT_STATUS0 0x00100
85 #define IXGBE_PHYINT_STATUS1 0x00104
86 #define IXGBE_PHYINT_STATUS2 0x00108
87 #define IXGBE_LEDCTL 0x00200
88 #define IXGBE_FRTIMER 0x00048
89 #define IXGBE_TCPTIMER 0x0004C
90 #define IXGBE_CORESPARE 0x00600
91 #define IXGBE_EXVET 0x05078
94 #define IXGBE_EEC 0x10010
95 #define IXGBE_EERD 0x10014
96 #define IXGBE_EEWR 0x10018
97 #define IXGBE_FLA 0x1001C
98 #define IXGBE_EEMNGCTL 0x10110
99 #define IXGBE_EEMNGDATA 0x10114
100 #define IXGBE_FLMNGCTL 0x10118
101 #define IXGBE_FLMNGDATA 0x1011C
102 #define IXGBE_FLMNGCNT 0x10120
103 #define IXGBE_FLOP 0x1013C
104 #define IXGBE_GRC 0x10200
105 #define IXGBE_SRAMREL 0x10210
106 #define IXGBE_PHYDBG 0x10218
108 /* General Receive Control */
109 #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
110 #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
112 #define IXGBE_VPDDIAG0 0x10204
113 #define IXGBE_VPDDIAG1 0x10208
115 /* I2CCTL Bit Masks */
116 #define IXGBE_I2C_CLK_IN 0x00000001
117 #define IXGBE_I2C_CLK_OUT 0x00000002
118 #define IXGBE_I2C_DATA_IN 0x00000004
119 #define IXGBE_I2C_DATA_OUT 0x00000008
120 #define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
122 /* Interrupt Registers */
123 #define IXGBE_EICR 0x00800
124 #define IXGBE_EICS 0x00808
125 #define IXGBE_EIMS 0x00880
126 #define IXGBE_EIMC 0x00888
127 #define IXGBE_EIAC 0x00810
128 #define IXGBE_EIAM 0x00890
129 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
130 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
131 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
132 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
133 /* 82599 EITR is only 12 bits, with the lower 3 always zero */
135 * 82598 EITR is 16 bits but set the limits based on the max
136 * supported by all ixgbe hardware
138 #define IXGBE_MAX_INT_RATE 488281
139 #define IXGBE_MIN_INT_RATE 956
140 #define IXGBE_MAX_EITR 0x00000FF8
141 #define IXGBE_MIN_EITR 8
142 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
143 (0x012300 + (((_i) - 24) * 4)))
144 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
145 #define IXGBE_EITR_LLI_MOD 0x00008000
146 #define IXGBE_EITR_CNT_WDIS 0x80000000
147 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
148 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
149 #define IXGBE_EITRSEL 0x00894
150 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
151 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
152 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
153 #define IXGBE_GPIE 0x00898
155 /* Flow Control Registers */
156 #define IXGBE_FCADBUL 0x03210
157 #define IXGBE_FCADBUH 0x03214
158 #define IXGBE_FCAMACL 0x04328
159 #define IXGBE_FCAMACH 0x0432C
160 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
161 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
162 #define IXGBE_PFCTOP 0x03008
163 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
164 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
165 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
166 #define IXGBE_FCRTV 0x032A0
167 #define IXGBE_FCCFG 0x03D00
168 #define IXGBE_TFCS 0x0CE00
170 /* Receive DMA Registers */
171 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
172 (0x0D000 + ((_i - 64) * 0x40)))
173 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
174 (0x0D004 + ((_i - 64) * 0x40)))
175 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
176 (0x0D008 + ((_i - 64) * 0x40)))
177 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
178 (0x0D010 + ((_i - 64) * 0x40)))
179 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
180 (0x0D018 + ((_i - 64) * 0x40)))
181 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
182 (0x0D028 + ((_i - 64) * 0x40)))
183 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
184 (0x0D02C + ((_i - 64) * 0x40)))
185 #define IXGBE_RSCDBU 0x03028
186 #define IXGBE_RDDCC 0x02F20
187 #define IXGBE_RXMEMWRAP 0x03190
188 #define IXGBE_STARCTRL 0x03024
190 * Split and Replication Receive Control Registers
191 * 00-15 : 0x02100 + n*4
192 * 16-64 : 0x01014 + n*0x40
193 * 64-127: 0x0D014 + (n-64)*0x40
195 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
196 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
197 (0x0D014 + ((_i - 64) * 0x40))))
199 * Rx DCA Control Register:
200 * 00-15 : 0x02200 + n*4
201 * 16-64 : 0x0100C + n*0x40
202 * 64-127: 0x0D00C + (n-64)*0x40
204 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
205 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
206 (0x0D00C + ((_i - 64) * 0x40))))
207 #define IXGBE_RDRXCTL 0x02F00
208 #define IXGBE_RDRXCTL_RSC_PUSH 0x80
209 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
210 /* 8 of these 0x03C00 - 0x03C1C */
211 #define IXGBE_RXCTRL 0x03000
212 #define IXGBE_DROPEN 0x03D04
213 #define IXGBE_RXPBSIZE_SHIFT 10
215 /* Receive Registers */
216 #define IXGBE_RXCSUM 0x05000
217 #define IXGBE_RFCTL 0x05008
218 #define IXGBE_DRECCCTL 0x02F08
219 #define IXGBE_DRECCCTL_DISABLE 0
220 #define IXGBE_DRECCCTL2 0x02F8C
222 /* Multicast Table Array - 128 entries */
223 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
224 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
225 (0x0A200 + ((_i) * 8)))
226 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
227 (0x0A204 + ((_i) * 8)))
228 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
229 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
230 /* Packet split receive type */
231 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
232 (0x0EA00 + ((_i) * 4)))
233 /* array of 4096 1-bit vlan filters */
234 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
235 /*array of 4096 4-bit vlan vmdq indices */
236 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
237 #define IXGBE_FCTRL 0x05080
238 #define IXGBE_VLNCTRL 0x05088
239 #define IXGBE_MCSTCTRL 0x05090
240 #define IXGBE_MRQC 0x05818
241 #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
242 #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
243 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
244 #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
245 #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
246 #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
247 #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
248 #define IXGBE_RQTC 0x0EC70
249 #define IXGBE_MTQC 0x08120
250 #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
251 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
252 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
253 #define IXGBE_VT_CTL 0x051B0
254 #define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */
255 #define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */
256 #define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */
257 #define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */
258 #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
259 #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
260 #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
261 #define IXGBE_QDE 0x2F04
262 #define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */
263 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
264 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
265 #define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
266 #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
267 #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
268 #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
269 #define IXGBE_RXFECCERR0 0x051B8
270 #define IXGBE_LLITHRESH 0x0EC90
271 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
272 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
273 #define IXGBE_IMIRVP 0x05AC0
274 #define IXGBE_VMD_CTL 0x0581C
275 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
276 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
278 /* Flow Director registers */
279 #define IXGBE_FDIRCTRL 0x0EE00
280 #define IXGBE_FDIRHKEY 0x0EE68
281 #define IXGBE_FDIRSKEY 0x0EE6C
282 #define IXGBE_FDIRDIP4M 0x0EE3C
283 #define IXGBE_FDIRSIP4M 0x0EE40
284 #define IXGBE_FDIRTCPM 0x0EE44
285 #define IXGBE_FDIRUDPM 0x0EE48
286 #define IXGBE_FDIRIP6M 0x0EE74
287 #define IXGBE_FDIRM 0x0EE70
289 /* Flow Director Stats registers */
290 #define IXGBE_FDIRFREE 0x0EE38
291 #define IXGBE_FDIRLEN 0x0EE4C
292 #define IXGBE_FDIRUSTAT 0x0EE50
293 #define IXGBE_FDIRFSTAT 0x0EE54
294 #define IXGBE_FDIRMATCH 0x0EE58
295 #define IXGBE_FDIRMISS 0x0EE5C
297 /* Flow Director Programming registers */
298 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
299 #define IXGBE_FDIRIPSA 0x0EE18
300 #define IXGBE_FDIRIPDA 0x0EE1C
301 #define IXGBE_FDIRPORT 0x0EE20
302 #define IXGBE_FDIRVLAN 0x0EE24
303 #define IXGBE_FDIRHASH 0x0EE28
304 #define IXGBE_FDIRCMD 0x0EE2C
306 /* Transmit DMA registers */
307 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
308 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
309 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
310 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
311 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
312 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
313 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
314 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
315 #define IXGBE_DTXCTL 0x07E00
317 #define IXGBE_DMATXCTL 0x04A80
318 #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
319 #define IXGBE_PFDTXGSWC 0x08220
320 #define IXGBE_DTXMXSZRQ 0x08100
321 #define IXGBE_DTXTCPFLGL 0x04A88
322 #define IXGBE_DTXTCPFLGH 0x04A8C
323 #define IXGBE_LBDRPEN 0x0CA00
324 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
326 #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
327 #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
328 #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
329 #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
331 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
333 /* Anti-spoofing defines */
334 #define IXGBE_SPOOF_MACAS_MASK 0xFF
335 #define IXGBE_SPOOF_VLANAS_MASK 0xFF00
336 #define IXGBE_SPOOF_VLANAS_SHIFT 8
337 #define IXGBE_PFVFSPOOF_REG_COUNT 8
338 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
339 /* Tx DCA Control register : 128 of these (0-127) */
340 #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
341 #define IXGBE_TIPG 0x0CB00
342 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
343 #define IXGBE_MNGTXMAP 0x0CD10
344 #define IXGBE_TIPG_FIBER_DEFAULT 3
345 #define IXGBE_TXPBSIZE_SHIFT 10
347 /* Wake up registers */
348 #define IXGBE_WUC 0x05800
349 #define IXGBE_WUFC 0x05808
350 #define IXGBE_WUS 0x05810
351 #define IXGBE_IPAV 0x05838
352 #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
353 #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
355 #define IXGBE_WUPL 0x05900
356 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
357 #define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
358 #define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
361 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
362 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
364 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
365 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
366 #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
367 #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
369 /* Definitions for power management and wakeup registers */
370 /* Wake Up Control */
371 #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
372 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
373 #define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */
375 /* Wake Up Filter Control */
376 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
377 #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
378 #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
379 #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
380 #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
381 #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
382 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
383 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
384 #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
386 #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
387 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
388 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
389 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
390 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
391 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
392 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
393 #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
394 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
395 #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all wakeup filters */
396 #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
399 #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
400 #define IXGBE_WUS_MAG IXGBE_WUFC_MAG
401 #define IXGBE_WUS_EX IXGBE_WUFC_EX
402 #define IXGBE_WUS_MC IXGBE_WUFC_MC
403 #define IXGBE_WUS_BC IXGBE_WUFC_BC
404 #define IXGBE_WUS_ARP IXGBE_WUFC_ARP
405 #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
406 #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
407 #define IXGBE_WUS_MNG IXGBE_WUFC_MNG
408 #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
409 #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
410 #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
411 #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
412 #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
413 #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
414 #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
416 /* Wake Up Packet Length */
417 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
420 #define MAX_TRAFFIC_CLASS 8
421 #define IXGBE_RMCS 0x03D00
422 #define IXGBE_DPMCS 0x07F40
423 #define IXGBE_PDPMCS 0x0CD00
424 #define IXGBE_RUPPBMR 0x050A0
425 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
426 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
427 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
428 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
429 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
430 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
433 /* Security Control Registers */
434 #define IXGBE_SECTXCTRL 0x08800
435 #define IXGBE_SECTXSTAT 0x08804
436 #define IXGBE_SECTXBUFFAF 0x08808
437 #define IXGBE_SECTXMINIFG 0x08810
438 #define IXGBE_SECRXCTRL 0x08D00
439 #define IXGBE_SECRXSTAT 0x08D04
441 /* Security Bit Fields and Masks */
442 #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
443 #define IXGBE_SECTXCTRL_TX_DIS 0x00000002
444 #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
446 #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
447 #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
449 #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
450 #define IXGBE_SECRXCTRL_RX_DIS 0x00000002
452 #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
453 #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
455 /* LinkSec (MacSec) Registers */
456 #define IXGBE_LSECTXCAP 0x08A00
457 #define IXGBE_LSECRXCAP 0x08F00
458 #define IXGBE_LSECTXCTRL 0x08A04
459 #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
460 #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
461 #define IXGBE_LSECTXSA 0x08A10
462 #define IXGBE_LSECTXPN0 0x08A14
463 #define IXGBE_LSECTXPN1 0x08A18
464 #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
465 #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
466 #define IXGBE_LSECRXCTRL 0x08F04
467 #define IXGBE_LSECRXSCL 0x08F08
468 #define IXGBE_LSECRXSCH 0x08F0C
469 #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
470 #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
471 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
472 #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
473 #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
474 #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
475 #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
476 #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
477 #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
478 #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
479 #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
480 #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
481 #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
482 #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
483 #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
484 #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
485 #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
486 #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
487 #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
488 #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
489 #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
490 #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
492 /* LinkSec (MacSec) Bit Fields and Masks */
493 #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
494 #define IXGBE_LSECTXCAP_SUM_SHIFT 16
495 #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
496 #define IXGBE_LSECRXCAP_SUM_SHIFT 16
498 #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
499 #define IXGBE_LSECTXCTRL_DISABLE 0x0
500 #define IXGBE_LSECTXCTRL_AUTH 0x1
501 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
502 #define IXGBE_LSECTXCTRL_AISCI 0x00000020
503 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
504 #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
506 #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
507 #define IXGBE_LSECRXCTRL_EN_SHIFT 2
508 #define IXGBE_LSECRXCTRL_DISABLE 0x0
509 #define IXGBE_LSECRXCTRL_CHECK 0x1
510 #define IXGBE_LSECRXCTRL_STRICT 0x2
511 #define IXGBE_LSECRXCTRL_DROP 0x3
512 #define IXGBE_LSECRXCTRL_PLSH 0x00000040
513 #define IXGBE_LSECRXCTRL_RP 0x00000080
514 #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
516 /* IpSec Registers */
517 #define IXGBE_IPSTXIDX 0x08900
518 #define IXGBE_IPSTXSALT 0x08904
519 #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
520 #define IXGBE_IPSRXIDX 0x08E00
521 #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
522 #define IXGBE_IPSRXSPI 0x08E14
523 #define IXGBE_IPSRXIPIDX 0x08E18
524 #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
525 #define IXGBE_IPSRXSALT 0x08E2C
526 #define IXGBE_IPSRXMOD 0x08E30
528 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
531 #define IXGBE_RTRPCS 0x02430
532 #define IXGBE_RTTDCS 0x04900
533 #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
534 #define IXGBE_RTTPCS 0x0CD00
535 #define IXGBE_RTRUP2TC 0x03020
536 #define IXGBE_RTTUP2TC 0x0C800
537 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
538 #define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
539 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
540 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
541 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
542 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
543 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
544 #define IXGBE_RTTDQSEL 0x04904
545 #define IXGBE_RTTDT1C 0x04908
546 #define IXGBE_RTTDT1S 0x0490C
547 #define IXGBE_RTTDTECC 0x04990
548 #define IXGBE_RTTDTECC_NO_BCN 0x00000100
550 #define IXGBE_RTTBCNRC 0x04984
551 #define IXGBE_RTTBCNRC_RS_ENA 0x80000000
552 #define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
553 #define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
554 #define IXGBE_RTTBCNRC_RF_INT_MASK \
555 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
556 #define IXGBE_RTTBCNRM 0x04980
558 /* BCN (for DCB) Registers */
559 #define IXGBE_RTTBCNRS 0x04988
560 #define IXGBE_RTTBCNCR 0x08B00
561 #define IXGBE_RTTBCNACH 0x08B04
562 #define IXGBE_RTTBCNACL 0x08B08
563 #define IXGBE_RTTBCNTG 0x04A90
564 #define IXGBE_RTTBCNIDX 0x08B0C
565 #define IXGBE_RTTBCNCP 0x08B10
566 #define IXGBE_RTFRTIMER 0x08B14
567 #define IXGBE_RTTBCNRTT 0x05150
568 #define IXGBE_RTTBCNRD 0x0498C
570 /* FCoE DMA Context Registers */
571 #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
572 #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
573 #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
574 #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
575 #define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
576 #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
577 #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
578 #define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
579 #define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
580 #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
581 #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
582 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
583 #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
584 #define IXGBE_FCBUFF_OFFSET_SHIFT 16
585 #define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
586 #define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
587 #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
588 #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
589 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
591 #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
592 #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
593 #define IXGBE_REOFF 0x05158 /* Rx FC EOF */
594 #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
595 /* FCoE Filter Context Registers */
596 #define IXGBE_FCFLT 0x05108 /* FC FLT Context */
597 #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
598 #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
599 #define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
600 #define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
601 #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
602 #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
603 #define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
604 #define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
605 #define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
606 /* FCoE Receive Control */
607 #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
608 #define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
609 #define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
610 #define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
611 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
612 #define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
613 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
614 #define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
615 #define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
616 #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
617 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
618 /* FCoE Redirection */
619 #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
620 #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
621 #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
622 #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
623 #define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */
624 #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
625 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
627 /* Stats registers */
628 #define IXGBE_CRCERRS 0x04000
629 #define IXGBE_ILLERRC 0x04004
630 #define IXGBE_ERRBC 0x04008
631 #define IXGBE_MSPDC 0x04010
632 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
633 #define IXGBE_MLFC 0x04034
634 #define IXGBE_MRFC 0x04038
635 #define IXGBE_RLEC 0x04040
636 #define IXGBE_LXONTXC 0x03F60
637 #define IXGBE_LXONRXC 0x0CF60
638 #define IXGBE_LXOFFTXC 0x03F68
639 #define IXGBE_LXOFFRXC 0x0CF68
640 #define IXGBE_LXONRXCNT 0x041A4
641 #define IXGBE_LXOFFRXCNT 0x041A8
642 #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
643 #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
644 #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
645 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
646 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
647 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
648 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
649 #define IXGBE_PRC64 0x0405C
650 #define IXGBE_PRC127 0x04060
651 #define IXGBE_PRC255 0x04064
652 #define IXGBE_PRC511 0x04068
653 #define IXGBE_PRC1023 0x0406C
654 #define IXGBE_PRC1522 0x04070
655 #define IXGBE_GPRC 0x04074
656 #define IXGBE_BPRC 0x04078
657 #define IXGBE_MPRC 0x0407C
658 #define IXGBE_GPTC 0x04080
659 #define IXGBE_GORCL 0x04088
660 #define IXGBE_GORCH 0x0408C
661 #define IXGBE_GOTCL 0x04090
662 #define IXGBE_GOTCH 0x04094
663 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
664 #define IXGBE_RUC 0x040A4
665 #define IXGBE_RFC 0x040A8
666 #define IXGBE_ROC 0x040AC
667 #define IXGBE_RJC 0x040B0
668 #define IXGBE_MNGPRC 0x040B4
669 #define IXGBE_MNGPDC 0x040B8
670 #define IXGBE_MNGPTC 0x0CF90
671 #define IXGBE_TORL 0x040C0
672 #define IXGBE_TORH 0x040C4
673 #define IXGBE_TPR 0x040D0
674 #define IXGBE_TPT 0x040D4
675 #define IXGBE_PTC64 0x040D8
676 #define IXGBE_PTC127 0x040DC
677 #define IXGBE_PTC255 0x040E0
678 #define IXGBE_PTC511 0x040E4
679 #define IXGBE_PTC1023 0x040E8
680 #define IXGBE_PTC1522 0x040EC
681 #define IXGBE_MPTC 0x040F0
682 #define IXGBE_BPTC 0x040F4
683 #define IXGBE_XEC 0x04120
684 #define IXGBE_SSVPC 0x08780
686 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
687 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
688 (0x08600 + ((_i) * 4)))
689 #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
691 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
692 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
693 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
694 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
695 #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
696 #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
697 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
698 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
699 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
700 #define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
701 #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
702 #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
703 #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
704 #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
705 #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
706 #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
707 #define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */
708 #define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */
709 #define IXGBE_O2BGPTC 0x041C4
710 #define IXGBE_O2BSPC 0x087B0
711 #define IXGBE_B2OSPC 0x041C0
712 #define IXGBE_B2OGPRC 0x02F90
713 #define IXGBE_BUPRC 0x04180
714 #define IXGBE_BMPRC 0x04184
715 #define IXGBE_BBPRC 0x04188
716 #define IXGBE_BUPTC 0x0418C
717 #define IXGBE_BMPTC 0x04190
718 #define IXGBE_BBPTC 0x04194
719 #define IXGBE_BCRCERRS 0x04198
720 #define IXGBE_BXONRXC 0x0419C
721 #define IXGBE_BXOFFRXC 0x041E0
722 #define IXGBE_BXONTXC 0x041E4
723 #define IXGBE_BXOFFTXC 0x041E8
724 #define IXGBE_PCRC8ECL 0x0E810
725 #define IXGBE_PCRC8ECH 0x0E811
726 #define IXGBE_PCRC8ECH_MASK 0x1F
727 #define IXGBE_LDPCECL 0x0E820
728 #define IXGBE_LDPCECH 0x0E821
731 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
732 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
733 #define IXGBE_MANC 0x05820
734 #define IXGBE_MFVAL 0x05824
735 #define IXGBE_MANC2H 0x05860
736 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
737 #define IXGBE_MIPAF 0x058B0
738 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
739 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
740 #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
741 #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
742 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
743 #define IXGBE_LSWFW 0x15014
744 #define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */
745 #define IXGBE_BMCIPVAL 0x05060
746 #define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
747 #define IXGBE_BMCIP_IPADDR_VALID 0x00000002
749 /* Management Bit Fields and Masks */
750 #define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Enable BMC2OS and OS2BMC
752 #define IXGBE_MANC_EN_BMC2OS_SHIFT 28
754 /* Firmware Semaphore Register */
755 #define IXGBE_FWSM_MODE_MASK 0xE
757 /* ARC Subsystem registers */
758 #define IXGBE_HICR 0x15F00
759 #define IXGBE_FWSTS 0x15F0C
760 #define IXGBE_HSMC0R 0x15F04
761 #define IXGBE_HSMC1R 0x15F08
762 #define IXGBE_SWSR 0x15F10
763 #define IXGBE_HFDR 0x15FE8
764 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
766 #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */
767 /* Driver sets this bit when done to put command in RAM */
768 #define IXGBE_HICR_C 0x02
769 #define IXGBE_HICR_SV 0x04 /* Status Validity */
770 #define IXGBE_HICR_FW_RESET_ENABLE 0x40
771 #define IXGBE_HICR_FW_RESET 0x80
773 /* PCI-E registers */
774 #define IXGBE_GCR 0x11000
775 #define IXGBE_GTV 0x11004
776 #define IXGBE_FUNCTAG 0x11008
777 #define IXGBE_GLT 0x1100C
778 #define IXGBE_PCIEPIPEADR 0x11004
779 #define IXGBE_PCIEPIPEDAT 0x11008
780 #define IXGBE_GSCL_1 0x11010
781 #define IXGBE_GSCL_2 0x11014
782 #define IXGBE_GSCL_3 0x11018
783 #define IXGBE_GSCL_4 0x1101C
784 #define IXGBE_GSCN_0 0x11020
785 #define IXGBE_GSCN_1 0x11024
786 #define IXGBE_GSCN_2 0x11028
787 #define IXGBE_GSCN_3 0x1102C
788 #define IXGBE_FACTPS 0x10150
789 #define IXGBE_PCIEANACTL 0x11040
790 #define IXGBE_SWSM 0x10140
791 #define IXGBE_FWSM 0x10148
792 #define IXGBE_GSSR 0x10160
793 #define IXGBE_MREVID 0x11064
794 #define IXGBE_DCA_ID 0x11070
795 #define IXGBE_DCA_CTRL 0x11074
796 #define IXGBE_SWFW_SYNC IXGBE_GSSR
798 /* PCI-E registers 82599-Specific */
799 #define IXGBE_GCR_EXT 0x11050
800 #define IXGBE_GSCL_5_82599 0x11030
801 #define IXGBE_GSCL_6_82599 0x11034
802 #define IXGBE_GSCL_7_82599 0x11038
803 #define IXGBE_GSCL_8_82599 0x1103C
804 #define IXGBE_PHYADR_82599 0x11040
805 #define IXGBE_PHYDAT_82599 0x11044
806 #define IXGBE_PHYCTL_82599 0x11048
807 #define IXGBE_PBACLR_82599 0x11068
808 #define IXGBE_CIAA_82599 0x11088
809 #define IXGBE_CIAD_82599 0x1108C
810 #define IXGBE_PICAUSE 0x110B0
811 #define IXGBE_PIENA 0x110B8
812 #define IXGBE_CDQ_MBR_82599 0x110B4
813 #define IXGBE_PCIESPARE 0x110BC
814 #define IXGBE_MISC_REG_82599 0x110F0
815 #define IXGBE_ECC_CTRL_0_82599 0x11100
816 #define IXGBE_ECC_CTRL_1_82599 0x11104
817 #define IXGBE_ECC_STATUS_82599 0x110E0
818 #define IXGBE_BAR_CTRL_82599 0x110F4
820 /* PCI Express Control */
821 #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
822 #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
823 #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
824 #define IXGBE_GCR_CAP_VER2 0x00040000
826 #define IXGBE_GCR_EXT_MSIX_EN 0x80000000
827 #define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
828 #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
829 #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
830 #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
831 #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
832 IXGBE_GCR_EXT_VT_MODE_64)
833 /* Time Sync Registers */
834 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
835 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
836 #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
837 #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
838 #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
839 #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
840 #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
841 #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
842 #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
843 #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
844 #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
845 #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
846 #define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */
847 #define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */
848 #define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */
849 #define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
850 #define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
851 #define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
852 #define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
853 #define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
854 #define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
855 #define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
856 #define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
857 #define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
858 #define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
860 /* Diagnostic Registers */
861 #define IXGBE_RDSTATCTL 0x02C20
862 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
863 #define IXGBE_RDHMPN 0x02F08
864 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
865 #define IXGBE_RDPROBE 0x02F20
866 #define IXGBE_RDMAM 0x02F30
867 #define IXGBE_RDMAD 0x02F34
868 #define IXGBE_TDSTATCTL 0x07C20
869 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
870 #define IXGBE_TDHMPN 0x07F08
871 #define IXGBE_TDHMPN2 0x082FC
872 #define IXGBE_TXDESCIC 0x082CC
873 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
874 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
875 #define IXGBE_TDPROBE 0x07F20
876 #define IXGBE_TXBUFCTRL 0x0C600
877 #define IXGBE_TXBUFDATA0 0x0C610
878 #define IXGBE_TXBUFDATA1 0x0C614
879 #define IXGBE_TXBUFDATA2 0x0C618
880 #define IXGBE_TXBUFDATA3 0x0C61C
881 #define IXGBE_RXBUFCTRL 0x03600
882 #define IXGBE_RXBUFDATA0 0x03610
883 #define IXGBE_RXBUFDATA1 0x03614
884 #define IXGBE_RXBUFDATA2 0x03618
885 #define IXGBE_RXBUFDATA3 0x0361C
886 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
887 #define IXGBE_RFVAL 0x050A4
888 #define IXGBE_MDFTC1 0x042B8
889 #define IXGBE_MDFTC2 0x042C0
890 #define IXGBE_MDFTFIFO1 0x042C4
891 #define IXGBE_MDFTFIFO2 0x042C8
892 #define IXGBE_MDFTS 0x042CC
893 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
894 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
895 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
896 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
897 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
898 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
899 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
900 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
901 #define IXGBE_PCIEECCCTL 0x1106C
902 #define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
903 #define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
904 #define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
905 #define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
906 #define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
907 #define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
908 #define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
909 #define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
910 #define IXGBE_PCIEECCCTL0 0x11100
911 #define IXGBE_PCIEECCCTL1 0x11104
912 #define IXGBE_RXDBUECC 0x03F70
913 #define IXGBE_TXDBUECC 0x0CF70
914 #define IXGBE_RXDBUEST 0x03F74
915 #define IXGBE_TXDBUEST 0x0CF74
916 #define IXGBE_PBTXECC 0x0C300
917 #define IXGBE_PBRXECC 0x03300
918 #define IXGBE_GHECCR 0x110B0
921 #define IXGBE_PCS1GCFIG 0x04200
922 #define IXGBE_PCS1GLCTL 0x04208
923 #define IXGBE_PCS1GLSTA 0x0420C
924 #define IXGBE_PCS1GDBG0 0x04210
925 #define IXGBE_PCS1GDBG1 0x04214
926 #define IXGBE_PCS1GANA 0x04218
927 #define IXGBE_PCS1GANLP 0x0421C
928 #define IXGBE_PCS1GANNP 0x04220
929 #define IXGBE_PCS1GANLPNP 0x04224
930 #define IXGBE_HLREG0 0x04240
931 #define IXGBE_HLREG1 0x04244
932 #define IXGBE_PAP 0x04248
933 #define IXGBE_MACA 0x0424C
934 #define IXGBE_APAE 0x04250
935 #define IXGBE_ARD 0x04254
936 #define IXGBE_AIS 0x04258
937 #define IXGBE_MSCA 0x0425C
938 #define IXGBE_MSRWD 0x04260
939 #define IXGBE_MLADD 0x04264
940 #define IXGBE_MHADD 0x04268
941 #define IXGBE_MAXFRS 0x04268
942 #define IXGBE_TREG 0x0426C
943 #define IXGBE_PCSS1 0x04288
944 #define IXGBE_PCSS2 0x0428C
945 #define IXGBE_XPCSS 0x04290
946 #define IXGBE_MFLCN 0x04294
947 #define IXGBE_SERDESC 0x04298
948 #define IXGBE_MACS 0x0429C
949 #define IXGBE_AUTOC 0x042A0
950 #define IXGBE_LINKS 0x042A4
951 #define IXGBE_LINKS2 0x04324
952 #define IXGBE_AUTOC2 0x042A8
953 #define IXGBE_AUTOC3 0x042AC
954 #define IXGBE_ANLP1 0x042B0
955 #define IXGBE_ANLP2 0x042B4
956 #define IXGBE_MACC 0x04330
957 #define IXGBE_ATLASCTL 0x04800
958 #define IXGBE_MMNGC 0x042D0
959 #define IXGBE_ANLPNP1 0x042D4
960 #define IXGBE_ANLPNP2 0x042D8
961 #define IXGBE_KRPCSFC 0x042E0
962 #define IXGBE_KRPCSS 0x042E4
963 #define IXGBE_FECS1 0x042E8
964 #define IXGBE_FECS2 0x042EC
965 #define IXGBE_SMADARCTL 0x14F10
966 #define IXGBE_MPVC 0x04318
967 #define IXGBE_SGMIIC 0x04314
969 /* Statistics Registers */
970 #define IXGBE_RXNFGPC 0x041B0
971 #define IXGBE_RXNFGBCL 0x041B4
972 #define IXGBE_RXNFGBCH 0x041B8
973 #define IXGBE_RXDGPC 0x02F50
974 #define IXGBE_RXDGBCL 0x02F54
975 #define IXGBE_RXDGBCH 0x02F58
976 #define IXGBE_RXDDGPC 0x02F5C
977 #define IXGBE_RXDDGBCL 0x02F60
978 #define IXGBE_RXDDGBCH 0x02F64
979 #define IXGBE_RXLPBKGPC 0x02F68
980 #define IXGBE_RXLPBKGBCL 0x02F6C
981 #define IXGBE_RXLPBKGBCH 0x02F70
982 #define IXGBE_RXDLPBKGPC 0x02F74
983 #define IXGBE_RXDLPBKGBCL 0x02F78
984 #define IXGBE_RXDLPBKGBCH 0x02F7C
985 #define IXGBE_TXDGPC 0x087A0
986 #define IXGBE_TXDGBCL 0x087A4
987 #define IXGBE_TXDGBCH 0x087A8
989 #define IXGBE_RXDSTATCTRL 0x02F40
991 /* Copper Pond 2 link timeout */
992 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
995 #define IXGBE_CORECTL 0x014F00
997 #define IXGBE_BARCTRL 0x110F4
998 #define IXGBE_BARCTRL_FLSIZE 0x0700
999 #define IXGBE_BARCTRL_FLSIZE_SHIFT 8
1000 #define IXGBE_BARCTRL_CSRSIZE 0x2000
1002 /* RSCCTL Bit Masks */
1003 #define IXGBE_RSCCTL_RSCEN 0x01
1004 #define IXGBE_RSCCTL_MAXDESC_1 0x00
1005 #define IXGBE_RSCCTL_MAXDESC_4 0x04
1006 #define IXGBE_RSCCTL_MAXDESC_8 0x08
1007 #define IXGBE_RSCCTL_MAXDESC_16 0x0C
1009 /* RSCDBU Bit Masks */
1010 #define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
1011 #define IXGBE_RSCDBU_RSCACKDIS 0x00000080
1013 /* RDRXCTL Bit Masks */
1014 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
1015 #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
1016 #define IXGBE_RDRXCTL_MVMEN 0x00000020
1017 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
1018 #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
1019 #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */
1020 #define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI */
1021 #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */
1022 #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
1024 /* RQTC Bit Masks and Shifts */
1025 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1026 #define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1027 #define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1028 #define IXGBE_RQTC_TC2_MASK (0x7 << 8)
1029 #define IXGBE_RQTC_TC3_MASK (0x7 << 12)
1030 #define IXGBE_RQTC_TC4_MASK (0x7 << 16)
1031 #define IXGBE_RQTC_TC5_MASK (0x7 << 20)
1032 #define IXGBE_RQTC_TC6_MASK (0x7 << 24)
1033 #define IXGBE_RQTC_TC7_MASK (0x7 << 28)
1035 /* PSRTYPE.RQPL Bit masks and shift */
1036 #define IXGBE_PSRTYPE_RQPL_MASK 0x7
1037 #define IXGBE_PSRTYPE_RQPL_SHIFT 29
1039 /* CTRL Bit Masks */
1040 #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
1041 #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
1042 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
1043 #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1046 #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
1048 /* MHADD Bit Masks */
1049 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000
1050 #define IXGBE_MHADD_MFS_SHIFT 16
1052 /* Extended Device Control */
1053 #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
1054 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
1055 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1056 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1058 /* Direct Cache Access (DCA) definitions */
1059 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
1060 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
1062 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
1063 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
1065 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1066 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
1067 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
1068 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
1069 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
1070 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
1071 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
1072 #define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
1073 #define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
1075 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
1076 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
1077 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
1078 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
1079 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
1080 #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
1082 /* MSCA Bit Masks */
1083 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
1084 #define IXGBE_MSCA_NP_ADDR_SHIFT 0
1085 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
1086 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
1087 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
1088 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
1089 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
1090 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
1091 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
1092 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
1093 #define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */
1094 #define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/
1095 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
1096 #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
1097 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
1098 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
1099 #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
1100 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
1102 /* MSRWD bit masks */
1103 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
1104 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
1105 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
1106 #define IXGBE_MSRWD_READ_DATA_SHIFT 16
1108 /* Atlas registers */
1109 #define IXGBE_ATLAS_PDN_LPBK 0x24
1110 #define IXGBE_ATLAS_PDN_10G 0xB
1111 #define IXGBE_ATLAS_PDN_1G 0xC
1112 #define IXGBE_ATLAS_PDN_AN 0xD
1114 /* Atlas bit masks */
1115 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
1116 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
1117 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
1118 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
1119 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1121 /* Omer bit masks */
1122 #define IXGBE_CORECTL_WRITE_CMD 0x00010000
1124 /* Device Type definitions for new protocol MDIO commands */
1125 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
1126 #define IXGBE_MDIO_PCS_DEV_TYPE 0x3
1127 #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
1128 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
1129 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
1130 #define IXGBE_TWINAX_DEV 1
1132 #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
1134 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
1135 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
1136 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
1137 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1138 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1139 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1141 #define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
1142 #define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
1143 #define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
1144 #define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */
1145 #define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
1146 #define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
1147 #define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
1148 #define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
1149 #define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
1150 #define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
1151 #define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
1152 #define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */
1153 #define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */
1154 #define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */
1155 #define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */
1156 #define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */
1157 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */
1159 #define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */
1160 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1161 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1162 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
1164 /* MII clause 22/28 definitions */
1165 #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
1167 #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */
1168 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1169 #define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
1170 #define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */
1171 #define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/
1172 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
1173 #define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
1174 #define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */
1175 #define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */
1176 #define IXGBE_MII_RESTART 0x200
1177 #define IXGBE_MII_AUTONEG_COMPLETE 0x20
1178 #define IXGBE_MII_AUTONEG_LINK_UP 0x04
1179 #define IXGBE_MII_AUTONEG_REG 0x0
1181 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1182 #define IXGBE_MAX_PHY_ADDR 32
1185 #define TN1010_PHY_ID 0x00A19410
1186 #define TNX_FW_REV 0xB
1187 #define X540_PHY_ID 0x01540200
1188 #define AQ_FW_REV 0x20
1189 #define QT2022_PHY_ID 0x0043A400
1190 #define ATH_PHY_ID 0x03429050
1193 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1195 /* Special PHY Init Routine */
1196 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1197 #define IXGBE_PHY_INIT_END_NL 0xFFFF
1198 #define IXGBE_CONTROL_MASK_NL 0xF000
1199 #define IXGBE_DATA_MASK_NL 0x0FFF
1200 #define IXGBE_CONTROL_SHIFT_NL 12
1201 #define IXGBE_DELAY_NL 0
1202 #define IXGBE_DATA_NL 1
1203 #define IXGBE_CONTROL_NL 0x000F
1204 #define IXGBE_CONTROL_EOL_NL 0x0FFF
1205 #define IXGBE_CONTROL_SOL_NL 0x0000
1207 /* General purpose Interrupt Enable */
1208 #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
1209 #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
1210 #define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
1211 #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
1212 #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
1213 #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
1214 #define IXGBE_GPIE_EIAME 0x40000000
1215 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000
1216 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1217 #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
1218 #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
1219 #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
1220 #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
1222 /* Packet Buffer Initialization */
1223 #define IXGBE_MAX_PACKET_BUFFERS 8
1225 #define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */
1226 #define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
1227 #define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
1228 #define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
1229 #define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
1230 #define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */
1231 #define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer */
1232 #define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer */
1234 #define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
1235 #define IXGBE_MAX_PB 8
1237 /* Packet buffer allocation strategies */
1239 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */
1240 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
1241 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */
1242 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
1245 /* Transmit Flow Control status */
1246 #define IXGBE_TFCS_TXOFF 0x00000001
1247 #define IXGBE_TFCS_TXOFF0 0x00000100
1248 #define IXGBE_TFCS_TXOFF1 0x00000200
1249 #define IXGBE_TFCS_TXOFF2 0x00000400
1250 #define IXGBE_TFCS_TXOFF3 0x00000800
1251 #define IXGBE_TFCS_TXOFF4 0x00001000
1252 #define IXGBE_TFCS_TXOFF5 0x00002000
1253 #define IXGBE_TFCS_TXOFF6 0x00004000
1254 #define IXGBE_TFCS_TXOFF7 0x00008000
1257 #define IXGBE_TCPTIMER_KS 0x00000100
1258 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1259 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1260 #define IXGBE_TCPTIMER_LOOP 0x00000800
1261 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1263 /* HLREG0 Bit Masks */
1264 #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
1265 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
1266 #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
1267 #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
1268 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
1269 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
1270 #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
1271 #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
1272 #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
1273 #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
1274 #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
1275 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
1276 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
1277 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
1278 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
1280 /* VMD_CTL bitmasks */
1281 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1282 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1284 /* VT_CTL bitmasks */
1285 #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
1286 #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
1287 #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
1288 #define IXGBE_VT_CTL_POOL_SHIFT 7
1289 #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1291 /* VMOLR bitmasks */
1292 #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
1293 #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
1294 #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
1295 #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
1296 #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
1299 #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1301 #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
1303 /* RDHMPN and TDHMPN bitmasks */
1304 #define IXGBE_RDHMPN_RDICADDR 0x007FF800
1305 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1306 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1307 #define IXGBE_TDHMPN_TDICADDR 0x003FF800
1308 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1309 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1311 #define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1312 #define IXGBE_RDMAM_DWORD_SHIFT 9
1313 #define IXGBE_RDMAM_DESC_COMP_FIFO 1
1314 #define IXGBE_RDMAM_DFC_CMD_FIFO 2
1315 #define IXGBE_RDMAM_RSC_HEADER_ADDR 3
1316 #define IXGBE_RDMAM_TCN_STATUS_RAM 4
1317 #define IXGBE_RDMAM_WB_COLL_FIFO 5
1318 #define IXGBE_RDMAM_QSC_CNT_RAM 6
1319 #define IXGBE_RDMAM_QSC_FCOE_RAM 7
1320 #define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1321 #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1322 #define IXGBE_RDMAM_QSC_RSC_RAM 0xB
1323 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1324 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1325 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1326 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1327 #define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32
1328 #define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4
1329 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1330 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1331 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1332 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1333 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1334 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1335 #define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512
1336 #define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5
1337 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1338 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1339 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1340 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1341 #define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32
1342 #define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8
1344 #define IXGBE_TXDESCIC_READY 0x80000000
1346 /* Receive Checksum Control */
1347 #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1348 #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1350 /* FCRTL Bit Masks */
1351 #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
1352 #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
1355 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
1357 /* RMCS Bit Masks */
1358 #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
1359 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1360 #define IXGBE_RMCS_RAC 0x00000004
1361 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
1362 #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
1363 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
1364 #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
1366 /* FCCFG Bit Masks */
1367 #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
1368 #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
1370 /* Interrupt register bitmasks */
1372 /* Extended Interrupt Cause Read */
1373 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
1374 #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1375 #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1376 #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1377 #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
1378 #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
1379 #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
1380 #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
1381 #define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */
1382 #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1383 #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
1384 #define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1385 #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
1386 #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1387 #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1388 #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1389 #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1391 /* Extended Interrupt Cause Set */
1392 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1393 #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1394 #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1395 #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1396 #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1397 #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1398 #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1399 #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1400 #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1401 #define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1402 #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
1403 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1404 #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
1405 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1406 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1408 /* Extended Interrupt Mask Set */
1409 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1410 #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1411 #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1412 #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1413 #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1414 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1415 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1416 #define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */
1417 #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1418 #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1419 #define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1420 #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
1421 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1422 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1423 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1424 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1426 /* Extended Interrupt Mask Clear */
1427 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1428 #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1429 #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1430 #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1431 #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1432 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1433 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1434 #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1435 #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1436 #define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1437 #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
1438 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1439 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
1440 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1441 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1443 #define IXGBE_EIMS_ENABLE_MASK ( \
1444 IXGBE_EIMS_RTX_QUEUE | \
1446 IXGBE_EIMS_TCP_TIMER | \
1449 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1450 #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
1451 #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
1452 #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
1453 #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
1454 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
1455 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
1456 #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
1457 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
1458 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
1459 #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
1460 #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
1461 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1462 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1463 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1464 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1465 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1466 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1467 #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */
1468 #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
1469 #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
1470 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1471 #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
1472 #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
1474 #define IXGBE_MAX_FTQF_FILTERS 128
1475 #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1476 #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1477 #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1478 #define IXGBE_FTQF_PROTOCOL_SCTP 2
1479 #define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1480 #define IXGBE_FTQF_PRIORITY_SHIFT 2
1481 #define IXGBE_FTQF_POOL_MASK 0x0000003F
1482 #define IXGBE_FTQF_POOL_SHIFT 8
1483 #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1484 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1485 #define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
1486 #define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
1487 #define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
1488 #define IXGBE_FTQF_DEST_PORT_MASK 0x17
1489 #define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
1490 #define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1491 #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
1493 /* Interrupt clear mask */
1494 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1496 /* Interrupt Vector Allocation Registers */
1497 #define IXGBE_IVAR_REG_NUM 25
1498 #define IXGBE_IVAR_REG_NUM_82599 64
1499 #define IXGBE_IVAR_TXRX_ENTRY 96
1500 #define IXGBE_IVAR_RX_ENTRY 64
1501 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1502 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1503 #define IXGBE_IVAR_TX_ENTRY 32
1505 #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
1506 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
1508 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1510 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
1512 /* ETYPE Queue Filter/Select Bit Masks */
1513 #define IXGBE_MAX_ETQF_FILTERS 8
1514 #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
1515 #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1516 #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1517 #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1518 #define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
1520 #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1521 #define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1522 #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1523 #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1526 * ETQF filter list: one static filter per filter consumer. This is
1527 * to avoid filter collisions later. Add new filters
1531 * EAPOL 802.1x (0x888e): Filter 0
1532 * FCoE (0x8906): Filter 2
1533 * 1588 (0x88f7): Filter 3
1534 * FIP (0x8914): Filter 4
1536 #define IXGBE_ETQF_FILTER_EAPOL 0
1537 #define IXGBE_ETQF_FILTER_FCOE 2
1538 #define IXGBE_ETQF_FILTER_1588 3
1539 #define IXGBE_ETQF_FILTER_FIP 4
1540 /* VLAN Control Bit Masks */
1541 #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
1542 #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
1543 #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
1544 #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
1545 #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
1547 /* VLAN pool filtering masks */
1548 #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1549 #define IXGBE_VLVF_ENTRIES 64
1550 #define IXGBE_VLVF_VLANID_MASK 0x00000FFF
1551 /* Per VF Port VLAN insertion rules */
1552 #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
1553 #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
1555 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
1557 /* STATUS Bit Masks */
1558 #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
1559 #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1560 #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
1562 #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
1563 #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
1565 /* ESDP Bit Masks */
1566 #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1567 #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1568 #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1569 #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1570 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1571 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1572 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1573 #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
1574 #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
1576 /* LEDCTL Bit Masks */
1577 #define IXGBE_LED_IVRT_BASE 0x00000040
1578 #define IXGBE_LED_BLINK_BASE 0x00000080
1579 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1580 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1581 #define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
1582 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1583 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1584 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1587 #define IXGBE_LED_LINK_UP 0x0
1588 #define IXGBE_LED_LINK_10G 0x1
1589 #define IXGBE_LED_MAC 0x2
1590 #define IXGBE_LED_FILTER 0x3
1591 #define IXGBE_LED_LINK_ACTIVE 0x4
1592 #define IXGBE_LED_LINK_1G 0x5
1593 #define IXGBE_LED_ON 0xE
1594 #define IXGBE_LED_OFF 0xF
1596 /* AUTOC Bit Masks */
1597 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1598 #define IXGBE_AUTOC_KX4_SUPP 0x80000000
1599 #define IXGBE_AUTOC_KX_SUPP 0x40000000
1600 #define IXGBE_AUTOC_PAUSE 0x30000000
1601 #define IXGBE_AUTOC_ASM_PAUSE 0x20000000
1602 #define IXGBE_AUTOC_SYM_PAUSE 0x10000000
1603 #define IXGBE_AUTOC_RF 0x08000000
1604 #define IXGBE_AUTOC_PD_TMR 0x06000000
1605 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1606 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1607 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1608 #define IXGBE_AUTOC_FECA 0x00040000
1609 #define IXGBE_AUTOC_FECR 0x00020000
1610 #define IXGBE_AUTOC_KR_SUPP 0x00010000
1611 #define IXGBE_AUTOC_AN_RESTART 0x00001000
1612 #define IXGBE_AUTOC_FLU 0x00000001
1613 #define IXGBE_AUTOC_LMS_SHIFT 13
1614 #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1615 #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1616 #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1617 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1618 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1619 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1620 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1621 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1622 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1623 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1624 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1625 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1627 #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1628 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1629 #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1630 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
1631 #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1632 #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1633 #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1634 #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1635 #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1636 #define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1637 #define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1639 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1640 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1641 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1642 #define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1643 #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1644 #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1646 #define IXGBE_MACC_FLU 0x00000001
1647 #define IXGBE_MACC_FSV_10G 0x00030000
1648 #define IXGBE_MACC_FS 0x00040000
1649 #define IXGBE_MAC_RX2TX_LPBK 0x00000002
1651 /* LINKS Bit Masks */
1652 #define IXGBE_LINKS_KX_AN_COMP 0x80000000
1653 #define IXGBE_LINKS_UP 0x40000000
1654 #define IXGBE_LINKS_SPEED 0x20000000
1655 #define IXGBE_LINKS_MODE 0x18000000
1656 #define IXGBE_LINKS_RX_MODE 0x06000000
1657 #define IXGBE_LINKS_TX_MODE 0x01800000
1658 #define IXGBE_LINKS_XGXS_EN 0x00400000
1659 #define IXGBE_LINKS_SGMII_EN 0x02000000
1660 #define IXGBE_LINKS_PCS_1G_EN 0x00200000
1661 #define IXGBE_LINKS_1G_AN_EN 0x00100000
1662 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1663 #define IXGBE_LINKS_1G_SYNC 0x00040000
1664 #define IXGBE_LINKS_10G_ALIGN 0x00020000
1665 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1666 #define IXGBE_LINKS_TL_FAULT 0x00001000
1667 #define IXGBE_LINKS_SIGNAL 0x00000F00
1669 #define IXGBE_LINKS_SPEED_82599 0x30000000
1670 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1671 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1672 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
1673 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
1674 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
1676 #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
1678 /* PCS1GLSTA Bit Masks */
1679 #define IXGBE_PCS1GLSTA_LINK_OK 1
1680 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1681 #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1682 #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1683 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1684 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1685 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1687 #define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1688 #define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1690 /* PCS1GLCTL Bit Masks */
1691 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
1692 #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1693 #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1694 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1695 #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1696 #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1698 /* ANLP1 Bit Masks */
1699 #define IXGBE_ANLP1_PAUSE 0x0C00
1700 #define IXGBE_ANLP1_SYM_PAUSE 0x0400
1701 #define IXGBE_ANLP1_ASM_PAUSE 0x0800
1702 #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
1704 /* SW Semaphore Register bitmasks */
1705 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1706 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1707 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1708 #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1710 /* SW_FW_SYNC/GSSR definitions */
1711 #define IXGBE_GSSR_EEP_SM 0x0001
1712 #define IXGBE_GSSR_PHY0_SM 0x0002
1713 #define IXGBE_GSSR_PHY1_SM 0x0004
1714 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
1715 #define IXGBE_GSSR_FLASH_SM 0x0010
1716 #define IXGBE_GSSR_SW_MNG_SM 0x0400
1718 /* FW Status register bitmask */
1719 #define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */
1722 #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
1723 #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
1724 #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
1725 #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
1726 #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
1727 #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
1728 #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
1729 #define IXGBE_EEC_FWE_SHIFT 4
1730 #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
1731 #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1732 #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1733 #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
1734 #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
1735 #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
1736 #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
1737 /* EEPROM Addressing bits based on type (0-small, 1-large) */
1738 #define IXGBE_EEC_ADDR_SIZE 0x00000400
1739 #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
1740 #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */
1742 #define IXGBE_EEC_SIZE_SHIFT 11
1743 #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
1744 #define IXGBE_EEPROM_OPCODE_BITS 8
1746 /* Part Number String Length */
1747 #define IXGBE_PBANUM_LENGTH 11
1749 /* Checksum and EEPROM pointers */
1750 #define IXGBE_PBANUM_PTR_GUARD 0xFAFA
1751 #define IXGBE_EEPROM_CHECKSUM 0x3F
1752 #define IXGBE_EEPROM_SUM 0xBABA
1753 #define IXGBE_PCIE_ANALOG_PTR 0x03
1754 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
1755 #define IXGBE_PHY_PTR 0x04
1756 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
1757 #define IXGBE_OPTION_ROM_PTR 0x05
1758 #define IXGBE_PCIE_GENERAL_PTR 0x06
1759 #define IXGBE_PCIE_CONFIG0_PTR 0x07
1760 #define IXGBE_PCIE_CONFIG1_PTR 0x08
1761 #define IXGBE_CORE0_PTR 0x09
1762 #define IXGBE_CORE1_PTR 0x0A
1763 #define IXGBE_MAC0_PTR 0x0B
1764 #define IXGBE_MAC1_PTR 0x0C
1765 #define IXGBE_CSR0_CONFIG_PTR 0x0D
1766 #define IXGBE_CSR1_CONFIG_PTR 0x0E
1767 #define IXGBE_FW_PTR 0x0F
1768 #define IXGBE_PBANUM0_PTR 0x15
1769 #define IXGBE_PBANUM1_PTR 0x16
1770 #define IXGBE_FREE_SPACE_PTR 0X3E
1771 #define IXGBE_SAN_MAC_ADDR_PTR 0x28
1772 #define IXGBE_DEVICE_CAPS 0x2C
1773 #define IXGBE_DEVICE_CAPS_EXT_THERMAL_SENSOR 0x10
1774 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
1775 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72
1776 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1778 /* MSI-X capability fields masks */
1779 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
1781 /* Legacy EEPROM word offsets */
1782 #define IXGBE_ISCSI_BOOT_CAPS 0x0033
1783 #define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1784 #define IXGBE_ISCSI_SETUP_PORT_1 0x0034
1786 /* EEPROM Commands - SPI */
1787 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
1788 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
1789 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1790 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1791 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
1792 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
1793 /* EEPROM reset Write Enable latch */
1794 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
1795 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
1796 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
1797 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1798 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1799 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1801 /* EEPROM Read Register */
1802 #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */
1803 #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */
1804 #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
1805 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1806 #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1807 #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */
1809 #define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1811 #define IXGBE_EEPROM_PAGE_SIZE_MAX 128
1812 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
1813 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
1815 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1816 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1819 /* Number of 5 microseconds we wait for EERD read and
1820 * EERW write to complete */
1821 #define IXGBE_EERD_EEWR_ATTEMPTS 100000
1823 /* # attempts we wait for flush update to complete */
1824 #define IXGBE_FLUDONE_ATTEMPTS 20000
1826 #define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */
1827 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
1828 #define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
1829 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
1831 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1832 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
1833 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
1834 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
1835 #define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
1836 #define IXGBE_FW_LESM_STATE_1 0x1
1837 #define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
1838 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
1839 #define IXGBE_FW_PATCH_VERSION_4 0x7
1840 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
1841 #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
1842 #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
1843 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */
1844 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */
1845 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
1846 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
1847 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
1848 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
1849 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
1850 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
1851 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
1852 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
1854 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */
1855 #define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */
1856 #define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */
1859 #define IXGBE_PCI_DEVICE_STATUS 0xAA
1860 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
1861 #define IXGBE_PCI_LINK_STATUS 0xB2
1862 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8
1863 #define IXGBE_PCI_LINK_WIDTH 0x3F0
1864 #define IXGBE_PCI_LINK_WIDTH_1 0x10
1865 #define IXGBE_PCI_LINK_WIDTH_2 0x20
1866 #define IXGBE_PCI_LINK_WIDTH_4 0x40
1867 #define IXGBE_PCI_LINK_WIDTH_8 0x80
1868 #define IXGBE_PCI_LINK_SPEED 0xF
1869 #define IXGBE_PCI_LINK_SPEED_2500 0x1
1870 #define IXGBE_PCI_LINK_SPEED_5000 0x2
1871 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1872 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1873 #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
1875 /* Number of 100 microseconds we wait for PCI Express master disable */
1876 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1878 /* Check whether address is multicast. This is little-endian specific check.*/
1879 #define IXGBE_IS_MULTICAST(Address) \
1880 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
1882 /* Check whether an address is broadcast. */
1883 #define IXGBE_IS_BROADCAST(Address) \
1884 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
1885 (((u8 *)(Address))[1] == ((u8)0xff)))
1888 #define IXGBE_RAH_VIND_MASK 0x003C0000
1889 #define IXGBE_RAH_VIND_SHIFT 18
1890 #define IXGBE_RAH_AV 0x80000000
1891 #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
1893 /* Header split receive */
1894 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001
1895 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
1896 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
1897 #define IXGBE_RFCTL_RSC_DIS 0x00000010
1898 #define IXGBE_RFCTL_NFSW_DIS 0x00000040
1899 #define IXGBE_RFCTL_NFSR_DIS 0x00000080
1900 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
1901 #define IXGBE_RFCTL_NFS_VER_SHIFT 8
1902 #define IXGBE_RFCTL_NFS_VER_2 0
1903 #define IXGBE_RFCTL_NFS_VER_3 1
1904 #define IXGBE_RFCTL_NFS_VER_4 2
1905 #define IXGBE_RFCTL_IPV6_DIS 0x00000400
1906 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
1907 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
1908 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
1909 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1911 /* Transmit Config masks */
1912 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
1913 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
1914 #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
1915 /* Enable short packet padding to 64 bytes */
1916 #define IXGBE_TX_PAD_ENABLE 0x00000400
1917 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
1918 /* This allows for 16K packets + 4k for vlan */
1919 #define IXGBE_MAX_FRAME_SZ 0x40040000
1921 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
1922 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
1924 /* Receive Config masks */
1925 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
1926 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
1927 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
1928 #define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */
1929 #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */
1930 #define IXGBE_RXDCTL_RLPML_EN 0x00008000
1931 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
1933 #define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
1934 #define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */
1936 #define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
1937 #define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
1938 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
1939 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
1940 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
1941 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
1942 #define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */
1944 #define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF
1945 #define IXGBE_RXMTRL_V1_SYNC_MSG 0x00
1946 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01
1947 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02
1948 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03
1949 #define IXGBE_RXMTRL_V1_MGMT_MSG 0x04
1951 #define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00
1952 #define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000
1953 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100
1954 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200
1955 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
1956 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800
1957 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900
1958 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
1959 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00
1960 #define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00
1961 #define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00
1963 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
1964 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
1965 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
1966 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
1967 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
1968 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
1969 /* Receive Priority Flow Control Enable */
1970 #define IXGBE_FCTRL_RPFCE 0x00004000
1971 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
1972 #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
1973 #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
1974 #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1975 #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
1976 #define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */
1978 /* Multiple Receive Queue Control */
1979 #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
1980 #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
1981 #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
1982 #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
1983 #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
1984 #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
1985 #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
1986 #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
1987 #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
1988 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
1989 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
1990 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
1991 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1992 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
1993 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
1994 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1995 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
1996 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1997 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
1998 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
1999 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2000 #define IXGBE_MRQC_L3L4TXSWEN 0x00008000
2002 /* Queue Drop Enable */
2003 #define IXGBE_QDE_ENABLE 0x00000001
2004 #define IXGBE_QDE_IDX_MASK 0x00007F00
2005 #define IXGBE_QDE_IDX_SHIFT 8
2007 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
2008 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
2009 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
2010 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
2011 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
2012 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
2013 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
2014 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
2015 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
2017 #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
2018 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
2019 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
2020 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
2021 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
2022 /* Multiple Transmit Queue Command Register */
2023 #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
2024 #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
2025 #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
2026 #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
2027 #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
2028 #define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */
2029 #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
2031 /* Receive Descriptor bit definitions */
2032 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
2033 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
2034 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
2035 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
2036 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
2037 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
2038 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
2039 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
2040 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
2041 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
2042 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
2043 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
2044 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
2045 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
2046 #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
2047 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
2048 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
2049 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
2050 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
2051 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
2052 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
2053 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
2054 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
2055 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
2056 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
2057 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
2058 #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
2059 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
2060 #define IXGBE_RXDADV_ERR_RXE 0x20000000 /* Any MAC Error */
2061 #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */
2062 #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
2063 #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */
2064 #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */
2065 #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */
2066 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
2067 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
2068 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
2069 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
2070 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
2071 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
2072 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
2073 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
2074 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
2075 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
2076 #define IXGBE_RXD_PRI_SHIFT 13
2077 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
2078 #define IXGBE_RXD_CFI_SHIFT 12
2080 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
2081 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
2082 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
2083 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
2084 #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
2085 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
2086 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
2087 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2088 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
2089 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2090 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
2091 #define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE1588 Time Stamp */
2093 /* PSRTYPE bit definitions */
2094 #define IXGBE_PSRTYPE_TCPHDR 0x00000010
2095 #define IXGBE_PSRTYPE_UDPHDR 0x00000020
2096 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100
2097 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200
2098 #define IXGBE_PSRTYPE_L2HDR 0x00001000
2100 /* SRRCTL bit definitions */
2101 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
2102 #define IXGBE_SRRCTL_RDMTS_SHIFT 22
2103 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
2104 #define IXGBE_SRRCTL_DROP_EN 0x10000000
2105 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
2106 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
2107 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
2108 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2109 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2110 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2111 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2112 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
2114 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
2115 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2117 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
2118 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
2119 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
2120 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
2121 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
2122 #define IXGBE_RXDADV_RSCCNT_SHIFT 17
2123 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
2124 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
2125 #define IXGBE_RXDADV_SPH 0x8000
2127 /* RSS Hash results */
2128 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
2129 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
2130 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
2131 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
2132 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
2133 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
2134 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2135 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
2136 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
2137 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2139 /* RSS Packet Types as indicated in the receive descriptor. */
2140 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
2141 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
2142 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
2143 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
2144 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
2145 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
2146 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
2147 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
2148 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
2149 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
2150 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
2151 #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
2152 #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
2153 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
2154 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
2156 /* Security Processing bit Indication */
2157 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
2158 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
2159 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
2160 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
2161 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
2163 /* Masks to determine if packets should be dropped due to frame errors */
2164 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2165 IXGBE_RXD_ERR_CE | \
2166 IXGBE_RXD_ERR_LE | \
2167 IXGBE_RXD_ERR_PE | \
2168 IXGBE_RXD_ERR_OSE | \
2171 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2172 IXGBE_RXDADV_ERR_CE | \
2173 IXGBE_RXDADV_ERR_LE | \
2174 IXGBE_RXDADV_ERR_PE | \
2175 IXGBE_RXDADV_ERR_OSE | \
2176 IXGBE_RXDADV_ERR_USE)
2178 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599 IXGBE_RXDADV_ERR_RXE
2180 /* Multicast bit mask */
2181 #define IXGBE_MCSTCTRL_MFE 0x4
2183 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2184 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
2185 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
2186 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
2188 /* Vlan-specific macros */
2189 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
2190 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
2191 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
2192 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2194 /* SR-IOV specific macros */
2195 #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
2196 #define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4))
2197 #define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
2198 #define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))
2200 /* Little Endian defines */
2212 /* Big Endian defines */
2218 enum ixgbe_fdir_pballoc_type {
2219 IXGBE_FDIR_PBALLOC_NONE = 0,
2220 IXGBE_FDIR_PBALLOC_64K = 1,
2221 IXGBE_FDIR_PBALLOC_128K = 2,
2222 IXGBE_FDIR_PBALLOC_256K = 3,
2225 /* Flow Director register values */
2226 #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
2227 #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
2228 #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
2229 #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
2230 #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
2231 #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
2232 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
2233 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
2234 #define IXGBE_FDIRCTRL_FLEX_SHIFT 16
2235 #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
2236 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
2237 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
2238 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
2240 #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
2241 #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
2242 #define IXGBE_FDIRIP6M_DIPM_SHIFT 16
2243 #define IXGBE_FDIRM_VLANID 0x00000001
2244 #define IXGBE_FDIRM_VLANP 0x00000002
2245 #define IXGBE_FDIRM_POOL 0x00000004
2246 #define IXGBE_FDIRM_L4P 0x00000008
2247 #define IXGBE_FDIRM_FLEX 0x00000010
2248 #define IXGBE_FDIRM_DIPv6 0x00000020
2250 #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
2251 #define IXGBE_FDIRFREE_FREE_SHIFT 0
2252 #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
2253 #define IXGBE_FDIRFREE_COLL_SHIFT 16
2254 #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
2255 #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
2256 #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
2257 #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
2258 #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
2259 #define IXGBE_FDIRUSTAT_ADD_SHIFT 0
2260 #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
2261 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
2262 #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
2263 #define IXGBE_FDIRFSTAT_FADD_SHIFT 0
2264 #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
2265 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
2266 #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
2267 #define IXGBE_FDIRVLAN_FLEX_SHIFT 16
2268 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
2269 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
2271 #define IXGBE_FDIRCMD_CMD_MASK 0x00000003
2272 #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
2273 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
2274 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
2275 #define IXGBE_FDIRCMD_FILTER_VALID 0x00000004
2276 #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
2277 #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
2278 #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
2279 #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
2280 #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2281 #define IXGBE_FDIRCMD_IPV6 0x00000080
2282 #define IXGBE_FDIRCMD_CLEARHT 0x00000100
2283 #define IXGBE_FDIRCMD_DROP 0x00000200
2284 #define IXGBE_FDIRCMD_INT 0x00000400
2285 #define IXGBE_FDIRCMD_LAST 0x00000800
2286 #define IXGBE_FDIRCMD_COLLISION 0x00001000
2287 #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
2288 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
2289 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2290 #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2291 #define IXGBE_FDIR_INIT_DONE_POLL 10
2292 #define IXGBE_FDIRCMD_CMD_POLL 10
2294 #define IXGBE_FDIR_DROP_QUEUE 127
2297 /* Manageablility Host Interface defines */
2298 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
2299 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
2300 #define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */
2303 #define FW_CEM_HDR_LEN 0x4
2304 #define FW_CEM_CMD_DRIVER_INFO 0xDD
2305 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
2306 #define FW_CEM_CMD_RESERVED 0X0
2307 #define FW_CEM_UNUSED_VER 0x0
2308 #define FW_CEM_MAX_RETRIES 3
2309 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
2311 /* Host Interface Command Structures */
2313 struct ixgbe_hic_hdr {
2323 struct ixgbe_hic_drv_info {
2324 struct ixgbe_hic_hdr hdr;
2330 u8 pad; /* end spacing to ensure length is mult. of dword */
2331 u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2334 /* Transmit Descriptor - Legacy */
2335 struct ixgbe_legacy_tx_desc {
2336 u64 buffer_addr; /* Address of the descriptor's data buffer */
2340 __le16 length; /* Data buffer length */
2341 u8 cso; /* Checksum offset */
2342 u8 cmd; /* Descriptor control */
2348 u8 status; /* Descriptor status */
2349 u8 css; /* Checksum start */
2355 /* Transmit Descriptor - Advanced */
2356 union ixgbe_adv_tx_desc {
2358 __le64 buffer_addr; /* Address of descriptor's data buf */
2359 __le32 cmd_type_len;
2360 __le32 olinfo_status;
2363 __le64 rsvd; /* Reserved */
2369 /* Receive Descriptor - Legacy */
2370 struct ixgbe_legacy_rx_desc {
2371 __le64 buffer_addr; /* Address of the descriptor's data buffer */
2372 __le16 length; /* Length of data DMAed into data buffer */
2373 __le16 csum; /* Packet checksum */
2374 u8 status; /* Descriptor status */
2375 u8 errors; /* Descriptor Errors */
2379 /* Receive Descriptor - Advanced */
2380 union ixgbe_adv_rx_desc {
2382 __le64 pkt_addr; /* Packet buffer address */
2383 __le64 hdr_addr; /* Header buffer address */
2390 __le16 pkt_info; /* RSS, Pkt type */
2391 __le16 hdr_info; /* Splithdr, hdrlen */
2395 __le32 rss; /* RSS Hash */
2397 __le16 ip_id; /* IP id */
2398 __le16 csum; /* Packet Checksum */
2403 __le32 status_error; /* ext status/error */
2404 __le16 length; /* Packet length */
2405 __le16 vlan; /* VLAN tag */
2407 } wb; /* writeback */
2410 /* Context descriptors */
2411 struct ixgbe_adv_tx_context_desc {
2412 __le32 vlan_macip_lens;
2414 __le32 type_tucmd_mlhl;
2415 __le32 mss_l4len_idx;
2418 /* Adv Transmit Descriptor Config Masks */
2419 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
2420 #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
2421 #define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 time stamp */
2422 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
2423 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
2424 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
2425 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
2426 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
2427 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
2428 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
2429 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
2430 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
2431 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
2432 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
2433 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
2434 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
2435 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
2436 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
2437 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
2438 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
2439 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
2440 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2441 IXGBE_ADVTXD_POPTS_SHIFT)
2442 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2443 IXGBE_ADVTXD_POPTS_SHIFT)
2444 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
2445 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
2446 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
2447 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
2448 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
2449 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
2450 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
2451 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
2452 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
2453 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
2454 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
2455 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
2456 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
2457 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
2458 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
2459 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2460 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2461 #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
2462 #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
2463 #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
2464 #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
2465 #define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */
2466 #define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */
2467 #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
2468 #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
2469 #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
2470 #define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
2471 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
2472 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
2474 /* Autonegotiation advertised speeds */
2475 typedef u32 ixgbe_autoneg_advertised;
2477 typedef u32 ixgbe_link_speed;
2478 #define IXGBE_LINK_SPEED_UNKNOWN 0
2479 #define IXGBE_LINK_SPEED_100_FULL 0x0008
2480 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2481 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080
2482 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2483 IXGBE_LINK_SPEED_10GB_FULL)
2484 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2485 IXGBE_LINK_SPEED_1GB_FULL | \
2486 IXGBE_LINK_SPEED_10GB_FULL)
2489 /* Physical layer type */
2490 typedef u32 ixgbe_physical_layer;
2491 #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
2492 #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
2493 #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
2494 #define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
2495 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
2496 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
2497 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
2498 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
2499 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
2500 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
2501 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
2502 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
2503 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
2504 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
2505 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
2507 /* Flow Control Data Sheet defined values
2508 * Calculation and defines taken from 802.1bb Annex O
2511 /* BitTimes (BT) conversion */
2512 #define IXGBE_BT2KB(BT) ((BT + 1023) / (8 * 1024))
2513 #define IXGBE_B2BT(BT) (BT * 8)
2515 /* Calculate Delay to respond to PFC */
2516 #define IXGBE_PFC_D 672
2518 /* Calculate Cable Delay */
2519 #define IXGBE_CABLE_DC 5556 /* Delay Copper */
2520 #define IXGBE_CABLE_DO 5000 /* Delay Optical */
2522 /* Calculate Interface Delay X540 */
2523 #define IXGBE_PHY_DC 25600 /* Delay 10G BASET */
2524 #define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */
2525 #define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */
2527 #define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
2529 /* Calculate Interface Delay 82598, 82599 */
2530 #define IXGBE_PHY_D 12800
2531 #define IXGBE_MAC_D 4096
2532 #define IXGBE_XAUI_D (2 * 1024)
2534 #define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
2536 /* Calculate Delay incurred from higher layer */
2537 #define IXGBE_HD 6144
2539 /* Calculate PCI Bus delay for low thresholds */
2540 #define IXGBE_PCI_DELAY 10000
2542 /* Calculate X540 delay value in bit times */
2543 #define IXGBE_FILL_RATE (36 / 25)
2545 #define IXGBE_DV_X540(LINK, TC) (IXGBE_FILL_RATE * \
2546 (IXGBE_B2BT(LINK) + IXGBE_PFC_D + \
2547 (2 * IXGBE_CABLE_DC) + \
2548 (2 * IXGBE_ID_X540) + \
2549 IXGBE_HD + IXGBE_B2BT(TC)))
2551 /* Calculate 82599, 82598 delay value in bit times */
2552 #define IXGBE_DV(LINK, TC) (IXGBE_FILL_RATE * \
2553 (IXGBE_B2BT(LINK) + IXGBE_PFC_D + \
2554 (2 * IXGBE_CABLE_DC) + (2 * IXGBE_ID) + \
2555 IXGBE_HD + IXGBE_B2BT(TC)))
2557 /* Calculate low threshold delay values */
2558 #define IXGBE_LOW_DV_X540(TC) (2 * IXGBE_B2BT(TC) + \
2559 (IXGBE_FILL_RATE * IXGBE_PCI_DELAY))
2560 #define IXGBE_LOW_DV(TC) (2 * IXGBE_LOW_DV_X540(TC))
2562 /* Software ATR hash keys */
2563 #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
2564 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2566 /* Software ATR input stream values and masks */
2567 #define IXGBE_ATR_HASH_MASK 0x7fff
2568 #define IXGBE_ATR_L4TYPE_MASK 0x3
2569 #define IXGBE_ATR_L4TYPE_UDP 0x1
2570 #define IXGBE_ATR_L4TYPE_TCP 0x2
2571 #define IXGBE_ATR_L4TYPE_SCTP 0x3
2572 #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2573 enum ixgbe_atr_flow_type {
2574 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
2575 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
2576 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
2577 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
2578 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
2579 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
2580 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
2581 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
2584 /* Flow Director ATR input struct. */
2585 union ixgbe_atr_input {
2587 * Byte layout in order, all values with MSB first:
2590 * flow_type - 1 byte
2594 * src_port - 2 bytes
2595 * dst_port - 2 bytes
2596 * flex_bytes - 2 bytes
2597 * bkt_hash - 2 bytes
2610 __be32 dword_stream[11];
2613 /* Flow Director compressed ATR hash input struct */
2614 union ixgbe_atr_hash_dword {
2631 * Unavailable: The FCoE Boot Option ROM is not present in the flash.
2632 * Disabled: Present; boot order is not set for any targets on the port.
2633 * Enabled: Present; boot order is set for at least one target on the port.
2635 enum ixgbe_fcoe_boot_status {
2636 ixgbe_fcoe_bootstatus_disabled = 0,
2637 ixgbe_fcoe_bootstatus_enabled = 1,
2638 ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
2641 enum ixgbe_eeprom_type {
2642 ixgbe_eeprom_uninitialized = 0,
2645 ixgbe_eeprom_none /* No NVM support */
2648 enum ixgbe_mac_type {
2649 ixgbe_mac_unknown = 0,
2658 enum ixgbe_phy_type {
2659 ixgbe_phy_unknown = 0,
2663 ixgbe_phy_cu_unknown,
2667 ixgbe_phy_sfp_passive_tyco,
2668 ixgbe_phy_sfp_passive_unknown,
2669 ixgbe_phy_sfp_active_unknown,
2670 ixgbe_phy_sfp_avago,
2672 ixgbe_phy_sfp_ftl_active,
2673 ixgbe_phy_sfp_unknown,
2674 ixgbe_phy_sfp_intel,
2675 ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
2680 * SFP+ module type IDs:
2687 * 3 SFP_DA_CU_CORE0 - 82599-specific
2688 * 4 SFP_DA_CU_CORE1 - 82599-specific
2689 * 5 SFP_SR/LR_CORE0 - 82599-specific
2690 * 6 SFP_SR/LR_CORE1 - 82599-specific
2692 enum ixgbe_sfp_type {
2693 ixgbe_sfp_type_da_cu = 0,
2694 ixgbe_sfp_type_sr = 1,
2695 ixgbe_sfp_type_lr = 2,
2696 ixgbe_sfp_type_da_cu_core0 = 3,
2697 ixgbe_sfp_type_da_cu_core1 = 4,
2698 ixgbe_sfp_type_srlr_core0 = 5,
2699 ixgbe_sfp_type_srlr_core1 = 6,
2700 ixgbe_sfp_type_da_act_lmt_core0 = 7,
2701 ixgbe_sfp_type_da_act_lmt_core1 = 8,
2702 ixgbe_sfp_type_1g_cu_core0 = 9,
2703 ixgbe_sfp_type_1g_cu_core1 = 10,
2704 ixgbe_sfp_type_not_present = 0xFFFE,
2705 ixgbe_sfp_type_unknown = 0xFFFF
2708 enum ixgbe_media_type {
2709 ixgbe_media_type_unknown = 0,
2710 ixgbe_media_type_fiber,
2711 ixgbe_media_type_copper,
2712 ixgbe_media_type_backplane,
2713 ixgbe_media_type_cx4,
2714 ixgbe_media_type_virtual
2717 /* Flow Control Settings */
2718 enum ixgbe_fc_mode {
2726 /* Smart Speed Settings */
2727 #define IXGBE_SMARTSPEED_MAX_RETRIES 3
2728 enum ixgbe_smart_speed {
2729 ixgbe_smart_speed_auto = 0,
2730 ixgbe_smart_speed_on,
2731 ixgbe_smart_speed_off
2735 enum ixgbe_bus_type {
2736 ixgbe_bus_type_unknown = 0,
2738 ixgbe_bus_type_pcix,
2739 ixgbe_bus_type_pci_express,
2740 ixgbe_bus_type_reserved
2743 /* PCI bus speeds */
2744 enum ixgbe_bus_speed {
2745 ixgbe_bus_speed_unknown = 0,
2746 ixgbe_bus_speed_33 = 33,
2747 ixgbe_bus_speed_66 = 66,
2748 ixgbe_bus_speed_100 = 100,
2749 ixgbe_bus_speed_120 = 120,
2750 ixgbe_bus_speed_133 = 133,
2751 ixgbe_bus_speed_2500 = 2500,
2752 ixgbe_bus_speed_5000 = 5000,
2753 ixgbe_bus_speed_reserved
2756 /* PCI bus widths */
2757 enum ixgbe_bus_width {
2758 ixgbe_bus_width_unknown = 0,
2759 ixgbe_bus_width_pcie_x1 = 1,
2760 ixgbe_bus_width_pcie_x2 = 2,
2761 ixgbe_bus_width_pcie_x4 = 4,
2762 ixgbe_bus_width_pcie_x8 = 8,
2763 ixgbe_bus_width_32 = 32,
2764 ixgbe_bus_width_64 = 64,
2765 ixgbe_bus_width_reserved
2768 struct ixgbe_addr_filter_info {
2772 u32 overflow_promisc;
2773 bool user_set_promisc;
2776 /* Bus parameters */
2777 struct ixgbe_bus_info {
2778 enum ixgbe_bus_speed speed;
2779 enum ixgbe_bus_width width;
2780 enum ixgbe_bus_type type;
2786 /* Flow control parameters */
2787 struct ixgbe_fc_info {
2788 u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */
2789 u32 low_water; /* Flow Control Low-water */
2790 u16 pause_time; /* Flow Control Pause timer */
2791 bool send_xon; /* Flow control send XON */
2792 bool strict_ieee; /* Strict IEEE mode */
2793 bool disable_fc_autoneg; /* Do not autonegotiate FC */
2794 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
2795 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2796 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
2799 /* Statistics counters collected by the MAC */
2800 struct ixgbe_hw_stats {
2857 u64 fdirustat_remove;
2859 u64 fdirfstat_fremove;
2870 u64 fcoe_noddp_ext_buff;
2879 /* forward declaration */
2882 /* iterator type for walking multicast address lists */
2883 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2886 /* Function pointer table */
2887 struct ixgbe_eeprom_operations {
2888 s32 (*init_params)(struct ixgbe_hw *);
2889 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2890 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2891 s32 (*write)(struct ixgbe_hw *, u16, u16);
2892 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
2893 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2894 s32 (*update_checksum)(struct ixgbe_hw *);
2895 u16 (*calc_checksum)(struct ixgbe_hw *);
2898 struct ixgbe_mac_operations {
2899 s32 (*init_hw)(struct ixgbe_hw *);
2900 s32 (*reset_hw)(struct ixgbe_hw *);
2901 s32 (*start_hw)(struct ixgbe_hw *);
2902 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
2903 void (*enable_relaxed_ordering)(struct ixgbe_hw *);
2904 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2905 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2906 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2907 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
2908 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
2909 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
2910 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
2911 s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
2912 s32 (*stop_adapter)(struct ixgbe_hw *);
2913 s32 (*get_bus_info)(struct ixgbe_hw *);
2914 void (*set_lan_id)(struct ixgbe_hw *);
2915 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2916 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2917 s32 (*setup_sfp)(struct ixgbe_hw *);
2918 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2919 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2920 void (*release_swfw_sync)(struct ixgbe_hw *, u16);
2923 void (*disable_tx_laser)(struct ixgbe_hw *);
2924 void (*enable_tx_laser)(struct ixgbe_hw *);
2925 void (*flap_tx_laser)(struct ixgbe_hw *);
2926 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
2927 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2928 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2931 /* Packet Buffer manipulation */
2932 void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);
2935 s32 (*led_on)(struct ixgbe_hw *, u32);
2936 s32 (*led_off)(struct ixgbe_hw *, u32);
2937 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2938 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2940 /* RAR, Multicast, VLAN */
2941 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2942 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
2943 s32 (*clear_rar)(struct ixgbe_hw *, u32);
2944 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
2945 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2946 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2947 s32 (*init_rx_addrs)(struct ixgbe_hw *);
2948 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2950 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2951 ixgbe_mc_addr_itr, bool clear);
2952 s32 (*enable_mc)(struct ixgbe_hw *);
2953 s32 (*disable_mc)(struct ixgbe_hw *);
2954 s32 (*clear_vfta)(struct ixgbe_hw *);
2955 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2956 s32 (*init_uta_tables)(struct ixgbe_hw *);
2957 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
2958 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
2961 s32 (*fc_enable)(struct ixgbe_hw *, s32);
2963 /* Manageability interface */
2964 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
2967 struct ixgbe_phy_operations {
2968 s32 (*identify)(struct ixgbe_hw *);
2969 s32 (*identify_sfp)(struct ixgbe_hw *);
2970 s32 (*init)(struct ixgbe_hw *);
2971 s32 (*reset)(struct ixgbe_hw *);
2972 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
2973 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
2974 s32 (*setup_link)(struct ixgbe_hw *);
2975 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
2977 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2978 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
2979 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2980 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2981 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2982 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
2983 void (*i2c_bus_clear)(struct ixgbe_hw *);
2984 s32 (*check_overtemp)(struct ixgbe_hw *);
2987 struct ixgbe_eeprom_info {
2988 struct ixgbe_eeprom_operations ops;
2989 enum ixgbe_eeprom_type type;
2990 u32 semaphore_delay;
2996 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
2997 struct ixgbe_mac_info {
2998 struct ixgbe_mac_operations ops;
2999 enum ixgbe_mac_type type;
3000 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3001 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3002 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
3003 /* prefix for World Wide Node Name (WWNN) */
3005 /* prefix for World Wide Port Name (WWPN) */
3007 #define IXGBE_MAX_MTA 128
3008 u32 mta_shadow[IXGBE_MAX_MTA];
3012 u32 num_rar_entries;
3017 u32 max_msix_vectors;
3018 bool msix_vectors_from_pcie;
3020 bool arc_subsystem_valid;
3022 bool orig_link_settings_stored;
3023 bool autotry_restart;
3027 struct ixgbe_phy_info {
3028 struct ixgbe_phy_operations ops;
3029 enum ixgbe_phy_type type;
3032 enum ixgbe_sfp_type sfp_type;
3033 bool sfp_setup_needed;
3035 enum ixgbe_media_type media_type;
3037 ixgbe_autoneg_advertised autoneg_advertised;
3038 enum ixgbe_smart_speed smart_speed;
3039 bool smart_speed_active;
3040 bool multispeed_fiber;
3041 bool reset_if_overtemp;
3044 #include "ixgbe_mbx.h"
3046 struct ixgbe_mbx_operations {
3047 void (*init_params)(struct ixgbe_hw *hw);
3048 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
3049 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
3050 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3051 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3052 s32 (*check_for_msg)(struct ixgbe_hw *, u16);
3053 s32 (*check_for_ack)(struct ixgbe_hw *, u16);
3054 s32 (*check_for_rst)(struct ixgbe_hw *, u16);
3057 struct ixgbe_mbx_stats {
3066 struct ixgbe_mbx_info {
3067 struct ixgbe_mbx_operations ops;
3068 struct ixgbe_mbx_stats stats;
3078 struct ixgbe_mac_info mac;
3079 struct ixgbe_addr_filter_info addr_ctrl;
3080 struct ixgbe_fc_info fc;
3081 struct ixgbe_phy_info phy;
3082 struct ixgbe_eeprom_info eeprom;
3083 struct ixgbe_bus_info bus;
3084 struct ixgbe_mbx_info mbx;
3087 u16 subsystem_device_id;
3088 u16 subsystem_vendor_id;
3090 bool adapter_stopped;
3091 bool force_full_reset;
3094 #define ixgbe_call_func(hw, func, params, error) \
3095 (func != NULL) ? func params : error
3099 #define IXGBE_SUCCESS 0
3100 #define IXGBE_ERR_EEPROM -1
3101 #define IXGBE_ERR_EEPROM_CHECKSUM -2
3102 #define IXGBE_ERR_PHY -3
3103 #define IXGBE_ERR_CONFIG -4
3104 #define IXGBE_ERR_PARAM -5
3105 #define IXGBE_ERR_MAC_TYPE -6
3106 #define IXGBE_ERR_UNKNOWN_PHY -7
3107 #define IXGBE_ERR_LINK_SETUP -8
3108 #define IXGBE_ERR_ADAPTER_STOPPED -9
3109 #define IXGBE_ERR_INVALID_MAC_ADDR -10
3110 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
3111 #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
3112 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13
3113 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
3114 #define IXGBE_ERR_RESET_FAILED -15
3115 #define IXGBE_ERR_SWFW_SYNC -16
3116 #define IXGBE_ERR_PHY_ADDR_INVALID -17
3117 #define IXGBE_ERR_I2C -18
3118 #define IXGBE_ERR_SFP_NOT_SUPPORTED -19
3119 #define IXGBE_ERR_SFP_NOT_PRESENT -20
3120 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
3121 #define IXGBE_ERR_NO_SAN_ADDR_PTR -22
3122 #define IXGBE_ERR_FDIR_REINIT_FAILED -23
3123 #define IXGBE_ERR_EEPROM_VERSION -24
3124 #define IXGBE_ERR_NO_SPACE -25
3125 #define IXGBE_ERR_OVERTEMP -26
3126 #define IXGBE_ERR_FC_NOT_NEGOTIATED -27
3127 #define IXGBE_ERR_FC_NOT_SUPPORTED -28
3128 #define IXGBE_ERR_FLOW_CONTROL -29
3129 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
3130 #define IXGBE_ERR_PBA_SECTION -31
3131 #define IXGBE_ERR_INVALID_ARGUMENT -32
3132 #define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
3133 #define IXGBE_ERR_OUT_OF_MEM -34
3135 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
3138 #endif /* _IXGBE_TYPE_H_ */