1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x540.h"
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_X540_MAX_TX_QUEUES 128
41 #define IXGBE_X540_MAX_RX_QUEUES 128
42 #define IXGBE_X540_RAR_ENTRIES 128
43 #define IXGBE_X540_MC_TBL_SIZE 128
44 #define IXGBE_X540_VFT_TBL_SIZE 128
45 #define IXGBE_X540_RX_PB_SIZE 384
47 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
48 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
49 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
50 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
54 * @hw: pointer to hardware structure
56 * Initialize the function pointers and assign the MAC type for X540.
57 * Does not touch the hardware.
59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
61 struct ixgbe_mac_info *mac = &hw->mac;
62 struct ixgbe_phy_info *phy = &hw->phy;
63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
66 DEBUGFUNC("ixgbe_init_ops_X540");
68 ret_val = ixgbe_init_phy_ops_generic(hw);
69 ret_val = ixgbe_init_ops_generic(hw);
73 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
74 eeprom->ops.read = &ixgbe_read_eerd_X540;
75 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
76 eeprom->ops.write = &ixgbe_write_eewr_X540;
77 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
78 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
79 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
80 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
83 phy->ops.init = &ixgbe_init_phy_ops_generic;
84 phy->ops.reset = NULL;
87 mac->ops.reset_hw = &ixgbe_reset_hw_X540;
88 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
89 mac->ops.get_media_type = &ixgbe_get_media_type_X540;
90 mac->ops.get_supported_physical_layer =
91 &ixgbe_get_supported_physical_layer_X540;
92 mac->ops.read_analog_reg8 = NULL;
93 mac->ops.write_analog_reg8 = NULL;
94 mac->ops.start_hw = &ixgbe_start_hw_X540;
95 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
96 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
97 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
98 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
99 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
100 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
101 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
102 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
103 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
105 /* RAR, Multicast, VLAN */
106 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
107 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
108 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
109 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
110 mac->rar_highwater = 1;
111 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
112 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
113 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
114 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
115 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
116 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
119 mac->ops.get_link_capabilities =
120 &ixgbe_get_copper_link_capabilities_generic;
121 mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
122 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
123 mac->ops.check_link = &ixgbe_check_mac_link_generic;
126 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
127 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
128 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
129 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
130 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
131 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
132 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
136 * ARC supported; valid only if manageability features are
139 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
140 IXGBE_FWSM_MODE_MASK) ? true : false;
142 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
145 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
146 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
148 /* Manageability interface */
149 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
151 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
157 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
158 * @hw: pointer to hardware structure
159 * @speed: pointer to link speed
160 * @autoneg: true when autoneg or autotry is enabled
162 * Determines the link capabilities by reading the AUTOC register.
164 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
165 ixgbe_link_speed *speed,
168 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
170 return IXGBE_SUCCESS;
174 * ixgbe_get_media_type_X540 - Get media type
175 * @hw: pointer to hardware structure
177 * Returns the media type (fiber, copper, backplane)
179 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
181 UNREFERENCED_1PARAMETER(hw);
182 return ixgbe_media_type_copper;
186 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
187 * @hw: pointer to hardware structure
188 * @speed: new link speed
189 * @autoneg_wait_to_complete: true when waiting for completion is needed
191 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
192 ixgbe_link_speed speed,
193 bool autoneg_wait_to_complete)
195 DEBUGFUNC("ixgbe_setup_mac_link_X540");
196 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
200 * ixgbe_reset_hw_X540 - Perform hardware reset
201 * @hw: pointer to hardware structure
203 * Resets the hardware by resetting the transmit and receive units, masks
204 * and clears all interrupts, and perform a reset.
206 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
211 DEBUGFUNC("ixgbe_reset_hw_X540");
213 /* Call adapter stop to disable tx/rx and clear interrupts */
214 status = hw->mac.ops.stop_adapter(hw);
215 if (status != IXGBE_SUCCESS)
218 /* flush pending Tx transactions */
219 ixgbe_clear_tx_pending(hw);
222 ctrl = IXGBE_CTRL_RST;
223 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
224 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
225 IXGBE_WRITE_FLUSH(hw);
227 /* Poll for reset bit to self-clear indicating reset is complete */
228 for (i = 0; i < 10; i++) {
230 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
231 if (!(ctrl & IXGBE_CTRL_RST_MASK))
235 if (ctrl & IXGBE_CTRL_RST_MASK) {
236 status = IXGBE_ERR_RESET_FAILED;
237 ERROR_REPORT1(IXGBE_ERROR_POLLING,
238 "Reset polling failed to complete.\n");
243 * Double resets are required for recovery from certain error
244 * conditions. Between resets, it is necessary to stall to allow time
245 * for any pending HW events to complete.
247 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
248 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
252 /* Set the Rx packet buffer size. */
253 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
255 /* Store the permanent mac address */
256 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
259 * Store MAC address from RAR0, clear receive address registers, and
260 * clear the multicast table. Also reset num_rar_entries to 128,
261 * since we modify this value when programming the SAN MAC address.
263 hw->mac.num_rar_entries = 128;
264 hw->mac.ops.init_rx_addrs(hw);
266 /* Store the permanent SAN mac address */
267 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
269 /* Add the SAN MAC address to the RAR only if it's a valid address */
270 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
271 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
272 hw->mac.san_addr, 0, IXGBE_RAH_AV);
274 /* Save the SAN MAC RAR index */
275 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
277 /* Reserve the last RAR for the SAN MAC address */
278 hw->mac.num_rar_entries--;
281 /* Store the alternative WWNN/WWPN prefix */
282 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
283 &hw->mac.wwpn_prefix);
290 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
291 * @hw: pointer to hardware structure
293 * Starts the hardware using the generic start_hw function
294 * and the generation start_hw function.
295 * Then performs revision-specific operations, if any.
297 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
299 s32 ret_val = IXGBE_SUCCESS;
301 DEBUGFUNC("ixgbe_start_hw_X540");
303 ret_val = ixgbe_start_hw_generic(hw);
304 if (ret_val != IXGBE_SUCCESS)
307 ret_val = ixgbe_start_hw_gen2(hw);
314 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
315 * @hw: pointer to hardware structure
317 * Determines physical layer capabilities of the current configuration.
319 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
321 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
324 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
326 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
327 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
328 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
329 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
330 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
331 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
332 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
333 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
335 return physical_layer;
339 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
340 * @hw: pointer to hardware structure
342 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
343 * ixgbe_hw struct in order to set up EEPROM access.
345 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
347 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
351 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
353 if (eeprom->type == ixgbe_eeprom_uninitialized) {
354 eeprom->semaphore_delay = 10;
355 eeprom->type = ixgbe_flash;
357 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
358 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
359 IXGBE_EEC_SIZE_SHIFT);
360 eeprom->word_size = 1 << (eeprom_size +
361 IXGBE_EEPROM_WORD_SIZE_SHIFT);
363 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
364 eeprom->type, eeprom->word_size);
367 return IXGBE_SUCCESS;
371 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
372 * @hw: pointer to hardware structure
373 * @offset: offset of word in the EEPROM to read
374 * @data: word read from the EEPROM
376 * Reads a 16 bit word from the EEPROM using the EERD register.
378 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
380 s32 status = IXGBE_SUCCESS;
382 DEBUGFUNC("ixgbe_read_eerd_X540");
383 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
385 status = ixgbe_read_eerd_generic(hw, offset, data);
386 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
388 status = IXGBE_ERR_SWFW_SYNC;
395 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
396 * @hw: pointer to hardware structure
397 * @offset: offset of word in the EEPROM to read
398 * @words: number of words
399 * @data: word(s) read from the EEPROM
401 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
403 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
404 u16 offset, u16 words, u16 *data)
406 s32 status = IXGBE_SUCCESS;
408 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
409 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
411 status = ixgbe_read_eerd_buffer_generic(hw, offset,
413 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
415 status = IXGBE_ERR_SWFW_SYNC;
422 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
423 * @hw: pointer to hardware structure
424 * @offset: offset of word in the EEPROM to write
425 * @data: word write to the EEPROM
427 * Write a 16 bit word to the EEPROM using the EEWR register.
429 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
431 s32 status = IXGBE_SUCCESS;
433 DEBUGFUNC("ixgbe_write_eewr_X540");
434 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
436 status = ixgbe_write_eewr_generic(hw, offset, data);
437 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
439 status = IXGBE_ERR_SWFW_SYNC;
446 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
447 * @hw: pointer to hardware structure
448 * @offset: offset of word in the EEPROM to write
449 * @words: number of words
450 * @data: word(s) write to the EEPROM
452 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
454 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
455 u16 offset, u16 words, u16 *data)
457 s32 status = IXGBE_SUCCESS;
459 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
460 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
462 status = ixgbe_write_eewr_buffer_generic(hw, offset,
464 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
466 status = IXGBE_ERR_SWFW_SYNC;
473 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
475 * This function does not use synchronization for EERD and EEWR. It can
476 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
478 * @hw: pointer to hardware structure
480 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
490 * Do not use hw->eeprom.ops.read because we do not want to take
491 * the synchronization semaphores here. Instead use
492 * ixgbe_read_eerd_generic
495 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
497 /* Include 0x0-0x3F in the checksum */
498 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
499 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
500 DEBUGOUT("EEPROM read failed\n");
507 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
508 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
510 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
511 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
514 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
515 DEBUGOUT("EEPROM read failed\n");
519 /* Skip pointer section if the pointer is invalid. */
520 if (pointer == 0xFFFF || pointer == 0 ||
521 pointer >= hw->eeprom.word_size)
524 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
526 DEBUGOUT("EEPROM read failed\n");
530 /* Skip pointer section if length is invalid. */
531 if (length == 0xFFFF || length == 0 ||
532 (pointer + length) >= hw->eeprom.word_size)
535 for (j = pointer+1; j <= pointer+length; j++) {
536 if (ixgbe_read_eerd_generic(hw, j, &word) !=
538 DEBUGOUT("EEPROM read failed\n");
545 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
551 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
552 * @hw: pointer to hardware structure
553 * @checksum_val: calculated checksum
555 * Performs checksum calculation and validates the EEPROM checksum. If the
556 * caller does not need checksum_val, the value can be NULL.
558 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
563 u16 read_checksum = 0;
565 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
568 * Read the first word from the EEPROM. If this times out or fails, do
569 * not continue or we could be in for a very long wait while every
572 status = hw->eeprom.ops.read(hw, 0, &checksum);
574 if (status != IXGBE_SUCCESS) {
575 DEBUGOUT("EEPROM read failed\n");
579 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
581 checksum = hw->eeprom.ops.calc_checksum(hw);
584 * Do not use hw->eeprom.ops.read because we do not want to take
585 * the synchronization semaphores twice here.
587 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
591 * Verify read checksum from EEPROM is the same as
592 * calculated checksum
594 if (read_checksum != checksum) {
595 status = IXGBE_ERR_EEPROM_CHECKSUM;
596 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
597 "Invalid EEPROM checksum");
600 /* If the user cares, return the calculated checksum */
602 *checksum_val = checksum;
603 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
605 status = IXGBE_ERR_SWFW_SYNC;
613 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
614 * @hw: pointer to hardware structure
616 * After writing EEPROM to shadow RAM using EEWR register, software calculates
617 * checksum and updates the EEPROM and instructs the hardware to update
620 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
625 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
628 * Read the first word from the EEPROM. If this times out or fails, do
629 * not continue or we could be in for a very long wait while every
632 status = hw->eeprom.ops.read(hw, 0, &checksum);
634 if (status != IXGBE_SUCCESS)
635 DEBUGOUT("EEPROM read failed\n");
637 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
639 checksum = hw->eeprom.ops.calc_checksum(hw);
642 * Do not use hw->eeprom.ops.write because we do not want to
643 * take the synchronization semaphores twice here.
645 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
648 if (status == IXGBE_SUCCESS)
649 status = ixgbe_update_flash_X540(hw);
650 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
652 status = IXGBE_ERR_SWFW_SYNC;
659 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
660 * @hw: pointer to hardware structure
662 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
663 * EEPROM from shadow RAM to the flash device.
665 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
670 DEBUGFUNC("ixgbe_update_flash_X540");
672 status = ixgbe_poll_flash_update_done_X540(hw);
673 if (status == IXGBE_ERR_EEPROM) {
674 DEBUGOUT("Flash update time out\n");
678 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
679 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
681 status = ixgbe_poll_flash_update_done_X540(hw);
682 if (status == IXGBE_SUCCESS)
683 DEBUGOUT("Flash update complete\n");
685 DEBUGOUT("Flash update time out\n");
687 if (hw->revision_id == 0) {
688 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
690 if (flup & IXGBE_EEC_SEC1VAL) {
691 flup |= IXGBE_EEC_FLUP;
692 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
695 status = ixgbe_poll_flash_update_done_X540(hw);
696 if (status == IXGBE_SUCCESS)
697 DEBUGOUT("Flash update complete\n");
699 DEBUGOUT("Flash update time out\n");
706 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
707 * @hw: pointer to hardware structure
709 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
710 * flash update is done.
712 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
716 s32 status = IXGBE_ERR_EEPROM;
718 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
720 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
721 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
722 if (reg & IXGBE_EEC_FLUDONE) {
723 status = IXGBE_SUCCESS;
729 if (i == IXGBE_FLUDONE_ATTEMPTS)
730 ERROR_REPORT1(IXGBE_ERROR_POLLING,
731 "Flash update status polling timed out");
737 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
738 * @hw: pointer to hardware structure
739 * @mask: Mask to specify which semaphore to acquire
741 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
742 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
744 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
748 u32 fwmask = mask << 5;
752 s32 ret_val = IXGBE_SUCCESS;
754 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
756 if (swmask == IXGBE_GSSR_EEP_SM)
757 hwmask = IXGBE_GSSR_FLASH_SM;
759 /* SW only mask doesn't have FW bit pair */
760 if (swmask == IXGBE_GSSR_SW_MNG_SM)
763 for (i = 0; i < timeout; i++) {
765 * SW NVM semaphore bit is used for access to all
766 * SW_FW_SYNC bits (not just NVM)
768 if (ixgbe_get_swfw_sync_semaphore(hw)) {
769 ret_val = IXGBE_ERR_SWFW_SYNC;
773 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
774 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
776 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
777 ixgbe_release_swfw_sync_semaphore(hw);
782 * Firmware currently using resource (fwmask), hardware
783 * currently using resource (hwmask), or other software
784 * thread currently using resource (swmask)
786 ixgbe_release_swfw_sync_semaphore(hw);
791 /* Failed to get SW only semaphore */
792 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
793 ret_val = IXGBE_ERR_SWFW_SYNC;
794 ERROR_REPORT1(IXGBE_ERROR_POLLING,
795 "Failed to get SW only semaphore");
799 /* If the resource is not released by the FW/HW the SW can assume that
800 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
801 * of the requested resource(s) while ignoring the corresponding FW/HW
802 * bits in the SW_FW_SYNC register.
804 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
805 if (swfw_sync & (fwmask | hwmask)) {
806 if (ixgbe_get_swfw_sync_semaphore(hw)) {
807 ret_val = IXGBE_ERR_SWFW_SYNC;
812 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
813 ixgbe_release_swfw_sync_semaphore(hw);
816 /* If the resource is not released by other SW the SW can assume that
817 * the other SW malfunctions. In that case the SW should clear all SW
818 * flags that it does not own and then repeat the whole process once
821 else if (swfw_sync & swmask) {
822 ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM |
823 IXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM |
824 IXGBE_GSSR_MAC_CSR_SM);
825 ret_val = IXGBE_ERR_SWFW_SYNC;
833 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
834 * @hw: pointer to hardware structure
835 * @mask: Mask to specify which semaphore to release
837 * Releases the SWFW semaphore through the SW_FW_SYNC register
838 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
840 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
845 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
847 ixgbe_get_swfw_sync_semaphore(hw);
849 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
850 swfw_sync &= ~swmask;
851 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
853 ixgbe_release_swfw_sync_semaphore(hw);
858 * ixgbe_get_nvm_semaphore - Get hardware semaphore
859 * @hw: pointer to hardware structure
861 * Sets the hardware semaphores so SW/FW can gain control of shared resources
863 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
865 s32 status = IXGBE_ERR_EEPROM;
870 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
872 /* Get SMBI software semaphore between device drivers first */
873 for (i = 0; i < timeout; i++) {
875 * If the SMBI bit is 0 when we read it, then the bit will be
876 * set and we have the semaphore
878 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
879 if (!(swsm & IXGBE_SWSM_SMBI)) {
880 status = IXGBE_SUCCESS;
886 /* Now get the semaphore between SW/FW through the REGSMP bit */
887 if (status == IXGBE_SUCCESS) {
888 for (i = 0; i < timeout; i++) {
889 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
890 if (!(swsm & IXGBE_SWFW_REGSMP))
897 * Release semaphores and return error if SW NVM semaphore
898 * was not granted because we don't have access to the EEPROM
901 ERROR_REPORT1(IXGBE_ERROR_POLLING,
902 "REGSMP Software NVM semaphore not granted.\n");
903 ixgbe_release_swfw_sync_semaphore(hw);
904 status = IXGBE_ERR_EEPROM;
907 ERROR_REPORT1(IXGBE_ERROR_POLLING,
908 "Software semaphore SMBI between device drivers "
916 * ixgbe_release_nvm_semaphore - Release hardware semaphore
917 * @hw: pointer to hardware structure
919 * This function clears hardware semaphore bits.
921 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
925 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
927 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
929 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
930 swsm &= ~IXGBE_SWSM_SMBI;
931 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
933 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
934 swsm &= ~IXGBE_SWFW_REGSMP;
935 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
937 IXGBE_WRITE_FLUSH(hw);
941 * ixgbe_blink_led_start_X540 - Blink LED based on index.
942 * @hw: pointer to hardware structure
943 * @index: led number to blink
945 * Devices that implement the version 2 interface:
948 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
952 ixgbe_link_speed speed;
955 DEBUGFUNC("ixgbe_blink_led_start_X540");
958 * Link should be up in order for the blink bit in the LED control
959 * register to work. Force link and speed in the MAC if link is down.
960 * This will be reversed when we stop the blinking.
962 hw->mac.ops.check_link(hw, &speed, &link_up, false);
963 if (link_up == false) {
964 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
965 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
966 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
968 /* Set the LED to LINK_UP + BLINK. */
969 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
970 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
971 ledctl_reg |= IXGBE_LED_BLINK(index);
972 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
973 IXGBE_WRITE_FLUSH(hw);
975 return IXGBE_SUCCESS;
979 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
980 * @hw: pointer to hardware structure
981 * @index: led number to stop blinking
983 * Devices that implement the version 2 interface:
986 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
991 DEBUGFUNC("ixgbe_blink_led_stop_X540");
993 /* Restore the LED to its default value. */
994 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
995 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
996 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
997 ledctl_reg &= ~IXGBE_LED_BLINK(index);
998 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1000 /* Unforce link and speed in the MAC. */
1001 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1002 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1003 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1004 IXGBE_WRITE_FLUSH(hw);
1006 return IXGBE_SUCCESS;