lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x540.h"
  35 #include "ixgbe_type.h"
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 #define IXGBE_X540_MAX_TX_QUEUES        128
  41 #define IXGBE_X540_MAX_RX_QUEUES        128
  42 #define IXGBE_X540_RAR_ENTRIES          128
  43 #define IXGBE_X540_MC_TBL_SIZE          128
  44 #define IXGBE_X540_VFT_TBL_SIZE         128
  45 #define IXGBE_X540_RX_PB_SIZE           384
  46
  47 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  48 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  49 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  50 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  51
  52 /**
  53  *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Initialize the function pointers and assign the MAC type for X540.
  57  *  Does not touch the hardware.
  58  **/
  59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_mac_info *mac = &hw->mac;
  62         struct ixgbe_phy_info *phy = &hw->phy;
  63         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  64         s32 ret_val;
  65
  66         DEBUGFUNC("ixgbe_init_ops_X540");
  67
  68         ret_val = ixgbe_init_phy_ops_generic(hw);
  69         ret_val = ixgbe_init_ops_generic(hw);
  70
  71
  72         /* EEPROM */
  73         eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
  74         eeprom->ops.read = &ixgbe_read_eerd_X540;
  75         eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
  76         eeprom->ops.write = &ixgbe_write_eewr_X540;
  77         eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
  78         eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
  79         eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
  80         eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
  81
  82         /* PHY */
  83         phy->ops.init = &ixgbe_init_phy_ops_generic;
  84         phy->ops.reset = NULL;
  85
  86         /* MAC */
  87         mac->ops.reset_hw = &ixgbe_reset_hw_X540;
  88         mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
  89         mac->ops.get_media_type = &ixgbe_get_media_type_X540;
  90         mac->ops.get_supported_physical_layer =
  91                                     &ixgbe_get_supported_physical_layer_X540;
  92         mac->ops.read_analog_reg8 = NULL;
  93         mac->ops.write_analog_reg8 = NULL;
  94         mac->ops.start_hw = &ixgbe_start_hw_X540;
  95         mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
  96         mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
  97         mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
  98         mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
  99         mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
 100         mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
 101         mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
 102         mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
 103         mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
 104
 105         /* RAR, Multicast, VLAN */
 106         mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
 107         mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
 108         mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
 109         mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
 110         mac->rar_highwater = 1;
 111         mac->ops.set_vfta = &ixgbe_set_vfta_generic;
 112         mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
 113         mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
 114         mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
 115         mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
 116         mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
 117
 118         /* Link */
 119         mac->ops.get_link_capabilities =
 120                                 &ixgbe_get_copper_link_capabilities_generic;
 121         mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
 122         mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
 123         mac->ops.check_link = &ixgbe_check_mac_link_generic;
 124
 125
 126         mac->mcft_size          = IXGBE_X540_MC_TBL_SIZE;
 127         mac->vft_size           = IXGBE_X540_VFT_TBL_SIZE;
 128         mac->num_rar_entries    = IXGBE_X540_RAR_ENTRIES;
 129         mac->rx_pb_size         = IXGBE_X540_RX_PB_SIZE;
 130         mac->max_rx_queues      = IXGBE_X540_MAX_RX_QUEUES;
 131         mac->max_tx_queues      = IXGBE_X540_MAX_TX_QUEUES;
 132         mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_generic(hw);
 133
 134         /*
 135          * FWSM register
 136          * ARC supported; valid only if manageability features are
 137          * enabled.
 138          */
 139         mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
 140                                    IXGBE_FWSM_MODE_MASK) ? true : false;
 141
 142         hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 143
 144         /* LEDs */
 145         mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
 146         mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
 147
 148         /* Manageability interface */
 149         mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
 150
 151         mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
 152
 153         return ret_val;
 154 }
 155
 156 /**
 157  *  ixgbe_get_link_capabilities_X540 - Determines link capabilities
 158  *  @hw: pointer to hardware structure
 159  *  @speed: pointer to link speed
 160  *  @autoneg: true when autoneg or autotry is enabled
 161  *
 162  *  Determines the link capabilities by reading the AUTOC register.
 163  **/
 164 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
 165                                      ixgbe_link_speed *speed,
 166                                      bool *autoneg)
 167 {
 168         ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
 169
 170         return IXGBE_SUCCESS;
 171 }
 172
 173 /**
 174  *  ixgbe_get_media_type_X540 - Get media type
 175  *  @hw: pointer to hardware structure
 176  *
 177  *  Returns the media type (fiber, copper, backplane)
 178  **/
 179 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
 180 {
 181         UNREFERENCED_1PARAMETER(hw);
 182         return ixgbe_media_type_copper;
 183 }
 184
 185 /**
 186  *  ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
 187  *  @hw: pointer to hardware structure
 188  *  @speed: new link speed
 189  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 190  **/
 191 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
 192                               ixgbe_link_speed speed,
 193                               bool autoneg_wait_to_complete)
 194 {
 195         DEBUGFUNC("ixgbe_setup_mac_link_X540");
 196         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
 197 }
 198
 199 /**
 200  *  ixgbe_reset_hw_X540 - Perform hardware reset
 201  *  @hw: pointer to hardware structure
 202  *
 203  *  Resets the hardware by resetting the transmit and receive units, masks
 204  *  and clears all interrupts, and perform a reset.
 205  **/
 206 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
 207 {
 208         s32 status;
 209         u32 ctrl, i;
 210
 211         DEBUGFUNC("ixgbe_reset_hw_X540");
 212
 213         /* Call adapter stop to disable tx/rx and clear interrupts */
 214         status = hw->mac.ops.stop_adapter(hw);
 215         if (status != IXGBE_SUCCESS)
 216                 goto reset_hw_out;
 217
 218         /* flush pending Tx transactions */
 219         ixgbe_clear_tx_pending(hw);
 220
 221 mac_reset_top:
 222         ctrl = IXGBE_CTRL_RST;
 223         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 224         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 225         IXGBE_WRITE_FLUSH(hw);
 226
 227         /* Poll for reset bit to self-clear indicating reset is complete */
 228         for (i = 0; i < 10; i++) {
 229                 usec_delay(1);
 230                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 231                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 232                         break;
 233         }
 234
 235         if (ctrl & IXGBE_CTRL_RST_MASK) {
 236                 status = IXGBE_ERR_RESET_FAILED;
 237                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 238                              "Reset polling failed to complete.\n");
 239         }
 240         msec_delay(100);
 241
 242         /*
 243          * Double resets are required for recovery from certain error
 244          * conditions.  Between resets, it is necessary to stall to allow time
 245          * for any pending HW events to complete.
 246          */
 247         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 248                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 249                 goto mac_reset_top;
 250         }
 251
 252         /* Set the Rx packet buffer size. */
 253         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 254
 255         /* Store the permanent mac address */
 256         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 257
 258         /*
 259          * Store MAC address from RAR0, clear receive address registers, and
 260          * clear the multicast table.  Also reset num_rar_entries to 128,
 261          * since we modify this value when programming the SAN MAC address.
 262          */
 263         hw->mac.num_rar_entries = 128;
 264         hw->mac.ops.init_rx_addrs(hw);
 265
 266         /* Store the permanent SAN mac address */
 267         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 268
 269         /* Add the SAN MAC address to the RAR only if it's a valid address */
 270         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 271                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 272                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 273
 274                 /* Save the SAN MAC RAR index */
 275                 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 276
 277                 /* Reserve the last RAR for the SAN MAC address */
 278                 hw->mac.num_rar_entries--;
 279         }
 280
 281         /* Store the alternative WWNN/WWPN prefix */
 282         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 283                                    &hw->mac.wwpn_prefix);
 284
 285 reset_hw_out:
 286         return status;
 287 }
 288
 289 /**
 290  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 291  *  @hw: pointer to hardware structure
 292  *
 293  *  Starts the hardware using the generic start_hw function
 294  *  and the generation start_hw function.
 295  *  Then performs revision-specific operations, if any.
 296  **/
 297 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 298 {
 299         s32 ret_val = IXGBE_SUCCESS;
 300
 301         DEBUGFUNC("ixgbe_start_hw_X540");
 302
 303         ret_val = ixgbe_start_hw_generic(hw);
 304         if (ret_val != IXGBE_SUCCESS)
 305                 goto out;
 306
 307         ret_val = ixgbe_start_hw_gen2(hw);
 308
 309 out:
 310         return ret_val;
 311 }
 312
 313 /**
 314  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 315  *  @hw: pointer to hardware structure
 316  *
 317  *  Determines physical layer capabilities of the current configuration.
 318  **/
 319 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 320 {
 321         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 322         u16 ext_ability = 0;
 323
 324         DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
 325
 326         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 327         IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 328         if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 329                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 330         if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
 331                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 332         if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 333                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 334
 335         return physical_layer;
 336 }
 337
 338 /**
 339  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 340  *  @hw: pointer to hardware structure
 341  *
 342  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 343  *  ixgbe_hw struct in order to set up EEPROM access.
 344  **/
 345 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 346 {
 347         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 348         u32 eec;
 349         u16 eeprom_size;
 350
 351         DEBUGFUNC("ixgbe_init_eeprom_params_X540");
 352
 353         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 354                 eeprom->semaphore_delay = 10;
 355                 eeprom->type = ixgbe_flash;
 356
 357                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 358                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 359                                     IXGBE_EEC_SIZE_SHIFT);
 360                 eeprom->word_size = 1 << (eeprom_size +
 361                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 362
 363                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 364                           eeprom->type, eeprom->word_size);
 365         }
 366
 367         return IXGBE_SUCCESS;
 368 }
 369
 370 /**
 371  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 372  *  @hw: pointer to hardware structure
 373  *  @offset: offset of  word in the EEPROM to read
 374  *  @data: word read from the EEPROM
 375  *
 376  *  Reads a 16 bit word from the EEPROM using the EERD register.
 377  **/
 378 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 379 {
 380         s32 status = IXGBE_SUCCESS;
 381
 382         DEBUGFUNC("ixgbe_read_eerd_X540");
 383         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 384             IXGBE_SUCCESS) {
 385                 status = ixgbe_read_eerd_generic(hw, offset, data);
 386                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 387         } else {
 388                 status = IXGBE_ERR_SWFW_SYNC;
 389         }
 390
 391         return status;
 392 }
 393
 394 /**
 395  *  ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
 396  *  @hw: pointer to hardware structure
 397  *  @offset: offset of  word in the EEPROM to read
 398  *  @words: number of words
 399  *  @data: word(s) read from the EEPROM
 400  *
 401  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 402  **/
 403 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 404                                 u16 offset, u16 words, u16 *data)
 405 {
 406         s32 status = IXGBE_SUCCESS;
 407
 408         DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
 409         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 410             IXGBE_SUCCESS) {
 411                 status = ixgbe_read_eerd_buffer_generic(hw, offset,
 412                                                         words, data);
 413                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 414         } else {
 415                 status = IXGBE_ERR_SWFW_SYNC;
 416         }
 417
 418         return status;
 419 }
 420
 421 /**
 422  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 423  *  @hw: pointer to hardware structure
 424  *  @offset: offset of  word in the EEPROM to write
 425  *  @data: word write to the EEPROM
 426  *
 427  *  Write a 16 bit word to the EEPROM using the EEWR register.
 428  **/
 429 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 430 {
 431         s32 status = IXGBE_SUCCESS;
 432
 433         DEBUGFUNC("ixgbe_write_eewr_X540");
 434         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 435             IXGBE_SUCCESS) {
 436                 status = ixgbe_write_eewr_generic(hw, offset, data);
 437                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 438         } else {
 439                 status = IXGBE_ERR_SWFW_SYNC;
 440         }
 441
 442         return status;
 443 }
 444
 445 /**
 446  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 447  *  @hw: pointer to hardware structure
 448  *  @offset: offset of  word in the EEPROM to write
 449  *  @words: number of words
 450  *  @data: word(s) write to the EEPROM
 451  *
 452  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 453  **/
 454 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 455                                  u16 offset, u16 words, u16 *data)
 456 {
 457         s32 status = IXGBE_SUCCESS;
 458
 459         DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
 460         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 461             IXGBE_SUCCESS) {
 462                 status = ixgbe_write_eewr_buffer_generic(hw, offset,
 463                                                          words, data);
 464                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 465         } else {
 466                 status = IXGBE_ERR_SWFW_SYNC;
 467         }
 468
 469         return status;
 470 }
 471
 472 /**
 473  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 474  *
 475  *  This function does not use synchronization for EERD and EEWR. It can
 476  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 477  *
 478  *  @hw: pointer to hardware structure
 479  **/
 480 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 481 {
 482         u16 i;
 483         u16 j;
 484         u16 checksum = 0;
 485         u16 length = 0;
 486         u16 pointer = 0;
 487         u16 word = 0;
 488
 489         /*
 490          * Do not use hw->eeprom.ops.read because we do not want to take
 491          * the synchronization semaphores here. Instead use
 492          * ixgbe_read_eerd_generic
 493          */
 494
 495         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
 496
 497         /* Include 0x0-0x3F in the checksum */
 498         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 499                 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
 500                         DEBUGOUT("EEPROM read failed\n");
 501                         break;
 502                 }
 503                 checksum += word;
 504         }
 505
 506         /*
 507          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 508          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 509          */
 510         for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
 511                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 512                         continue;
 513
 514                 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
 515                         DEBUGOUT("EEPROM read failed\n");
 516                         break;
 517                 }
 518
 519                 /* Skip pointer section if the pointer is invalid. */
 520                 if (pointer == 0xFFFF || pointer == 0 ||
 521                     pointer >= hw->eeprom.word_size)
 522                         continue;
 523
 524                 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
 525                     IXGBE_SUCCESS) {
 526                         DEBUGOUT("EEPROM read failed\n");
 527                         break;
 528                 }
 529
 530                 /* Skip pointer section if length is invalid. */
 531                 if (length == 0xFFFF || length == 0 ||
 532                     (pointer + length) >= hw->eeprom.word_size)
 533                         continue;
 534
 535                 for (j = pointer+1; j <= pointer+length; j++) {
 536                         if (ixgbe_read_eerd_generic(hw, j, &word) !=
 537                             IXGBE_SUCCESS) {
 538                                 DEBUGOUT("EEPROM read failed\n");
 539                                 break;
 540                         }
 541                         checksum += word;
 542                 }
 543         }
 544
 545         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 546
 547         return checksum;
 548 }
 549
 550 /**
 551  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 552  *  @hw: pointer to hardware structure
 553  *  @checksum_val: calculated checksum
 554  *
 555  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 556  *  caller does not need checksum_val, the value can be NULL.
 557  **/
 558 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 559                                         u16 *checksum_val)
 560 {
 561         s32 status;
 562         u16 checksum;
 563         u16 read_checksum = 0;
 564
 565         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
 566
 567         /*
 568          * Read the first word from the EEPROM. If this times out or fails, do
 569          * not continue or we could be in for a very long wait while every
 570          * EEPROM read fails
 571          */
 572         status = hw->eeprom.ops.read(hw, 0, &checksum);
 573
 574         if (status != IXGBE_SUCCESS) {
 575                 DEBUGOUT("EEPROM read failed\n");
 576                 goto out;
 577         }
 578
 579         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 580             IXGBE_SUCCESS) {
 581                 checksum = hw->eeprom.ops.calc_checksum(hw);
 582
 583                 /*
 584                  * Do not use hw->eeprom.ops.read because we do not want to take
 585                  * the synchronization semaphores twice here.
 586                 */
 587                 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 588                                         &read_checksum);
 589
 590                 /*
 591                  * Verify read checksum from EEPROM is the same as
 592                  * calculated checksum
 593                  */
 594                 if (read_checksum != checksum) {
 595                         status = IXGBE_ERR_EEPROM_CHECKSUM;
 596                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 597                                      "Invalid EEPROM checksum");
 598                 }
 599
 600                 /* If the user cares, return the calculated checksum */
 601                 if (checksum_val)
 602                         *checksum_val = checksum;
 603                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 604         } else {
 605                 status = IXGBE_ERR_SWFW_SYNC;
 606         }
 607
 608 out:
 609         return status;
 610 }
 611
 612 /**
 613  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 614  * @hw: pointer to hardware structure
 615  *
 616  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 617  * checksum and updates the EEPROM and instructs the hardware to update
 618  * the flash.
 619  **/
 620 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 621 {
 622         s32 status;
 623         u16 checksum;
 624
 625         DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
 626
 627         /*
 628          * Read the first word from the EEPROM. If this times out or fails, do
 629          * not continue or we could be in for a very long wait while every
 630          * EEPROM read fails
 631          */
 632         status = hw->eeprom.ops.read(hw, 0, &checksum);
 633
 634         if (status != IXGBE_SUCCESS)
 635                 DEBUGOUT("EEPROM read failed\n");
 636
 637         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 638             IXGBE_SUCCESS) {
 639                 checksum = hw->eeprom.ops.calc_checksum(hw);
 640
 641                 /*
 642                  * Do not use hw->eeprom.ops.write because we do not want to
 643                  * take the synchronization semaphores twice here.
 644                 */
 645                 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
 646                                                   checksum);
 647
 648                 if (status == IXGBE_SUCCESS)
 649                         status = ixgbe_update_flash_X540(hw);
 650                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 651         } else {
 652                 status = IXGBE_ERR_SWFW_SYNC;
 653         }
 654
 655         return status;
 656 }
 657
 658 /**
 659  *  ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 660  *  @hw: pointer to hardware structure
 661  *
 662  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 663  *  EEPROM from shadow RAM to the flash device.
 664  **/
 665 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 666 {
 667         u32 flup;
 668         s32 status;
 669
 670         DEBUGFUNC("ixgbe_update_flash_X540");
 671
 672         status = ixgbe_poll_flash_update_done_X540(hw);
 673         if (status == IXGBE_ERR_EEPROM) {
 674                 DEBUGOUT("Flash update time out\n");
 675                 goto out;
 676         }
 677
 678         flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
 679         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 680
 681         status = ixgbe_poll_flash_update_done_X540(hw);
 682         if (status == IXGBE_SUCCESS)
 683                 DEBUGOUT("Flash update complete\n");
 684         else
 685                 DEBUGOUT("Flash update time out\n");
 686
 687         if (hw->revision_id == 0) {
 688                 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 689
 690                 if (flup & IXGBE_EEC_SEC1VAL) {
 691                         flup |= IXGBE_EEC_FLUP;
 692                         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 693                 }
 694
 695                 status = ixgbe_poll_flash_update_done_X540(hw);
 696                 if (status == IXGBE_SUCCESS)
 697                         DEBUGOUT("Flash update complete\n");
 698                 else
 699                         DEBUGOUT("Flash update time out\n");
 700         }
 701 out:
 702         return status;
 703 }
 704
 705 /**
 706  *  ixgbe_poll_flash_update_done_X540 - Poll flash update status
 707  *  @hw: pointer to hardware structure
 708  *
 709  *  Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 710  *  flash update is done.
 711  **/
 712 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 713 {
 714         u32 i;
 715         u32 reg;
 716         s32 status = IXGBE_ERR_EEPROM;
 717
 718         DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
 719
 720         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 721                 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
 722                 if (reg & IXGBE_EEC_FLUDONE) {
 723                         status = IXGBE_SUCCESS;
 724                         break;
 725                 }
 726                 usec_delay(5);
 727         }
 728
 729         if (i == IXGBE_FLUDONE_ATTEMPTS)
 730                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 731                              "Flash update status polling timed out");
 732
 733         return status;
 734 }
 735
 736 /**
 737  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 738  *  @hw: pointer to hardware structure
 739  *  @mask: Mask to specify which semaphore to acquire
 740  *
 741  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 742  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
 743  **/
 744 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 745 {
 746         u32 swfw_sync;
 747         u32 swmask = mask;
 748         u32 fwmask = mask << 5;
 749         u32 hwmask = 0;
 750         u32 timeout = 200;
 751         u32 i;
 752         s32 ret_val = IXGBE_SUCCESS;
 753
 754         DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
 755
 756         if (swmask == IXGBE_GSSR_EEP_SM)
 757                 hwmask = IXGBE_GSSR_FLASH_SM;
 758
 759         /* SW only mask doesn't have FW bit pair */
 760         if (swmask == IXGBE_GSSR_SW_MNG_SM)
 761                 fwmask = 0;
 762
 763         for (i = 0; i < timeout; i++) {
 764                 /*
 765                  * SW NVM semaphore bit is used for access to all
 766                  * SW_FW_SYNC bits (not just NVM)
 767                  */
 768                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 769                         ret_val = IXGBE_ERR_SWFW_SYNC;
 770                         goto out;
 771                 }
 772
 773                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 774                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 775                         swfw_sync |= swmask;
 776                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 777                         ixgbe_release_swfw_sync_semaphore(hw);
 778                         msec_delay(5);
 779                         goto out;
 780                 } else {
 781                         /*
 782                          * Firmware currently using resource (fwmask), hardware
 783                          * currently using resource (hwmask), or other software
 784                          * thread currently using resource (swmask)
 785                          */
 786                         ixgbe_release_swfw_sync_semaphore(hw);
 787                         msec_delay(5);
 788                 }
 789         }
 790
 791         /* Failed to get SW only semaphore */
 792         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 793                 ret_val = IXGBE_ERR_SWFW_SYNC;
 794                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 795                              "Failed to get SW only semaphore");
 796                 goto out;
 797         }
 798
 799         /* If the resource is not released by the FW/HW the SW can assume that
 800          * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
 801          * of the requested resource(s) while ignoring the corresponding FW/HW
 802          * bits in the SW_FW_SYNC register.
 803          */
 804         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 805         if (swfw_sync & (fwmask | hwmask)) {
 806                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 807                         ret_val = IXGBE_ERR_SWFW_SYNC;
 808                         goto out;
 809                 }
 810
 811                 swfw_sync |= swmask;
 812                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 813                 ixgbe_release_swfw_sync_semaphore(hw);
 814                 msec_delay(5);
 815         }
 816         /* If the resource is not released by other SW the SW can assume that
 817          * the other SW malfunctions. In that case the SW should clear all SW
 818          * flags that it does not own and then repeat the whole process once
 819          * again.
 820          */
 821         else if (swfw_sync & swmask) {
 822                 ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM |
 823                         IXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM |
 824                         IXGBE_GSSR_MAC_CSR_SM);
 825                 ret_val = IXGBE_ERR_SWFW_SYNC;
 826         }
 827
 828 out:
 829         return ret_val;
 830 }
 831
 832 /**
 833  *  ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 834  *  @hw: pointer to hardware structure
 835  *  @mask: Mask to specify which semaphore to release
 836  *
 837  *  Releases the SWFW semaphore through the SW_FW_SYNC register
 838  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 839  **/
 840 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 841 {
 842         u32 swfw_sync;
 843         u32 swmask = mask;
 844
 845         DEBUGFUNC("ixgbe_release_swfw_sync_X540");
 846
 847         ixgbe_get_swfw_sync_semaphore(hw);
 848
 849         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 850         swfw_sync &= ~swmask;
 851         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 852
 853         ixgbe_release_swfw_sync_semaphore(hw);
 854         msec_delay(5);
 855 }
 856
 857 /**
 858  *  ixgbe_get_nvm_semaphore - Get hardware semaphore
 859  *  @hw: pointer to hardware structure
 860  *
 861  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
 862  **/
 863 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 864 {
 865         s32 status = IXGBE_ERR_EEPROM;
 866         u32 timeout = 2000;
 867         u32 i;
 868         u32 swsm;
 869
 870         DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
 871
 872         /* Get SMBI software semaphore between device drivers first */
 873         for (i = 0; i < timeout; i++) {
 874                 /*
 875                  * If the SMBI bit is 0 when we read it, then the bit will be
 876                  * set and we have the semaphore
 877                  */
 878                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 879                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 880                         status = IXGBE_SUCCESS;
 881                         break;
 882                 }
 883                 usec_delay(50);
 884         }
 885
 886         /* Now get the semaphore between SW/FW through the REGSMP bit */
 887         if (status == IXGBE_SUCCESS) {
 888                 for (i = 0; i < timeout; i++) {
 889                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 890                         if (!(swsm & IXGBE_SWFW_REGSMP))
 891                                 break;
 892
 893                         usec_delay(50);
 894                 }
 895
 896                 /*
 897                  * Release semaphores and return error if SW NVM semaphore
 898                  * was not granted because we don't have access to the EEPROM
 899                  */
 900                 if (i >= timeout) {
 901                         ERROR_REPORT1(IXGBE_ERROR_POLLING,
 902                                 "REGSMP Software NVM semaphore not granted.\n");
 903                         ixgbe_release_swfw_sync_semaphore(hw);
 904                         status = IXGBE_ERR_EEPROM;
 905                 }
 906         } else {
 907                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 908                              "Software semaphore SMBI between device drivers "
 909                              "not granted.\n");
 910         }
 911
 912         return status;
 913 }
 914
 915 /**
 916  *  ixgbe_release_nvm_semaphore - Release hardware semaphore
 917  *  @hw: pointer to hardware structure
 918  *
 919  *  This function clears hardware semaphore bits.
 920  **/
 921 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 922 {
 923         u32 swsm;
 924
 925         DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
 926
 927         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 928
 929         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 930         swsm &= ~IXGBE_SWSM_SMBI;
 931         IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 932
 933         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 934         swsm &= ~IXGBE_SWFW_REGSMP;
 935         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 936
 937         IXGBE_WRITE_FLUSH(hw);
 938 }
 939
 940 /**
 941  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 942  * @hw: pointer to hardware structure
 943  * @index: led number to blink
 944  *
 945  * Devices that implement the version 2 interface:
 946  *   X540
 947  **/
 948 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 949 {
 950         u32 macc_reg;
 951         u32 ledctl_reg;
 952         ixgbe_link_speed speed;
 953         bool link_up;
 954
 955         DEBUGFUNC("ixgbe_blink_led_start_X540");
 956
 957         /*
 958          * Link should be up in order for the blink bit in the LED control
 959          * register to work. Force link and speed in the MAC if link is down.
 960          * This will be reversed when we stop the blinking.
 961          */
 962         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 963         if (link_up == false) {
 964                 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 965                 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 966                 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 967         }
 968         /* Set the LED to LINK_UP + BLINK. */
 969         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 970         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 971         ledctl_reg |= IXGBE_LED_BLINK(index);
 972         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 973         IXGBE_WRITE_FLUSH(hw);
 974
 975         return IXGBE_SUCCESS;
 976 }
 977
 978 /**
 979  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 980  * @hw: pointer to hardware structure
 981  * @index: led number to stop blinking
 982  *
 983  * Devices that implement the version 2 interface:
 984  *   X540
 985  **/
 986 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 987 {
 988         u32 macc_reg;
 989         u32 ledctl_reg;
 990
 991         DEBUGFUNC("ixgbe_blink_led_stop_X540");
 992
 993         /* Restore the LED to its default value. */
 994         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 995         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 996         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 997         ledctl_reg &= ~IXGBE_LED_BLINK(index);
 998         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 999
1000         /* Unforce link and speed in the MAC. */
1001         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1002         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1003         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1004         IXGBE_WRITE_FLUSH(hw);
1005
1006         return IXGBE_SUCCESS;
1007 }
1008
1009