lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x540.h"
  35 #include "ixgbe_type.h"
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 #define IXGBE_X540_MAX_TX_QUEUES        128
  41 #define IXGBE_X540_MAX_RX_QUEUES        128
  42 #define IXGBE_X540_RAR_ENTRIES          128
  43 #define IXGBE_X540_MC_TBL_SIZE          128
  44 #define IXGBE_X540_VFT_TBL_SIZE         128
  45 #define IXGBE_X540_RX_PB_SIZE           384
  46
  47 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  48 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  49 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  50
  51 /**
  52  *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type
  53  *  @hw: pointer to hardware structure
  54  *
  55  *  Initialize the function pointers and assign the MAC type for X540.
  56  *  Does not touch the hardware.
  57  **/
  58 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
  59 {
  60         struct ixgbe_mac_info *mac = &hw->mac;
  61         struct ixgbe_phy_info *phy = &hw->phy;
  62         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  63         s32 ret_val;
  64
  65         DEBUGFUNC("ixgbe_init_ops_X540");
  66
  67         ret_val = ixgbe_init_phy_ops_generic(hw);
  68         ret_val = ixgbe_init_ops_generic(hw);
  69
  70
  71         /* EEPROM */
  72         eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
  73         eeprom->ops.read = &ixgbe_read_eerd_X540;
  74         eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
  75         eeprom->ops.write = &ixgbe_write_eewr_X540;
  76         eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
  77         eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
  78         eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
  79         eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
  80
  81         /* PHY */
  82         phy->ops.init = &ixgbe_init_phy_ops_generic;
  83         phy->ops.reset = NULL;
  84
  85         /* MAC */
  86         mac->ops.reset_hw = &ixgbe_reset_hw_X540;
  87         mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
  88         mac->ops.get_media_type = &ixgbe_get_media_type_X540;
  89         mac->ops.get_supported_physical_layer =
  90                                     &ixgbe_get_supported_physical_layer_X540;
  91         mac->ops.read_analog_reg8 = NULL;
  92         mac->ops.write_analog_reg8 = NULL;
  93         mac->ops.start_hw = &ixgbe_start_hw_X540;
  94         mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
  95         mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
  96         mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
  97         mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
  98         mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
  99         mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
 100         mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
 101         mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
 102         mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
 103
 104         /* RAR, Multicast, VLAN */
 105         mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
 106         mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
 107         mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
 108         mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
 109         mac->rar_highwater = 1;
 110         mac->ops.set_vfta = &ixgbe_set_vfta_generic;
 111         mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
 112         mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
 113         mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
 114         mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
 115         mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
 116
 117         /* Link */
 118         mac->ops.get_link_capabilities =
 119                                 &ixgbe_get_copper_link_capabilities_generic;
 120         mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
 121         mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
 122         mac->ops.check_link = &ixgbe_check_mac_link_generic;
 123
 124
 125         mac->mcft_size          = IXGBE_X540_MC_TBL_SIZE;
 126         mac->vft_size           = IXGBE_X540_VFT_TBL_SIZE;
 127         mac->num_rar_entries    = IXGBE_X540_RAR_ENTRIES;
 128         mac->rx_pb_size         = IXGBE_X540_RX_PB_SIZE;
 129         mac->max_rx_queues      = IXGBE_X540_MAX_RX_QUEUES;
 130         mac->max_tx_queues      = IXGBE_X540_MAX_TX_QUEUES;
 131         mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_generic(hw);
 132
 133         /*
 134          * FWSM register
 135          * ARC supported; valid only if manageability features are
 136          * enabled.
 137          */
 138         mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
 139                                    IXGBE_FWSM_MODE_MASK) ? true : false;
 140
 141         hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 142
 143         /* LEDs */
 144         mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
 145         mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
 146
 147         /* Manageability interface */
 148         mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
 149
 150         mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
 151
 152         return ret_val;
 153 }
 154
 155 /**
 156  *  ixgbe_get_link_capabilities_X540 - Determines link capabilities
 157  *  @hw: pointer to hardware structure
 158  *  @speed: pointer to link speed
 159  *  @autoneg: true when autoneg or autotry is enabled
 160  *
 161  *  Determines the link capabilities by reading the AUTOC register.
 162  **/
 163 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
 164                                      ixgbe_link_speed *speed,
 165                                      bool *autoneg)
 166 {
 167         ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
 168
 169         return IXGBE_SUCCESS;
 170 }
 171
 172 /**
 173  *  ixgbe_get_media_type_X540 - Get media type
 174  *  @hw: pointer to hardware structure
 175  *
 176  *  Returns the media type (fiber, copper, backplane)
 177  **/
 178 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
 179 {
 180         UNREFERENCED_1PARAMETER(hw);
 181         return ixgbe_media_type_copper;
 182 }
 183
 184 /**
 185  *  ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
 186  *  @hw: pointer to hardware structure
 187  *  @speed: new link speed
 188  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 189  **/
 190 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
 191                               ixgbe_link_speed speed,
 192                               bool autoneg_wait_to_complete)
 193 {
 194         DEBUGFUNC("ixgbe_setup_mac_link_X540");
 195         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
 196 }
 197
 198 /**
 199  *  ixgbe_reset_hw_X540 - Perform hardware reset
 200  *  @hw: pointer to hardware structure
 201  *
 202  *  Resets the hardware by resetting the transmit and receive units, masks
 203  *  and clears all interrupts, and perform a reset.
 204  **/
 205 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
 206 {
 207         s32 status;
 208         u32 ctrl, i;
 209
 210         DEBUGFUNC("ixgbe_reset_hw_X540");
 211
 212         /* Call adapter stop to disable tx/rx and clear interrupts */
 213         status = hw->mac.ops.stop_adapter(hw);
 214         if (status != IXGBE_SUCCESS)
 215                 goto reset_hw_out;
 216
 217         /* flush pending Tx transactions */
 218         ixgbe_clear_tx_pending(hw);
 219
 220 mac_reset_top:
 221         ctrl = IXGBE_CTRL_RST;
 222         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 223         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 224         IXGBE_WRITE_FLUSH(hw);
 225
 226         /* Poll for reset bit to self-clear indicating reset is complete */
 227         for (i = 0; i < 10; i++) {
 228                 usec_delay(1);
 229                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 230                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 231                         break;
 232         }
 233
 234         if (ctrl & IXGBE_CTRL_RST_MASK) {
 235                 status = IXGBE_ERR_RESET_FAILED;
 236                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 237                              "Reset polling failed to complete.\n");
 238         }
 239         msec_delay(100);
 240
 241         /*
 242          * Double resets are required for recovery from certain error
 243          * conditions.  Between resets, it is necessary to stall to allow time
 244          * for any pending HW events to complete.
 245          */
 246         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 247                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 248                 goto mac_reset_top;
 249         }
 250
 251         /* Set the Rx packet buffer size. */
 252         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 253
 254         /* Store the permanent mac address */
 255         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 256
 257         /*
 258          * Store MAC address from RAR0, clear receive address registers, and
 259          * clear the multicast table.  Also reset num_rar_entries to 128,
 260          * since we modify this value when programming the SAN MAC address.
 261          */
 262         hw->mac.num_rar_entries = 128;
 263         hw->mac.ops.init_rx_addrs(hw);
 264
 265         /* Store the permanent SAN mac address */
 266         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 267
 268         /* Add the SAN MAC address to the RAR only if it's a valid address */
 269         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 270                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 271                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 272
 273                 /* Save the SAN MAC RAR index */
 274                 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 275
 276                 /* Reserve the last RAR for the SAN MAC address */
 277                 hw->mac.num_rar_entries--;
 278         }
 279
 280         /* Store the alternative WWNN/WWPN prefix */
 281         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 282                                    &hw->mac.wwpn_prefix);
 283
 284 reset_hw_out:
 285         return status;
 286 }
 287
 288 /**
 289  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 290  *  @hw: pointer to hardware structure
 291  *
 292  *  Starts the hardware using the generic start_hw function
 293  *  and the generation start_hw function.
 294  *  Then performs revision-specific operations, if any.
 295  **/
 296 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 297 {
 298         s32 ret_val = IXGBE_SUCCESS;
 299
 300         DEBUGFUNC("ixgbe_start_hw_X540");
 301
 302         ret_val = ixgbe_start_hw_generic(hw);
 303         if (ret_val != IXGBE_SUCCESS)
 304                 goto out;
 305
 306         ret_val = ixgbe_start_hw_gen2(hw);
 307
 308 out:
 309         return ret_val;
 310 }
 311
 312 /**
 313  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 314  *  @hw: pointer to hardware structure
 315  *
 316  *  Determines physical layer capabilities of the current configuration.
 317  **/
 318 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 319 {
 320         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 321         u16 ext_ability = 0;
 322
 323         DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
 324
 325         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 326         IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 327         if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 328                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 329         if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
 330                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 331         if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 332                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 333
 334         return physical_layer;
 335 }
 336
 337 /**
 338  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 339  *  @hw: pointer to hardware structure
 340  *
 341  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 342  *  ixgbe_hw struct in order to set up EEPROM access.
 343  **/
 344 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 345 {
 346         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 347         u32 eec;
 348         u16 eeprom_size;
 349
 350         DEBUGFUNC("ixgbe_init_eeprom_params_X540");
 351
 352         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 353                 eeprom->semaphore_delay = 10;
 354                 eeprom->type = ixgbe_flash;
 355
 356                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 357                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 358                                     IXGBE_EEC_SIZE_SHIFT);
 359                 eeprom->word_size = 1 << (eeprom_size +
 360                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 361
 362                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 363                           eeprom->type, eeprom->word_size);
 364         }
 365
 366         return IXGBE_SUCCESS;
 367 }
 368
 369 /**
 370  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 371  *  @hw: pointer to hardware structure
 372  *  @offset: offset of  word in the EEPROM to read
 373  *  @data: word read from the EEPROM
 374  *
 375  *  Reads a 16 bit word from the EEPROM using the EERD register.
 376  **/
 377 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 378 {
 379         s32 status = IXGBE_SUCCESS;
 380
 381         DEBUGFUNC("ixgbe_read_eerd_X540");
 382         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 383             IXGBE_SUCCESS) {
 384                 status = ixgbe_read_eerd_generic(hw, offset, data);
 385                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 386         } else {
 387                 status = IXGBE_ERR_SWFW_SYNC;
 388         }
 389
 390         return status;
 391 }
 392
 393 /**
 394  *  ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
 395  *  @hw: pointer to hardware structure
 396  *  @offset: offset of  word in the EEPROM to read
 397  *  @words: number of words
 398  *  @data: word(s) read from the EEPROM
 399  *
 400  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 401  **/
 402 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 403                                 u16 offset, u16 words, u16 *data)
 404 {
 405         s32 status = IXGBE_SUCCESS;
 406
 407         DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
 408         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 409             IXGBE_SUCCESS) {
 410                 status = ixgbe_read_eerd_buffer_generic(hw, offset,
 411                                                         words, data);
 412                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 413         } else {
 414                 status = IXGBE_ERR_SWFW_SYNC;
 415         }
 416
 417         return status;
 418 }
 419
 420 /**
 421  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 422  *  @hw: pointer to hardware structure
 423  *  @offset: offset of  word in the EEPROM to write
 424  *  @data: word write to the EEPROM
 425  *
 426  *  Write a 16 bit word to the EEPROM using the EEWR register.
 427  **/
 428 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 429 {
 430         s32 status = IXGBE_SUCCESS;
 431
 432         DEBUGFUNC("ixgbe_write_eewr_X540");
 433         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 434             IXGBE_SUCCESS) {
 435                 status = ixgbe_write_eewr_generic(hw, offset, data);
 436                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 437         } else {
 438                 status = IXGBE_ERR_SWFW_SYNC;
 439         }
 440
 441         return status;
 442 }
 443
 444 /**
 445  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 446  *  @hw: pointer to hardware structure
 447  *  @offset: offset of  word in the EEPROM to write
 448  *  @words: number of words
 449  *  @data: word(s) write to the EEPROM
 450  *
 451  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 452  **/
 453 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 454                                  u16 offset, u16 words, u16 *data)
 455 {
 456         s32 status = IXGBE_SUCCESS;
 457
 458         DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
 459         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 460             IXGBE_SUCCESS) {
 461                 status = ixgbe_write_eewr_buffer_generic(hw, offset,
 462                                                          words, data);
 463                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 464         } else {
 465                 status = IXGBE_ERR_SWFW_SYNC;
 466         }
 467
 468         return status;
 469 }
 470
 471 /**
 472  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 473  *
 474  *  This function does not use synchronization for EERD and EEWR. It can
 475  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 476  *
 477  *  @hw: pointer to hardware structure
 478  **/
 479 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 480 {
 481         u16 i, j;
 482         u16 checksum = 0;
 483         u16 length = 0;
 484         u16 pointer = 0;
 485         u16 word = 0;
 486         u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
 487         u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
 488
 489         /*
 490          * Do not use hw->eeprom.ops.read because we do not want to take
 491          * the synchronization semaphores here. Instead use
 492          * ixgbe_read_eerd_generic
 493          */
 494
 495         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
 496
 497         /* Include 0x0-0x3F in the checksum */
 498         for (i = 0; i <= checksum_last_word; i++) {
 499                 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
 500                         DEBUGOUT("EEPROM read failed\n");
 501                         break;
 502                 }
 503                 if (i != IXGBE_EEPROM_CHECKSUM)
 504                         checksum += word;
 505         }
 506
 507         /*
 508          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 509          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 510          */
 511         for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
 512                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 513                         continue;
 514
 515                 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
 516                         DEBUGOUT("EEPROM read failed\n");
 517                         break;
 518                 }
 519
 520                 /* Skip pointer section if the pointer is invalid. */
 521                 if (pointer == 0xFFFF || pointer == 0 ||
 522                     pointer >= hw->eeprom.word_size)
 523                         continue;
 524
 525                 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
 526                     IXGBE_SUCCESS) {
 527                         DEBUGOUT("EEPROM read failed\n");
 528                         break;
 529                 }
 530
 531                 /* Skip pointer section if length is invalid. */
 532                 if (length == 0xFFFF || length == 0 ||
 533                     (pointer + length) >= hw->eeprom.word_size)
 534                         continue;
 535
 536                 for (j = pointer+1; j <= pointer+length; j++) {
 537                         if (ixgbe_read_eerd_generic(hw, j, &word) !=
 538                             IXGBE_SUCCESS) {
 539                                 DEBUGOUT("EEPROM read failed\n");
 540                                 break;
 541                         }
 542                         checksum += word;
 543                 }
 544         }
 545
 546         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 547
 548         return checksum;
 549 }
 550
 551 /**
 552  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 553  *  @hw: pointer to hardware structure
 554  *  @checksum_val: calculated checksum
 555  *
 556  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 557  *  caller does not need checksum_val, the value can be NULL.
 558  **/
 559 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 560                                         u16 *checksum_val)
 561 {
 562         s32 status;
 563         u16 checksum;
 564         u16 read_checksum = 0;
 565
 566         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
 567
 568         /*
 569          * Read the first word from the EEPROM. If this times out or fails, do
 570          * not continue or we could be in for a very long wait while every
 571          * EEPROM read fails
 572          */
 573         status = hw->eeprom.ops.read(hw, 0, &checksum);
 574
 575         if (status != IXGBE_SUCCESS) {
 576                 DEBUGOUT("EEPROM read failed\n");
 577                 goto out;
 578         }
 579
 580         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 581             IXGBE_SUCCESS) {
 582                 checksum = hw->eeprom.ops.calc_checksum(hw);
 583
 584                 /*
 585                  * Do not use hw->eeprom.ops.read because we do not want to take
 586                  * the synchronization semaphores twice here.
 587                 */
 588                 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 589                                         &read_checksum);
 590
 591                 /*
 592                  * Verify read checksum from EEPROM is the same as
 593                  * calculated checksum
 594                  */
 595                 if (read_checksum != checksum) {
 596                         status = IXGBE_ERR_EEPROM_CHECKSUM;
 597                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 598                                      "Invalid EEPROM checksum");
 599                 }
 600
 601                 /* If the user cares, return the calculated checksum */
 602                 if (checksum_val)
 603                         *checksum_val = checksum;
 604                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 605         } else {
 606                 status = IXGBE_ERR_SWFW_SYNC;
 607         }
 608
 609 out:
 610         return status;
 611 }
 612
 613 /**
 614  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 615  * @hw: pointer to hardware structure
 616  *
 617  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 618  * checksum and updates the EEPROM and instructs the hardware to update
 619  * the flash.
 620  **/
 621 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 622 {
 623         s32 status;
 624         u16 checksum;
 625
 626         DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
 627
 628         /*
 629          * Read the first word from the EEPROM. If this times out or fails, do
 630          * not continue or we could be in for a very long wait while every
 631          * EEPROM read fails
 632          */
 633         status = hw->eeprom.ops.read(hw, 0, &checksum);
 634
 635         if (status != IXGBE_SUCCESS) {
 636                 DEBUGOUT("EEPROM read failed\n");
 637                 return status;
 638         }
 639
 640         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 641             IXGBE_SUCCESS) {
 642                 checksum = hw->eeprom.ops.calc_checksum(hw);
 643
 644                 /*
 645                  * Do not use hw->eeprom.ops.write because we do not want to
 646                  * take the synchronization semaphores twice here.
 647                  */
 648                 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
 649                                                   checksum);
 650
 651                 if (status == IXGBE_SUCCESS)
 652                         status = ixgbe_update_flash_X540(hw);
 653                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 654         } else {
 655                 status = IXGBE_ERR_SWFW_SYNC;
 656         }
 657
 658         return status;
 659 }
 660
 661 /**
 662  *  ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 663  *  @hw: pointer to hardware structure
 664  *
 665  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 666  *  EEPROM from shadow RAM to the flash device.
 667  **/
 668 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 669 {
 670         u32 flup;
 671         s32 status;
 672
 673         DEBUGFUNC("ixgbe_update_flash_X540");
 674
 675         status = ixgbe_poll_flash_update_done_X540(hw);
 676         if (status == IXGBE_ERR_EEPROM) {
 677                 DEBUGOUT("Flash update time out\n");
 678                 goto out;
 679         }
 680
 681         flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
 682         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 683
 684         status = ixgbe_poll_flash_update_done_X540(hw);
 685         if (status == IXGBE_SUCCESS)
 686                 DEBUGOUT("Flash update complete\n");
 687         else
 688                 DEBUGOUT("Flash update time out\n");
 689
 690         if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
 691                 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 692
 693                 if (flup & IXGBE_EEC_SEC1VAL) {
 694                         flup |= IXGBE_EEC_FLUP;
 695                         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 696                 }
 697
 698                 status = ixgbe_poll_flash_update_done_X540(hw);
 699                 if (status == IXGBE_SUCCESS)
 700                         DEBUGOUT("Flash update complete\n");
 701                 else
 702                         DEBUGOUT("Flash update time out\n");
 703         }
 704 out:
 705         return status;
 706 }
 707
 708 /**
 709  *  ixgbe_poll_flash_update_done_X540 - Poll flash update status
 710  *  @hw: pointer to hardware structure
 711  *
 712  *  Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 713  *  flash update is done.
 714  **/
 715 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 716 {
 717         u32 i;
 718         u32 reg;
 719         s32 status = IXGBE_ERR_EEPROM;
 720
 721         DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
 722
 723         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 724                 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
 725                 if (reg & IXGBE_EEC_FLUDONE) {
 726                         status = IXGBE_SUCCESS;
 727                         break;
 728                 }
 729                 usec_delay(5);
 730         }
 731
 732         if (i == IXGBE_FLUDONE_ATTEMPTS)
 733                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 734                              "Flash update status polling timed out");
 735
 736         return status;
 737 }
 738
 739 /**
 740  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 741  *  @hw: pointer to hardware structure
 742  *  @mask: Mask to specify which semaphore to acquire
 743  *
 744  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 745  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
 746  **/
 747 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 748 {
 749         u32 swfw_sync;
 750         u32 swmask = mask;
 751         u32 fwmask = mask << 5;
 752         u32 hwmask = 0;
 753         u32 timeout = 200;
 754         u32 i;
 755         s32 ret_val = IXGBE_SUCCESS;
 756
 757         DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
 758
 759         if (swmask == IXGBE_GSSR_EEP_SM)
 760                 hwmask = IXGBE_GSSR_FLASH_SM;
 761
 762         /* SW only mask doesn't have FW bit pair */
 763         if (swmask == IXGBE_GSSR_SW_MNG_SM)
 764                 fwmask = 0;
 765
 766         for (i = 0; i < timeout; i++) {
 767                 /*
 768                  * SW NVM semaphore bit is used for access to all
 769                  * SW_FW_SYNC bits (not just NVM)
 770                  */
 771                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 772                         ret_val = IXGBE_ERR_SWFW_SYNC;
 773                         goto out;
 774                 }
 775
 776                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 777                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 778                         swfw_sync |= swmask;
 779                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 780                         ixgbe_release_swfw_sync_semaphore(hw);
 781                         msec_delay(5);
 782                         goto out;
 783                 } else {
 784                         /*
 785                          * Firmware currently using resource (fwmask), hardware
 786                          * currently using resource (hwmask), or other software
 787                          * thread currently using resource (swmask)
 788                          */
 789                         ixgbe_release_swfw_sync_semaphore(hw);
 790                         msec_delay(5);
 791                 }
 792         }
 793
 794         /* Failed to get SW only semaphore */
 795         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 796                 ret_val = IXGBE_ERR_SWFW_SYNC;
 797                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 798                              "Failed to get SW only semaphore");
 799                 goto out;
 800         }
 801
 802         /* If the resource is not released by the FW/HW the SW can assume that
 803          * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
 804          * of the requested resource(s) while ignoring the corresponding FW/HW
 805          * bits in the SW_FW_SYNC register.
 806          */
 807         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 808         if (swfw_sync & (fwmask | hwmask)) {
 809                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 810                         ret_val = IXGBE_ERR_SWFW_SYNC;
 811                         goto out;
 812                 }
 813
 814                 swfw_sync |= swmask;
 815                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 816                 ixgbe_release_swfw_sync_semaphore(hw);
 817                 msec_delay(5);
 818         }
 819         /* If the resource is not released by other SW the SW can assume that
 820          * the other SW malfunctions. In that case the SW should clear all SW
 821          * flags that it does not own and then repeat the whole process once
 822          * again.
 823          */
 824         else if (swfw_sync & swmask) {
 825                 ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM |
 826                         IXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM |
 827                         IXGBE_GSSR_MAC_CSR_SM);
 828                 ret_val = IXGBE_ERR_SWFW_SYNC;
 829         }
 830
 831 out:
 832         return ret_val;
 833 }
 834
 835 /**
 836  *  ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 837  *  @hw: pointer to hardware structure
 838  *  @mask: Mask to specify which semaphore to release
 839  *
 840  *  Releases the SWFW semaphore through the SW_FW_SYNC register
 841  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 842  **/
 843 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 844 {
 845         u32 swfw_sync;
 846         u32 swmask = mask;
 847
 848         DEBUGFUNC("ixgbe_release_swfw_sync_X540");
 849
 850         ixgbe_get_swfw_sync_semaphore(hw);
 851
 852         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 853         swfw_sync &= ~swmask;
 854         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 855
 856         ixgbe_release_swfw_sync_semaphore(hw);
 857         msec_delay(5);
 858 }
 859
 860 /**
 861  *  ixgbe_get_nvm_semaphore - Get hardware semaphore
 862  *  @hw: pointer to hardware structure
 863  *
 864  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
 865  **/
 866 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 867 {
 868         s32 status = IXGBE_ERR_EEPROM;
 869         u32 timeout = 2000;
 870         u32 i;
 871         u32 swsm;
 872
 873         DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
 874
 875         /* Get SMBI software semaphore between device drivers first */
 876         for (i = 0; i < timeout; i++) {
 877                 /*
 878                  * If the SMBI bit is 0 when we read it, then the bit will be
 879                  * set and we have the semaphore
 880                  */
 881                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 882                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 883                         status = IXGBE_SUCCESS;
 884                         break;
 885                 }
 886                 usec_delay(50);
 887         }
 888
 889         /* Now get the semaphore between SW/FW through the REGSMP bit */
 890         if (status == IXGBE_SUCCESS) {
 891                 for (i = 0; i < timeout; i++) {
 892                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 893                         if (!(swsm & IXGBE_SWFW_REGSMP))
 894                                 break;
 895
 896                         usec_delay(50);
 897                 }
 898
 899                 /*
 900                  * Release semaphores and return error if SW NVM semaphore
 901                  * was not granted because we don't have access to the EEPROM
 902                  */
 903                 if (i >= timeout) {
 904                         ERROR_REPORT1(IXGBE_ERROR_POLLING,
 905                                 "REGSMP Software NVM semaphore not granted.\n");
 906                         ixgbe_release_swfw_sync_semaphore(hw);
 907                         status = IXGBE_ERR_EEPROM;
 908                 }
 909         } else {
 910                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 911                              "Software semaphore SMBI between device drivers "
 912                              "not granted.\n");
 913         }
 914
 915         return status;
 916 }
 917
 918 /**
 919  *  ixgbe_release_nvm_semaphore - Release hardware semaphore
 920  *  @hw: pointer to hardware structure
 921  *
 922  *  This function clears hardware semaphore bits.
 923  **/
 924 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 925 {
 926         u32 swsm;
 927
 928         DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
 929
 930         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 931
 932         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 933         swsm &= ~IXGBE_SWSM_SMBI;
 934         IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 935
 936         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 937         swsm &= ~IXGBE_SWFW_REGSMP;
 938         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 939
 940         IXGBE_WRITE_FLUSH(hw);
 941 }
 942
 943 /**
 944  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 945  * @hw: pointer to hardware structure
 946  * @index: led number to blink
 947  *
 948  * Devices that implement the version 2 interface:
 949  *   X540
 950  **/
 951 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 952 {
 953         u32 macc_reg;
 954         u32 ledctl_reg;
 955         ixgbe_link_speed speed;
 956         bool link_up;
 957
 958         DEBUGFUNC("ixgbe_blink_led_start_X540");
 959
 960         /*
 961          * Link should be up in order for the blink bit in the LED control
 962          * register to work. Force link and speed in the MAC if link is down.
 963          * This will be reversed when we stop the blinking.
 964          */
 965         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 966         if (link_up == false) {
 967                 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 968                 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 969                 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 970         }
 971         /* Set the LED to LINK_UP + BLINK. */
 972         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 973         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 974         ledctl_reg |= IXGBE_LED_BLINK(index);
 975         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 976         IXGBE_WRITE_FLUSH(hw);
 977
 978         return IXGBE_SUCCESS;
 979 }
 980
 981 /**
 982  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 983  * @hw: pointer to hardware structure
 984  * @index: led number to stop blinking
 985  *
 986  * Devices that implement the version 2 interface:
 987  *   X540
 988  **/
 989 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 990 {
 991         u32 macc_reg;
 992         u32 ledctl_reg;
 993
 994         DEBUGFUNC("ixgbe_blink_led_stop_X540");
 995
 996         /* Restore the LED to its default value. */
 997         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 998         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 999         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1000         ledctl_reg &= ~IXGBE_LED_BLINK(index);
1001         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1002
1003         /* Unforce link and speed in the MAC. */
1004         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1005         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1006         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1007         IXGBE_WRITE_FLUSH(hw);
1008
1009         return IXGBE_SUCCESS;
1010 }
1011
1012