lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x540.h"
  35 #include "ixgbe_type.h"
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  41 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  42 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  43 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  44
  45 /**
  46  *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X540.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_phy_info *phy = &hw->phy;
  56         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  57         s32 ret_val;
  58
  59         DEBUGFUNC("ixgbe_init_ops_X540");
  60
  61         ret_val = ixgbe_init_phy_ops_generic(hw);
  62         ret_val = ixgbe_init_ops_generic(hw);
  63
  64
  65         /* EEPROM */
  66         eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
  67         eeprom->ops.read = &ixgbe_read_eerd_X540;
  68         eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
  69         eeprom->ops.write = &ixgbe_write_eewr_X540;
  70         eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
  71         eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
  72         eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
  73         eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
  74
  75         /* PHY */
  76         phy->ops.init = &ixgbe_init_phy_ops_generic;
  77         phy->ops.reset = NULL;
  78
  79         /* MAC */
  80         mac->ops.reset_hw = &ixgbe_reset_hw_X540;
  81         mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
  82         mac->ops.get_media_type = &ixgbe_get_media_type_X540;
  83         mac->ops.get_supported_physical_layer =
  84                                     &ixgbe_get_supported_physical_layer_X540;
  85         mac->ops.read_analog_reg8 = NULL;
  86         mac->ops.write_analog_reg8 = NULL;
  87         mac->ops.start_hw = &ixgbe_start_hw_X540;
  88         mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
  89         mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
  90         mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
  91         mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
  92         mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
  93         mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
  94         mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
  95         mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
  96         mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
  97
  98         /* RAR, Multicast, VLAN */
  99         mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
 100         mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
 101         mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
 102         mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
 103         mac->rar_highwater = 1;
 104         mac->ops.set_vfta = &ixgbe_set_vfta_generic;
 105         mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
 106         mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
 107         mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
 108         mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
 109         mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
 110
 111         /* Link */
 112         mac->ops.get_link_capabilities =
 113                                 &ixgbe_get_copper_link_capabilities_generic;
 114         mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
 115         mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
 116         mac->ops.check_link = &ixgbe_check_mac_link_generic;
 117
 118
 119         mac->mcft_size          = 128;
 120         mac->vft_size           = 128;
 121         mac->num_rar_entries    = 128;
 122         mac->rx_pb_size         = 384;
 123         mac->max_tx_queues      = 128;
 124         mac->max_rx_queues      = 128;
 125         mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_generic(hw);
 126
 127         /*
 128          * FWSM register
 129          * ARC supported; valid only if manageability features are
 130          * enabled.
 131          */
 132         mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
 133                                    IXGBE_FWSM_MODE_MASK) ? true : false;
 134
 135         hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 136
 137         /* LEDs */
 138         mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
 139         mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
 140
 141         /* Manageability interface */
 142         mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
 143
 144         return ret_val;
 145 }
 146
 147 /**
 148  *  ixgbe_get_link_capabilities_X540 - Determines link capabilities
 149  *  @hw: pointer to hardware structure
 150  *  @speed: pointer to link speed
 151  *  @autoneg: true when autoneg or autotry is enabled
 152  *
 153  *  Determines the link capabilities by reading the AUTOC register.
 154  **/
 155 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
 156                                      ixgbe_link_speed *speed,
 157                                      bool *autoneg)
 158 {
 159         ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
 160
 161         return IXGBE_SUCCESS;
 162 }
 163
 164 /**
 165  *  ixgbe_get_media_type_X540 - Get media type
 166  *  @hw: pointer to hardware structure
 167  *
 168  *  Returns the media type (fiber, copper, backplane)
 169  **/
 170 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
 171 {
 172         UNREFERENCED_1PARAMETER(hw);
 173         return ixgbe_media_type_copper;
 174 }
 175
 176 /**
 177  *  ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
 178  *  @hw: pointer to hardware structure
 179  *  @speed: new link speed
 180  *  @autoneg: true if autonegotiation enabled
 181  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 182  **/
 183 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
 184                               ixgbe_link_speed speed, bool autoneg,
 185                               bool autoneg_wait_to_complete)
 186 {
 187         DEBUGFUNC("ixgbe_setup_mac_link_X540");
 188         return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 189                                             autoneg_wait_to_complete);
 190 }
 191
 192 /**
 193  *  ixgbe_reset_hw_X540 - Perform hardware reset
 194  *  @hw: pointer to hardware structure
 195  *
 196  *  Resets the hardware by resetting the transmit and receive units, masks
 197  *  and clears all interrupts, and perform a reset.
 198  **/
 199 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
 200 {
 201         s32 status;
 202         u32 ctrl, i;
 203
 204         DEBUGFUNC("ixgbe_reset_hw_X540");
 205
 206         /* Call adapter stop to disable tx/rx and clear interrupts */
 207         status = hw->mac.ops.stop_adapter(hw);
 208         if (status != IXGBE_SUCCESS)
 209                 goto reset_hw_out;
 210
 211         /* flush pending Tx transactions */
 212         ixgbe_clear_tx_pending(hw);
 213
 214 mac_reset_top:
 215         ctrl = IXGBE_CTRL_RST;
 216         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 217         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 218         IXGBE_WRITE_FLUSH(hw);
 219
 220         /* Poll for reset bit to self-clear indicating reset is complete */
 221         for (i = 0; i < 10; i++) {
 222                 usec_delay(1);
 223                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 224                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 225                         break;
 226         }
 227
 228         if (ctrl & IXGBE_CTRL_RST_MASK) {
 229                 status = IXGBE_ERR_RESET_FAILED;
 230                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 231                              "Reset polling failed to complete.\n");
 232         }
 233         msec_delay(100);
 234
 235         /*
 236          * Double resets are required for recovery from certain error
 237          * conditions.  Between resets, it is necessary to stall to allow time
 238          * for any pending HW events to complete.
 239          */
 240         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 241                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 242                 goto mac_reset_top;
 243         }
 244
 245         /* Set the Rx packet buffer size. */
 246         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 247
 248         /* Store the permanent mac address */
 249         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 250
 251         /*
 252          * Store MAC address from RAR0, clear receive address registers, and
 253          * clear the multicast table.  Also reset num_rar_entries to 128,
 254          * since we modify this value when programming the SAN MAC address.
 255          */
 256         hw->mac.num_rar_entries = 128;
 257         hw->mac.ops.init_rx_addrs(hw);
 258
 259         /* Store the permanent SAN mac address */
 260         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 261
 262         /* Add the SAN MAC address to the RAR only if it's a valid address */
 263         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 264                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 265                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 266
 267                 /* Save the SAN MAC RAR index */
 268                 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 269
 270                 /* Reserve the last RAR for the SAN MAC address */
 271                 hw->mac.num_rar_entries--;
 272         }
 273
 274         /* Store the alternative WWNN/WWPN prefix */
 275         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 276                                    &hw->mac.wwpn_prefix);
 277
 278 reset_hw_out:
 279         return status;
 280 }
 281
 282 /**
 283  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 284  *  @hw: pointer to hardware structure
 285  *
 286  *  Starts the hardware using the generic start_hw function
 287  *  and the generation start_hw function.
 288  *  Then performs revision-specific operations, if any.
 289  **/
 290 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 291 {
 292         s32 ret_val = IXGBE_SUCCESS;
 293
 294         DEBUGFUNC("ixgbe_start_hw_X540");
 295
 296         ret_val = ixgbe_start_hw_generic(hw);
 297         if (ret_val != IXGBE_SUCCESS)
 298                 goto out;
 299
 300         ret_val = ixgbe_start_hw_gen2(hw);
 301
 302 out:
 303         return ret_val;
 304 }
 305
 306 /**
 307  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 308  *  @hw: pointer to hardware structure
 309  *
 310  *  Determines physical layer capabilities of the current configuration.
 311  **/
 312 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 313 {
 314         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 315         u16 ext_ability = 0;
 316
 317         DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
 318
 319         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 320         IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 321         if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 322                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 323         if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
 324                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 325         if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 326                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 327
 328         return physical_layer;
 329 }
 330
 331 /**
 332  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 333  *  @hw: pointer to hardware structure
 334  *
 335  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 336  *  ixgbe_hw struct in order to set up EEPROM access.
 337  **/
 338 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 339 {
 340         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 341         u32 eec;
 342         u16 eeprom_size;
 343
 344         DEBUGFUNC("ixgbe_init_eeprom_params_X540");
 345
 346         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 347                 eeprom->semaphore_delay = 10;
 348                 eeprom->type = ixgbe_flash;
 349
 350                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 351                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 352                                     IXGBE_EEC_SIZE_SHIFT);
 353                 eeprom->word_size = 1 << (eeprom_size +
 354                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 355
 356                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 357                           eeprom->type, eeprom->word_size);
 358         }
 359
 360         return IXGBE_SUCCESS;
 361 }
 362
 363 /**
 364  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 365  *  @hw: pointer to hardware structure
 366  *  @offset: offset of  word in the EEPROM to read
 367  *  @data: word read from the EEPROM
 368  *
 369  *  Reads a 16 bit word from the EEPROM using the EERD register.
 370  **/
 371 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 372 {
 373         s32 status = IXGBE_SUCCESS;
 374
 375         DEBUGFUNC("ixgbe_read_eerd_X540");
 376         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 377             IXGBE_SUCCESS)
 378                 status = ixgbe_read_eerd_generic(hw, offset, data);
 379         else
 380                 status = IXGBE_ERR_SWFW_SYNC;
 381
 382         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 383         return status;
 384 }
 385
 386 /**
 387  *  ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
 388  *  @hw: pointer to hardware structure
 389  *  @offset: offset of  word in the EEPROM to read
 390  *  @words: number of words
 391  *  @data: word(s) read from the EEPROM
 392  *
 393  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 394  **/
 395 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 396                                 u16 offset, u16 words, u16 *data)
 397 {
 398         s32 status = IXGBE_SUCCESS;
 399
 400         DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
 401         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 402             IXGBE_SUCCESS)
 403                 status = ixgbe_read_eerd_buffer_generic(hw, offset,
 404                                                         words, data);
 405         else
 406                 status = IXGBE_ERR_SWFW_SYNC;
 407
 408         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 409         return status;
 410 }
 411
 412 /**
 413  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 414  *  @hw: pointer to hardware structure
 415  *  @offset: offset of  word in the EEPROM to write
 416  *  @data: word write to the EEPROM
 417  *
 418  *  Write a 16 bit word to the EEPROM using the EEWR register.
 419  **/
 420 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 421 {
 422         s32 status = IXGBE_SUCCESS;
 423
 424         DEBUGFUNC("ixgbe_write_eewr_X540");
 425         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 426             IXGBE_SUCCESS)
 427                 status = ixgbe_write_eewr_generic(hw, offset, data);
 428         else
 429                 status = IXGBE_ERR_SWFW_SYNC;
 430
 431         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 432         return status;
 433 }
 434
 435 /**
 436  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 437  *  @hw: pointer to hardware structure
 438  *  @offset: offset of  word in the EEPROM to write
 439  *  @words: number of words
 440  *  @data: word(s) write to the EEPROM
 441  *
 442  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 443  **/
 444 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 445                                  u16 offset, u16 words, u16 *data)
 446 {
 447         s32 status = IXGBE_SUCCESS;
 448
 449         DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
 450         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 451             IXGBE_SUCCESS)
 452                 status = ixgbe_write_eewr_buffer_generic(hw, offset,
 453                                                          words, data);
 454         else
 455                 status = IXGBE_ERR_SWFW_SYNC;
 456
 457         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 458         return status;
 459 }
 460
 461 /**
 462  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 463  *
 464  *  This function does not use synchronization for EERD and EEWR. It can
 465  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 466  *
 467  *  @hw: pointer to hardware structure
 468  **/
 469 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 470 {
 471         u16 i;
 472         u16 j;
 473         u16 checksum = 0;
 474         u16 length = 0;
 475         u16 pointer = 0;
 476         u16 word = 0;
 477
 478         /*
 479          * Do not use hw->eeprom.ops.read because we do not want to take
 480          * the synchronization semaphores here. Instead use
 481          * ixgbe_read_eerd_generic
 482          */
 483
 484         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
 485
 486         /* Include 0x0-0x3F in the checksum */
 487         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 488                 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
 489                         DEBUGOUT("EEPROM read failed\n");
 490                         break;
 491                 }
 492                 checksum += word;
 493         }
 494
 495         /*
 496          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 497          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 498          */
 499         for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
 500                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 501                         continue;
 502
 503                 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
 504                         DEBUGOUT("EEPROM read failed\n");
 505                         break;
 506                 }
 507
 508                 /* Skip pointer section if the pointer is invalid. */
 509                 if (pointer == 0xFFFF || pointer == 0 ||
 510                     pointer >= hw->eeprom.word_size)
 511                         continue;
 512
 513                 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
 514                     IXGBE_SUCCESS) {
 515                         DEBUGOUT("EEPROM read failed\n");
 516                         break;
 517                 }
 518
 519                 /* Skip pointer section if length is invalid. */
 520                 if (length == 0xFFFF || length == 0 ||
 521                     (pointer + length) >= hw->eeprom.word_size)
 522                         continue;
 523
 524                 for (j = pointer+1; j <= pointer+length; j++) {
 525                         if (ixgbe_read_eerd_generic(hw, j, &word) !=
 526                             IXGBE_SUCCESS) {
 527                                 DEBUGOUT("EEPROM read failed\n");
 528                                 break;
 529                         }
 530                         checksum += word;
 531                 }
 532         }
 533
 534         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 535
 536         return checksum;
 537 }
 538
 539 /**
 540  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 541  *  @hw: pointer to hardware structure
 542  *  @checksum_val: calculated checksum
 543  *
 544  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 545  *  caller does not need checksum_val, the value can be NULL.
 546  **/
 547 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 548                                         u16 *checksum_val)
 549 {
 550         s32 status;
 551         u16 checksum;
 552         u16 read_checksum = 0;
 553
 554         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
 555
 556         /*
 557          * Read the first word from the EEPROM. If this times out or fails, do
 558          * not continue or we could be in for a very long wait while every
 559          * EEPROM read fails
 560          */
 561         status = hw->eeprom.ops.read(hw, 0, &checksum);
 562
 563         if (status != IXGBE_SUCCESS) {
 564                 DEBUGOUT("EEPROM read failed\n");
 565                 goto out;
 566         }
 567
 568         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 569             IXGBE_SUCCESS) {
 570                 checksum = hw->eeprom.ops.calc_checksum(hw);
 571
 572                 /*
 573                  * Do not use hw->eeprom.ops.read because we do not want to take
 574                  * the synchronization semaphores twice here.
 575                 */
 576                 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 577                                         &read_checksum);
 578
 579                 /*
 580                  * Verify read checksum from EEPROM is the same as
 581                  * calculated checksum
 582                  */
 583                 if (read_checksum != checksum) {
 584                         status = IXGBE_ERR_EEPROM_CHECKSUM;
 585                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 586                                      "Invalid EEPROM checksum");
 587                 }
 588
 589                 /* If the user cares, return the calculated checksum */
 590                 if (checksum_val)
 591                         *checksum_val = checksum;
 592         } else {
 593                 status = IXGBE_ERR_SWFW_SYNC;
 594         }
 595
 596         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 597 out:
 598         return status;
 599 }
 600
 601 /**
 602  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 603  * @hw: pointer to hardware structure
 604  *
 605  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 606  * checksum and updates the EEPROM and instructs the hardware to update
 607  * the flash.
 608  **/
 609 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 610 {
 611         s32 status;
 612         u16 checksum;
 613
 614         DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
 615
 616         /*
 617          * Read the first word from the EEPROM. If this times out or fails, do
 618          * not continue or we could be in for a very long wait while every
 619          * EEPROM read fails
 620          */
 621         status = hw->eeprom.ops.read(hw, 0, &checksum);
 622
 623         if (status != IXGBE_SUCCESS)
 624                 DEBUGOUT("EEPROM read failed\n");
 625
 626         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 627             IXGBE_SUCCESS) {
 628                 checksum = hw->eeprom.ops.calc_checksum(hw);
 629
 630                 /*
 631                  * Do not use hw->eeprom.ops.write because we do not want to
 632                  * take the synchronization semaphores twice here.
 633                 */
 634                 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
 635                                                   checksum);
 636
 637         if (status == IXGBE_SUCCESS)
 638                 status = ixgbe_update_flash_X540(hw);
 639         else
 640                 status = IXGBE_ERR_SWFW_SYNC;
 641         }
 642
 643         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 644
 645         return status;
 646 }
 647
 648 /**
 649  *  ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 650  *  @hw: pointer to hardware structure
 651  *
 652  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 653  *  EEPROM from shadow RAM to the flash device.
 654  **/
 655 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 656 {
 657         u32 flup;
 658         s32 status;
 659
 660         DEBUGFUNC("ixgbe_update_flash_X540");
 661
 662         status = ixgbe_poll_flash_update_done_X540(hw);
 663         if (status == IXGBE_ERR_EEPROM) {
 664                 DEBUGOUT("Flash update time out\n");
 665                 goto out;
 666         }
 667
 668         flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
 669         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 670
 671         status = ixgbe_poll_flash_update_done_X540(hw);
 672         if (status == IXGBE_SUCCESS)
 673                 DEBUGOUT("Flash update complete\n");
 674         else
 675                 DEBUGOUT("Flash update time out\n");
 676
 677         if (hw->revision_id == 0) {
 678                 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 679
 680                 if (flup & IXGBE_EEC_SEC1VAL) {
 681                         flup |= IXGBE_EEC_FLUP;
 682                         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 683                 }
 684
 685                 status = ixgbe_poll_flash_update_done_X540(hw);
 686                 if (status == IXGBE_SUCCESS)
 687                         DEBUGOUT("Flash update complete\n");
 688                 else
 689                         DEBUGOUT("Flash update time out\n");
 690         }
 691 out:
 692         return status;
 693 }
 694
 695 /**
 696  *  ixgbe_poll_flash_update_done_X540 - Poll flash update status
 697  *  @hw: pointer to hardware structure
 698  *
 699  *  Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 700  *  flash update is done.
 701  **/
 702 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 703 {
 704         u32 i;
 705         u32 reg;
 706         s32 status = IXGBE_ERR_EEPROM;
 707
 708         DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
 709
 710         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 711                 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
 712                 if (reg & IXGBE_EEC_FLUDONE) {
 713                         status = IXGBE_SUCCESS;
 714                         break;
 715                 }
 716                 usec_delay(5);
 717         }
 718
 719         if (i == IXGBE_FLUDONE_ATTEMPTS)
 720                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 721                              "Flash update status polling timed out");
 722
 723         return status;
 724 }
 725
 726 /**
 727  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 728  *  @hw: pointer to hardware structure
 729  *  @mask: Mask to specify which semaphore to acquire
 730  *
 731  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 732  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
 733  **/
 734 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 735 {
 736         u32 swfw_sync;
 737         u32 swmask = mask;
 738         u32 fwmask = mask << 5;
 739         u32 hwmask = 0;
 740         u32 timeout = 200;
 741         u32 i;
 742         s32 ret_val = IXGBE_SUCCESS;
 743
 744         DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
 745
 746         if (swmask == IXGBE_GSSR_EEP_SM)
 747                 hwmask = IXGBE_GSSR_FLASH_SM;
 748
 749         /* SW only mask doesn't have FW bit pair */
 750         if (swmask == IXGBE_GSSR_SW_MNG_SM)
 751                 fwmask = 0;
 752
 753         for (i = 0; i < timeout; i++) {
 754                 /*
 755                  * SW NVM semaphore bit is used for access to all
 756                  * SW_FW_SYNC bits (not just NVM)
 757                  */
 758                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 759                         ret_val = IXGBE_ERR_SWFW_SYNC;
 760                         goto out;
 761                 }
 762
 763                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 764                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 765                         swfw_sync |= swmask;
 766                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 767                         ixgbe_release_swfw_sync_semaphore(hw);
 768                         msec_delay(5);
 769                         goto out;
 770                 } else {
 771                         /*
 772                          * Firmware currently using resource (fwmask), hardware
 773                          * currently using resource (hwmask), or other software
 774                          * thread currently using resource (swmask)
 775                          */
 776                         ixgbe_release_swfw_sync_semaphore(hw);
 777                         msec_delay(5);
 778                 }
 779         }
 780
 781         /* Failed to get SW only semaphore */
 782         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 783                 ret_val = IXGBE_ERR_SWFW_SYNC;
 784                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 785                              "Failed to get SW only semaphore");
 786                 goto out;
 787         }
 788
 789         /* If the resource is not released by the FW/HW the SW can assume that
 790          * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
 791          * of the requested resource(s) while ignoring the corresponding FW/HW
 792          * bits in the SW_FW_SYNC register.
 793          */
 794         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 795         if (swfw_sync & (fwmask | hwmask)) {
 796                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 797                         ret_val = IXGBE_ERR_SWFW_SYNC;
 798                         goto out;
 799                 }
 800
 801                 swfw_sync |= swmask;
 802                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 803                 ixgbe_release_swfw_sync_semaphore(hw);
 804                 msec_delay(5);
 805         }
 806
 807 out:
 808         return ret_val;
 809 }
 810
 811 /**
 812  *  ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 813  *  @hw: pointer to hardware structure
 814  *  @mask: Mask to specify which semaphore to release
 815  *
 816  *  Releases the SWFW semaphore through the SW_FW_SYNC register
 817  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 818  **/
 819 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 820 {
 821         u32 swfw_sync;
 822         u32 swmask = mask;
 823
 824         DEBUGFUNC("ixgbe_release_swfw_sync_X540");
 825
 826         ixgbe_get_swfw_sync_semaphore(hw);
 827
 828         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 829         swfw_sync &= ~swmask;
 830         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 831
 832         ixgbe_release_swfw_sync_semaphore(hw);
 833         msec_delay(5);
 834 }
 835
 836 /**
 837  *  ixgbe_get_nvm_semaphore - Get hardware semaphore
 838  *  @hw: pointer to hardware structure
 839  *
 840  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
 841  **/
 842 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 843 {
 844         s32 status = IXGBE_ERR_EEPROM;
 845         u32 timeout = 2000;
 846         u32 i;
 847         u32 swsm;
 848
 849         DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
 850
 851         /* Get SMBI software semaphore between device drivers first */
 852         for (i = 0; i < timeout; i++) {
 853                 /*
 854                  * If the SMBI bit is 0 when we read it, then the bit will be
 855                  * set and we have the semaphore
 856                  */
 857                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 858                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 859                         status = IXGBE_SUCCESS;
 860                         break;
 861                 }
 862                 usec_delay(50);
 863         }
 864
 865         /* Now get the semaphore between SW/FW through the REGSMP bit */
 866         if (status == IXGBE_SUCCESS) {
 867                 for (i = 0; i < timeout; i++) {
 868                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 869                         if (!(swsm & IXGBE_SWFW_REGSMP))
 870                                 break;
 871
 872                         usec_delay(50);
 873                 }
 874
 875                 /*
 876                  * Release semaphores and return error if SW NVM semaphore
 877                  * was not granted because we don't have access to the EEPROM
 878                  */
 879                 if (i >= timeout) {
 880                         ERROR_REPORT1(IXGBE_ERROR_POLLING,
 881                                 "REGSMP Software NVM semaphore not granted.\n");
 882                         ixgbe_release_swfw_sync_semaphore(hw);
 883                         status = IXGBE_ERR_EEPROM;
 884                 }
 885         } else {
 886                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 887                              "Software semaphore SMBI between device drivers "
 888                              "not granted.\n");
 889         }
 890
 891         return status;
 892 }
 893
 894 /**
 895  *  ixgbe_release_nvm_semaphore - Release hardware semaphore
 896  *  @hw: pointer to hardware structure
 897  *
 898  *  This function clears hardware semaphore bits.
 899  **/
 900 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 901 {
 902         u32 swsm;
 903
 904         DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
 905
 906         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 907
 908         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 909         swsm &= ~IXGBE_SWSM_SMBI;
 910         IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 911
 912         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 913         swsm &= ~IXGBE_SWFW_REGSMP;
 914         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 915
 916         IXGBE_WRITE_FLUSH(hw);
 917 }
 918
 919 /**
 920  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 921  * @hw: pointer to hardware structure
 922  * @index: led number to blink
 923  *
 924  * Devices that implement the version 2 interface:
 925  *   X540
 926  **/
 927 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 928 {
 929         u32 macc_reg;
 930         u32 ledctl_reg;
 931         ixgbe_link_speed speed;
 932         bool link_up;
 933
 934         DEBUGFUNC("ixgbe_blink_led_start_X540");
 935
 936         /*
 937          * Link should be up in order for the blink bit in the LED control
 938          * register to work. Force link and speed in the MAC if link is down.
 939          * This will be reversed when we stop the blinking.
 940          */
 941         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 942         if (link_up == false) {
 943                 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 944                 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 945                 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 946         }
 947         /* Set the LED to LINK_UP + BLINK. */
 948         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 949         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 950         ledctl_reg |= IXGBE_LED_BLINK(index);
 951         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 952         IXGBE_WRITE_FLUSH(hw);
 953
 954         return IXGBE_SUCCESS;
 955 }
 956
 957 /**
 958  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 959  * @hw: pointer to hardware structure
 960  * @index: led number to stop blinking
 961  *
 962  * Devices that implement the version 2 interface:
 963  *   X540
 964  **/
 965 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 966 {
 967         u32 macc_reg;
 968         u32 ledctl_reg;
 969
 970         DEBUGFUNC("ixgbe_blink_led_stop_X540");
 971
 972         /* Restore the LED to its default value. */
 973         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 974         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 975         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 976         ledctl_reg &= ~IXGBE_LED_BLINK(index);
 977         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 978
 979         /* Unforce link and speed in the MAC. */
 980         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 981         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
 982         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 983         IXGBE_WRITE_FLUSH(hw);
 984
 985         return IXGBE_SUCCESS;
 986 }
 987
 988