lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x540.h"
  35 #include "ixgbe_type.h"
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
  41 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
  42                                       ixgbe_link_speed *speed,
  43                                       bool *autoneg);
  44 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw);
  45 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
  46                                ixgbe_link_speed speed,
  47                                bool autoneg, bool link_up_wait_to_complete);
  48 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw);
  49 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw);
  50 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);
  51
  52 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw);
  53 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data);
  54 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
  55                                 u16 offset, u16 words, u16 *data);
  56 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data);
  57 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
  58                                  u16 offset, u16 words, u16 *data);
  59 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);
  60 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);
  61 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);
  62
  63 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
  64 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
  65
  66 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  67 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  68 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  69 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  70
  71 /**
  72  *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type
  73  *  @hw: pointer to hardware structure
  74  *
  75  *  Initialize the function pointers and assign the MAC type for 82599.
  76  *  Does not touch the hardware.
  77  **/
  78 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
  79 {
  80         struct ixgbe_mac_info *mac = &hw->mac;
  81         struct ixgbe_phy_info *phy = &hw->phy;
  82         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  83         s32 ret_val;
  84
  85         DEBUGFUNC("ixgbe_init_ops_X540");
  86
  87         ret_val = ixgbe_init_phy_ops_generic(hw);
  88         ret_val = ixgbe_init_ops_generic(hw);
  89
  90
  91         /* EEPROM */
  92         eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
  93         eeprom->ops.read = &ixgbe_read_eerd_X540;
  94         eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
  95         eeprom->ops.write = &ixgbe_write_eewr_X540;
  96         eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
  97         eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
  98         eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
  99         eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
 100
 101         /* PHY */
 102         phy->ops.init = &ixgbe_init_phy_ops_generic;
 103         phy->ops.reset = NULL;
 104
 105         /* MAC */
 106         mac->ops.reset_hw = &ixgbe_reset_hw_X540;
 107         mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
 108         mac->ops.get_media_type = &ixgbe_get_media_type_X540;
 109         mac->ops.get_supported_physical_layer =
 110                                     &ixgbe_get_supported_physical_layer_X540;
 111         mac->ops.read_analog_reg8 = NULL;
 112         mac->ops.write_analog_reg8 = NULL;
 113         mac->ops.start_hw = &ixgbe_start_hw_X540;
 114         mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
 115         mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
 116         mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
 117         mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
 118         mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
 119         mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
 120         mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
 121
 122         /* RAR, Multicast, VLAN */
 123         mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
 124         mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
 125         mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
 126         mac->rar_highwater = 1;
 127         mac->ops.set_vfta = &ixgbe_set_vfta_generic;
 128         mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
 129         mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
 130         mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
 131         mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
 132
 133         /* Link */
 134         mac->ops.get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic;
 135         mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
 136         mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
 137         mac->ops.check_link = &ixgbe_check_mac_link_generic;
 138
 139         mac->mcft_size        = 128;
 140         mac->vft_size         = 128;
 141         mac->num_rar_entries  = 128;
 142         mac->rx_pb_size       = 384;
 143         mac->max_tx_queues    = 128;
 144         mac->max_rx_queues    = 128;
 145         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
 146
 147         /*
 148          * FWSM register
 149          * ARC supported; valid only if manageability features are
 150          * enabled.
 151          */
 152         mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
 153                                    IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
 154
 155         hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 156
 157         /* LEDs */
 158         mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
 159         mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
 160
 161         /* Manageability interface */
 162         mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
 163
 164         return ret_val;
 165 }
 166
 167 /**
 168  *  ixgbe_get_link_capabilities_X540 - Determines link capabilities
 169  *  @hw: pointer to hardware structure
 170  *  @speed: pointer to link speed
 171  *  @negotiation: TRUE when autoneg or autotry is enabled
 172  *
 173  *  Determines the link capabilities by reading the AUTOC register.
 174  **/
 175 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
 176                                      ixgbe_link_speed *speed,
 177                                      bool *negotiation)
 178 {
 179         ixgbe_get_copper_link_capabilities_generic(hw, speed, negotiation);
 180
 181         return IXGBE_SUCCESS;
 182 }
 183
 184 /**
 185  *  ixgbe_get_media_type_X540 - Get media type
 186  *  @hw: pointer to hardware structure
 187  *
 188  *  Returns the media type (fiber, copper, backplane)
 189  **/
 190 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
 191 {
 192         UNREFERENCED_1PARAMETER(hw);
 193         return ixgbe_media_type_copper;
 194 }
 195
 196 /**
 197  *  ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
 198  *  @hw: pointer to hardware structure
 199  *  @speed: new link speed
 200  *  @autoneg: TRUE if autonegotiation enabled
 201  *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
 202  **/
 203 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
 204                                      ixgbe_link_speed speed, bool autoneg,
 205                                      bool autoneg_wait_to_complete)
 206 {
 207         DEBUGFUNC("ixgbe_setup_mac_link_X540");
 208         return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 209                                             autoneg_wait_to_complete);
 210 }
 211
 212 /**
 213  *  ixgbe_reset_hw_X540 - Perform hardware reset
 214  *  @hw: pointer to hardware structure
 215  *
 216  *  Resets the hardware by resetting the transmit and receive units, masks
 217  *  and clears all interrupts, and perform a reset.
 218  **/
 219 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
 220 {
 221         s32 status;
 222         u32 ctrl, i;
 223
 224         DEBUGFUNC("ixgbe_reset_hw_X540");
 225
 226         /* Call adapter stop to disable tx/rx and clear interrupts */
 227         status = hw->mac.ops.stop_adapter(hw);
 228         if (status != IXGBE_SUCCESS)
 229                 goto reset_hw_out;
 230
 231         /* flush pending Tx transactions */
 232         ixgbe_clear_tx_pending(hw);
 233
 234 mac_reset_top:
 235         ctrl = IXGBE_CTRL_RST;
 236         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 237         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 238         IXGBE_WRITE_FLUSH(hw);
 239
 240         /* Poll for reset bit to self-clear indicating reset is complete */
 241         for (i = 0; i < 10; i++) {
 242                 usec_delay(1);
 243                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 244                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 245                         break;
 246         }
 247
 248         if (ctrl & IXGBE_CTRL_RST_MASK) {
 249                 status = IXGBE_ERR_RESET_FAILED;
 250                 DEBUGOUT("Reset polling failed to complete.\n");
 251         }
 252         msec_delay(100);
 253
 254         /*
 255          * Double resets are required for recovery from certain error
 256          * conditions.  Between resets, it is necessary to stall to allow time
 257          * for any pending HW events to complete.
 258          */
 259         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 260                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 261                 goto mac_reset_top;
 262         }
 263
 264         /* Set the Rx packet buffer size. */
 265         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 266
 267         /* Store the permanent mac address */
 268         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 269
 270         /*
 271          * Store MAC address from RAR0, clear receive address registers, and
 272          * clear the multicast table.  Also reset num_rar_entries to 128,
 273          * since we modify this value when programming the SAN MAC address.
 274          */
 275         hw->mac.num_rar_entries = 128;
 276         hw->mac.ops.init_rx_addrs(hw);
 277
 278         /* Store the permanent SAN mac address */
 279         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 280
 281         /* Add the SAN MAC address to the RAR only if it's a valid address */
 282         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 283                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 284                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 285
 286                 /* Reserve the last RAR for the SAN MAC address */
 287                 hw->mac.num_rar_entries--;
 288         }
 289
 290         /* Store the alternative WWNN/WWPN prefix */
 291         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 292                                        &hw->mac.wwpn_prefix);
 293
 294 reset_hw_out:
 295         return status;
 296 }
 297
 298 /**
 299  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 300  *  @hw: pointer to hardware structure
 301  *
 302  *  Starts the hardware using the generic start_hw function
 303  *  and the generation start_hw function.
 304  *  Then performs revision-specific operations, if any.
 305  **/
 306 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 307 {
 308         s32 ret_val = IXGBE_SUCCESS;
 309
 310         DEBUGFUNC("ixgbe_start_hw_X540");
 311
 312         ret_val = ixgbe_start_hw_generic(hw);
 313         if (ret_val != IXGBE_SUCCESS)
 314                 goto out;
 315
 316         ret_val = ixgbe_start_hw_gen2(hw);
 317
 318 out:
 319         return ret_val;
 320 }
 321
 322 /**
 323  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 324  *  @hw: pointer to hardware structure
 325  *
 326  *  Determines physical layer capabilities of the current configuration.
 327  **/
 328 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 329 {
 330         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 331         u16 ext_ability = 0;
 332
 333         DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
 334
 335         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 336         IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 337         if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 338                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 339         if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
 340                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 341         if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 342                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 343
 344         return physical_layer;
 345 }
 346
 347 /**
 348  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 349  *  @hw: pointer to hardware structure
 350  *
 351  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 352  *  ixgbe_hw struct in order to set up EEPROM access.
 353  **/
 354 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 355 {
 356         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 357         u32 eec;
 358         u16 eeprom_size;
 359
 360         DEBUGFUNC("ixgbe_init_eeprom_params_X540");
 361
 362         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 363                 eeprom->semaphore_delay = 10;
 364                 eeprom->type = ixgbe_flash;
 365
 366                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 367                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 368                                     IXGBE_EEC_SIZE_SHIFT);
 369                 eeprom->word_size = 1 << (eeprom_size +
 370                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 371
 372                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 373                           eeprom->type, eeprom->word_size);
 374         }
 375
 376         return IXGBE_SUCCESS;
 377 }
 378
 379 /**
 380  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 381  *  @hw: pointer to hardware structure
 382  *  @offset: offset of  word in the EEPROM to read
 383  *  @data: word read from the EEPROM
 384  *
 385  *  Reads a 16 bit word from the EEPROM using the EERD register.
 386  **/
 387 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 388 {
 389         s32 status = IXGBE_SUCCESS;
 390
 391         DEBUGFUNC("ixgbe_read_eerd_X540");
 392         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 393             IXGBE_SUCCESS)
 394                 status = ixgbe_read_eerd_generic(hw, offset, data);
 395         else
 396                 status = IXGBE_ERR_SWFW_SYNC;
 397
 398         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 399         return status;
 400 }
 401
 402 /**
 403  *  ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
 404  *  @hw: pointer to hardware structure
 405  *  @offset: offset of  word in the EEPROM to read
 406  *  @words: number of words
 407  *  @data: word(s) read from the EEPROM
 408  *
 409  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 410  **/
 411 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 412                                 u16 offset, u16 words, u16 *data)
 413 {
 414         s32 status = IXGBE_SUCCESS;
 415
 416         DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
 417         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 418             IXGBE_SUCCESS)
 419                 status = ixgbe_read_eerd_buffer_generic(hw, offset,
 420                                                         words, data);
 421         else
 422                 status = IXGBE_ERR_SWFW_SYNC;
 423
 424         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 425         return status;
 426 }
 427
 428 /**
 429  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 430  *  @hw: pointer to hardware structure
 431  *  @offset: offset of  word in the EEPROM to write
 432  *  @data: word write to the EEPROM
 433  *
 434  *  Write a 16 bit word to the EEPROM using the EEWR register.
 435  **/
 436 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 437 {
 438         s32 status = IXGBE_SUCCESS;
 439
 440         DEBUGFUNC("ixgbe_write_eewr_X540");
 441         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 442             IXGBE_SUCCESS)
 443                 status = ixgbe_write_eewr_generic(hw, offset, data);
 444         else
 445                 status = IXGBE_ERR_SWFW_SYNC;
 446
 447         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 448         return status;
 449 }
 450
 451 /**
 452  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 453  *  @hw: pointer to hardware structure
 454  *  @offset: offset of  word in the EEPROM to write
 455  *  @words: number of words
 456  *  @data: word(s) write to the EEPROM
 457  *
 458  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 459  **/
 460 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 461                                  u16 offset, u16 words, u16 *data)
 462 {
 463         s32 status = IXGBE_SUCCESS;
 464
 465         DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
 466         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 467             IXGBE_SUCCESS)
 468                 status = ixgbe_write_eewr_buffer_generic(hw, offset,
 469                                                          words, data);
 470         else
 471                 status = IXGBE_ERR_SWFW_SYNC;
 472
 473         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 474         return status;
 475 }
 476
 477 /**
 478  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 479  *
 480  *  This function does not use synchronization for EERD and EEWR. It can
 481  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 482  *
 483  *  @hw: pointer to hardware structure
 484  **/
 485 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 486 {
 487         u16 i;
 488         u16 j;
 489         u16 checksum = 0;
 490         u16 length = 0;
 491         u16 pointer = 0;
 492         u16 word = 0;
 493
 494         /*
 495          * Do not use hw->eeprom.ops.read because we do not want to take
 496          * the synchronization semaphores here. Instead use
 497          * ixgbe_read_eerd_generic
 498          */
 499
 500         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
 501
 502         /* Include 0x0-0x3F in the checksum */
 503         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 504                 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
 505                         DEBUGOUT("EEPROM read failed\n");
 506                         break;
 507                 }
 508                 checksum += word;
 509         }
 510
 511         /*
 512          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 513          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 514          */
 515         for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
 516                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 517                         continue;
 518
 519                 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
 520                         DEBUGOUT("EEPROM read failed\n");
 521                         break;
 522                 }
 523
 524                 /* Skip pointer section if the pointer is invalid. */
 525                 if (pointer == 0xFFFF || pointer == 0 ||
 526                     pointer >= hw->eeprom.word_size)
 527                         continue;
 528
 529                 if (ixgbe_read_eerd_generic(hw, pointer, &length)!=
 530                     IXGBE_SUCCESS) {
 531                         DEBUGOUT("EEPROM read failed\n");
 532                         break;
 533                 }
 534
 535                 /* Skip pointer section if length is invalid. */
 536                 if (length == 0xFFFF || length == 0 ||
 537                     (pointer + length) >= hw->eeprom.word_size)
 538                         continue;
 539
 540                 for (j = pointer+1; j <= pointer+length; j++) {
 541                         if (ixgbe_read_eerd_generic(hw, j, &word) !=
 542                             IXGBE_SUCCESS) {
 543                                 DEBUGOUT("EEPROM read failed\n");
 544                                 break;
 545                         }
 546                         checksum += word;
 547                 }
 548         }
 549
 550         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 551
 552         return checksum;
 553 }
 554
 555 /**
 556  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 557  *  @hw: pointer to hardware structure
 558  *  @checksum_val: calculated checksum
 559  *
 560  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 561  *  caller does not need checksum_val, the value can be NULL.
 562  **/
 563 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 564                                         u16 *checksum_val)
 565 {
 566         s32 status;
 567         u16 checksum;
 568         u16 read_checksum = 0;
 569
 570         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
 571
 572         /*
 573          * Read the first word from the EEPROM. If this times out or fails, do
 574          * not continue or we could be in for a very long wait while every
 575          * EEPROM read fails
 576          */
 577         status = hw->eeprom.ops.read(hw, 0, &checksum);
 578
 579         if (status != IXGBE_SUCCESS) {
 580                 DEBUGOUT("EEPROM read failed\n");
 581                 goto out;
 582         }
 583
 584         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 585             IXGBE_SUCCESS) {
 586                 checksum = hw->eeprom.ops.calc_checksum(hw);
 587
 588                 /*
 589                  * Do not use hw->eeprom.ops.read because we do not want to take
 590                  * the synchronization semaphores twice here.
 591                 */
 592                 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 593                                         &read_checksum);
 594
 595                 /*
 596                  * Verify read checksum from EEPROM is the same as
 597                  * calculated checksum
 598                  */
 599                 if (read_checksum != checksum)
 600                         status = IXGBE_ERR_EEPROM_CHECKSUM;
 601
 602                 /* If the user cares, return the calculated checksum */
 603                 if (checksum_val)
 604                         *checksum_val = checksum;
 605         } else {
 606                 status = IXGBE_ERR_SWFW_SYNC;
 607         }
 608
 609         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 610 out:
 611         return status;
 612 }
 613
 614 /**
 615  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 616  * @hw: pointer to hardware structure
 617  *
 618  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 619  * checksum and updates the EEPROM and instructs the hardware to update
 620  * the flash.
 621  **/
 622 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 623 {
 624         s32 status;
 625         u16 checksum;
 626
 627         DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
 628
 629         /*
 630          * Read the first word from the EEPROM. If this times out or fails, do
 631          * not continue or we could be in for a very long wait while every
 632          * EEPROM read fails
 633          */
 634         status = hw->eeprom.ops.read(hw, 0, &checksum);
 635
 636         if (status != IXGBE_SUCCESS)
 637                 DEBUGOUT("EEPROM read failed\n");
 638
 639         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 640             IXGBE_SUCCESS) {
 641                 checksum = hw->eeprom.ops.calc_checksum(hw);
 642
 643                 /*
 644                  * Do not use hw->eeprom.ops.write because we do not want to
 645                  * take the synchronization semaphores twice here.
 646                 */
 647                 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
 648                                                   checksum);
 649
 650         if (status == IXGBE_SUCCESS)
 651                 status = ixgbe_update_flash_X540(hw);
 652         else
 653                 status = IXGBE_ERR_SWFW_SYNC;
 654         }
 655
 656         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 657
 658         return status;
 659 }
 660
 661 /**
 662  *  ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 663  *  @hw: pointer to hardware structure
 664  *
 665  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 666  *  EEPROM from shadow RAM to the flash device.
 667  **/
 668 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 669 {
 670         u32 flup;
 671         s32 status = IXGBE_ERR_EEPROM;
 672
 673         DEBUGFUNC("ixgbe_update_flash_X540");
 674
 675         status = ixgbe_poll_flash_update_done_X540(hw);
 676         if (status == IXGBE_ERR_EEPROM) {
 677                 DEBUGOUT("Flash update time out\n");
 678                 goto out;
 679         }
 680
 681         flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
 682         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 683
 684         status = ixgbe_poll_flash_update_done_X540(hw);
 685         if (status == IXGBE_SUCCESS)
 686                 DEBUGOUT("Flash update complete\n");
 687         else
 688                 DEBUGOUT("Flash update time out\n");
 689
 690         if (hw->revision_id == 0) {
 691                 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 692
 693                 if (flup & IXGBE_EEC_SEC1VAL) {
 694                         flup |= IXGBE_EEC_FLUP;
 695                         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 696                 }
 697
 698                 status = ixgbe_poll_flash_update_done_X540(hw);
 699                 if (status == IXGBE_SUCCESS)
 700                         DEBUGOUT("Flash update complete\n");
 701                 else
 702                         DEBUGOUT("Flash update time out\n");
 703         }
 704 out:
 705         return status;
 706 }
 707
 708 /**
 709  *  ixgbe_poll_flash_update_done_X540 - Poll flash update status
 710  *  @hw: pointer to hardware structure
 711  *
 712  *  Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 713  *  flash update is done.
 714  **/
 715 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 716 {
 717         u32 i;
 718         u32 reg;
 719         s32 status = IXGBE_ERR_EEPROM;
 720
 721         DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
 722
 723         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 724                 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
 725                 if (reg & IXGBE_EEC_FLUDONE) {
 726                         status = IXGBE_SUCCESS;
 727                         break;
 728                 }
 729                 usec_delay(5);
 730         }
 731         return status;
 732 }
 733
 734 /**
 735  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 736  *  @hw: pointer to hardware structure
 737  *  @mask: Mask to specify which semaphore to acquire
 738  *
 739  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 740  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
 741  **/
 742 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 743 {
 744         u32 swfw_sync;
 745         u32 swmask = mask;
 746         u32 fwmask = mask << 5;
 747         u32 hwmask = 0;
 748         u32 timeout = 200;
 749         u32 i;
 750         s32 ret_val = IXGBE_SUCCESS;
 751
 752         DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
 753
 754         if (swmask == IXGBE_GSSR_EEP_SM)
 755                 hwmask = IXGBE_GSSR_FLASH_SM;
 756
 757         /* SW only mask doesn't have FW bit pair */
 758         if (swmask == IXGBE_GSSR_SW_MNG_SM)
 759                 fwmask = 0;
 760
 761         for (i = 0; i < timeout; i++) {
 762                 /*
 763                  * SW NVM semaphore bit is used for access to all
 764                  * SW_FW_SYNC bits (not just NVM)
 765                  */
 766                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 767                         ret_val = IXGBE_ERR_SWFW_SYNC;
 768                         goto out;
 769                 }
 770
 771                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 772                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 773                         swfw_sync |= swmask;
 774                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 775                         ixgbe_release_swfw_sync_semaphore(hw);
 776                         msec_delay(5);
 777                         goto out;
 778                 } else {
 779                         /*
 780                          * Firmware currently using resource (fwmask), hardware currently
 781                          * using resource (hwmask), or other software thread currently
 782                          * using resource (swmask)
 783                          */
 784                         ixgbe_release_swfw_sync_semaphore(hw);
 785                         msec_delay(5);
 786                 }
 787         }
 788
 789         /* Failed to get SW only semaphore */
 790         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 791                 ret_val = IXGBE_ERR_SWFW_SYNC;
 792                 goto out;
 793         }
 794
 795         /* If the resource is not released by the FW/HW the SW can assume that
 796          * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
 797          * of the requested resource(s) while ignoring the corresponding FW/HW
 798          * bits in the SW_FW_SYNC register.
 799          */
 800         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 801         if (swfw_sync & (fwmask| hwmask)) {
 802                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 803                         ret_val = IXGBE_ERR_SWFW_SYNC;
 804                         goto out;
 805                 }
 806
 807                 swfw_sync |= swmask;
 808                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 809                 ixgbe_release_swfw_sync_semaphore(hw);
 810                 msec_delay(5);
 811         }
 812
 813 out:
 814         return ret_val;
 815 }
 816
 817 /**
 818  *  ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 819  *  @hw: pointer to hardware structure
 820  *  @mask: Mask to specify which semaphore to release
 821  *
 822  *  Releases the SWFW semaphore throught the SW_FW_SYNC register
 823  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 824  **/
 825 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 826 {
 827         u32 swfw_sync;
 828         u32 swmask = mask;
 829
 830         DEBUGFUNC("ixgbe_release_swfw_sync_X540");
 831
 832         ixgbe_get_swfw_sync_semaphore(hw);
 833
 834         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 835         swfw_sync &= ~swmask;
 836         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 837
 838         ixgbe_release_swfw_sync_semaphore(hw);
 839         msec_delay(5);
 840 }
 841
 842 /**
 843  *  ixgbe_get_nvm_semaphore - Get hardware semaphore
 844  *  @hw: pointer to hardware structure
 845  *
 846  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
 847  **/
 848 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 849 {
 850         s32 status = IXGBE_ERR_EEPROM;
 851         u32 timeout = 2000;
 852         u32 i;
 853         u32 swsm;
 854
 855         DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
 856
 857         /* Get SMBI software semaphore between device drivers first */
 858         for (i = 0; i < timeout; i++) {
 859                 /*
 860                  * If the SMBI bit is 0 when we read it, then the bit will be
 861                  * set and we have the semaphore
 862                  */
 863                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 864                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 865                         status = IXGBE_SUCCESS;
 866                         break;
 867                 }
 868                 usec_delay(50);
 869         }
 870
 871         /* Now get the semaphore between SW/FW through the REGSMP bit */
 872         if (status == IXGBE_SUCCESS) {
 873                 for (i = 0; i < timeout; i++) {
 874                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 875                         if (!(swsm & IXGBE_SWFW_REGSMP))
 876                                 break;
 877
 878                         usec_delay(50);
 879                 }
 880
 881                 /*
 882                  * Release semaphores and return error if SW NVM semaphore
 883                  * was not granted because we don't have access to the EEPROM
 884                  */
 885                 if (i >= timeout) {
 886                         DEBUGOUT("REGSMP Software NVM semaphore not granted.\n");
 887                         ixgbe_release_swfw_sync_semaphore(hw);
 888                         status = IXGBE_ERR_EEPROM;
 889                 }
 890         } else {
 891                 DEBUGOUT("Software semaphore SMBI between device drivers "
 892                          "not granted.\n");
 893         }
 894
 895         return status;
 896 }
 897
 898 /**
 899  *  ixgbe_release_nvm_semaphore - Release hardware semaphore
 900  *  @hw: pointer to hardware structure
 901  *
 902  *  This function clears hardware semaphore bits.
 903  **/
 904 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 905 {
 906         u32 swsm;
 907
 908         DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
 909
 910         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 911
 912         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 913         swsm &= ~IXGBE_SWSM_SMBI;
 914         IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 915
 916         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 917         swsm &= ~IXGBE_SWFW_REGSMP;
 918         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 919
 920         IXGBE_WRITE_FLUSH(hw);
 921 }
 922
 923 /**
 924  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 925  * @hw: pointer to hardware structure
 926  * @index: led number to blink
 927  *
 928  * Devices that implement the version 2 interface:
 929  *   X540
 930  **/
 931 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 932 {
 933         u32 macc_reg;
 934         u32 ledctl_reg;
 935
 936         DEBUGFUNC("ixgbe_blink_led_start_X540");
 937
 938         /*
 939          * In order for the blink bit in the LED control register
 940          * to work, link and speed must be forced in the MAC. We
 941          * will reverse this when we stop the blinking.
 942          */
 943         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 944         macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 945         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 946
 947         /* Set the LED to LINK_UP + BLINK. */
 948         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 949         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 950         ledctl_reg |= IXGBE_LED_BLINK(index);
 951         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 952         IXGBE_WRITE_FLUSH(hw);
 953
 954         return IXGBE_SUCCESS;
 955 }
 956
 957 /**
 958  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 959  * @hw: pointer to hardware structure
 960  * @index: led number to stop blinking
 961  *
 962  * Devices that implement the version 2 interface:
 963  *   X540
 964  **/
 965 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 966 {
 967         u32 macc_reg;
 968         u32 ledctl_reg;
 969
 970         DEBUGFUNC("ixgbe_blink_led_stop_X540");
 971
 972         /* Restore the LED to its default value. */
 973         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 974         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 975         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 976         ledctl_reg &= ~IXGBE_LED_BLINK(index);
 977         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 978
 979         /* Unforce link and speed in the MAC. */
 980         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 981         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
 982         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 983         IXGBE_WRITE_FLUSH(hw);
 984
 985         return IXGBE_SUCCESS;
 986 }
 987
 988