1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x540.h"
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
41 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
44 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw);
45 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg, bool link_up_wait_to_complete);
48 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw);
49 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw);
50 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);
52 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw);
53 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data);
54 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
55 u16 offset, u16 words, u16 *data);
56 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data);
57 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
58 u16 offset, u16 words, u16 *data);
59 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);
60 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);
61 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);
63 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
64 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
66 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
67 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
68 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
69 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
72 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
73 * @hw: pointer to hardware structure
75 * Initialize the function pointers and assign the MAC type for 82599.
76 * Does not touch the hardware.
78 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
80 struct ixgbe_mac_info *mac = &hw->mac;
81 struct ixgbe_phy_info *phy = &hw->phy;
82 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
85 DEBUGFUNC("ixgbe_init_ops_X540");
87 ret_val = ixgbe_init_phy_ops_generic(hw);
88 ret_val = ixgbe_init_ops_generic(hw);
92 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
93 eeprom->ops.read = &ixgbe_read_eerd_X540;
94 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
95 eeprom->ops.write = &ixgbe_write_eewr_X540;
96 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
97 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
98 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
99 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
102 phy->ops.init = &ixgbe_init_phy_ops_generic;
103 phy->ops.reset = NULL;
106 mac->ops.reset_hw = &ixgbe_reset_hw_X540;
107 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
108 mac->ops.get_media_type = &ixgbe_get_media_type_X540;
109 mac->ops.get_supported_physical_layer =
110 &ixgbe_get_supported_physical_layer_X540;
111 mac->ops.read_analog_reg8 = NULL;
112 mac->ops.write_analog_reg8 = NULL;
113 mac->ops.start_hw = &ixgbe_start_hw_X540;
114 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
115 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
116 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
117 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
118 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
119 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
120 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
122 /* RAR, Multicast, VLAN */
123 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
124 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
125 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
126 mac->rar_highwater = 1;
127 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
128 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
129 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
130 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
131 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
134 mac->ops.get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic;
135 mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
136 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
137 mac->ops.check_link = &ixgbe_check_mac_link_generic;
139 mac->mcft_size = 128;
141 mac->num_rar_entries = 128;
142 mac->rx_pb_size = 384;
143 mac->max_tx_queues = 128;
144 mac->max_rx_queues = 128;
145 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
149 * ARC supported; valid only if manageability features are
152 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
153 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
155 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
158 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
159 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
161 /* Manageability interface */
162 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
168 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
169 * @hw: pointer to hardware structure
170 * @speed: pointer to link speed
171 * @negotiation: TRUE when autoneg or autotry is enabled
173 * Determines the link capabilities by reading the AUTOC register.
175 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
176 ixgbe_link_speed *speed,
179 ixgbe_get_copper_link_capabilities_generic(hw, speed, negotiation);
181 return IXGBE_SUCCESS;
185 * ixgbe_get_media_type_X540 - Get media type
186 * @hw: pointer to hardware structure
188 * Returns the media type (fiber, copper, backplane)
190 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
192 UNREFERENCED_1PARAMETER(hw);
193 return ixgbe_media_type_copper;
197 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
198 * @hw: pointer to hardware structure
199 * @speed: new link speed
200 * @autoneg: TRUE if autonegotiation enabled
201 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
203 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
204 ixgbe_link_speed speed, bool autoneg,
205 bool autoneg_wait_to_complete)
207 DEBUGFUNC("ixgbe_setup_mac_link_X540");
208 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
209 autoneg_wait_to_complete);
213 * ixgbe_reset_hw_X540 - Perform hardware reset
214 * @hw: pointer to hardware structure
216 * Resets the hardware by resetting the transmit and receive units, masks
217 * and clears all interrupts, and perform a reset.
219 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
224 DEBUGFUNC("ixgbe_reset_hw_X540");
226 /* Call adapter stop to disable tx/rx and clear interrupts */
227 status = hw->mac.ops.stop_adapter(hw);
228 if (status != IXGBE_SUCCESS)
231 /* flush pending Tx transactions */
232 ixgbe_clear_tx_pending(hw);
235 ctrl = IXGBE_CTRL_RST;
236 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
237 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
238 IXGBE_WRITE_FLUSH(hw);
240 /* Poll for reset bit to self-clear indicating reset is complete */
241 for (i = 0; i < 10; i++) {
243 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
244 if (!(ctrl & IXGBE_CTRL_RST_MASK))
248 if (ctrl & IXGBE_CTRL_RST_MASK) {
249 status = IXGBE_ERR_RESET_FAILED;
250 DEBUGOUT("Reset polling failed to complete.\n");
255 * Double resets are required for recovery from certain error
256 * conditions. Between resets, it is necessary to stall to allow time
257 * for any pending HW events to complete.
259 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
260 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
264 /* Set the Rx packet buffer size. */
265 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
267 /* Store the permanent mac address */
268 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
271 * Store MAC address from RAR0, clear receive address registers, and
272 * clear the multicast table. Also reset num_rar_entries to 128,
273 * since we modify this value when programming the SAN MAC address.
275 hw->mac.num_rar_entries = 128;
276 hw->mac.ops.init_rx_addrs(hw);
278 /* Store the permanent SAN mac address */
279 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
281 /* Add the SAN MAC address to the RAR only if it's a valid address */
282 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
283 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
284 hw->mac.san_addr, 0, IXGBE_RAH_AV);
286 /* Reserve the last RAR for the SAN MAC address */
287 hw->mac.num_rar_entries--;
290 /* Store the alternative WWNN/WWPN prefix */
291 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
292 &hw->mac.wwpn_prefix);
299 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
300 * @hw: pointer to hardware structure
302 * Starts the hardware using the generic start_hw function
303 * and the generation start_hw function.
304 * Then performs revision-specific operations, if any.
306 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
308 s32 ret_val = IXGBE_SUCCESS;
310 DEBUGFUNC("ixgbe_start_hw_X540");
312 ret_val = ixgbe_start_hw_generic(hw);
313 if (ret_val != IXGBE_SUCCESS)
316 ret_val = ixgbe_start_hw_gen2(hw);
323 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
324 * @hw: pointer to hardware structure
326 * Determines physical layer capabilities of the current configuration.
328 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
330 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
333 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
335 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
336 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
337 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
338 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
339 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
340 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
341 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
342 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
344 return physical_layer;
348 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
349 * @hw: pointer to hardware structure
351 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
352 * ixgbe_hw struct in order to set up EEPROM access.
354 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
356 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
360 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
362 if (eeprom->type == ixgbe_eeprom_uninitialized) {
363 eeprom->semaphore_delay = 10;
364 eeprom->type = ixgbe_flash;
366 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
367 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
368 IXGBE_EEC_SIZE_SHIFT);
369 eeprom->word_size = 1 << (eeprom_size +
370 IXGBE_EEPROM_WORD_SIZE_SHIFT);
372 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
373 eeprom->type, eeprom->word_size);
376 return IXGBE_SUCCESS;
380 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
381 * @hw: pointer to hardware structure
382 * @offset: offset of word in the EEPROM to read
383 * @data: word read from the EEPROM
385 * Reads a 16 bit word from the EEPROM using the EERD register.
387 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
389 s32 status = IXGBE_SUCCESS;
391 DEBUGFUNC("ixgbe_read_eerd_X540");
392 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
394 status = ixgbe_read_eerd_generic(hw, offset, data);
396 status = IXGBE_ERR_SWFW_SYNC;
398 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
403 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
404 * @hw: pointer to hardware structure
405 * @offset: offset of word in the EEPROM to read
406 * @words: number of words
407 * @data: word(s) read from the EEPROM
409 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
411 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
412 u16 offset, u16 words, u16 *data)
414 s32 status = IXGBE_SUCCESS;
416 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
417 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
419 status = ixgbe_read_eerd_buffer_generic(hw, offset,
422 status = IXGBE_ERR_SWFW_SYNC;
424 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
429 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
430 * @hw: pointer to hardware structure
431 * @offset: offset of word in the EEPROM to write
432 * @data: word write to the EEPROM
434 * Write a 16 bit word to the EEPROM using the EEWR register.
436 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
438 s32 status = IXGBE_SUCCESS;
440 DEBUGFUNC("ixgbe_write_eewr_X540");
441 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
443 status = ixgbe_write_eewr_generic(hw, offset, data);
445 status = IXGBE_ERR_SWFW_SYNC;
447 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
452 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
453 * @hw: pointer to hardware structure
454 * @offset: offset of word in the EEPROM to write
455 * @words: number of words
456 * @data: word(s) write to the EEPROM
458 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
460 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
461 u16 offset, u16 words, u16 *data)
463 s32 status = IXGBE_SUCCESS;
465 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
466 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
468 status = ixgbe_write_eewr_buffer_generic(hw, offset,
471 status = IXGBE_ERR_SWFW_SYNC;
473 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
478 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
480 * This function does not use synchronization for EERD and EEWR. It can
481 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
483 * @hw: pointer to hardware structure
485 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
495 * Do not use hw->eeprom.ops.read because we do not want to take
496 * the synchronization semaphores here. Instead use
497 * ixgbe_read_eerd_generic
500 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
502 /* Include 0x0-0x3F in the checksum */
503 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
504 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
505 DEBUGOUT("EEPROM read failed\n");
512 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
513 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
515 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
516 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
519 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
520 DEBUGOUT("EEPROM read failed\n");
524 /* Skip pointer section if the pointer is invalid. */
525 if (pointer == 0xFFFF || pointer == 0 ||
526 pointer >= hw->eeprom.word_size)
529 if (ixgbe_read_eerd_generic(hw, pointer, &length)!=
531 DEBUGOUT("EEPROM read failed\n");
535 /* Skip pointer section if length is invalid. */
536 if (length == 0xFFFF || length == 0 ||
537 (pointer + length) >= hw->eeprom.word_size)
540 for (j = pointer+1; j <= pointer+length; j++) {
541 if (ixgbe_read_eerd_generic(hw, j, &word) !=
543 DEBUGOUT("EEPROM read failed\n");
550 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
556 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
557 * @hw: pointer to hardware structure
558 * @checksum_val: calculated checksum
560 * Performs checksum calculation and validates the EEPROM checksum. If the
561 * caller does not need checksum_val, the value can be NULL.
563 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
568 u16 read_checksum = 0;
570 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
573 * Read the first word from the EEPROM. If this times out or fails, do
574 * not continue or we could be in for a very long wait while every
577 status = hw->eeprom.ops.read(hw, 0, &checksum);
579 if (status != IXGBE_SUCCESS) {
580 DEBUGOUT("EEPROM read failed\n");
584 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
586 checksum = hw->eeprom.ops.calc_checksum(hw);
589 * Do not use hw->eeprom.ops.read because we do not want to take
590 * the synchronization semaphores twice here.
592 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
596 * Verify read checksum from EEPROM is the same as
597 * calculated checksum
599 if (read_checksum != checksum)
600 status = IXGBE_ERR_EEPROM_CHECKSUM;
602 /* If the user cares, return the calculated checksum */
604 *checksum_val = checksum;
606 status = IXGBE_ERR_SWFW_SYNC;
609 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
615 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
616 * @hw: pointer to hardware structure
618 * After writing EEPROM to shadow RAM using EEWR register, software calculates
619 * checksum and updates the EEPROM and instructs the hardware to update
622 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
627 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
630 * Read the first word from the EEPROM. If this times out or fails, do
631 * not continue or we could be in for a very long wait while every
634 status = hw->eeprom.ops.read(hw, 0, &checksum);
636 if (status != IXGBE_SUCCESS)
637 DEBUGOUT("EEPROM read failed\n");
639 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
641 checksum = hw->eeprom.ops.calc_checksum(hw);
644 * Do not use hw->eeprom.ops.write because we do not want to
645 * take the synchronization semaphores twice here.
647 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
650 if (status == IXGBE_SUCCESS)
651 status = ixgbe_update_flash_X540(hw);
653 status = IXGBE_ERR_SWFW_SYNC;
656 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
662 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
663 * @hw: pointer to hardware structure
665 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
666 * EEPROM from shadow RAM to the flash device.
668 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
671 s32 status = IXGBE_ERR_EEPROM;
673 DEBUGFUNC("ixgbe_update_flash_X540");
675 status = ixgbe_poll_flash_update_done_X540(hw);
676 if (status == IXGBE_ERR_EEPROM) {
677 DEBUGOUT("Flash update time out\n");
681 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
682 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
684 status = ixgbe_poll_flash_update_done_X540(hw);
685 if (status == IXGBE_SUCCESS)
686 DEBUGOUT("Flash update complete\n");
688 DEBUGOUT("Flash update time out\n");
690 if (hw->revision_id == 0) {
691 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
693 if (flup & IXGBE_EEC_SEC1VAL) {
694 flup |= IXGBE_EEC_FLUP;
695 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
698 status = ixgbe_poll_flash_update_done_X540(hw);
699 if (status == IXGBE_SUCCESS)
700 DEBUGOUT("Flash update complete\n");
702 DEBUGOUT("Flash update time out\n");
709 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
710 * @hw: pointer to hardware structure
712 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
713 * flash update is done.
715 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
719 s32 status = IXGBE_ERR_EEPROM;
721 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
723 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
724 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
725 if (reg & IXGBE_EEC_FLUDONE) {
726 status = IXGBE_SUCCESS;
735 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
736 * @hw: pointer to hardware structure
737 * @mask: Mask to specify which semaphore to acquire
739 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
740 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
742 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
746 u32 fwmask = mask << 5;
750 s32 ret_val = IXGBE_SUCCESS;
752 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
754 if (swmask == IXGBE_GSSR_EEP_SM)
755 hwmask = IXGBE_GSSR_FLASH_SM;
757 /* SW only mask doesn't have FW bit pair */
758 if (swmask == IXGBE_GSSR_SW_MNG_SM)
761 for (i = 0; i < timeout; i++) {
763 * SW NVM semaphore bit is used for access to all
764 * SW_FW_SYNC bits (not just NVM)
766 if (ixgbe_get_swfw_sync_semaphore(hw)) {
767 ret_val = IXGBE_ERR_SWFW_SYNC;
771 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
772 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
774 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
775 ixgbe_release_swfw_sync_semaphore(hw);
780 * Firmware currently using resource (fwmask), hardware currently
781 * using resource (hwmask), or other software thread currently
782 * using resource (swmask)
784 ixgbe_release_swfw_sync_semaphore(hw);
789 /* Failed to get SW only semaphore */
790 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
791 ret_val = IXGBE_ERR_SWFW_SYNC;
795 /* If the resource is not released by the FW/HW the SW can assume that
796 * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
797 * of the requested resource(s) while ignoring the corresponding FW/HW
798 * bits in the SW_FW_SYNC register.
800 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
801 if (swfw_sync & (fwmask| hwmask)) {
802 if (ixgbe_get_swfw_sync_semaphore(hw)) {
803 ret_val = IXGBE_ERR_SWFW_SYNC;
808 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
809 ixgbe_release_swfw_sync_semaphore(hw);
818 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
819 * @hw: pointer to hardware structure
820 * @mask: Mask to specify which semaphore to release
822 * Releases the SWFW semaphore throught the SW_FW_SYNC register
823 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
825 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
830 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
832 ixgbe_get_swfw_sync_semaphore(hw);
834 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
835 swfw_sync &= ~swmask;
836 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
838 ixgbe_release_swfw_sync_semaphore(hw);
843 * ixgbe_get_nvm_semaphore - Get hardware semaphore
844 * @hw: pointer to hardware structure
846 * Sets the hardware semaphores so SW/FW can gain control of shared resources
848 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
850 s32 status = IXGBE_ERR_EEPROM;
855 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
857 /* Get SMBI software semaphore between device drivers first */
858 for (i = 0; i < timeout; i++) {
860 * If the SMBI bit is 0 when we read it, then the bit will be
861 * set and we have the semaphore
863 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
864 if (!(swsm & IXGBE_SWSM_SMBI)) {
865 status = IXGBE_SUCCESS;
871 /* Now get the semaphore between SW/FW through the REGSMP bit */
872 if (status == IXGBE_SUCCESS) {
873 for (i = 0; i < timeout; i++) {
874 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
875 if (!(swsm & IXGBE_SWFW_REGSMP))
882 * Release semaphores and return error if SW NVM semaphore
883 * was not granted because we don't have access to the EEPROM
886 DEBUGOUT("REGSMP Software NVM semaphore not granted.\n");
887 ixgbe_release_swfw_sync_semaphore(hw);
888 status = IXGBE_ERR_EEPROM;
891 DEBUGOUT("Software semaphore SMBI between device drivers "
899 * ixgbe_release_nvm_semaphore - Release hardware semaphore
900 * @hw: pointer to hardware structure
902 * This function clears hardware semaphore bits.
904 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
908 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
910 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
912 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
913 swsm &= ~IXGBE_SWSM_SMBI;
914 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
916 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
917 swsm &= ~IXGBE_SWFW_REGSMP;
918 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
920 IXGBE_WRITE_FLUSH(hw);
924 * ixgbe_blink_led_start_X540 - Blink LED based on index.
925 * @hw: pointer to hardware structure
926 * @index: led number to blink
928 * Devices that implement the version 2 interface:
931 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
936 DEBUGFUNC("ixgbe_blink_led_start_X540");
939 * In order for the blink bit in the LED control register
940 * to work, link and speed must be forced in the MAC. We
941 * will reverse this when we stop the blinking.
943 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
944 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
945 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
947 /* Set the LED to LINK_UP + BLINK. */
948 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
949 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
950 ledctl_reg |= IXGBE_LED_BLINK(index);
951 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
952 IXGBE_WRITE_FLUSH(hw);
954 return IXGBE_SUCCESS;
958 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
959 * @hw: pointer to hardware structure
960 * @index: led number to stop blinking
962 * Devices that implement the version 2 interface:
965 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
970 DEBUGFUNC("ixgbe_blink_led_stop_X540");
972 /* Restore the LED to its default value. */
973 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
974 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
975 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
976 ledctl_reg &= ~IXGBE_LED_BLINK(index);
977 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
979 /* Unforce link and speed in the MAC. */
980 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
981 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
982 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
983 IXGBE_WRITE_FLUSH(hw);
985 return IXGBE_SUCCESS;