lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x540.h"
  35 #include "ixgbe_type.h"
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 #define IXGBE_X540_MAX_TX_QUEUES        128
  41 #define IXGBE_X540_MAX_RX_QUEUES        128
  42 #define IXGBE_X540_RAR_ENTRIES          128
  43 #define IXGBE_X540_MC_TBL_SIZE          128
  44 #define IXGBE_X540_VFT_TBL_SIZE         128
  45 #define IXGBE_X540_RX_PB_SIZE           384
  46
  47 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  48 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  49 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  50 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  51
  52 /**
  53  *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Initialize the function pointers and assign the MAC type for X540.
  57  *  Does not touch the hardware.
  58  **/
  59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_mac_info *mac = &hw->mac;
  62         struct ixgbe_phy_info *phy = &hw->phy;
  63         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  64         s32 ret_val;
  65
  66         DEBUGFUNC("ixgbe_init_ops_X540");
  67
  68         ret_val = ixgbe_init_phy_ops_generic(hw);
  69         ret_val = ixgbe_init_ops_generic(hw);
  70
  71
  72         /* EEPROM */
  73         eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
  74         eeprom->ops.read = &ixgbe_read_eerd_X540;
  75         eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
  76         eeprom->ops.write = &ixgbe_write_eewr_X540;
  77         eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
  78         eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
  79         eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
  80         eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
  81
  82         /* PHY */
  83         phy->ops.init = &ixgbe_init_phy_ops_generic;
  84         phy->ops.reset = NULL;
  85
  86         /* MAC */
  87         mac->ops.reset_hw = &ixgbe_reset_hw_X540;
  88         mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
  89         mac->ops.get_media_type = &ixgbe_get_media_type_X540;
  90         mac->ops.get_supported_physical_layer =
  91                                     &ixgbe_get_supported_physical_layer_X540;
  92         mac->ops.read_analog_reg8 = NULL;
  93         mac->ops.write_analog_reg8 = NULL;
  94         mac->ops.start_hw = &ixgbe_start_hw_X540;
  95         mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
  96         mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
  97         mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
  98         mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
  99         mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
 100         mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
 101         mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
 102         mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
 103         mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
 104
 105         /* RAR, Multicast, VLAN */
 106         mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
 107         mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
 108         mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
 109         mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
 110         mac->rar_highwater = 1;
 111         mac->ops.set_vfta = &ixgbe_set_vfta_generic;
 112         mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
 113         mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
 114         mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
 115         mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
 116         mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
 117
 118         /* Link */
 119         mac->ops.get_link_capabilities =
 120                                 &ixgbe_get_copper_link_capabilities_generic;
 121         mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
 122         mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
 123         mac->ops.check_link = &ixgbe_check_mac_link_generic;
 124
 125
 126         mac->mcft_size          = IXGBE_X540_MC_TBL_SIZE;
 127         mac->vft_size           = IXGBE_X540_VFT_TBL_SIZE;
 128         mac->num_rar_entries    = IXGBE_X540_RAR_ENTRIES;
 129         mac->rx_pb_size         = IXGBE_X540_RX_PB_SIZE;
 130         mac->max_rx_queues      = IXGBE_X540_MAX_RX_QUEUES;
 131         mac->max_tx_queues      = IXGBE_X540_MAX_TX_QUEUES;
 132         mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_generic(hw);
 133
 134         /*
 135          * FWSM register
 136          * ARC supported; valid only if manageability features are
 137          * enabled.
 138          */
 139         mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
 140                                    IXGBE_FWSM_MODE_MASK) ? true : false;
 141
 142         hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 143
 144         /* LEDs */
 145         mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
 146         mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
 147
 148         /* Manageability interface */
 149         mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
 150
 151         return ret_val;
 152 }
 153
 154 /**
 155  *  ixgbe_get_link_capabilities_X540 - Determines link capabilities
 156  *  @hw: pointer to hardware structure
 157  *  @speed: pointer to link speed
 158  *  @autoneg: true when autoneg or autotry is enabled
 159  *
 160  *  Determines the link capabilities by reading the AUTOC register.
 161  **/
 162 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
 163                                      ixgbe_link_speed *speed,
 164                                      bool *autoneg)
 165 {
 166         ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
 167
 168         return IXGBE_SUCCESS;
 169 }
 170
 171 /**
 172  *  ixgbe_get_media_type_X540 - Get media type
 173  *  @hw: pointer to hardware structure
 174  *
 175  *  Returns the media type (fiber, copper, backplane)
 176  **/
 177 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
 178 {
 179         UNREFERENCED_1PARAMETER(hw);
 180         return ixgbe_media_type_copper;
 181 }
 182
 183 /**
 184  *  ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
 185  *  @hw: pointer to hardware structure
 186  *  @speed: new link speed
 187  *  @autoneg: true if autonegotiation enabled
 188  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 189  **/
 190 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
 191                               ixgbe_link_speed speed, bool autoneg,
 192                               bool autoneg_wait_to_complete)
 193 {
 194         DEBUGFUNC("ixgbe_setup_mac_link_X540");
 195         return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 196                                             autoneg_wait_to_complete);
 197 }
 198
 199 /**
 200  *  ixgbe_reset_hw_X540 - Perform hardware reset
 201  *  @hw: pointer to hardware structure
 202  *
 203  *  Resets the hardware by resetting the transmit and receive units, masks
 204  *  and clears all interrupts, and perform a reset.
 205  **/
 206 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
 207 {
 208         s32 status;
 209         u32 ctrl, i;
 210
 211         DEBUGFUNC("ixgbe_reset_hw_X540");
 212
 213         /* Call adapter stop to disable tx/rx and clear interrupts */
 214         status = hw->mac.ops.stop_adapter(hw);
 215         if (status != IXGBE_SUCCESS)
 216                 goto reset_hw_out;
 217
 218         /* flush pending Tx transactions */
 219         ixgbe_clear_tx_pending(hw);
 220
 221 mac_reset_top:
 222         ctrl = IXGBE_CTRL_RST;
 223         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 224         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 225         IXGBE_WRITE_FLUSH(hw);
 226
 227         /* Poll for reset bit to self-clear indicating reset is complete */
 228         for (i = 0; i < 10; i++) {
 229                 usec_delay(1);
 230                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 231                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 232                         break;
 233         }
 234
 235         if (ctrl & IXGBE_CTRL_RST_MASK) {
 236                 status = IXGBE_ERR_RESET_FAILED;
 237                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 238                              "Reset polling failed to complete.\n");
 239         }
 240         msec_delay(100);
 241
 242         /*
 243          * Double resets are required for recovery from certain error
 244          * conditions.  Between resets, it is necessary to stall to allow time
 245          * for any pending HW events to complete.
 246          */
 247         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 248                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 249                 goto mac_reset_top;
 250         }
 251
 252         /* Set the Rx packet buffer size. */
 253         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 254
 255         /* Store the permanent mac address */
 256         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 257
 258         /*
 259          * Store MAC address from RAR0, clear receive address registers, and
 260          * clear the multicast table.  Also reset num_rar_entries to 128,
 261          * since we modify this value when programming the SAN MAC address.
 262          */
 263         hw->mac.num_rar_entries = 128;
 264         hw->mac.ops.init_rx_addrs(hw);
 265
 266         /* Store the permanent SAN mac address */
 267         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 268
 269         /* Add the SAN MAC address to the RAR only if it's a valid address */
 270         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 271                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 272                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 273
 274                 /* Save the SAN MAC RAR index */
 275                 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 276
 277                 /* Reserve the last RAR for the SAN MAC address */
 278                 hw->mac.num_rar_entries--;
 279         }
 280
 281         /* Store the alternative WWNN/WWPN prefix */
 282         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 283                                    &hw->mac.wwpn_prefix);
 284
 285 reset_hw_out:
 286         return status;
 287 }
 288
 289 /**
 290  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 291  *  @hw: pointer to hardware structure
 292  *
 293  *  Starts the hardware using the generic start_hw function
 294  *  and the generation start_hw function.
 295  *  Then performs revision-specific operations, if any.
 296  **/
 297 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 298 {
 299         s32 ret_val = IXGBE_SUCCESS;
 300
 301         DEBUGFUNC("ixgbe_start_hw_X540");
 302
 303         ret_val = ixgbe_start_hw_generic(hw);
 304         if (ret_val != IXGBE_SUCCESS)
 305                 goto out;
 306
 307         ret_val = ixgbe_start_hw_gen2(hw);
 308
 309 out:
 310         return ret_val;
 311 }
 312
 313 /**
 314  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 315  *  @hw: pointer to hardware structure
 316  *
 317  *  Determines physical layer capabilities of the current configuration.
 318  **/
 319 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 320 {
 321         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 322         u16 ext_ability = 0;
 323
 324         DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
 325
 326         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 327         IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 328         if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 329                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 330         if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
 331                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 332         if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 333                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 334
 335         return physical_layer;
 336 }
 337
 338 /**
 339  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 340  *  @hw: pointer to hardware structure
 341  *
 342  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 343  *  ixgbe_hw struct in order to set up EEPROM access.
 344  **/
 345 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 346 {
 347         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 348         u32 eec;
 349         u16 eeprom_size;
 350
 351         DEBUGFUNC("ixgbe_init_eeprom_params_X540");
 352
 353         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 354                 eeprom->semaphore_delay = 10;
 355                 eeprom->type = ixgbe_flash;
 356
 357                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 358                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 359                                     IXGBE_EEC_SIZE_SHIFT);
 360                 eeprom->word_size = 1 << (eeprom_size +
 361                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 362
 363                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 364                           eeprom->type, eeprom->word_size);
 365         }
 366
 367         return IXGBE_SUCCESS;
 368 }
 369
 370 /**
 371  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 372  *  @hw: pointer to hardware structure
 373  *  @offset: offset of  word in the EEPROM to read
 374  *  @data: word read from the EEPROM
 375  *
 376  *  Reads a 16 bit word from the EEPROM using the EERD register.
 377  **/
 378 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 379 {
 380         s32 status = IXGBE_SUCCESS;
 381
 382         DEBUGFUNC("ixgbe_read_eerd_X540");
 383         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 384             IXGBE_SUCCESS)
 385                 status = ixgbe_read_eerd_generic(hw, offset, data);
 386         else
 387                 status = IXGBE_ERR_SWFW_SYNC;
 388
 389         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 390         return status;
 391 }
 392
 393 /**
 394  *  ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
 395  *  @hw: pointer to hardware structure
 396  *  @offset: offset of  word in the EEPROM to read
 397  *  @words: number of words
 398  *  @data: word(s) read from the EEPROM
 399  *
 400  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 401  **/
 402 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 403                                 u16 offset, u16 words, u16 *data)
 404 {
 405         s32 status = IXGBE_SUCCESS;
 406
 407         DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
 408         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 409             IXGBE_SUCCESS)
 410                 status = ixgbe_read_eerd_buffer_generic(hw, offset,
 411                                                         words, data);
 412         else
 413                 status = IXGBE_ERR_SWFW_SYNC;
 414
 415         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 416         return status;
 417 }
 418
 419 /**
 420  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 421  *  @hw: pointer to hardware structure
 422  *  @offset: offset of  word in the EEPROM to write
 423  *  @data: word write to the EEPROM
 424  *
 425  *  Write a 16 bit word to the EEPROM using the EEWR register.
 426  **/
 427 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 428 {
 429         s32 status = IXGBE_SUCCESS;
 430
 431         DEBUGFUNC("ixgbe_write_eewr_X540");
 432         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 433             IXGBE_SUCCESS)
 434                 status = ixgbe_write_eewr_generic(hw, offset, data);
 435         else
 436                 status = IXGBE_ERR_SWFW_SYNC;
 437
 438         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 439         return status;
 440 }
 441
 442 /**
 443  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 444  *  @hw: pointer to hardware structure
 445  *  @offset: offset of  word in the EEPROM to write
 446  *  @words: number of words
 447  *  @data: word(s) write to the EEPROM
 448  *
 449  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 450  **/
 451 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 452                                  u16 offset, u16 words, u16 *data)
 453 {
 454         s32 status = IXGBE_SUCCESS;
 455
 456         DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
 457         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 458             IXGBE_SUCCESS)
 459                 status = ixgbe_write_eewr_buffer_generic(hw, offset,
 460                                                          words, data);
 461         else
 462                 status = IXGBE_ERR_SWFW_SYNC;
 463
 464         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 465         return status;
 466 }
 467
 468 /**
 469  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 470  *
 471  *  This function does not use synchronization for EERD and EEWR. It can
 472  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 473  *
 474  *  @hw: pointer to hardware structure
 475  **/
 476 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 477 {
 478         u16 i;
 479         u16 j;
 480         u16 checksum = 0;
 481         u16 length = 0;
 482         u16 pointer = 0;
 483         u16 word = 0;
 484
 485         /*
 486          * Do not use hw->eeprom.ops.read because we do not want to take
 487          * the synchronization semaphores here. Instead use
 488          * ixgbe_read_eerd_generic
 489          */
 490
 491         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
 492
 493         /* Include 0x0-0x3F in the checksum */
 494         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 495                 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
 496                         DEBUGOUT("EEPROM read failed\n");
 497                         break;
 498                 }
 499                 checksum += word;
 500         }
 501
 502         /*
 503          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 504          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 505          */
 506         for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
 507                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 508                         continue;
 509
 510                 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
 511                         DEBUGOUT("EEPROM read failed\n");
 512                         break;
 513                 }
 514
 515                 /* Skip pointer section if the pointer is invalid. */
 516                 if (pointer == 0xFFFF || pointer == 0 ||
 517                     pointer >= hw->eeprom.word_size)
 518                         continue;
 519
 520                 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
 521                     IXGBE_SUCCESS) {
 522                         DEBUGOUT("EEPROM read failed\n");
 523                         break;
 524                 }
 525
 526                 /* Skip pointer section if length is invalid. */
 527                 if (length == 0xFFFF || length == 0 ||
 528                     (pointer + length) >= hw->eeprom.word_size)
 529                         continue;
 530
 531                 for (j = pointer+1; j <= pointer+length; j++) {
 532                         if (ixgbe_read_eerd_generic(hw, j, &word) !=
 533                             IXGBE_SUCCESS) {
 534                                 DEBUGOUT("EEPROM read failed\n");
 535                                 break;
 536                         }
 537                         checksum += word;
 538                 }
 539         }
 540
 541         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 542
 543         return checksum;
 544 }
 545
 546 /**
 547  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 548  *  @hw: pointer to hardware structure
 549  *  @checksum_val: calculated checksum
 550  *
 551  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 552  *  caller does not need checksum_val, the value can be NULL.
 553  **/
 554 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 555                                         u16 *checksum_val)
 556 {
 557         s32 status;
 558         u16 checksum;
 559         u16 read_checksum = 0;
 560
 561         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
 562
 563         /*
 564          * Read the first word from the EEPROM. If this times out or fails, do
 565          * not continue or we could be in for a very long wait while every
 566          * EEPROM read fails
 567          */
 568         status = hw->eeprom.ops.read(hw, 0, &checksum);
 569
 570         if (status != IXGBE_SUCCESS) {
 571                 DEBUGOUT("EEPROM read failed\n");
 572                 goto out;
 573         }
 574
 575         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 576             IXGBE_SUCCESS) {
 577                 checksum = hw->eeprom.ops.calc_checksum(hw);
 578
 579                 /*
 580                  * Do not use hw->eeprom.ops.read because we do not want to take
 581                  * the synchronization semaphores twice here.
 582                 */
 583                 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 584                                         &read_checksum);
 585
 586                 /*
 587                  * Verify read checksum from EEPROM is the same as
 588                  * calculated checksum
 589                  */
 590                 if (read_checksum != checksum) {
 591                         status = IXGBE_ERR_EEPROM_CHECKSUM;
 592                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 593                                      "Invalid EEPROM checksum");
 594                 }
 595
 596                 /* If the user cares, return the calculated checksum */
 597                 if (checksum_val)
 598                         *checksum_val = checksum;
 599         } else {
 600                 status = IXGBE_ERR_SWFW_SYNC;
 601         }
 602
 603         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 604 out:
 605         return status;
 606 }
 607
 608 /**
 609  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 610  * @hw: pointer to hardware structure
 611  *
 612  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 613  * checksum and updates the EEPROM and instructs the hardware to update
 614  * the flash.
 615  **/
 616 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 617 {
 618         s32 status;
 619         u16 checksum;
 620
 621         DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
 622
 623         /*
 624          * Read the first word from the EEPROM. If this times out or fails, do
 625          * not continue or we could be in for a very long wait while every
 626          * EEPROM read fails
 627          */
 628         status = hw->eeprom.ops.read(hw, 0, &checksum);
 629
 630         if (status != IXGBE_SUCCESS)
 631                 DEBUGOUT("EEPROM read failed\n");
 632
 633         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 634             IXGBE_SUCCESS) {
 635                 checksum = hw->eeprom.ops.calc_checksum(hw);
 636
 637                 /*
 638                  * Do not use hw->eeprom.ops.write because we do not want to
 639                  * take the synchronization semaphores twice here.
 640                 */
 641                 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
 642                                                   checksum);
 643
 644         if (status == IXGBE_SUCCESS)
 645                 status = ixgbe_update_flash_X540(hw);
 646         else
 647                 status = IXGBE_ERR_SWFW_SYNC;
 648         }
 649
 650         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 651
 652         return status;
 653 }
 654
 655 /**
 656  *  ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 657  *  @hw: pointer to hardware structure
 658  *
 659  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 660  *  EEPROM from shadow RAM to the flash device.
 661  **/
 662 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 663 {
 664         u32 flup;
 665         s32 status;
 666
 667         DEBUGFUNC("ixgbe_update_flash_X540");
 668
 669         status = ixgbe_poll_flash_update_done_X540(hw);
 670         if (status == IXGBE_ERR_EEPROM) {
 671                 DEBUGOUT("Flash update time out\n");
 672                 goto out;
 673         }
 674
 675         flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
 676         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 677
 678         status = ixgbe_poll_flash_update_done_X540(hw);
 679         if (status == IXGBE_SUCCESS)
 680                 DEBUGOUT("Flash update complete\n");
 681         else
 682                 DEBUGOUT("Flash update time out\n");
 683
 684         if (hw->revision_id == 0) {
 685                 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 686
 687                 if (flup & IXGBE_EEC_SEC1VAL) {
 688                         flup |= IXGBE_EEC_FLUP;
 689                         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 690                 }
 691
 692                 status = ixgbe_poll_flash_update_done_X540(hw);
 693                 if (status == IXGBE_SUCCESS)
 694                         DEBUGOUT("Flash update complete\n");
 695                 else
 696                         DEBUGOUT("Flash update time out\n");
 697         }
 698 out:
 699         return status;
 700 }
 701
 702 /**
 703  *  ixgbe_poll_flash_update_done_X540 - Poll flash update status
 704  *  @hw: pointer to hardware structure
 705  *
 706  *  Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 707  *  flash update is done.
 708  **/
 709 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 710 {
 711         u32 i;
 712         u32 reg;
 713         s32 status = IXGBE_ERR_EEPROM;
 714
 715         DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
 716
 717         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 718                 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
 719                 if (reg & IXGBE_EEC_FLUDONE) {
 720                         status = IXGBE_SUCCESS;
 721                         break;
 722                 }
 723                 usec_delay(5);
 724         }
 725
 726         if (i == IXGBE_FLUDONE_ATTEMPTS)
 727                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 728                              "Flash update status polling timed out");
 729
 730         return status;
 731 }
 732
 733 /**
 734  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 735  *  @hw: pointer to hardware structure
 736  *  @mask: Mask to specify which semaphore to acquire
 737  *
 738  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 739  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
 740  **/
 741 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 742 {
 743         u32 swfw_sync;
 744         u32 swmask = mask;
 745         u32 fwmask = mask << 5;
 746         u32 hwmask = 0;
 747         u32 timeout = 200;
 748         u32 i;
 749         s32 ret_val = IXGBE_SUCCESS;
 750
 751         DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
 752
 753         if (swmask == IXGBE_GSSR_EEP_SM)
 754                 hwmask = IXGBE_GSSR_FLASH_SM;
 755
 756         /* SW only mask doesn't have FW bit pair */
 757         if (swmask == IXGBE_GSSR_SW_MNG_SM)
 758                 fwmask = 0;
 759
 760         for (i = 0; i < timeout; i++) {
 761                 /*
 762                  * SW NVM semaphore bit is used for access to all
 763                  * SW_FW_SYNC bits (not just NVM)
 764                  */
 765                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 766                         ret_val = IXGBE_ERR_SWFW_SYNC;
 767                         goto out;
 768                 }
 769
 770                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 771                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 772                         swfw_sync |= swmask;
 773                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 774                         ixgbe_release_swfw_sync_semaphore(hw);
 775                         msec_delay(5);
 776                         goto out;
 777                 } else {
 778                         /*
 779                          * Firmware currently using resource (fwmask), hardware
 780                          * currently using resource (hwmask), or other software
 781                          * thread currently using resource (swmask)
 782                          */
 783                         ixgbe_release_swfw_sync_semaphore(hw);
 784                         msec_delay(5);
 785                 }
 786         }
 787
 788         /* Failed to get SW only semaphore */
 789         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 790                 ret_val = IXGBE_ERR_SWFW_SYNC;
 791                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 792                              "Failed to get SW only semaphore");
 793                 goto out;
 794         }
 795
 796         /* If the resource is not released by the FW/HW the SW can assume that
 797          * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
 798          * of the requested resource(s) while ignoring the corresponding FW/HW
 799          * bits in the SW_FW_SYNC register.
 800          */
 801         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 802         if (swfw_sync & (fwmask | hwmask)) {
 803                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 804                         ret_val = IXGBE_ERR_SWFW_SYNC;
 805                         goto out;
 806                 }
 807
 808                 swfw_sync |= swmask;
 809                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 810                 ixgbe_release_swfw_sync_semaphore(hw);
 811                 msec_delay(5);
 812         }
 813
 814 out:
 815         return ret_val;
 816 }
 817
 818 /**
 819  *  ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 820  *  @hw: pointer to hardware structure
 821  *  @mask: Mask to specify which semaphore to release
 822  *
 823  *  Releases the SWFW semaphore through the SW_FW_SYNC register
 824  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 825  **/
 826 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 827 {
 828         u32 swfw_sync;
 829         u32 swmask = mask;
 830
 831         DEBUGFUNC("ixgbe_release_swfw_sync_X540");
 832
 833         ixgbe_get_swfw_sync_semaphore(hw);
 834
 835         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 836         swfw_sync &= ~swmask;
 837         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 838
 839         ixgbe_release_swfw_sync_semaphore(hw);
 840         msec_delay(5);
 841 }
 842
 843 /**
 844  *  ixgbe_get_nvm_semaphore - Get hardware semaphore
 845  *  @hw: pointer to hardware structure
 846  *
 847  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
 848  **/
 849 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 850 {
 851         s32 status = IXGBE_ERR_EEPROM;
 852         u32 timeout = 2000;
 853         u32 i;
 854         u32 swsm;
 855
 856         DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
 857
 858         /* Get SMBI software semaphore between device drivers first */
 859         for (i = 0; i < timeout; i++) {
 860                 /*
 861                  * If the SMBI bit is 0 when we read it, then the bit will be
 862                  * set and we have the semaphore
 863                  */
 864                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 865                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 866                         status = IXGBE_SUCCESS;
 867                         break;
 868                 }
 869                 usec_delay(50);
 870         }
 871
 872         /* Now get the semaphore between SW/FW through the REGSMP bit */
 873         if (status == IXGBE_SUCCESS) {
 874                 for (i = 0; i < timeout; i++) {
 875                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 876                         if (!(swsm & IXGBE_SWFW_REGSMP))
 877                                 break;
 878
 879                         usec_delay(50);
 880                 }
 881
 882                 /*
 883                  * Release semaphores and return error if SW NVM semaphore
 884                  * was not granted because we don't have access to the EEPROM
 885                  */
 886                 if (i >= timeout) {
 887                         ERROR_REPORT1(IXGBE_ERROR_POLLING,
 888                                 "REGSMP Software NVM semaphore not granted.\n");
 889                         ixgbe_release_swfw_sync_semaphore(hw);
 890                         status = IXGBE_ERR_EEPROM;
 891                 }
 892         } else {
 893                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 894                              "Software semaphore SMBI between device drivers "
 895                              "not granted.\n");
 896         }
 897
 898         return status;
 899 }
 900
 901 /**
 902  *  ixgbe_release_nvm_semaphore - Release hardware semaphore
 903  *  @hw: pointer to hardware structure
 904  *
 905  *  This function clears hardware semaphore bits.
 906  **/
 907 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 908 {
 909         u32 swsm;
 910
 911         DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
 912
 913         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 914
 915         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 916         swsm &= ~IXGBE_SWSM_SMBI;
 917         IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 918
 919         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 920         swsm &= ~IXGBE_SWFW_REGSMP;
 921         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 922
 923         IXGBE_WRITE_FLUSH(hw);
 924 }
 925
 926 /**
 927  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 928  * @hw: pointer to hardware structure
 929  * @index: led number to blink
 930  *
 931  * Devices that implement the version 2 interface:
 932  *   X540
 933  **/
 934 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 935 {
 936         u32 macc_reg;
 937         u32 ledctl_reg;
 938         ixgbe_link_speed speed;
 939         bool link_up;
 940
 941         DEBUGFUNC("ixgbe_blink_led_start_X540");
 942
 943         /*
 944          * Link should be up in order for the blink bit in the LED control
 945          * register to work. Force link and speed in the MAC if link is down.
 946          * This will be reversed when we stop the blinking.
 947          */
 948         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 949         if (link_up == false) {
 950                 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 951                 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 952                 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 953         }
 954         /* Set the LED to LINK_UP + BLINK. */
 955         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 956         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 957         ledctl_reg |= IXGBE_LED_BLINK(index);
 958         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 959         IXGBE_WRITE_FLUSH(hw);
 960
 961         return IXGBE_SUCCESS;
 962 }
 963
 964 /**
 965  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 966  * @hw: pointer to hardware structure
 967  * @index: led number to stop blinking
 968  *
 969  * Devices that implement the version 2 interface:
 970  *   X540
 971  **/
 972 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 973 {
 974         u32 macc_reg;
 975         u32 ledctl_reg;
 976
 977         DEBUGFUNC("ixgbe_blink_led_stop_X540");
 978
 979         /* Restore the LED to its default value. */
 980         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 981         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 982         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 983         ledctl_reg &= ~IXGBE_LED_BLINK(index);
 984         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 985
 986         /* Unforce link and speed in the MAC. */
 987         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 988         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
 989         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 990         IXGBE_WRITE_FLUSH(hw);
 991
 992         return IXGBE_SUCCESS;
 993 }
 994
 995