1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
41 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
42 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
43 ixgbe_link_speed *speed,
45 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw);
46 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg, bool link_up_wait_to_complete);
49 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw);
50 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw);
51 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);
53 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw);
54 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data);
55 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
56 u16 offset, u16 words, u16 *data);
57 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data);
58 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
59 u16 offset, u16 words, u16 *data);
60 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);
61 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);
62 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);
64 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
65 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
67 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
68 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
69 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
70 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
73 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
74 * @hw: pointer to hardware structure
76 * Initialize the function pointers and assign the MAC type for 82599.
77 * Does not touch the hardware.
79 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
81 struct ixgbe_mac_info *mac = &hw->mac;
82 struct ixgbe_phy_info *phy = &hw->phy;
83 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
86 DEBUGFUNC("ixgbe_init_ops_X540");
88 ret_val = ixgbe_init_phy_ops_generic(hw);
89 ret_val = ixgbe_init_ops_generic(hw);
93 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
94 eeprom->ops.read = &ixgbe_read_eerd_X540;
95 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
96 eeprom->ops.write = &ixgbe_write_eewr_X540;
97 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
98 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
99 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
100 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
103 phy->ops.init = &ixgbe_init_phy_ops_generic;
104 phy->ops.reset = NULL;
107 mac->ops.reset_hw = &ixgbe_reset_hw_X540;
108 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
109 mac->ops.get_media_type = &ixgbe_get_media_type_X540;
110 mac->ops.get_supported_physical_layer =
111 &ixgbe_get_supported_physical_layer_X540;
112 mac->ops.read_analog_reg8 = NULL;
113 mac->ops.write_analog_reg8 = NULL;
114 mac->ops.start_hw = &ixgbe_start_hw_X540;
115 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
116 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
117 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
118 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
119 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
120 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
121 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
123 /* RAR, Multicast, VLAN */
124 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
125 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
126 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
127 mac->rar_highwater = 1;
128 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
129 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
130 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
131 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
132 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
135 mac->ops.get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic;
136 mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
137 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
138 mac->ops.check_link = &ixgbe_check_mac_link_generic;
140 mac->mcft_size = 128;
142 mac->num_rar_entries = 128;
143 mac->rx_pb_size = 384;
144 mac->max_tx_queues = 128;
145 mac->max_rx_queues = 128;
146 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
150 * ARC supported; valid only if manageability features are
153 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
154 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
156 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
159 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
160 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
162 /* Manageability interface */
163 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
169 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
170 * @hw: pointer to hardware structure
171 * @speed: pointer to link speed
172 * @negotiation: TRUE when autoneg or autotry is enabled
174 * Determines the link capabilities by reading the AUTOC register.
176 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
177 ixgbe_link_speed *speed,
180 ixgbe_get_copper_link_capabilities_generic(hw, speed, negotiation);
182 return IXGBE_SUCCESS;
186 * ixgbe_get_media_type_X540 - Get media type
187 * @hw: pointer to hardware structure
189 * Returns the media type (fiber, copper, backplane)
191 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
193 UNREFERENCED_1PARAMETER(hw);
194 return ixgbe_media_type_copper;
198 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
199 * @hw: pointer to hardware structure
200 * @speed: new link speed
201 * @autoneg: TRUE if autonegotiation enabled
202 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
204 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
205 ixgbe_link_speed speed, bool autoneg,
206 bool autoneg_wait_to_complete)
208 DEBUGFUNC("ixgbe_setup_mac_link_X540");
209 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
210 autoneg_wait_to_complete);
214 * ixgbe_reset_hw_X540 - Perform hardware reset
215 * @hw: pointer to hardware structure
217 * Resets the hardware by resetting the transmit and receive units, masks
218 * and clears all interrupts, and perform a reset.
220 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
225 DEBUGFUNC("ixgbe_reset_hw_X540");
227 /* Call adapter stop to disable tx/rx and clear interrupts */
228 status = hw->mac.ops.stop_adapter(hw);
229 if (status != IXGBE_SUCCESS)
232 /* flush pending Tx transactions */
233 ixgbe_clear_tx_pending(hw);
236 ctrl = IXGBE_CTRL_RST;
237 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
238 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
239 IXGBE_WRITE_FLUSH(hw);
241 /* Poll for reset bit to self-clear indicating reset is complete */
242 for (i = 0; i < 10; i++) {
244 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
245 if (!(ctrl & IXGBE_CTRL_RST_MASK))
249 if (ctrl & IXGBE_CTRL_RST_MASK) {
250 status = IXGBE_ERR_RESET_FAILED;
251 DEBUGOUT("Reset polling failed to complete.\n");
256 * Double resets are required for recovery from certain error
257 * conditions. Between resets, it is necessary to stall to allow time
258 * for any pending HW events to complete.
260 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
261 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
265 /* Set the Rx packet buffer size. */
266 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
268 /* Store the permanent mac address */
269 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
272 * Store MAC address from RAR0, clear receive address registers, and
273 * clear the multicast table. Also reset num_rar_entries to 128,
274 * since we modify this value when programming the SAN MAC address.
276 hw->mac.num_rar_entries = 128;
277 hw->mac.ops.init_rx_addrs(hw);
279 /* Store the permanent SAN mac address */
280 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
282 /* Add the SAN MAC address to the RAR only if it's a valid address */
283 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
284 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
285 hw->mac.san_addr, 0, IXGBE_RAH_AV);
287 /* Reserve the last RAR for the SAN MAC address */
288 hw->mac.num_rar_entries--;
291 /* Store the alternative WWNN/WWPN prefix */
292 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
293 &hw->mac.wwpn_prefix);
300 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
301 * @hw: pointer to hardware structure
303 * Starts the hardware using the generic start_hw function
304 * and the generation start_hw function.
305 * Then performs revision-specific operations, if any.
307 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
309 s32 ret_val = IXGBE_SUCCESS;
311 DEBUGFUNC("ixgbe_start_hw_X540");
313 ret_val = ixgbe_start_hw_generic(hw);
314 if (ret_val != IXGBE_SUCCESS)
317 ret_val = ixgbe_start_hw_gen2(hw);
324 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
325 * @hw: pointer to hardware structure
327 * Determines physical layer capabilities of the current configuration.
329 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
331 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
334 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
336 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
337 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
338 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
339 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
340 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
341 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
342 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
343 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
345 return physical_layer;
349 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
350 * @hw: pointer to hardware structure
352 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
353 * ixgbe_hw struct in order to set up EEPROM access.
355 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
357 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
361 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
363 if (eeprom->type == ixgbe_eeprom_uninitialized) {
364 eeprom->semaphore_delay = 10;
365 eeprom->type = ixgbe_flash;
367 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
368 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
369 IXGBE_EEC_SIZE_SHIFT);
370 eeprom->word_size = 1 << (eeprom_size +
371 IXGBE_EEPROM_WORD_SIZE_SHIFT);
373 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
374 eeprom->type, eeprom->word_size);
377 return IXGBE_SUCCESS;
381 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
382 * @hw: pointer to hardware structure
383 * @offset: offset of word in the EEPROM to read
384 * @data: word read from the EEPROM
386 * Reads a 16 bit word from the EEPROM using the EERD register.
388 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
390 s32 status = IXGBE_SUCCESS;
392 DEBUGFUNC("ixgbe_read_eerd_X540");
393 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
395 status = ixgbe_read_eerd_generic(hw, offset, data);
397 status = IXGBE_ERR_SWFW_SYNC;
399 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
404 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
405 * @hw: pointer to hardware structure
406 * @offset: offset of word in the EEPROM to read
407 * @words: number of words
408 * @data: word(s) read from the EEPROM
410 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
412 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
413 u16 offset, u16 words, u16 *data)
415 s32 status = IXGBE_SUCCESS;
417 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
418 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
420 status = ixgbe_read_eerd_buffer_generic(hw, offset,
423 status = IXGBE_ERR_SWFW_SYNC;
425 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
430 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
431 * @hw: pointer to hardware structure
432 * @offset: offset of word in the EEPROM to write
433 * @data: word write to the EEPROM
435 * Write a 16 bit word to the EEPROM using the EEWR register.
437 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
439 s32 status = IXGBE_SUCCESS;
441 DEBUGFUNC("ixgbe_write_eewr_X540");
442 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
444 status = ixgbe_write_eewr_generic(hw, offset, data);
446 status = IXGBE_ERR_SWFW_SYNC;
448 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
453 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
454 * @hw: pointer to hardware structure
455 * @offset: offset of word in the EEPROM to write
456 * @words: number of words
457 * @data: word(s) write to the EEPROM
459 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
461 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
462 u16 offset, u16 words, u16 *data)
464 s32 status = IXGBE_SUCCESS;
466 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
467 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
469 status = ixgbe_write_eewr_buffer_generic(hw, offset,
472 status = IXGBE_ERR_SWFW_SYNC;
474 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
479 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
481 * This function does not use synchronization for EERD and EEWR. It can
482 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
484 * @hw: pointer to hardware structure
486 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
496 * Do not use hw->eeprom.ops.read because we do not want to take
497 * the synchronization semaphores here. Instead use
498 * ixgbe_read_eerd_generic
501 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
503 /* Include 0x0-0x3F in the checksum */
504 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
505 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
506 DEBUGOUT("EEPROM read failed\n");
513 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
514 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
516 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
517 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
520 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
521 DEBUGOUT("EEPROM read failed\n");
525 /* Skip pointer section if the pointer is invalid. */
526 if (pointer == 0xFFFF || pointer == 0 ||
527 pointer >= hw->eeprom.word_size)
530 if (ixgbe_read_eerd_generic(hw, pointer, &length)!=
532 DEBUGOUT("EEPROM read failed\n");
536 /* Skip pointer section if length is invalid. */
537 if (length == 0xFFFF || length == 0 ||
538 (pointer + length) >= hw->eeprom.word_size)
541 for (j = pointer+1; j <= pointer+length; j++) {
542 if (ixgbe_read_eerd_generic(hw, j, &word) !=
544 DEBUGOUT("EEPROM read failed\n");
551 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
557 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
558 * @hw: pointer to hardware structure
559 * @checksum_val: calculated checksum
561 * Performs checksum calculation and validates the EEPROM checksum. If the
562 * caller does not need checksum_val, the value can be NULL.
564 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
569 u16 read_checksum = 0;
571 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
574 * Read the first word from the EEPROM. If this times out or fails, do
575 * not continue or we could be in for a very long wait while every
578 status = hw->eeprom.ops.read(hw, 0, &checksum);
580 if (status != IXGBE_SUCCESS) {
581 DEBUGOUT("EEPROM read failed\n");
585 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
587 checksum = hw->eeprom.ops.calc_checksum(hw);
590 * Do not use hw->eeprom.ops.read because we do not want to take
591 * the synchronization semaphores twice here.
593 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
597 * Verify read checksum from EEPROM is the same as
598 * calculated checksum
600 if (read_checksum != checksum)
601 status = IXGBE_ERR_EEPROM_CHECKSUM;
603 /* If the user cares, return the calculated checksum */
605 *checksum_val = checksum;
607 status = IXGBE_ERR_SWFW_SYNC;
610 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
616 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
617 * @hw: pointer to hardware structure
619 * After writing EEPROM to shadow RAM using EEWR register, software calculates
620 * checksum and updates the EEPROM and instructs the hardware to update
623 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
628 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
631 * Read the first word from the EEPROM. If this times out or fails, do
632 * not continue or we could be in for a very long wait while every
635 status = hw->eeprom.ops.read(hw, 0, &checksum);
637 if (status != IXGBE_SUCCESS)
638 DEBUGOUT("EEPROM read failed\n");
640 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
642 checksum = hw->eeprom.ops.calc_checksum(hw);
645 * Do not use hw->eeprom.ops.write because we do not want to
646 * take the synchronization semaphores twice here.
648 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
651 if (status == IXGBE_SUCCESS)
652 status = ixgbe_update_flash_X540(hw);
654 status = IXGBE_ERR_SWFW_SYNC;
657 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
663 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
664 * @hw: pointer to hardware structure
666 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
667 * EEPROM from shadow RAM to the flash device.
669 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
672 s32 status = IXGBE_ERR_EEPROM;
674 DEBUGFUNC("ixgbe_update_flash_X540");
676 status = ixgbe_poll_flash_update_done_X540(hw);
677 if (status == IXGBE_ERR_EEPROM) {
678 DEBUGOUT("Flash update time out\n");
682 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
683 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
685 status = ixgbe_poll_flash_update_done_X540(hw);
686 if (status == IXGBE_SUCCESS)
687 DEBUGOUT("Flash update complete\n");
689 DEBUGOUT("Flash update time out\n");
691 if (hw->revision_id == 0) {
692 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
694 if (flup & IXGBE_EEC_SEC1VAL) {
695 flup |= IXGBE_EEC_FLUP;
696 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
699 status = ixgbe_poll_flash_update_done_X540(hw);
700 if (status == IXGBE_SUCCESS)
701 DEBUGOUT("Flash update complete\n");
703 DEBUGOUT("Flash update time out\n");
710 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
711 * @hw: pointer to hardware structure
713 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
714 * flash update is done.
716 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
720 s32 status = IXGBE_ERR_EEPROM;
722 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
724 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
725 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
726 if (reg & IXGBE_EEC_FLUDONE) {
727 status = IXGBE_SUCCESS;
736 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
737 * @hw: pointer to hardware structure
738 * @mask: Mask to specify which semaphore to acquire
740 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
741 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
743 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
747 u32 fwmask = mask << 5;
751 s32 ret_val = IXGBE_SUCCESS;
753 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
755 if (swmask == IXGBE_GSSR_EEP_SM)
756 hwmask = IXGBE_GSSR_FLASH_SM;
758 /* SW only mask doesn't have FW bit pair */
759 if (swmask == IXGBE_GSSR_SW_MNG_SM)
762 for (i = 0; i < timeout; i++) {
764 * SW NVM semaphore bit is used for access to all
765 * SW_FW_SYNC bits (not just NVM)
767 if (ixgbe_get_swfw_sync_semaphore(hw)) {
768 ret_val = IXGBE_ERR_SWFW_SYNC;
772 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
773 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
775 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
776 ixgbe_release_swfw_sync_semaphore(hw);
781 * Firmware currently using resource (fwmask), hardware currently
782 * using resource (hwmask), or other software thread currently
783 * using resource (swmask)
785 ixgbe_release_swfw_sync_semaphore(hw);
790 /* Failed to get SW only semaphore */
791 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
792 ret_val = IXGBE_ERR_SWFW_SYNC;
796 /* If the resource is not released by the FW/HW the SW can assume that
797 * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
798 * of the requested resource(s) while ignoring the corresponding FW/HW
799 * bits in the SW_FW_SYNC register.
801 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
802 if (swfw_sync & (fwmask| hwmask)) {
803 if (ixgbe_get_swfw_sync_semaphore(hw)) {
804 ret_val = IXGBE_ERR_SWFW_SYNC;
809 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
810 ixgbe_release_swfw_sync_semaphore(hw);
819 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
820 * @hw: pointer to hardware structure
821 * @mask: Mask to specify which semaphore to release
823 * Releases the SWFW semaphore throught the SW_FW_SYNC register
824 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
826 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
831 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
833 ixgbe_get_swfw_sync_semaphore(hw);
835 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
836 swfw_sync &= ~swmask;
837 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
839 ixgbe_release_swfw_sync_semaphore(hw);
844 * ixgbe_get_nvm_semaphore - Get hardware semaphore
845 * @hw: pointer to hardware structure
847 * Sets the hardware semaphores so SW/FW can gain control of shared resources
849 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
851 s32 status = IXGBE_ERR_EEPROM;
856 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
858 /* Get SMBI software semaphore between device drivers first */
859 for (i = 0; i < timeout; i++) {
861 * If the SMBI bit is 0 when we read it, then the bit will be
862 * set and we have the semaphore
864 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
865 if (!(swsm & IXGBE_SWSM_SMBI)) {
866 status = IXGBE_SUCCESS;
872 /* Now get the semaphore between SW/FW through the REGSMP bit */
873 if (status == IXGBE_SUCCESS) {
874 for (i = 0; i < timeout; i++) {
875 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
876 if (!(swsm & IXGBE_SWFW_REGSMP))
883 * Release semaphores and return error if SW NVM semaphore
884 * was not granted because we don't have access to the EEPROM
887 DEBUGOUT("REGSMP Software NVM semaphore not granted.\n");
888 ixgbe_release_swfw_sync_semaphore(hw);
889 status = IXGBE_ERR_EEPROM;
892 DEBUGOUT("Software semaphore SMBI between device drivers "
900 * ixgbe_release_nvm_semaphore - Release hardware semaphore
901 * @hw: pointer to hardware structure
903 * This function clears hardware semaphore bits.
905 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
909 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
911 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
913 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
914 swsm &= ~IXGBE_SWSM_SMBI;
915 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
917 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
918 swsm &= ~IXGBE_SWFW_REGSMP;
919 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
921 IXGBE_WRITE_FLUSH(hw);
925 * ixgbe_blink_led_start_X540 - Blink LED based on index.
926 * @hw: pointer to hardware structure
927 * @index: led number to blink
929 * Devices that implement the version 2 interface:
932 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
937 DEBUGFUNC("ixgbe_blink_led_start_X540");
940 * In order for the blink bit in the LED control register
941 * to work, link and speed must be forced in the MAC. We
942 * will reverse this when we stop the blinking.
944 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
945 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
946 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
948 /* Set the LED to LINK_UP + BLINK. */
949 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
950 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
951 ledctl_reg |= IXGBE_LED_BLINK(index);
952 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
953 IXGBE_WRITE_FLUSH(hw);
955 return IXGBE_SUCCESS;
959 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
960 * @hw: pointer to hardware structure
961 * @index: led number to stop blinking
963 * Devices that implement the version 2 interface:
966 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
971 DEBUGFUNC("ixgbe_blink_led_stop_X540");
973 /* Restore the LED to its default value. */
974 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
975 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
976 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
977 ledctl_reg &= ~IXGBE_LED_BLINK(index);
978 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
980 /* Unforce link and speed in the MAC. */
981 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
982 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
983 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
984 IXGBE_WRITE_FLUSH(hw);
986 return IXGBE_SUCCESS;