lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x540.h"
  35 #include "ixgbe_type.h"
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 #define IXGBE_X540_MAX_TX_QUEUES        128
  41 #define IXGBE_X540_MAX_RX_QUEUES        128
  42 #define IXGBE_X540_RAR_ENTRIES          128
  43 #define IXGBE_X540_MC_TBL_SIZE          128
  44 #define IXGBE_X540_VFT_TBL_SIZE         128
  45 #define IXGBE_X540_RX_PB_SIZE           384
  46
  47 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  48 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  49 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  50 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  51
  52 /**
  53  *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Initialize the function pointers and assign the MAC type for X540.
  57  *  Does not touch the hardware.
  58  **/
  59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_mac_info *mac = &hw->mac;
  62         struct ixgbe_phy_info *phy = &hw->phy;
  63         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  64         s32 ret_val;
  65
  66         DEBUGFUNC("ixgbe_init_ops_X540");
  67
  68         ret_val = ixgbe_init_phy_ops_generic(hw);
  69         ret_val = ixgbe_init_ops_generic(hw);
  70
  71
  72         /* EEPROM */
  73         eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
  74         eeprom->ops.read = &ixgbe_read_eerd_X540;
  75         eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
  76         eeprom->ops.write = &ixgbe_write_eewr_X540;
  77         eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
  78         eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
  79         eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
  80         eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
  81
  82         /* PHY */
  83         phy->ops.init = &ixgbe_init_phy_ops_generic;
  84         phy->ops.reset = NULL;
  85
  86         /* MAC */
  87         mac->ops.reset_hw = &ixgbe_reset_hw_X540;
  88         mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
  89         mac->ops.get_media_type = &ixgbe_get_media_type_X540;
  90         mac->ops.get_supported_physical_layer =
  91                                     &ixgbe_get_supported_physical_layer_X540;
  92         mac->ops.read_analog_reg8 = NULL;
  93         mac->ops.write_analog_reg8 = NULL;
  94         mac->ops.start_hw = &ixgbe_start_hw_X540;
  95         mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
  96         mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
  97         mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
  98         mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
  99         mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
 100         mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
 101         mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
 102         mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
 103         mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
 104
 105         /* RAR, Multicast, VLAN */
 106         mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
 107         mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
 108         mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
 109         mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
 110         mac->rar_highwater = 1;
 111         mac->ops.set_vfta = &ixgbe_set_vfta_generic;
 112         mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
 113         mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
 114         mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
 115         mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
 116         mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
 117
 118         /* Link */
 119         mac->ops.get_link_capabilities =
 120                                 &ixgbe_get_copper_link_capabilities_generic;
 121         mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
 122         mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
 123         mac->ops.check_link = &ixgbe_check_mac_link_generic;
 124
 125
 126         mac->mcft_size          = IXGBE_X540_MC_TBL_SIZE;
 127         mac->vft_size           = IXGBE_X540_VFT_TBL_SIZE;
 128         mac->num_rar_entries    = IXGBE_X540_RAR_ENTRIES;
 129         mac->rx_pb_size         = IXGBE_X540_RX_PB_SIZE;
 130         mac->max_rx_queues      = IXGBE_X540_MAX_RX_QUEUES;
 131         mac->max_tx_queues      = IXGBE_X540_MAX_TX_QUEUES;
 132         mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_generic(hw);
 133
 134         /*
 135          * FWSM register
 136          * ARC supported; valid only if manageability features are
 137          * enabled.
 138          */
 139         mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
 140                                    IXGBE_FWSM_MODE_MASK) ? true : false;
 141
 142         hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 143
 144         /* LEDs */
 145         mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
 146         mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
 147
 148         /* Manageability interface */
 149         mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
 150
 151         mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
 152
 153         return ret_val;
 154 }
 155
 156 /**
 157  *  ixgbe_get_link_capabilities_X540 - Determines link capabilities
 158  *  @hw: pointer to hardware structure
 159  *  @speed: pointer to link speed
 160  *  @autoneg: true when autoneg or autotry is enabled
 161  *
 162  *  Determines the link capabilities by reading the AUTOC register.
 163  **/
 164 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
 165                                      ixgbe_link_speed *speed,
 166                                      bool *autoneg)
 167 {
 168         ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
 169
 170         return IXGBE_SUCCESS;
 171 }
 172
 173 /**
 174  *  ixgbe_get_media_type_X540 - Get media type
 175  *  @hw: pointer to hardware structure
 176  *
 177  *  Returns the media type (fiber, copper, backplane)
 178  **/
 179 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
 180 {
 181         UNREFERENCED_1PARAMETER(hw);
 182         return ixgbe_media_type_copper;
 183 }
 184
 185 /**
 186  *  ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
 187  *  @hw: pointer to hardware structure
 188  *  @speed: new link speed
 189  *  @autoneg: true if autonegotiation enabled
 190  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 191  **/
 192 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
 193                               ixgbe_link_speed speed, bool autoneg,
 194                               bool autoneg_wait_to_complete)
 195 {
 196         DEBUGFUNC("ixgbe_setup_mac_link_X540");
 197         return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 198                                             autoneg_wait_to_complete);
 199 }
 200
 201 /**
 202  *  ixgbe_reset_hw_X540 - Perform hardware reset
 203  *  @hw: pointer to hardware structure
 204  *
 205  *  Resets the hardware by resetting the transmit and receive units, masks
 206  *  and clears all interrupts, and perform a reset.
 207  **/
 208 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
 209 {
 210         s32 status;
 211         u32 ctrl, i;
 212
 213         DEBUGFUNC("ixgbe_reset_hw_X540");
 214
 215         /* Call adapter stop to disable tx/rx and clear interrupts */
 216         status = hw->mac.ops.stop_adapter(hw);
 217         if (status != IXGBE_SUCCESS)
 218                 goto reset_hw_out;
 219
 220         /* flush pending Tx transactions */
 221         ixgbe_clear_tx_pending(hw);
 222
 223 mac_reset_top:
 224         ctrl = IXGBE_CTRL_RST;
 225         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 226         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 227         IXGBE_WRITE_FLUSH(hw);
 228
 229         /* Poll for reset bit to self-clear indicating reset is complete */
 230         for (i = 0; i < 10; i++) {
 231                 usec_delay(1);
 232                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 233                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 234                         break;
 235         }
 236
 237         if (ctrl & IXGBE_CTRL_RST_MASK) {
 238                 status = IXGBE_ERR_RESET_FAILED;
 239                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 240                              "Reset polling failed to complete.\n");
 241         }
 242         msec_delay(100);
 243
 244         /*
 245          * Double resets are required for recovery from certain error
 246          * conditions.  Between resets, it is necessary to stall to allow time
 247          * for any pending HW events to complete.
 248          */
 249         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 250                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 251                 goto mac_reset_top;
 252         }
 253
 254         /* Set the Rx packet buffer size. */
 255         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 256
 257         /* Store the permanent mac address */
 258         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 259
 260         /*
 261          * Store MAC address from RAR0, clear receive address registers, and
 262          * clear the multicast table.  Also reset num_rar_entries to 128,
 263          * since we modify this value when programming the SAN MAC address.
 264          */
 265         hw->mac.num_rar_entries = 128;
 266         hw->mac.ops.init_rx_addrs(hw);
 267
 268         /* Store the permanent SAN mac address */
 269         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 270
 271         /* Add the SAN MAC address to the RAR only if it's a valid address */
 272         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 273                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 274                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 275
 276                 /* Save the SAN MAC RAR index */
 277                 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 278
 279                 /* Reserve the last RAR for the SAN MAC address */
 280                 hw->mac.num_rar_entries--;
 281         }
 282
 283         /* Store the alternative WWNN/WWPN prefix */
 284         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 285                                    &hw->mac.wwpn_prefix);
 286
 287 reset_hw_out:
 288         return status;
 289 }
 290
 291 /**
 292  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 293  *  @hw: pointer to hardware structure
 294  *
 295  *  Starts the hardware using the generic start_hw function
 296  *  and the generation start_hw function.
 297  *  Then performs revision-specific operations, if any.
 298  **/
 299 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 300 {
 301         s32 ret_val = IXGBE_SUCCESS;
 302
 303         DEBUGFUNC("ixgbe_start_hw_X540");
 304
 305         ret_val = ixgbe_start_hw_generic(hw);
 306         if (ret_val != IXGBE_SUCCESS)
 307                 goto out;
 308
 309         ret_val = ixgbe_start_hw_gen2(hw);
 310
 311 out:
 312         return ret_val;
 313 }
 314
 315 /**
 316  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 317  *  @hw: pointer to hardware structure
 318  *
 319  *  Determines physical layer capabilities of the current configuration.
 320  **/
 321 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 322 {
 323         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 324         u16 ext_ability = 0;
 325
 326         DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
 327
 328         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 329         IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 330         if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 331                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 332         if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
 333                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 334         if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 335                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 336
 337         return physical_layer;
 338 }
 339
 340 /**
 341  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 342  *  @hw: pointer to hardware structure
 343  *
 344  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 345  *  ixgbe_hw struct in order to set up EEPROM access.
 346  **/
 347 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 348 {
 349         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 350         u32 eec;
 351         u16 eeprom_size;
 352
 353         DEBUGFUNC("ixgbe_init_eeprom_params_X540");
 354
 355         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 356                 eeprom->semaphore_delay = 10;
 357                 eeprom->type = ixgbe_flash;
 358
 359                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 360                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 361                                     IXGBE_EEC_SIZE_SHIFT);
 362                 eeprom->word_size = 1 << (eeprom_size +
 363                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 364
 365                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 366                           eeprom->type, eeprom->word_size);
 367         }
 368
 369         return IXGBE_SUCCESS;
 370 }
 371
 372 /**
 373  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 374  *  @hw: pointer to hardware structure
 375  *  @offset: offset of  word in the EEPROM to read
 376  *  @data: word read from the EEPROM
 377  *
 378  *  Reads a 16 bit word from the EEPROM using the EERD register.
 379  **/
 380 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 381 {
 382         s32 status = IXGBE_SUCCESS;
 383
 384         DEBUGFUNC("ixgbe_read_eerd_X540");
 385         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 386             IXGBE_SUCCESS)
 387                 status = ixgbe_read_eerd_generic(hw, offset, data);
 388         else
 389                 status = IXGBE_ERR_SWFW_SYNC;
 390
 391         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 392         return status;
 393 }
 394
 395 /**
 396  *  ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
 397  *  @hw: pointer to hardware structure
 398  *  @offset: offset of  word in the EEPROM to read
 399  *  @words: number of words
 400  *  @data: word(s) read from the EEPROM
 401  *
 402  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 403  **/
 404 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 405                                 u16 offset, u16 words, u16 *data)
 406 {
 407         s32 status = IXGBE_SUCCESS;
 408
 409         DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
 410         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 411             IXGBE_SUCCESS)
 412                 status = ixgbe_read_eerd_buffer_generic(hw, offset,
 413                                                         words, data);
 414         else
 415                 status = IXGBE_ERR_SWFW_SYNC;
 416
 417         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 418         return status;
 419 }
 420
 421 /**
 422  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 423  *  @hw: pointer to hardware structure
 424  *  @offset: offset of  word in the EEPROM to write
 425  *  @data: word write to the EEPROM
 426  *
 427  *  Write a 16 bit word to the EEPROM using the EEWR register.
 428  **/
 429 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 430 {
 431         s32 status = IXGBE_SUCCESS;
 432
 433         DEBUGFUNC("ixgbe_write_eewr_X540");
 434         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 435             IXGBE_SUCCESS)
 436                 status = ixgbe_write_eewr_generic(hw, offset, data);
 437         else
 438                 status = IXGBE_ERR_SWFW_SYNC;
 439
 440         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 441         return status;
 442 }
 443
 444 /**
 445  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 446  *  @hw: pointer to hardware structure
 447  *  @offset: offset of  word in the EEPROM to write
 448  *  @words: number of words
 449  *  @data: word(s) write to the EEPROM
 450  *
 451  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 452  **/
 453 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 454                                  u16 offset, u16 words, u16 *data)
 455 {
 456         s32 status = IXGBE_SUCCESS;
 457
 458         DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
 459         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 460             IXGBE_SUCCESS)
 461                 status = ixgbe_write_eewr_buffer_generic(hw, offset,
 462                                                          words, data);
 463         else
 464                 status = IXGBE_ERR_SWFW_SYNC;
 465
 466         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 467         return status;
 468 }
 469
 470 /**
 471  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 472  *
 473  *  This function does not use synchronization for EERD and EEWR. It can
 474  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 475  *
 476  *  @hw: pointer to hardware structure
 477  **/
 478 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 479 {
 480         u16 i;
 481         u16 j;
 482         u16 checksum = 0;
 483         u16 length = 0;
 484         u16 pointer = 0;
 485         u16 word = 0;
 486
 487         /*
 488          * Do not use hw->eeprom.ops.read because we do not want to take
 489          * the synchronization semaphores here. Instead use
 490          * ixgbe_read_eerd_generic
 491          */
 492
 493         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
 494
 495         /* Include 0x0-0x3F in the checksum */
 496         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 497                 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
 498                         DEBUGOUT("EEPROM read failed\n");
 499                         break;
 500                 }
 501                 checksum += word;
 502         }
 503
 504         /*
 505          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 506          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 507          */
 508         for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
 509                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 510                         continue;
 511
 512                 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
 513                         DEBUGOUT("EEPROM read failed\n");
 514                         break;
 515                 }
 516
 517                 /* Skip pointer section if the pointer is invalid. */
 518                 if (pointer == 0xFFFF || pointer == 0 ||
 519                     pointer >= hw->eeprom.word_size)
 520                         continue;
 521
 522                 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
 523                     IXGBE_SUCCESS) {
 524                         DEBUGOUT("EEPROM read failed\n");
 525                         break;
 526                 }
 527
 528                 /* Skip pointer section if length is invalid. */
 529                 if (length == 0xFFFF || length == 0 ||
 530                     (pointer + length) >= hw->eeprom.word_size)
 531                         continue;
 532
 533                 for (j = pointer+1; j <= pointer+length; j++) {
 534                         if (ixgbe_read_eerd_generic(hw, j, &word) !=
 535                             IXGBE_SUCCESS) {
 536                                 DEBUGOUT("EEPROM read failed\n");
 537                                 break;
 538                         }
 539                         checksum += word;
 540                 }
 541         }
 542
 543         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 544
 545         return checksum;
 546 }
 547
 548 /**
 549  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 550  *  @hw: pointer to hardware structure
 551  *  @checksum_val: calculated checksum
 552  *
 553  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 554  *  caller does not need checksum_val, the value can be NULL.
 555  **/
 556 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 557                                         u16 *checksum_val)
 558 {
 559         s32 status;
 560         u16 checksum;
 561         u16 read_checksum = 0;
 562
 563         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
 564
 565         /*
 566          * Read the first word from the EEPROM. If this times out or fails, do
 567          * not continue or we could be in for a very long wait while every
 568          * EEPROM read fails
 569          */
 570         status = hw->eeprom.ops.read(hw, 0, &checksum);
 571
 572         if (status != IXGBE_SUCCESS) {
 573                 DEBUGOUT("EEPROM read failed\n");
 574                 goto out;
 575         }
 576
 577         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 578             IXGBE_SUCCESS) {
 579                 checksum = hw->eeprom.ops.calc_checksum(hw);
 580
 581                 /*
 582                  * Do not use hw->eeprom.ops.read because we do not want to take
 583                  * the synchronization semaphores twice here.
 584                 */
 585                 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 586                                         &read_checksum);
 587
 588                 /*
 589                  * Verify read checksum from EEPROM is the same as
 590                  * calculated checksum
 591                  */
 592                 if (read_checksum != checksum) {
 593                         status = IXGBE_ERR_EEPROM_CHECKSUM;
 594                         ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 595                                      "Invalid EEPROM checksum");
 596                 }
 597
 598                 /* If the user cares, return the calculated checksum */
 599                 if (checksum_val)
 600                         *checksum_val = checksum;
 601         } else {
 602                 status = IXGBE_ERR_SWFW_SYNC;
 603         }
 604
 605         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 606 out:
 607         return status;
 608 }
 609
 610 /**
 611  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 612  * @hw: pointer to hardware structure
 613  *
 614  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 615  * checksum and updates the EEPROM and instructs the hardware to update
 616  * the flash.
 617  **/
 618 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 619 {
 620         s32 status;
 621         u16 checksum;
 622
 623         DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
 624
 625         /*
 626          * Read the first word from the EEPROM. If this times out or fails, do
 627          * not continue or we could be in for a very long wait while every
 628          * EEPROM read fails
 629          */
 630         status = hw->eeprom.ops.read(hw, 0, &checksum);
 631
 632         if (status != IXGBE_SUCCESS)
 633                 DEBUGOUT("EEPROM read failed\n");
 634
 635         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 636             IXGBE_SUCCESS) {
 637                 checksum = hw->eeprom.ops.calc_checksum(hw);
 638
 639                 /*
 640                  * Do not use hw->eeprom.ops.write because we do not want to
 641                  * take the synchronization semaphores twice here.
 642                 */
 643                 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
 644                                                   checksum);
 645
 646         if (status == IXGBE_SUCCESS)
 647                 status = ixgbe_update_flash_X540(hw);
 648         else
 649                 status = IXGBE_ERR_SWFW_SYNC;
 650         }
 651
 652         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 653
 654         return status;
 655 }
 656
 657 /**
 658  *  ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 659  *  @hw: pointer to hardware structure
 660  *
 661  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 662  *  EEPROM from shadow RAM to the flash device.
 663  **/
 664 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 665 {
 666         u32 flup;
 667         s32 status;
 668
 669         DEBUGFUNC("ixgbe_update_flash_X540");
 670
 671         status = ixgbe_poll_flash_update_done_X540(hw);
 672         if (status == IXGBE_ERR_EEPROM) {
 673                 DEBUGOUT("Flash update time out\n");
 674                 goto out;
 675         }
 676
 677         flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
 678         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 679
 680         status = ixgbe_poll_flash_update_done_X540(hw);
 681         if (status == IXGBE_SUCCESS)
 682                 DEBUGOUT("Flash update complete\n");
 683         else
 684                 DEBUGOUT("Flash update time out\n");
 685
 686         if (hw->revision_id == 0) {
 687                 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 688
 689                 if (flup & IXGBE_EEC_SEC1VAL) {
 690                         flup |= IXGBE_EEC_FLUP;
 691                         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 692                 }
 693
 694                 status = ixgbe_poll_flash_update_done_X540(hw);
 695                 if (status == IXGBE_SUCCESS)
 696                         DEBUGOUT("Flash update complete\n");
 697                 else
 698                         DEBUGOUT("Flash update time out\n");
 699         }
 700 out:
 701         return status;
 702 }
 703
 704 /**
 705  *  ixgbe_poll_flash_update_done_X540 - Poll flash update status
 706  *  @hw: pointer to hardware structure
 707  *
 708  *  Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 709  *  flash update is done.
 710  **/
 711 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 712 {
 713         u32 i;
 714         u32 reg;
 715         s32 status = IXGBE_ERR_EEPROM;
 716
 717         DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
 718
 719         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 720                 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
 721                 if (reg & IXGBE_EEC_FLUDONE) {
 722                         status = IXGBE_SUCCESS;
 723                         break;
 724                 }
 725                 usec_delay(5);
 726         }
 727
 728         if (i == IXGBE_FLUDONE_ATTEMPTS)
 729                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 730                              "Flash update status polling timed out");
 731
 732         return status;
 733 }
 734
 735 /**
 736  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 737  *  @hw: pointer to hardware structure
 738  *  @mask: Mask to specify which semaphore to acquire
 739  *
 740  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 741  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
 742  **/
 743 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 744 {
 745         u32 swfw_sync;
 746         u32 swmask = mask;
 747         u32 fwmask = mask << 5;
 748         u32 hwmask = 0;
 749         u32 timeout = 200;
 750         u32 i;
 751         s32 ret_val = IXGBE_SUCCESS;
 752
 753         DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
 754
 755         if (swmask == IXGBE_GSSR_EEP_SM)
 756                 hwmask = IXGBE_GSSR_FLASH_SM;
 757
 758         /* SW only mask doesn't have FW bit pair */
 759         if (swmask == IXGBE_GSSR_SW_MNG_SM)
 760                 fwmask = 0;
 761
 762         for (i = 0; i < timeout; i++) {
 763                 /*
 764                  * SW NVM semaphore bit is used for access to all
 765                  * SW_FW_SYNC bits (not just NVM)
 766                  */
 767                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 768                         ret_val = IXGBE_ERR_SWFW_SYNC;
 769                         goto out;
 770                 }
 771
 772                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 773                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 774                         swfw_sync |= swmask;
 775                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 776                         ixgbe_release_swfw_sync_semaphore(hw);
 777                         msec_delay(5);
 778                         goto out;
 779                 } else {
 780                         /*
 781                          * Firmware currently using resource (fwmask), hardware
 782                          * currently using resource (hwmask), or other software
 783                          * thread currently using resource (swmask)
 784                          */
 785                         ixgbe_release_swfw_sync_semaphore(hw);
 786                         msec_delay(5);
 787                 }
 788         }
 789
 790         /* Failed to get SW only semaphore */
 791         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 792                 ret_val = IXGBE_ERR_SWFW_SYNC;
 793                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 794                              "Failed to get SW only semaphore");
 795                 goto out;
 796         }
 797
 798         /* If the resource is not released by the FW/HW the SW can assume that
 799          * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
 800          * of the requested resource(s) while ignoring the corresponding FW/HW
 801          * bits in the SW_FW_SYNC register.
 802          */
 803         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 804         if (swfw_sync & (fwmask | hwmask)) {
 805                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 806                         ret_val = IXGBE_ERR_SWFW_SYNC;
 807                         goto out;
 808                 }
 809
 810                 swfw_sync |= swmask;
 811                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 812                 ixgbe_release_swfw_sync_semaphore(hw);
 813                 msec_delay(5);
 814         }
 815
 816 out:
 817         return ret_val;
 818 }
 819
 820 /**
 821  *  ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 822  *  @hw: pointer to hardware structure
 823  *  @mask: Mask to specify which semaphore to release
 824  *
 825  *  Releases the SWFW semaphore through the SW_FW_SYNC register
 826  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 827  **/
 828 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 829 {
 830         u32 swfw_sync;
 831         u32 swmask = mask;
 832
 833         DEBUGFUNC("ixgbe_release_swfw_sync_X540");
 834
 835         ixgbe_get_swfw_sync_semaphore(hw);
 836
 837         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 838         swfw_sync &= ~swmask;
 839         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 840
 841         ixgbe_release_swfw_sync_semaphore(hw);
 842         msec_delay(5);
 843 }
 844
 845 /**
 846  *  ixgbe_get_nvm_semaphore - Get hardware semaphore
 847  *  @hw: pointer to hardware structure
 848  *
 849  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
 850  **/
 851 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 852 {
 853         s32 status = IXGBE_ERR_EEPROM;
 854         u32 timeout = 2000;
 855         u32 i;
 856         u32 swsm;
 857
 858         DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
 859
 860         /* Get SMBI software semaphore between device drivers first */
 861         for (i = 0; i < timeout; i++) {
 862                 /*
 863                  * If the SMBI bit is 0 when we read it, then the bit will be
 864                  * set and we have the semaphore
 865                  */
 866                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 867                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 868                         status = IXGBE_SUCCESS;
 869                         break;
 870                 }
 871                 usec_delay(50);
 872         }
 873
 874         /* Now get the semaphore between SW/FW through the REGSMP bit */
 875         if (status == IXGBE_SUCCESS) {
 876                 for (i = 0; i < timeout; i++) {
 877                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 878                         if (!(swsm & IXGBE_SWFW_REGSMP))
 879                                 break;
 880
 881                         usec_delay(50);
 882                 }
 883
 884                 /*
 885                  * Release semaphores and return error if SW NVM semaphore
 886                  * was not granted because we don't have access to the EEPROM
 887                  */
 888                 if (i >= timeout) {
 889                         ERROR_REPORT1(IXGBE_ERROR_POLLING,
 890                                 "REGSMP Software NVM semaphore not granted.\n");
 891                         ixgbe_release_swfw_sync_semaphore(hw);
 892                         status = IXGBE_ERR_EEPROM;
 893                 }
 894         } else {
 895                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 896                              "Software semaphore SMBI between device drivers "
 897                              "not granted.\n");
 898         }
 899
 900         return status;
 901 }
 902
 903 /**
 904  *  ixgbe_release_nvm_semaphore - Release hardware semaphore
 905  *  @hw: pointer to hardware structure
 906  *
 907  *  This function clears hardware semaphore bits.
 908  **/
 909 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 910 {
 911         u32 swsm;
 912
 913         DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
 914
 915         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 916
 917         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 918         swsm &= ~IXGBE_SWSM_SMBI;
 919         IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 920
 921         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 922         swsm &= ~IXGBE_SWFW_REGSMP;
 923         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 924
 925         IXGBE_WRITE_FLUSH(hw);
 926 }
 927
 928 /**
 929  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 930  * @hw: pointer to hardware structure
 931  * @index: led number to blink
 932  *
 933  * Devices that implement the version 2 interface:
 934  *   X540
 935  **/
 936 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 937 {
 938         u32 macc_reg;
 939         u32 ledctl_reg;
 940         ixgbe_link_speed speed;
 941         bool link_up;
 942
 943         DEBUGFUNC("ixgbe_blink_led_start_X540");
 944
 945         /*
 946          * Link should be up in order for the blink bit in the LED control
 947          * register to work. Force link and speed in the MAC if link is down.
 948          * This will be reversed when we stop the blinking.
 949          */
 950         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 951         if (link_up == false) {
 952                 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 953                 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 954                 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 955         }
 956         /* Set the LED to LINK_UP + BLINK. */
 957         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 958         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 959         ledctl_reg |= IXGBE_LED_BLINK(index);
 960         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 961         IXGBE_WRITE_FLUSH(hw);
 962
 963         return IXGBE_SUCCESS;
 964 }
 965
 966 /**
 967  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 968  * @hw: pointer to hardware structure
 969  * @index: led number to stop blinking
 970  *
 971  * Devices that implement the version 2 interface:
 972  *   X540
 973  **/
 974 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 975 {
 976         u32 macc_reg;
 977         u32 ledctl_reg;
 978
 979         DEBUGFUNC("ixgbe_blink_led_stop_X540");
 980
 981         /* Restore the LED to its default value. */
 982         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 983         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 984         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 985         ledctl_reg &= ~IXGBE_LED_BLINK(index);
 986         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 987
 988         /* Unforce link and speed in the MAC. */
 989         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 990         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
 991         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 992         IXGBE_WRITE_FLUSH(hw);
 993
 994         return IXGBE_SUCCESS;
 995 }
 996
 997