1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x540.h"
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
42 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
43 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
46 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
47 * @hw: pointer to hardware structure
49 * Initialize the function pointers and assign the MAC type for X540.
50 * Does not touch the hardware.
52 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_phy_info *phy = &hw->phy;
56 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
59 DEBUGFUNC("ixgbe_init_ops_X540");
61 ret_val = ixgbe_init_phy_ops_generic(hw);
62 ret_val = ixgbe_init_ops_generic(hw);
66 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
67 eeprom->ops.read = &ixgbe_read_eerd_X540;
68 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
69 eeprom->ops.write = &ixgbe_write_eewr_X540;
70 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
71 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
72 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
73 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
76 phy->ops.init = &ixgbe_init_phy_ops_generic;
77 phy->ops.reset = NULL;
80 mac->ops.reset_hw = &ixgbe_reset_hw_X540;
81 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
82 mac->ops.get_media_type = &ixgbe_get_media_type_X540;
83 mac->ops.get_supported_physical_layer =
84 &ixgbe_get_supported_physical_layer_X540;
85 mac->ops.read_analog_reg8 = NULL;
86 mac->ops.write_analog_reg8 = NULL;
87 mac->ops.start_hw = &ixgbe_start_hw_X540;
88 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
89 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
90 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
91 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
92 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
93 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
94 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
95 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
96 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
98 /* RAR, Multicast, VLAN */
99 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
100 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
101 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
102 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
103 mac->rar_highwater = 1;
104 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
105 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
106 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
107 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
108 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
109 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
112 mac->ops.get_link_capabilities =
113 &ixgbe_get_copper_link_capabilities_generic;
114 mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
115 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
116 mac->ops.check_link = &ixgbe_check_mac_link_generic;
119 mac->mcft_size = 128;
121 mac->num_rar_entries = 128;
122 mac->rx_pb_size = 384;
123 mac->max_tx_queues = 128;
124 mac->max_rx_queues = 128;
125 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
129 * ARC supported; valid only if manageability features are
132 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
133 IXGBE_FWSM_MODE_MASK) ? true : false;
135 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
138 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
139 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
141 /* Manageability interface */
142 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
148 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
149 * @hw: pointer to hardware structure
150 * @speed: pointer to link speed
151 * @autoneg: true when autoneg or autotry is enabled
153 * Determines the link capabilities by reading the AUTOC register.
155 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
156 ixgbe_link_speed *speed,
159 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
161 return IXGBE_SUCCESS;
165 * ixgbe_get_media_type_X540 - Get media type
166 * @hw: pointer to hardware structure
168 * Returns the media type (fiber, copper, backplane)
170 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
172 UNREFERENCED_1PARAMETER(hw);
173 return ixgbe_media_type_copper;
177 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
178 * @hw: pointer to hardware structure
179 * @speed: new link speed
180 * @autoneg: true if autonegotiation enabled
181 * @autoneg_wait_to_complete: true when waiting for completion is needed
183 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
184 ixgbe_link_speed speed, bool autoneg,
185 bool autoneg_wait_to_complete)
187 DEBUGFUNC("ixgbe_setup_mac_link_X540");
188 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
189 autoneg_wait_to_complete);
193 * ixgbe_reset_hw_X540 - Perform hardware reset
194 * @hw: pointer to hardware structure
196 * Resets the hardware by resetting the transmit and receive units, masks
197 * and clears all interrupts, and perform a reset.
199 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
204 DEBUGFUNC("ixgbe_reset_hw_X540");
206 /* Call adapter stop to disable tx/rx and clear interrupts */
207 status = hw->mac.ops.stop_adapter(hw);
208 if (status != IXGBE_SUCCESS)
211 /* flush pending Tx transactions */
212 ixgbe_clear_tx_pending(hw);
215 ctrl = IXGBE_CTRL_RST;
216 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
217 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
218 IXGBE_WRITE_FLUSH(hw);
220 /* Poll for reset bit to self-clear indicating reset is complete */
221 for (i = 0; i < 10; i++) {
223 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
224 if (!(ctrl & IXGBE_CTRL_RST_MASK))
228 if (ctrl & IXGBE_CTRL_RST_MASK) {
229 status = IXGBE_ERR_RESET_FAILED;
230 DEBUGOUT("Reset polling failed to complete.\n");
235 * Double resets are required for recovery from certain error
236 * conditions. Between resets, it is necessary to stall to allow time
237 * for any pending HW events to complete.
239 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
240 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
244 /* Set the Rx packet buffer size. */
245 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
247 /* Store the permanent mac address */
248 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
251 * Store MAC address from RAR0, clear receive address registers, and
252 * clear the multicast table. Also reset num_rar_entries to 128,
253 * since we modify this value when programming the SAN MAC address.
255 hw->mac.num_rar_entries = 128;
256 hw->mac.ops.init_rx_addrs(hw);
258 /* Store the permanent SAN mac address */
259 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
261 /* Add the SAN MAC address to the RAR only if it's a valid address */
262 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
263 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
264 hw->mac.san_addr, 0, IXGBE_RAH_AV);
266 /* Save the SAN MAC RAR index */
267 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
269 /* Reserve the last RAR for the SAN MAC address */
270 hw->mac.num_rar_entries--;
273 /* Store the alternative WWNN/WWPN prefix */
274 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
275 &hw->mac.wwpn_prefix);
282 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
283 * @hw: pointer to hardware structure
285 * Starts the hardware using the generic start_hw function
286 * and the generation start_hw function.
287 * Then performs revision-specific operations, if any.
289 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
291 s32 ret_val = IXGBE_SUCCESS;
293 DEBUGFUNC("ixgbe_start_hw_X540");
295 ret_val = ixgbe_start_hw_generic(hw);
296 if (ret_val != IXGBE_SUCCESS)
299 ret_val = ixgbe_start_hw_gen2(hw);
306 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
307 * @hw: pointer to hardware structure
309 * Determines physical layer capabilities of the current configuration.
311 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
313 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
316 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
318 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
319 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
320 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
321 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
322 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
323 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
324 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
325 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
327 return physical_layer;
331 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
332 * @hw: pointer to hardware structure
334 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
335 * ixgbe_hw struct in order to set up EEPROM access.
337 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
339 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
343 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
345 if (eeprom->type == ixgbe_eeprom_uninitialized) {
346 eeprom->semaphore_delay = 10;
347 eeprom->type = ixgbe_flash;
349 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
350 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
351 IXGBE_EEC_SIZE_SHIFT);
352 eeprom->word_size = 1 << (eeprom_size +
353 IXGBE_EEPROM_WORD_SIZE_SHIFT);
355 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
356 eeprom->type, eeprom->word_size);
359 return IXGBE_SUCCESS;
363 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
364 * @hw: pointer to hardware structure
365 * @offset: offset of word in the EEPROM to read
366 * @data: word read from the EEPROM
368 * Reads a 16 bit word from the EEPROM using the EERD register.
370 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
372 s32 status = IXGBE_SUCCESS;
374 DEBUGFUNC("ixgbe_read_eerd_X540");
375 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
377 status = ixgbe_read_eerd_generic(hw, offset, data);
379 status = IXGBE_ERR_SWFW_SYNC;
381 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
386 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
387 * @hw: pointer to hardware structure
388 * @offset: offset of word in the EEPROM to read
389 * @words: number of words
390 * @data: word(s) read from the EEPROM
392 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
394 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
395 u16 offset, u16 words, u16 *data)
397 s32 status = IXGBE_SUCCESS;
399 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
400 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
402 status = ixgbe_read_eerd_buffer_generic(hw, offset,
405 status = IXGBE_ERR_SWFW_SYNC;
407 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
412 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
413 * @hw: pointer to hardware structure
414 * @offset: offset of word in the EEPROM to write
415 * @data: word write to the EEPROM
417 * Write a 16 bit word to the EEPROM using the EEWR register.
419 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
421 s32 status = IXGBE_SUCCESS;
423 DEBUGFUNC("ixgbe_write_eewr_X540");
424 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
426 status = ixgbe_write_eewr_generic(hw, offset, data);
428 status = IXGBE_ERR_SWFW_SYNC;
430 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
435 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
436 * @hw: pointer to hardware structure
437 * @offset: offset of word in the EEPROM to write
438 * @words: number of words
439 * @data: word(s) write to the EEPROM
441 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
443 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
444 u16 offset, u16 words, u16 *data)
446 s32 status = IXGBE_SUCCESS;
448 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
449 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
451 status = ixgbe_write_eewr_buffer_generic(hw, offset,
454 status = IXGBE_ERR_SWFW_SYNC;
456 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
461 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
463 * This function does not use synchronization for EERD and EEWR. It can
464 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
466 * @hw: pointer to hardware structure
468 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
478 * Do not use hw->eeprom.ops.read because we do not want to take
479 * the synchronization semaphores here. Instead use
480 * ixgbe_read_eerd_generic
483 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
485 /* Include 0x0-0x3F in the checksum */
486 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
487 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
488 DEBUGOUT("EEPROM read failed\n");
495 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
496 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
498 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
499 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
502 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
503 DEBUGOUT("EEPROM read failed\n");
507 /* Skip pointer section if the pointer is invalid. */
508 if (pointer == 0xFFFF || pointer == 0 ||
509 pointer >= hw->eeprom.word_size)
512 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
514 DEBUGOUT("EEPROM read failed\n");
518 /* Skip pointer section if length is invalid. */
519 if (length == 0xFFFF || length == 0 ||
520 (pointer + length) >= hw->eeprom.word_size)
523 for (j = pointer+1; j <= pointer+length; j++) {
524 if (ixgbe_read_eerd_generic(hw, j, &word) !=
526 DEBUGOUT("EEPROM read failed\n");
533 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
539 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
540 * @hw: pointer to hardware structure
541 * @checksum_val: calculated checksum
543 * Performs checksum calculation and validates the EEPROM checksum. If the
544 * caller does not need checksum_val, the value can be NULL.
546 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
551 u16 read_checksum = 0;
553 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
556 * Read the first word from the EEPROM. If this times out or fails, do
557 * not continue or we could be in for a very long wait while every
560 status = hw->eeprom.ops.read(hw, 0, &checksum);
562 if (status != IXGBE_SUCCESS) {
563 DEBUGOUT("EEPROM read failed\n");
567 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
569 checksum = hw->eeprom.ops.calc_checksum(hw);
572 * Do not use hw->eeprom.ops.read because we do not want to take
573 * the synchronization semaphores twice here.
575 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
579 * Verify read checksum from EEPROM is the same as
580 * calculated checksum
582 if (read_checksum != checksum)
583 status = IXGBE_ERR_EEPROM_CHECKSUM;
585 /* If the user cares, return the calculated checksum */
587 *checksum_val = checksum;
589 status = IXGBE_ERR_SWFW_SYNC;
592 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
598 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
599 * @hw: pointer to hardware structure
601 * After writing EEPROM to shadow RAM using EEWR register, software calculates
602 * checksum and updates the EEPROM and instructs the hardware to update
605 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
610 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
613 * Read the first word from the EEPROM. If this times out or fails, do
614 * not continue or we could be in for a very long wait while every
617 status = hw->eeprom.ops.read(hw, 0, &checksum);
619 if (status != IXGBE_SUCCESS)
620 DEBUGOUT("EEPROM read failed\n");
622 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
624 checksum = hw->eeprom.ops.calc_checksum(hw);
627 * Do not use hw->eeprom.ops.write because we do not want to
628 * take the synchronization semaphores twice here.
630 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
633 if (status == IXGBE_SUCCESS)
634 status = ixgbe_update_flash_X540(hw);
636 status = IXGBE_ERR_SWFW_SYNC;
639 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
645 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
646 * @hw: pointer to hardware structure
648 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
649 * EEPROM from shadow RAM to the flash device.
651 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
656 DEBUGFUNC("ixgbe_update_flash_X540");
658 status = ixgbe_poll_flash_update_done_X540(hw);
659 if (status == IXGBE_ERR_EEPROM) {
660 DEBUGOUT("Flash update time out\n");
664 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
665 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
667 status = ixgbe_poll_flash_update_done_X540(hw);
668 if (status == IXGBE_SUCCESS)
669 DEBUGOUT("Flash update complete\n");
671 DEBUGOUT("Flash update time out\n");
673 if (hw->revision_id == 0) {
674 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
676 if (flup & IXGBE_EEC_SEC1VAL) {
677 flup |= IXGBE_EEC_FLUP;
678 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
681 status = ixgbe_poll_flash_update_done_X540(hw);
682 if (status == IXGBE_SUCCESS)
683 DEBUGOUT("Flash update complete\n");
685 DEBUGOUT("Flash update time out\n");
692 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
693 * @hw: pointer to hardware structure
695 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
696 * flash update is done.
698 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
702 s32 status = IXGBE_ERR_EEPROM;
704 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
706 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
707 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
708 if (reg & IXGBE_EEC_FLUDONE) {
709 status = IXGBE_SUCCESS;
718 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
719 * @hw: pointer to hardware structure
720 * @mask: Mask to specify which semaphore to acquire
722 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
723 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
725 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
729 u32 fwmask = mask << 5;
733 s32 ret_val = IXGBE_SUCCESS;
735 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
737 if (swmask == IXGBE_GSSR_EEP_SM)
738 hwmask = IXGBE_GSSR_FLASH_SM;
740 /* SW only mask doesn't have FW bit pair */
741 if (swmask == IXGBE_GSSR_SW_MNG_SM)
744 for (i = 0; i < timeout; i++) {
746 * SW NVM semaphore bit is used for access to all
747 * SW_FW_SYNC bits (not just NVM)
749 if (ixgbe_get_swfw_sync_semaphore(hw)) {
750 ret_val = IXGBE_ERR_SWFW_SYNC;
754 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
755 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
757 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
758 ixgbe_release_swfw_sync_semaphore(hw);
763 * Firmware currently using resource (fwmask), hardware
764 * currently using resource (hwmask), or other software
765 * thread currently using resource (swmask)
767 ixgbe_release_swfw_sync_semaphore(hw);
772 /* Failed to get SW only semaphore */
773 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
774 ret_val = IXGBE_ERR_SWFW_SYNC;
778 /* If the resource is not released by the FW/HW the SW can assume that
779 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
780 * of the requested resource(s) while ignoring the corresponding FW/HW
781 * bits in the SW_FW_SYNC register.
783 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
784 if (swfw_sync & (fwmask | hwmask)) {
785 if (ixgbe_get_swfw_sync_semaphore(hw)) {
786 ret_val = IXGBE_ERR_SWFW_SYNC;
791 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
792 ixgbe_release_swfw_sync_semaphore(hw);
801 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
802 * @hw: pointer to hardware structure
803 * @mask: Mask to specify which semaphore to release
805 * Releases the SWFW semaphore through the SW_FW_SYNC register
806 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
808 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
813 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
815 ixgbe_get_swfw_sync_semaphore(hw);
817 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
818 swfw_sync &= ~swmask;
819 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
821 ixgbe_release_swfw_sync_semaphore(hw);
826 * ixgbe_get_nvm_semaphore - Get hardware semaphore
827 * @hw: pointer to hardware structure
829 * Sets the hardware semaphores so SW/FW can gain control of shared resources
831 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
833 s32 status = IXGBE_ERR_EEPROM;
838 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
840 /* Get SMBI software semaphore between device drivers first */
841 for (i = 0; i < timeout; i++) {
843 * If the SMBI bit is 0 when we read it, then the bit will be
844 * set and we have the semaphore
846 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
847 if (!(swsm & IXGBE_SWSM_SMBI)) {
848 status = IXGBE_SUCCESS;
854 /* Now get the semaphore between SW/FW through the REGSMP bit */
855 if (status == IXGBE_SUCCESS) {
856 for (i = 0; i < timeout; i++) {
857 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
858 if (!(swsm & IXGBE_SWFW_REGSMP))
865 * Release semaphores and return error if SW NVM semaphore
866 * was not granted because we don't have access to the EEPROM
869 DEBUGOUT("REGSMP Software NVM semaphore not "
871 ixgbe_release_swfw_sync_semaphore(hw);
872 status = IXGBE_ERR_EEPROM;
875 DEBUGOUT("Software semaphore SMBI between device drivers "
883 * ixgbe_release_nvm_semaphore - Release hardware semaphore
884 * @hw: pointer to hardware structure
886 * This function clears hardware semaphore bits.
888 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
892 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
894 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
896 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
897 swsm &= ~IXGBE_SWSM_SMBI;
898 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
900 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
901 swsm &= ~IXGBE_SWFW_REGSMP;
902 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
904 IXGBE_WRITE_FLUSH(hw);
908 * ixgbe_blink_led_start_X540 - Blink LED based on index.
909 * @hw: pointer to hardware structure
910 * @index: led number to blink
912 * Devices that implement the version 2 interface:
915 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
919 ixgbe_link_speed speed;
922 DEBUGFUNC("ixgbe_blink_led_start_X540");
925 * Link should be up in order for the blink bit in the LED control
926 * register to work. Force link and speed in the MAC if link is down.
927 * This will be reversed when we stop the blinking.
929 hw->mac.ops.check_link(hw, &speed, &link_up, false);
930 if (link_up == false) {
931 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
932 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
933 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
935 /* Set the LED to LINK_UP + BLINK. */
936 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
937 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
938 ledctl_reg |= IXGBE_LED_BLINK(index);
939 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
940 IXGBE_WRITE_FLUSH(hw);
942 return IXGBE_SUCCESS;
946 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
947 * @hw: pointer to hardware structure
948 * @index: led number to stop blinking
950 * Devices that implement the version 2 interface:
953 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
958 DEBUGFUNC("ixgbe_blink_led_stop_X540");
960 /* Restore the LED to its default value. */
961 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
962 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
963 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
964 ledctl_reg &= ~IXGBE_LED_BLINK(index);
965 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
967 /* Unforce link and speed in the MAC. */
968 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
969 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
970 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
971 IXGBE_WRITE_FLUSH(hw);
973 return IXGBE_SUCCESS;