1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x540.h"
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_X540_MAX_TX_QUEUES 128
41 #define IXGBE_X540_MAX_RX_QUEUES 128
42 #define IXGBE_X540_RAR_ENTRIES 128
43 #define IXGBE_X540_MC_TBL_SIZE 128
44 #define IXGBE_X540_VFT_TBL_SIZE 128
45 #define IXGBE_X540_RX_PB_SIZE 384
47 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
48 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
49 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
50 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
54 * @hw: pointer to hardware structure
56 * Initialize the function pointers and assign the MAC type for X540.
57 * Does not touch the hardware.
59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
61 struct ixgbe_mac_info *mac = &hw->mac;
62 struct ixgbe_phy_info *phy = &hw->phy;
63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
66 DEBUGFUNC("ixgbe_init_ops_X540");
68 ret_val = ixgbe_init_phy_ops_generic(hw);
69 ret_val = ixgbe_init_ops_generic(hw);
73 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
74 eeprom->ops.read = &ixgbe_read_eerd_X540;
75 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
76 eeprom->ops.write = &ixgbe_write_eewr_X540;
77 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
78 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
79 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
80 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
83 phy->ops.init = &ixgbe_init_phy_ops_generic;
84 phy->ops.reset = NULL;
87 mac->ops.reset_hw = &ixgbe_reset_hw_X540;
88 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
89 mac->ops.get_media_type = &ixgbe_get_media_type_X540;
90 mac->ops.get_supported_physical_layer =
91 &ixgbe_get_supported_physical_layer_X540;
92 mac->ops.read_analog_reg8 = NULL;
93 mac->ops.write_analog_reg8 = NULL;
94 mac->ops.start_hw = &ixgbe_start_hw_X540;
95 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
96 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
97 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
98 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
99 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
100 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
101 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
102 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
103 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
105 /* RAR, Multicast, VLAN */
106 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
107 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
108 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
109 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
110 mac->rar_highwater = 1;
111 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
112 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
113 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
114 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
115 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
116 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
119 mac->ops.get_link_capabilities =
120 &ixgbe_get_copper_link_capabilities_generic;
121 mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
122 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
123 mac->ops.check_link = &ixgbe_check_mac_link_generic;
126 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
127 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
128 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
129 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
130 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
131 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
132 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
136 * ARC supported; valid only if manageability features are
139 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
140 IXGBE_FWSM_MODE_MASK) ? true : false;
142 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
145 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
146 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
148 /* Manageability interface */
149 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
151 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
157 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
158 * @hw: pointer to hardware structure
159 * @speed: pointer to link speed
160 * @autoneg: true when autoneg or autotry is enabled
162 * Determines the link capabilities by reading the AUTOC register.
164 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
165 ixgbe_link_speed *speed,
168 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
170 return IXGBE_SUCCESS;
174 * ixgbe_get_media_type_X540 - Get media type
175 * @hw: pointer to hardware structure
177 * Returns the media type (fiber, copper, backplane)
179 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
181 UNREFERENCED_1PARAMETER(hw);
182 return ixgbe_media_type_copper;
186 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
187 * @hw: pointer to hardware structure
188 * @speed: new link speed
189 * @autoneg_wait_to_complete: true when waiting for completion is needed
191 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
192 ixgbe_link_speed speed,
193 bool autoneg_wait_to_complete)
195 DEBUGFUNC("ixgbe_setup_mac_link_X540");
196 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
200 * ixgbe_reset_hw_X540 - Perform hardware reset
201 * @hw: pointer to hardware structure
203 * Resets the hardware by resetting the transmit and receive units, masks
204 * and clears all interrupts, and perform a reset.
206 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
211 DEBUGFUNC("ixgbe_reset_hw_X540");
213 /* Call adapter stop to disable tx/rx and clear interrupts */
214 status = hw->mac.ops.stop_adapter(hw);
215 if (status != IXGBE_SUCCESS)
218 /* flush pending Tx transactions */
219 ixgbe_clear_tx_pending(hw);
222 ctrl = IXGBE_CTRL_RST;
223 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
224 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
225 IXGBE_WRITE_FLUSH(hw);
227 /* Poll for reset bit to self-clear indicating reset is complete */
228 for (i = 0; i < 10; i++) {
230 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
231 if (!(ctrl & IXGBE_CTRL_RST_MASK))
235 if (ctrl & IXGBE_CTRL_RST_MASK) {
236 status = IXGBE_ERR_RESET_FAILED;
237 ERROR_REPORT1(IXGBE_ERROR_POLLING,
238 "Reset polling failed to complete.\n");
243 * Double resets are required for recovery from certain error
244 * conditions. Between resets, it is necessary to stall to allow time
245 * for any pending HW events to complete.
247 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
248 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
252 /* Set the Rx packet buffer size. */
253 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
255 /* Store the permanent mac address */
256 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
259 * Store MAC address from RAR0, clear receive address registers, and
260 * clear the multicast table. Also reset num_rar_entries to 128,
261 * since we modify this value when programming the SAN MAC address.
263 hw->mac.num_rar_entries = 128;
264 hw->mac.ops.init_rx_addrs(hw);
266 /* Store the permanent SAN mac address */
267 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
269 /* Add the SAN MAC address to the RAR only if it's a valid address */
270 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
271 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
272 hw->mac.san_addr, 0, IXGBE_RAH_AV);
274 /* Save the SAN MAC RAR index */
275 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
277 /* Reserve the last RAR for the SAN MAC address */
278 hw->mac.num_rar_entries--;
281 /* Store the alternative WWNN/WWPN prefix */
282 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
283 &hw->mac.wwpn_prefix);
290 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
291 * @hw: pointer to hardware structure
293 * Starts the hardware using the generic start_hw function
294 * and the generation start_hw function.
295 * Then performs revision-specific operations, if any.
297 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
299 s32 ret_val = IXGBE_SUCCESS;
301 DEBUGFUNC("ixgbe_start_hw_X540");
303 ret_val = ixgbe_start_hw_generic(hw);
304 if (ret_val != IXGBE_SUCCESS)
307 ret_val = ixgbe_start_hw_gen2(hw);
314 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
315 * @hw: pointer to hardware structure
317 * Determines physical layer capabilities of the current configuration.
319 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
321 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
324 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
326 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
327 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
328 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
329 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
330 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
331 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
332 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
333 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
335 return physical_layer;
339 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
340 * @hw: pointer to hardware structure
342 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
343 * ixgbe_hw struct in order to set up EEPROM access.
345 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
347 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
351 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
353 if (eeprom->type == ixgbe_eeprom_uninitialized) {
354 eeprom->semaphore_delay = 10;
355 eeprom->type = ixgbe_flash;
357 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
358 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
359 IXGBE_EEC_SIZE_SHIFT);
360 eeprom->word_size = 1 << (eeprom_size +
361 IXGBE_EEPROM_WORD_SIZE_SHIFT);
363 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
364 eeprom->type, eeprom->word_size);
367 return IXGBE_SUCCESS;
371 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
372 * @hw: pointer to hardware structure
373 * @offset: offset of word in the EEPROM to read
374 * @data: word read from the EEPROM
376 * Reads a 16 bit word from the EEPROM using the EERD register.
378 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
380 s32 status = IXGBE_SUCCESS;
382 DEBUGFUNC("ixgbe_read_eerd_X540");
383 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
385 status = ixgbe_read_eerd_generic(hw, offset, data);
387 status = IXGBE_ERR_SWFW_SYNC;
389 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
394 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
395 * @hw: pointer to hardware structure
396 * @offset: offset of word in the EEPROM to read
397 * @words: number of words
398 * @data: word(s) read from the EEPROM
400 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
402 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
403 u16 offset, u16 words, u16 *data)
405 s32 status = IXGBE_SUCCESS;
407 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
408 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
410 status = ixgbe_read_eerd_buffer_generic(hw, offset,
413 status = IXGBE_ERR_SWFW_SYNC;
415 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
420 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
421 * @hw: pointer to hardware structure
422 * @offset: offset of word in the EEPROM to write
423 * @data: word write to the EEPROM
425 * Write a 16 bit word to the EEPROM using the EEWR register.
427 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
429 s32 status = IXGBE_SUCCESS;
431 DEBUGFUNC("ixgbe_write_eewr_X540");
432 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
434 status = ixgbe_write_eewr_generic(hw, offset, data);
436 status = IXGBE_ERR_SWFW_SYNC;
438 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
443 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
444 * @hw: pointer to hardware structure
445 * @offset: offset of word in the EEPROM to write
446 * @words: number of words
447 * @data: word(s) write to the EEPROM
449 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
451 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
452 u16 offset, u16 words, u16 *data)
454 s32 status = IXGBE_SUCCESS;
456 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
457 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
459 status = ixgbe_write_eewr_buffer_generic(hw, offset,
462 status = IXGBE_ERR_SWFW_SYNC;
464 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
469 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
471 * This function does not use synchronization for EERD and EEWR. It can
472 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
474 * @hw: pointer to hardware structure
476 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
486 * Do not use hw->eeprom.ops.read because we do not want to take
487 * the synchronization semaphores here. Instead use
488 * ixgbe_read_eerd_generic
491 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
493 /* Include 0x0-0x3F in the checksum */
494 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
495 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
496 DEBUGOUT("EEPROM read failed\n");
503 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
504 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
506 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
507 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
510 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
511 DEBUGOUT("EEPROM read failed\n");
515 /* Skip pointer section if the pointer is invalid. */
516 if (pointer == 0xFFFF || pointer == 0 ||
517 pointer >= hw->eeprom.word_size)
520 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
522 DEBUGOUT("EEPROM read failed\n");
526 /* Skip pointer section if length is invalid. */
527 if (length == 0xFFFF || length == 0 ||
528 (pointer + length) >= hw->eeprom.word_size)
531 for (j = pointer+1; j <= pointer+length; j++) {
532 if (ixgbe_read_eerd_generic(hw, j, &word) !=
534 DEBUGOUT("EEPROM read failed\n");
541 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
547 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
548 * @hw: pointer to hardware structure
549 * @checksum_val: calculated checksum
551 * Performs checksum calculation and validates the EEPROM checksum. If the
552 * caller does not need checksum_val, the value can be NULL.
554 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
559 u16 read_checksum = 0;
561 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
564 * Read the first word from the EEPROM. If this times out or fails, do
565 * not continue or we could be in for a very long wait while every
568 status = hw->eeprom.ops.read(hw, 0, &checksum);
570 if (status != IXGBE_SUCCESS) {
571 DEBUGOUT("EEPROM read failed\n");
575 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
577 checksum = hw->eeprom.ops.calc_checksum(hw);
580 * Do not use hw->eeprom.ops.read because we do not want to take
581 * the synchronization semaphores twice here.
583 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
587 * Verify read checksum from EEPROM is the same as
588 * calculated checksum
590 if (read_checksum != checksum) {
591 status = IXGBE_ERR_EEPROM_CHECKSUM;
592 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
593 "Invalid EEPROM checksum");
596 /* If the user cares, return the calculated checksum */
598 *checksum_val = checksum;
600 status = IXGBE_ERR_SWFW_SYNC;
603 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
609 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
610 * @hw: pointer to hardware structure
612 * After writing EEPROM to shadow RAM using EEWR register, software calculates
613 * checksum and updates the EEPROM and instructs the hardware to update
616 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
621 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
624 * Read the first word from the EEPROM. If this times out or fails, do
625 * not continue or we could be in for a very long wait while every
628 status = hw->eeprom.ops.read(hw, 0, &checksum);
630 if (status != IXGBE_SUCCESS)
631 DEBUGOUT("EEPROM read failed\n");
633 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
635 checksum = hw->eeprom.ops.calc_checksum(hw);
638 * Do not use hw->eeprom.ops.write because we do not want to
639 * take the synchronization semaphores twice here.
641 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
644 if (status == IXGBE_SUCCESS)
645 status = ixgbe_update_flash_X540(hw);
647 status = IXGBE_ERR_SWFW_SYNC;
650 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
656 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
657 * @hw: pointer to hardware structure
659 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
660 * EEPROM from shadow RAM to the flash device.
662 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
667 DEBUGFUNC("ixgbe_update_flash_X540");
669 status = ixgbe_poll_flash_update_done_X540(hw);
670 if (status == IXGBE_ERR_EEPROM) {
671 DEBUGOUT("Flash update time out\n");
675 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
676 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
678 status = ixgbe_poll_flash_update_done_X540(hw);
679 if (status == IXGBE_SUCCESS)
680 DEBUGOUT("Flash update complete\n");
682 DEBUGOUT("Flash update time out\n");
684 if (hw->revision_id == 0) {
685 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
687 if (flup & IXGBE_EEC_SEC1VAL) {
688 flup |= IXGBE_EEC_FLUP;
689 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
692 status = ixgbe_poll_flash_update_done_X540(hw);
693 if (status == IXGBE_SUCCESS)
694 DEBUGOUT("Flash update complete\n");
696 DEBUGOUT("Flash update time out\n");
703 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
704 * @hw: pointer to hardware structure
706 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
707 * flash update is done.
709 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
713 s32 status = IXGBE_ERR_EEPROM;
715 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
717 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
718 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
719 if (reg & IXGBE_EEC_FLUDONE) {
720 status = IXGBE_SUCCESS;
726 if (i == IXGBE_FLUDONE_ATTEMPTS)
727 ERROR_REPORT1(IXGBE_ERROR_POLLING,
728 "Flash update status polling timed out");
734 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
735 * @hw: pointer to hardware structure
736 * @mask: Mask to specify which semaphore to acquire
738 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
739 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
741 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
745 u32 fwmask = mask << 5;
749 s32 ret_val = IXGBE_SUCCESS;
751 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
753 if (swmask == IXGBE_GSSR_EEP_SM)
754 hwmask = IXGBE_GSSR_FLASH_SM;
756 /* SW only mask doesn't have FW bit pair */
757 if (swmask == IXGBE_GSSR_SW_MNG_SM)
760 for (i = 0; i < timeout; i++) {
762 * SW NVM semaphore bit is used for access to all
763 * SW_FW_SYNC bits (not just NVM)
765 if (ixgbe_get_swfw_sync_semaphore(hw)) {
766 ret_val = IXGBE_ERR_SWFW_SYNC;
770 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
771 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
773 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
774 ixgbe_release_swfw_sync_semaphore(hw);
779 * Firmware currently using resource (fwmask), hardware
780 * currently using resource (hwmask), or other software
781 * thread currently using resource (swmask)
783 ixgbe_release_swfw_sync_semaphore(hw);
788 /* Failed to get SW only semaphore */
789 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
790 ret_val = IXGBE_ERR_SWFW_SYNC;
791 ERROR_REPORT1(IXGBE_ERROR_POLLING,
792 "Failed to get SW only semaphore");
796 /* If the resource is not released by the FW/HW the SW can assume that
797 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
798 * of the requested resource(s) while ignoring the corresponding FW/HW
799 * bits in the SW_FW_SYNC register.
801 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
802 if (swfw_sync & (fwmask | hwmask)) {
803 if (ixgbe_get_swfw_sync_semaphore(hw)) {
804 ret_val = IXGBE_ERR_SWFW_SYNC;
809 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
810 ixgbe_release_swfw_sync_semaphore(hw);
819 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
820 * @hw: pointer to hardware structure
821 * @mask: Mask to specify which semaphore to release
823 * Releases the SWFW semaphore through the SW_FW_SYNC register
824 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
826 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
831 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
833 ixgbe_get_swfw_sync_semaphore(hw);
835 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
836 swfw_sync &= ~swmask;
837 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
839 ixgbe_release_swfw_sync_semaphore(hw);
844 * ixgbe_get_nvm_semaphore - Get hardware semaphore
845 * @hw: pointer to hardware structure
847 * Sets the hardware semaphores so SW/FW can gain control of shared resources
849 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
851 s32 status = IXGBE_ERR_EEPROM;
856 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
858 /* Get SMBI software semaphore between device drivers first */
859 for (i = 0; i < timeout; i++) {
861 * If the SMBI bit is 0 when we read it, then the bit will be
862 * set and we have the semaphore
864 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
865 if (!(swsm & IXGBE_SWSM_SMBI)) {
866 status = IXGBE_SUCCESS;
872 /* Now get the semaphore between SW/FW through the REGSMP bit */
873 if (status == IXGBE_SUCCESS) {
874 for (i = 0; i < timeout; i++) {
875 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
876 if (!(swsm & IXGBE_SWFW_REGSMP))
883 * Release semaphores and return error if SW NVM semaphore
884 * was not granted because we don't have access to the EEPROM
887 ERROR_REPORT1(IXGBE_ERROR_POLLING,
888 "REGSMP Software NVM semaphore not granted.\n");
889 ixgbe_release_swfw_sync_semaphore(hw);
890 status = IXGBE_ERR_EEPROM;
893 ERROR_REPORT1(IXGBE_ERROR_POLLING,
894 "Software semaphore SMBI between device drivers "
902 * ixgbe_release_nvm_semaphore - Release hardware semaphore
903 * @hw: pointer to hardware structure
905 * This function clears hardware semaphore bits.
907 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
911 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
913 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
915 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
916 swsm &= ~IXGBE_SWSM_SMBI;
917 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
919 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
920 swsm &= ~IXGBE_SWFW_REGSMP;
921 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
923 IXGBE_WRITE_FLUSH(hw);
927 * ixgbe_blink_led_start_X540 - Blink LED based on index.
928 * @hw: pointer to hardware structure
929 * @index: led number to blink
931 * Devices that implement the version 2 interface:
934 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
938 ixgbe_link_speed speed;
941 DEBUGFUNC("ixgbe_blink_led_start_X540");
944 * Link should be up in order for the blink bit in the LED control
945 * register to work. Force link and speed in the MAC if link is down.
946 * This will be reversed when we stop the blinking.
948 hw->mac.ops.check_link(hw, &speed, &link_up, false);
949 if (link_up == false) {
950 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
951 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
952 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
954 /* Set the LED to LINK_UP + BLINK. */
955 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
956 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
957 ledctl_reg |= IXGBE_LED_BLINK(index);
958 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
959 IXGBE_WRITE_FLUSH(hw);
961 return IXGBE_SUCCESS;
965 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
966 * @hw: pointer to hardware structure
967 * @index: led number to stop blinking
969 * Devices that implement the version 2 interface:
972 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
977 DEBUGFUNC("ixgbe_blink_led_stop_X540");
979 /* Restore the LED to its default value. */
980 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
981 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
982 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
983 ledctl_reg &= ~IXGBE_LED_BLINK(index);
984 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
986 /* Unforce link and speed in the MAC. */
987 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
988 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
989 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
990 IXGBE_WRITE_FLUSH(hw);
992 return IXGBE_SUCCESS;