1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x540.h"
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_X540_MAX_TX_QUEUES 128
41 #define IXGBE_X540_MAX_RX_QUEUES 128
42 #define IXGBE_X540_RAR_ENTRIES 128
43 #define IXGBE_X540_MC_TBL_SIZE 128
44 #define IXGBE_X540_VFT_TBL_SIZE 128
45 #define IXGBE_X540_RX_PB_SIZE 384
47 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
48 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
49 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
50 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
54 * @hw: pointer to hardware structure
56 * Initialize the function pointers and assign the MAC type for X540.
57 * Does not touch the hardware.
59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
61 struct ixgbe_mac_info *mac = &hw->mac;
62 struct ixgbe_phy_info *phy = &hw->phy;
63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
66 DEBUGFUNC("ixgbe_init_ops_X540");
68 ret_val = ixgbe_init_phy_ops_generic(hw);
69 ret_val = ixgbe_init_ops_generic(hw);
73 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
74 eeprom->ops.read = &ixgbe_read_eerd_X540;
75 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
76 eeprom->ops.write = &ixgbe_write_eewr_X540;
77 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
78 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
79 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
80 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
83 phy->ops.init = &ixgbe_init_phy_ops_generic;
84 phy->ops.reset = NULL;
87 mac->ops.reset_hw = &ixgbe_reset_hw_X540;
88 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
89 mac->ops.get_media_type = &ixgbe_get_media_type_X540;
90 mac->ops.get_supported_physical_layer =
91 &ixgbe_get_supported_physical_layer_X540;
92 mac->ops.read_analog_reg8 = NULL;
93 mac->ops.write_analog_reg8 = NULL;
94 mac->ops.start_hw = &ixgbe_start_hw_X540;
95 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
96 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
97 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
98 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
99 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
100 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
101 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
102 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
103 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
105 /* RAR, Multicast, VLAN */
106 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
107 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
108 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
109 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
110 mac->rar_highwater = 1;
111 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
112 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
113 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
114 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
115 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
116 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
119 mac->ops.get_link_capabilities =
120 &ixgbe_get_copper_link_capabilities_generic;
121 mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
122 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
123 mac->ops.check_link = &ixgbe_check_mac_link_generic;
126 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
127 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
128 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
129 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
130 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
131 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
132 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
136 * ARC supported; valid only if manageability features are
139 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
140 IXGBE_FWSM_MODE_MASK) ? true : false;
142 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
145 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
146 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
148 /* Manageability interface */
149 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
151 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
157 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
158 * @hw: pointer to hardware structure
159 * @speed: pointer to link speed
160 * @autoneg: true when autoneg or autotry is enabled
162 * Determines the link capabilities by reading the AUTOC register.
164 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
165 ixgbe_link_speed *speed,
168 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
170 return IXGBE_SUCCESS;
174 * ixgbe_get_media_type_X540 - Get media type
175 * @hw: pointer to hardware structure
177 * Returns the media type (fiber, copper, backplane)
179 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
181 UNREFERENCED_1PARAMETER(hw);
182 return ixgbe_media_type_copper;
186 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
187 * @hw: pointer to hardware structure
188 * @speed: new link speed
189 * @autoneg: true if autonegotiation enabled
190 * @autoneg_wait_to_complete: true when waiting for completion is needed
192 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
193 ixgbe_link_speed speed, bool autoneg,
194 bool autoneg_wait_to_complete)
196 DEBUGFUNC("ixgbe_setup_mac_link_X540");
197 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
198 autoneg_wait_to_complete);
202 * ixgbe_reset_hw_X540 - Perform hardware reset
203 * @hw: pointer to hardware structure
205 * Resets the hardware by resetting the transmit and receive units, masks
206 * and clears all interrupts, and perform a reset.
208 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
213 DEBUGFUNC("ixgbe_reset_hw_X540");
215 /* Call adapter stop to disable tx/rx and clear interrupts */
216 status = hw->mac.ops.stop_adapter(hw);
217 if (status != IXGBE_SUCCESS)
220 /* flush pending Tx transactions */
221 ixgbe_clear_tx_pending(hw);
224 ctrl = IXGBE_CTRL_RST;
225 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
226 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
227 IXGBE_WRITE_FLUSH(hw);
229 /* Poll for reset bit to self-clear indicating reset is complete */
230 for (i = 0; i < 10; i++) {
232 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
233 if (!(ctrl & IXGBE_CTRL_RST_MASK))
237 if (ctrl & IXGBE_CTRL_RST_MASK) {
238 status = IXGBE_ERR_RESET_FAILED;
239 ERROR_REPORT1(IXGBE_ERROR_POLLING,
240 "Reset polling failed to complete.\n");
245 * Double resets are required for recovery from certain error
246 * conditions. Between resets, it is necessary to stall to allow time
247 * for any pending HW events to complete.
249 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
250 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
254 /* Set the Rx packet buffer size. */
255 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
257 /* Store the permanent mac address */
258 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
261 * Store MAC address from RAR0, clear receive address registers, and
262 * clear the multicast table. Also reset num_rar_entries to 128,
263 * since we modify this value when programming the SAN MAC address.
265 hw->mac.num_rar_entries = 128;
266 hw->mac.ops.init_rx_addrs(hw);
268 /* Store the permanent SAN mac address */
269 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
271 /* Add the SAN MAC address to the RAR only if it's a valid address */
272 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
273 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
274 hw->mac.san_addr, 0, IXGBE_RAH_AV);
276 /* Save the SAN MAC RAR index */
277 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
279 /* Reserve the last RAR for the SAN MAC address */
280 hw->mac.num_rar_entries--;
283 /* Store the alternative WWNN/WWPN prefix */
284 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
285 &hw->mac.wwpn_prefix);
292 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
293 * @hw: pointer to hardware structure
295 * Starts the hardware using the generic start_hw function
296 * and the generation start_hw function.
297 * Then performs revision-specific operations, if any.
299 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
301 s32 ret_val = IXGBE_SUCCESS;
303 DEBUGFUNC("ixgbe_start_hw_X540");
305 ret_val = ixgbe_start_hw_generic(hw);
306 if (ret_val != IXGBE_SUCCESS)
309 ret_val = ixgbe_start_hw_gen2(hw);
316 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
317 * @hw: pointer to hardware structure
319 * Determines physical layer capabilities of the current configuration.
321 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
323 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
326 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
328 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
329 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
330 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
331 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
332 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
333 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
334 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
335 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
337 return physical_layer;
341 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
342 * @hw: pointer to hardware structure
344 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
345 * ixgbe_hw struct in order to set up EEPROM access.
347 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
349 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
353 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
355 if (eeprom->type == ixgbe_eeprom_uninitialized) {
356 eeprom->semaphore_delay = 10;
357 eeprom->type = ixgbe_flash;
359 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
360 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
361 IXGBE_EEC_SIZE_SHIFT);
362 eeprom->word_size = 1 << (eeprom_size +
363 IXGBE_EEPROM_WORD_SIZE_SHIFT);
365 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
366 eeprom->type, eeprom->word_size);
369 return IXGBE_SUCCESS;
373 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
374 * @hw: pointer to hardware structure
375 * @offset: offset of word in the EEPROM to read
376 * @data: word read from the EEPROM
378 * Reads a 16 bit word from the EEPROM using the EERD register.
380 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
382 s32 status = IXGBE_SUCCESS;
384 DEBUGFUNC("ixgbe_read_eerd_X540");
385 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
387 status = ixgbe_read_eerd_generic(hw, offset, data);
389 status = IXGBE_ERR_SWFW_SYNC;
391 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
396 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
397 * @hw: pointer to hardware structure
398 * @offset: offset of word in the EEPROM to read
399 * @words: number of words
400 * @data: word(s) read from the EEPROM
402 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
404 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
405 u16 offset, u16 words, u16 *data)
407 s32 status = IXGBE_SUCCESS;
409 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
410 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
412 status = ixgbe_read_eerd_buffer_generic(hw, offset,
415 status = IXGBE_ERR_SWFW_SYNC;
417 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
422 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
423 * @hw: pointer to hardware structure
424 * @offset: offset of word in the EEPROM to write
425 * @data: word write to the EEPROM
427 * Write a 16 bit word to the EEPROM using the EEWR register.
429 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
431 s32 status = IXGBE_SUCCESS;
433 DEBUGFUNC("ixgbe_write_eewr_X540");
434 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
436 status = ixgbe_write_eewr_generic(hw, offset, data);
438 status = IXGBE_ERR_SWFW_SYNC;
440 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
445 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
446 * @hw: pointer to hardware structure
447 * @offset: offset of word in the EEPROM to write
448 * @words: number of words
449 * @data: word(s) write to the EEPROM
451 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
453 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
454 u16 offset, u16 words, u16 *data)
456 s32 status = IXGBE_SUCCESS;
458 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
459 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
461 status = ixgbe_write_eewr_buffer_generic(hw, offset,
464 status = IXGBE_ERR_SWFW_SYNC;
466 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
471 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
473 * This function does not use synchronization for EERD and EEWR. It can
474 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
476 * @hw: pointer to hardware structure
478 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
488 * Do not use hw->eeprom.ops.read because we do not want to take
489 * the synchronization semaphores here. Instead use
490 * ixgbe_read_eerd_generic
493 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
495 /* Include 0x0-0x3F in the checksum */
496 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
497 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
498 DEBUGOUT("EEPROM read failed\n");
505 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
506 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
508 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
509 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
512 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
513 DEBUGOUT("EEPROM read failed\n");
517 /* Skip pointer section if the pointer is invalid. */
518 if (pointer == 0xFFFF || pointer == 0 ||
519 pointer >= hw->eeprom.word_size)
522 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
524 DEBUGOUT("EEPROM read failed\n");
528 /* Skip pointer section if length is invalid. */
529 if (length == 0xFFFF || length == 0 ||
530 (pointer + length) >= hw->eeprom.word_size)
533 for (j = pointer+1; j <= pointer+length; j++) {
534 if (ixgbe_read_eerd_generic(hw, j, &word) !=
536 DEBUGOUT("EEPROM read failed\n");
543 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
549 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
550 * @hw: pointer to hardware structure
551 * @checksum_val: calculated checksum
553 * Performs checksum calculation and validates the EEPROM checksum. If the
554 * caller does not need checksum_val, the value can be NULL.
556 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
561 u16 read_checksum = 0;
563 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
566 * Read the first word from the EEPROM. If this times out or fails, do
567 * not continue or we could be in for a very long wait while every
570 status = hw->eeprom.ops.read(hw, 0, &checksum);
572 if (status != IXGBE_SUCCESS) {
573 DEBUGOUT("EEPROM read failed\n");
577 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
579 checksum = hw->eeprom.ops.calc_checksum(hw);
582 * Do not use hw->eeprom.ops.read because we do not want to take
583 * the synchronization semaphores twice here.
585 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
589 * Verify read checksum from EEPROM is the same as
590 * calculated checksum
592 if (read_checksum != checksum) {
593 status = IXGBE_ERR_EEPROM_CHECKSUM;
594 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
595 "Invalid EEPROM checksum");
598 /* If the user cares, return the calculated checksum */
600 *checksum_val = checksum;
602 status = IXGBE_ERR_SWFW_SYNC;
605 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
611 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
612 * @hw: pointer to hardware structure
614 * After writing EEPROM to shadow RAM using EEWR register, software calculates
615 * checksum and updates the EEPROM and instructs the hardware to update
618 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
623 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
626 * Read the first word from the EEPROM. If this times out or fails, do
627 * not continue or we could be in for a very long wait while every
630 status = hw->eeprom.ops.read(hw, 0, &checksum);
632 if (status != IXGBE_SUCCESS)
633 DEBUGOUT("EEPROM read failed\n");
635 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
637 checksum = hw->eeprom.ops.calc_checksum(hw);
640 * Do not use hw->eeprom.ops.write because we do not want to
641 * take the synchronization semaphores twice here.
643 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
646 if (status == IXGBE_SUCCESS)
647 status = ixgbe_update_flash_X540(hw);
649 status = IXGBE_ERR_SWFW_SYNC;
652 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
658 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
659 * @hw: pointer to hardware structure
661 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
662 * EEPROM from shadow RAM to the flash device.
664 STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
669 DEBUGFUNC("ixgbe_update_flash_X540");
671 status = ixgbe_poll_flash_update_done_X540(hw);
672 if (status == IXGBE_ERR_EEPROM) {
673 DEBUGOUT("Flash update time out\n");
677 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
678 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
680 status = ixgbe_poll_flash_update_done_X540(hw);
681 if (status == IXGBE_SUCCESS)
682 DEBUGOUT("Flash update complete\n");
684 DEBUGOUT("Flash update time out\n");
686 if (hw->revision_id == 0) {
687 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
689 if (flup & IXGBE_EEC_SEC1VAL) {
690 flup |= IXGBE_EEC_FLUP;
691 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
694 status = ixgbe_poll_flash_update_done_X540(hw);
695 if (status == IXGBE_SUCCESS)
696 DEBUGOUT("Flash update complete\n");
698 DEBUGOUT("Flash update time out\n");
705 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
706 * @hw: pointer to hardware structure
708 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
709 * flash update is done.
711 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
715 s32 status = IXGBE_ERR_EEPROM;
717 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
719 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
720 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
721 if (reg & IXGBE_EEC_FLUDONE) {
722 status = IXGBE_SUCCESS;
728 if (i == IXGBE_FLUDONE_ATTEMPTS)
729 ERROR_REPORT1(IXGBE_ERROR_POLLING,
730 "Flash update status polling timed out");
736 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
737 * @hw: pointer to hardware structure
738 * @mask: Mask to specify which semaphore to acquire
740 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
741 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
743 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
747 u32 fwmask = mask << 5;
751 s32 ret_val = IXGBE_SUCCESS;
753 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
755 if (swmask == IXGBE_GSSR_EEP_SM)
756 hwmask = IXGBE_GSSR_FLASH_SM;
758 /* SW only mask doesn't have FW bit pair */
759 if (swmask == IXGBE_GSSR_SW_MNG_SM)
762 for (i = 0; i < timeout; i++) {
764 * SW NVM semaphore bit is used for access to all
765 * SW_FW_SYNC bits (not just NVM)
767 if (ixgbe_get_swfw_sync_semaphore(hw)) {
768 ret_val = IXGBE_ERR_SWFW_SYNC;
772 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
773 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
775 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
776 ixgbe_release_swfw_sync_semaphore(hw);
781 * Firmware currently using resource (fwmask), hardware
782 * currently using resource (hwmask), or other software
783 * thread currently using resource (swmask)
785 ixgbe_release_swfw_sync_semaphore(hw);
790 /* Failed to get SW only semaphore */
791 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
792 ret_val = IXGBE_ERR_SWFW_SYNC;
793 ERROR_REPORT1(IXGBE_ERROR_POLLING,
794 "Failed to get SW only semaphore");
798 /* If the resource is not released by the FW/HW the SW can assume that
799 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
800 * of the requested resource(s) while ignoring the corresponding FW/HW
801 * bits in the SW_FW_SYNC register.
803 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
804 if (swfw_sync & (fwmask | hwmask)) {
805 if (ixgbe_get_swfw_sync_semaphore(hw)) {
806 ret_val = IXGBE_ERR_SWFW_SYNC;
811 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
812 ixgbe_release_swfw_sync_semaphore(hw);
821 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
822 * @hw: pointer to hardware structure
823 * @mask: Mask to specify which semaphore to release
825 * Releases the SWFW semaphore through the SW_FW_SYNC register
826 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
828 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
833 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
835 ixgbe_get_swfw_sync_semaphore(hw);
837 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
838 swfw_sync &= ~swmask;
839 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
841 ixgbe_release_swfw_sync_semaphore(hw);
846 * ixgbe_get_nvm_semaphore - Get hardware semaphore
847 * @hw: pointer to hardware structure
849 * Sets the hardware semaphores so SW/FW can gain control of shared resources
851 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
853 s32 status = IXGBE_ERR_EEPROM;
858 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
860 /* Get SMBI software semaphore between device drivers first */
861 for (i = 0; i < timeout; i++) {
863 * If the SMBI bit is 0 when we read it, then the bit will be
864 * set and we have the semaphore
866 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
867 if (!(swsm & IXGBE_SWSM_SMBI)) {
868 status = IXGBE_SUCCESS;
874 /* Now get the semaphore between SW/FW through the REGSMP bit */
875 if (status == IXGBE_SUCCESS) {
876 for (i = 0; i < timeout; i++) {
877 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
878 if (!(swsm & IXGBE_SWFW_REGSMP))
885 * Release semaphores and return error if SW NVM semaphore
886 * was not granted because we don't have access to the EEPROM
889 ERROR_REPORT1(IXGBE_ERROR_POLLING,
890 "REGSMP Software NVM semaphore not granted.\n");
891 ixgbe_release_swfw_sync_semaphore(hw);
892 status = IXGBE_ERR_EEPROM;
895 ERROR_REPORT1(IXGBE_ERROR_POLLING,
896 "Software semaphore SMBI between device drivers "
904 * ixgbe_release_nvm_semaphore - Release hardware semaphore
905 * @hw: pointer to hardware structure
907 * This function clears hardware semaphore bits.
909 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
913 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
915 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
917 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
918 swsm &= ~IXGBE_SWSM_SMBI;
919 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
921 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
922 swsm &= ~IXGBE_SWFW_REGSMP;
923 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
925 IXGBE_WRITE_FLUSH(hw);
929 * ixgbe_blink_led_start_X540 - Blink LED based on index.
930 * @hw: pointer to hardware structure
931 * @index: led number to blink
933 * Devices that implement the version 2 interface:
936 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
940 ixgbe_link_speed speed;
943 DEBUGFUNC("ixgbe_blink_led_start_X540");
946 * Link should be up in order for the blink bit in the LED control
947 * register to work. Force link and speed in the MAC if link is down.
948 * This will be reversed when we stop the blinking.
950 hw->mac.ops.check_link(hw, &speed, &link_up, false);
951 if (link_up == false) {
952 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
953 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
954 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
956 /* Set the LED to LINK_UP + BLINK. */
957 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
958 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
959 ledctl_reg |= IXGBE_LED_BLINK(index);
960 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
961 IXGBE_WRITE_FLUSH(hw);
963 return IXGBE_SUCCESS;
967 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
968 * @hw: pointer to hardware structure
969 * @index: led number to stop blinking
971 * Devices that implement the version 2 interface:
974 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
979 DEBUGFUNC("ixgbe_blink_led_stop_X540");
981 /* Restore the LED to its default value. */
982 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
983 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
984 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
985 ledctl_reg &= ~IXGBE_LED_BLINK(index);
986 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
988 /* Unforce link and speed in the MAC. */
989 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
990 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
991 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
992 IXGBE_WRITE_FLUSH(hw);
994 return IXGBE_SUCCESS;