1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
42 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
43 * @hw: pointer to hardware structure
45 * Initialize the function pointers and assign the MAC type for X550.
46 * Does not touch the hardware.
48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
50 struct ixgbe_mac_info *mac = &hw->mac;
51 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
54 DEBUGFUNC("ixgbe_init_ops_X550");
56 ret_val = ixgbe_init_ops_X540(hw);
57 mac->ops.dmac_config = ixgbe_dmac_config_X550;
58 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
59 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
60 mac->ops.setup_eee = ixgbe_setup_eee_X550;
61 mac->ops.set_source_address_pruning =
62 ixgbe_set_source_address_pruning_X550;
63 mac->ops.set_ethertype_anti_spoofing =
64 ixgbe_set_ethertype_anti_spoofing_X550;
66 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
67 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
68 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
69 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
70 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
71 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
72 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
73 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
74 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
76 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
77 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
78 mac->ops.mdd_event = ixgbe_mdd_event_X550;
79 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
80 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 * ixgbe_identify_phy_x550em - Get PHY type based on device id
86 * @hw: pointer to hardware structure
90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
92 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
94 switch (hw->device_id) {
95 case IXGBE_DEV_ID_X550EM_X_SFP:
96 /* set up for CS4227 usage */
97 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
98 IXGBE_STATUS_LAN_ID_1;
99 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
100 if (hw->phy.lan_id) {
102 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
103 esdp |= IXGBE_ESDP_SDP1_DIR;
105 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
106 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
108 return ixgbe_identify_module_generic(hw);
110 case IXGBE_DEV_ID_X550EM_X_KX4:
111 hw->phy.type = ixgbe_phy_x550em_kx4;
113 case IXGBE_DEV_ID_X550EM_X_KR:
114 case IXGBE_DEV_ID_X550EM_X:
115 hw->phy.type = ixgbe_phy_x550em_kr;
120 return IXGBE_SUCCESS;
123 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
124 u32 device_type, u16 *phy_data)
126 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
127 return IXGBE_NOT_IMPLEMENTED;
130 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
131 u32 device_type, u16 phy_data)
133 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
134 return IXGBE_NOT_IMPLEMENTED;
138 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
139 * @hw: pointer to hardware structure
141 * Initialize the function pointers and for MAC type X550EM.
142 * Does not touch the hardware.
144 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
146 struct ixgbe_mac_info *mac = &hw->mac;
147 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
148 struct ixgbe_phy_info *phy = &hw->phy;
151 DEBUGFUNC("ixgbe_init_ops_X550EM");
153 /* Similar to X550 so start there. */
154 ret_val = ixgbe_init_ops_X550(hw);
156 /* Since this function eventually calls
157 * ixgbe_init_ops_540 by design, we are setting
158 * the pointers to NULL explicitly here to overwrite
159 * the values being set in the x540 function.
161 /* Thermal sensor not supported in x550EM */
162 mac->ops.get_thermal_sensor_data = NULL;
163 mac->ops.init_thermal_sensor_thresh = NULL;
164 mac->thermal_sensor_enabled = false;
166 /* FCOE not supported in x550EM */
167 mac->ops.get_san_mac_addr = NULL;
168 mac->ops.set_san_mac_addr = NULL;
169 mac->ops.get_wwn_prefix = NULL;
170 mac->ops.get_fcoe_boot_status = NULL;
172 /* IPsec not supported in x550EM */
173 mac->ops.disable_sec_rx_path = NULL;
174 mac->ops.enable_sec_rx_path = NULL;
176 /* X550EM bus type is internal*/
177 hw->bus.type = ixgbe_bus_type_internal;
178 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
180 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
181 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
182 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
183 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
184 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
185 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
186 mac->ops.get_supported_physical_layer =
187 ixgbe_get_supported_physical_layer_X550em;
190 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
191 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
192 phy->ops.init = ixgbe_init_phy_ops_X550em;
193 phy->ops.identify = ixgbe_identify_phy_x550em;
194 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
195 phy->ops.set_phy_power = NULL;
199 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
200 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
201 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
202 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
203 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
204 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
205 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
206 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
212 * ixgbe_dmac_config_X550
213 * @hw: pointer to hardware structure
215 * Configure DMA coalescing. If enabling dmac, dmac is activated.
216 * When disabling dmac, dmac enable dmac bit is cleared.
218 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
220 u32 reg, high_pri_tc;
222 DEBUGFUNC("ixgbe_dmac_config_X550");
224 /* Disable DMA coalescing before configuring */
225 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
226 reg &= ~IXGBE_DMACR_DMAC_EN;
227 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
229 /* Disable DMA Coalescing if the watchdog timer is 0 */
230 if (!hw->mac.dmac_config.watchdog_timer)
233 ixgbe_dmac_config_tcs_X550(hw);
235 /* Configure DMA Coalescing Control Register */
236 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
238 /* Set the watchdog timer in units of 40.96 usec */
239 reg &= ~IXGBE_DMACR_DMACWT_MASK;
240 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
242 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
243 /* If fcoe is enabled, set high priority traffic class */
244 if (hw->mac.dmac_config.fcoe_en) {
245 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
246 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
247 IXGBE_DMACR_HIGH_PRI_TC_MASK);
249 reg |= IXGBE_DMACR_EN_MNG_IND;
251 /* Enable DMA coalescing after configuration */
252 reg |= IXGBE_DMACR_DMAC_EN;
253 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
256 return IXGBE_SUCCESS;
260 * ixgbe_dmac_config_tcs_X550
261 * @hw: pointer to hardware structure
263 * Configure DMA coalescing threshold per TC. The dmac enable bit must
264 * be cleared before configuring.
266 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
268 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
270 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
272 /* Configure DMA coalescing enabled */
273 switch (hw->mac.dmac_config.link_speed) {
274 case IXGBE_LINK_SPEED_100_FULL:
275 pb_headroom = IXGBE_DMACRXT_100M;
277 case IXGBE_LINK_SPEED_1GB_FULL:
278 pb_headroom = IXGBE_DMACRXT_1G;
281 pb_headroom = IXGBE_DMACRXT_10G;
285 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
286 IXGBE_MHADD_MFS_SHIFT) / 1024);
288 /* Set the per Rx packet buffer receive threshold */
289 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
290 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
291 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
293 if (tc < hw->mac.dmac_config.num_tcs) {
295 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
296 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
297 IXGBE_RXPBSIZE_SHIFT;
299 /* Calculate receive buffer threshold in kilobytes */
300 if (rx_pb_size > pb_headroom)
301 rx_pb_size = rx_pb_size - pb_headroom;
305 /* Minimum of MFS shall be set for DMCTH */
306 reg |= (rx_pb_size > maxframe_size_kb) ?
307 rx_pb_size : maxframe_size_kb;
309 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
311 return IXGBE_SUCCESS;
315 * ixgbe_dmac_update_tcs_X550
316 * @hw: pointer to hardware structure
318 * Disables dmac, updates per TC settings, and then enables dmac.
320 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
324 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
326 /* Disable DMA coalescing before configuring */
327 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
328 reg &= ~IXGBE_DMACR_DMAC_EN;
329 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
331 ixgbe_dmac_config_tcs_X550(hw);
333 /* Enable DMA coalescing after configuration */
334 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
335 reg |= IXGBE_DMACR_DMAC_EN;
336 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
338 return IXGBE_SUCCESS;
342 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
343 * @hw: pointer to hardware structure
345 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
346 * ixgbe_hw struct in order to set up EEPROM access.
348 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
350 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
354 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
356 if (eeprom->type == ixgbe_eeprom_uninitialized) {
357 eeprom->semaphore_delay = 10;
358 eeprom->type = ixgbe_flash;
360 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
361 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
362 IXGBE_EEC_SIZE_SHIFT);
363 eeprom->word_size = 1 << (eeprom_size +
364 IXGBE_EEPROM_WORD_SIZE_SHIFT);
366 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
367 eeprom->type, eeprom->word_size);
370 return IXGBE_SUCCESS;
374 * ixgbe_setup_eee_X550 - Enable/disable EEE support
375 * @hw: pointer to the HW structure
376 * @enable_eee: boolean flag to enable EEE
378 * Enable/disable EEE based on enable_eee flag.
379 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
383 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
390 DEBUGFUNC("ixgbe_setup_eee_X550");
392 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
393 /* Enable or disable EEE per flag */
395 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
397 if (hw->device_id == IXGBE_DEV_ID_X550T) {
398 /* Advertise EEE capability */
399 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
400 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
402 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
403 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
404 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
406 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
407 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
408 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
409 hw->device_id == IXGBE_DEV_ID_X550EM_X) {
410 status = ixgbe_read_iosf_sb_reg_x550(hw,
411 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
412 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
413 if (status != IXGBE_SUCCESS)
416 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
417 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
419 status = ixgbe_write_iosf_sb_reg_x550(hw,
420 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
421 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
422 if (status != IXGBE_SUCCESS)
426 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
428 if (hw->device_id == IXGBE_DEV_ID_X550T) {
429 /* Disable advertised EEE capability */
430 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
431 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
433 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
434 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
435 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
437 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
438 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
439 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
440 hw->device_id == IXGBE_DEV_ID_X550EM_X) {
441 status = ixgbe_read_iosf_sb_reg_x550(hw,
442 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
443 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
444 if (status != IXGBE_SUCCESS)
447 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
448 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
450 status = ixgbe_write_iosf_sb_reg_x550(hw,
451 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
452 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
453 if (status != IXGBE_SUCCESS)
457 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
459 return IXGBE_SUCCESS;
463 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
464 * @hw: pointer to hardware structure
465 * @enable: enable or disable source address pruning
466 * @pool: Rx pool to set source address pruning for
468 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
473 /* max rx pool is 63 */
477 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
478 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
481 pfflp |= (1ULL << pool);
483 pfflp &= ~(1ULL << pool);
485 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
486 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
490 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
491 * @hw: pointer to hardware structure
492 * @enable: enable or disable switch for Ethertype anti-spoofing
493 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
496 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
499 int vf_target_reg = vf >> 3;
500 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
503 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
505 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
507 pfvfspoof |= (1 << vf_target_shift);
509 pfvfspoof &= ~(1 << vf_target_shift);
511 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
515 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
517 * @hw: pointer to hardware structure
518 * @reg_addr: 32 bit PHY register to write
519 * @device_type: 3 bit device type
520 * @data: Data to write to the register
522 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
523 u32 device_type, u32 data)
525 u32 i, command, error;
527 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
528 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
530 /* Write IOSF control register */
531 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
533 /* Write IOSF data register */
534 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
536 * Check every 10 usec to see if the address cycle completed.
537 * The SB IOSF BUSY bit will clear when the operation is
540 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
543 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
544 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
548 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
549 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
550 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
551 ERROR_REPORT2(IXGBE_ERROR_POLLING,
552 "Failed to write, error %x\n", error);
553 return IXGBE_ERR_PHY;
556 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
557 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
558 return IXGBE_ERR_PHY;
561 return IXGBE_SUCCESS;
565 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
567 * @hw: pointer to hardware structure
568 * @reg_addr: 32 bit PHY register to write
569 * @device_type: 3 bit device type
570 * @phy_data: Pointer to read data from the register
572 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
573 u32 device_type, u32 *data)
575 u32 i, command, error;
577 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
578 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
580 /* Write IOSF control register */
581 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
584 * Check every 10 usec to see if the address cycle completed.
585 * The SB IOSF BUSY bit will clear when the operation is
588 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
591 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
592 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
596 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
597 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
598 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
599 ERROR_REPORT2(IXGBE_ERROR_POLLING,
600 "Failed to read, error %x\n", error);
601 return IXGBE_ERR_PHY;
604 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
605 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
606 return IXGBE_ERR_PHY;
609 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
611 return IXGBE_SUCCESS;
615 * ixgbe_disable_mdd_X550
616 * @hw: pointer to hardware structure
618 * Disable malicious driver detection
620 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
624 DEBUGFUNC("ixgbe_disable_mdd_X550");
626 /* Disable MDD for TX DMA and interrupt */
627 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
628 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
629 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
631 /* Disable MDD for RX and interrupt */
632 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
633 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
634 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
638 * ixgbe_enable_mdd_X550
639 * @hw: pointer to hardware structure
641 * Enable malicious driver detection
643 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
647 DEBUGFUNC("ixgbe_enable_mdd_X550");
649 /* Enable MDD for TX DMA and interrupt */
650 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
651 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
652 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
654 /* Enable MDD for RX and interrupt */
655 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
656 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
657 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
661 * ixgbe_restore_mdd_vf_X550
662 * @hw: pointer to hardware structure
665 * Restore VF that was disabled during malicious driver detection event
667 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
669 u32 idx, reg, num_qs, start_q, bitmask;
671 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
673 /* Map VF to queues */
674 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
675 switch (reg & IXGBE_MRQC_MRQE_MASK) {
676 case IXGBE_MRQC_VMDQRT8TCEN:
677 num_qs = 8; /* 16 VFs / pools */
678 bitmask = 0x000000FF;
680 case IXGBE_MRQC_VMDQRSS32EN:
681 case IXGBE_MRQC_VMDQRT4TCEN:
682 num_qs = 4; /* 32 VFs / pools */
683 bitmask = 0x0000000F;
685 default: /* 64 VFs / pools */
687 bitmask = 0x00000003;
690 start_q = vf * num_qs;
692 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
695 reg |= (bitmask << (start_q % 32));
696 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
697 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
701 * ixgbe_mdd_event_X550
702 * @hw: pointer to hardware structure
703 * @vf_bitmap: vf bitmap of malicious vfs
705 * Handle malicious driver detection event.
707 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
710 u32 i, j, reg, q, shift, vf, idx;
712 DEBUGFUNC("ixgbe_mdd_event_X550");
714 /* figure out pool size for mapping to vf's */
715 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
716 switch (reg & IXGBE_MRQC_MRQE_MASK) {
717 case IXGBE_MRQC_VMDQRT8TCEN:
718 shift = 3; /* 16 VFs / pools */
720 case IXGBE_MRQC_VMDQRSS32EN:
721 case IXGBE_MRQC_VMDQRT4TCEN:
722 shift = 2; /* 32 VFs / pools */
725 shift = 1; /* 64 VFs / pools */
729 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
730 for (i = 0; i < 4; i++) {
731 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
732 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
737 /* Get malicious queue */
738 for (j = 0; j < 32 && wqbr; j++) {
740 if (!(wqbr & (1 << j)))
743 /* Get queue from bitmask */
746 /* Map queue to vf */
749 /* Set vf bit in vf_bitmap */
751 vf_bitmap[idx] |= (1 << (vf % 32));
758 * ixgbe_get_media_type_X550em - Get media type
759 * @hw: pointer to hardware structure
761 * Returns the media type (fiber, copper, backplane)
763 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
765 enum ixgbe_media_type media_type;
767 DEBUGFUNC("ixgbe_get_media_type_X550em");
769 /* Detect if there is a copper PHY attached. */
770 switch (hw->device_id) {
771 case IXGBE_DEV_ID_X550EM_X:
772 case IXGBE_DEV_ID_X550EM_X_KR:
773 case IXGBE_DEV_ID_X550EM_X_KX4:
774 media_type = ixgbe_media_type_backplane;
776 case IXGBE_DEV_ID_X550EM_X_SFP:
777 media_type = ixgbe_media_type_fiber;
780 media_type = ixgbe_media_type_unknown;
787 * ixgbe_setup_sfp_modules_X550em - Setup SFP module
788 * @hw: pointer to hardware structure
790 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
793 u16 reg_slice, edc_mode;
796 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
798 switch (hw->phy.sfp_type) {
799 case ixgbe_sfp_type_unknown:
800 return IXGBE_SUCCESS;
801 case ixgbe_sfp_type_not_present:
802 return IXGBE_ERR_SFP_NOT_PRESENT;
803 case ixgbe_sfp_type_da_cu_core0:
804 case ixgbe_sfp_type_da_cu_core1:
807 case ixgbe_sfp_type_srlr_core0:
808 case ixgbe_sfp_type_srlr_core1:
809 case ixgbe_sfp_type_da_act_lmt_core0:
810 case ixgbe_sfp_type_da_act_lmt_core1:
811 case ixgbe_sfp_type_1g_sx_core0:
812 case ixgbe_sfp_type_1g_sx_core1:
813 case ixgbe_sfp_type_1g_lx_core0:
814 case ixgbe_sfp_type_1g_lx_core1:
815 setup_linear = false;
818 return IXGBE_ERR_SFP_NOT_SUPPORTED;
821 ixgbe_init_mac_link_ops_X550em(hw);
822 hw->phy.ops.reset = NULL;
824 /* The CS4227 slice address is the base address + the port-pair reg
825 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
827 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);
830 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
832 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
834 /* Configure CS4227 for connection type. */
835 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
838 if (ret_val != IXGBE_SUCCESS)
839 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
846 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
847 * @hw: pointer to hardware structure
849 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
851 struct ixgbe_mac_info *mac = &hw->mac;
853 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
855 /* CS4227 does not support autoneg, so disable the laser control
856 * functions for SFP+ fiber
858 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
859 mac->ops.disable_tx_laser = NULL;
860 mac->ops.enable_tx_laser = NULL;
861 mac->ops.flap_tx_laser = NULL;
866 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
867 * @hw: pointer to hardware structure
868 * @speed: pointer to link speed
869 * @autoneg: true when autoneg or autotry is enabled
871 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
872 ixgbe_link_speed *speed,
875 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
878 if (hw->phy.media_type == ixgbe_media_type_fiber) {
880 /* CS4227 SFP must not enable auto-negotiation */
883 /* Check if 1G SFP module. */
884 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
885 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
886 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
887 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
888 *speed = IXGBE_LINK_SPEED_1GB_FULL;
889 return IXGBE_SUCCESS;
892 /* Link capabilities are based on SFP */
893 if (hw->phy.multispeed_fiber)
894 *speed = IXGBE_LINK_SPEED_10GB_FULL |
895 IXGBE_LINK_SPEED_1GB_FULL;
897 *speed = IXGBE_LINK_SPEED_10GB_FULL;
899 *speed = IXGBE_LINK_SPEED_10GB_FULL |
900 IXGBE_LINK_SPEED_1GB_FULL;
904 return IXGBE_SUCCESS;
908 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
909 * @hw: pointer to hardware structure
911 * Initialize any function pointers that were not able to be
912 * set during init_shared_code because the PHY/SFP type was
913 * not known. Perform the SFP init if necessary.
915 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
917 struct ixgbe_phy_info *phy = &hw->phy;
921 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
923 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
924 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
925 phy->lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
926 IXGBE_STATUS_LAN_ID_1;
927 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
929 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
930 esdp |= IXGBE_ESDP_SDP1_DIR;
932 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
933 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
936 /* Identify the PHY or SFP module */
937 ret_val = phy->ops.identify(hw);
938 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
941 /* Setup function pointers based on detected SFP module and speeds */
942 ixgbe_init_mac_link_ops_X550em(hw);
943 if (phy->sfp_type != ixgbe_sfp_type_unknown)
944 phy->ops.reset = NULL;
946 /* Set functions pointers based on phy type */
947 switch (hw->phy.type) {
948 case ixgbe_phy_x550em_kr:
949 phy->ops.setup_link = ixgbe_setup_kr_x550em;
958 * ixgbe_reset_hw_X550em - Perform hardware reset
959 * @hw: pointer to hardware structure
961 * Resets the hardware by resetting the transmit and receive units, masks
962 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
965 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
967 ixgbe_link_speed link_speed;
971 bool link_up = false;
973 DEBUGFUNC("ixgbe_reset_hw_X550em");
975 /* Call adapter stop to disable Tx/Rx and clear interrupts */
976 status = hw->mac.ops.stop_adapter(hw);
977 if (status != IXGBE_SUCCESS)
980 /* flush pending Tx transactions */
981 ixgbe_clear_tx_pending(hw);
983 /* PHY ops must be identified and initialized prior to reset */
985 /* Identify PHY and related function pointers */
986 status = hw->phy.ops.init(hw);
988 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
991 /* Setup SFP module if there is one present. */
992 if (hw->phy.sfp_setup_needed) {
993 status = hw->mac.ops.setup_sfp(hw);
994 hw->phy.sfp_setup_needed = false;
997 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1001 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1002 hw->phy.ops.reset(hw);
1005 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1006 * If link reset is used when link is up, it might reset the PHY when
1007 * mng is using it. If link is down or the flag to force full link
1008 * reset is set, then perform link reset.
1010 ctrl = IXGBE_CTRL_LNK_RST;
1011 if (!hw->force_full_reset) {
1012 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1014 ctrl = IXGBE_CTRL_RST;
1017 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1018 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1019 IXGBE_WRITE_FLUSH(hw);
1021 /* Poll for reset bit to self-clear meaning reset is complete */
1022 for (i = 0; i < 10; i++) {
1024 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1025 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1029 if (ctrl & IXGBE_CTRL_RST_MASK) {
1030 status = IXGBE_ERR_RESET_FAILED;
1031 DEBUGOUT("Reset polling failed to complete.\n");
1036 /* Double resets are required for recovery from certain error
1037 * conditions. Between resets, it is necessary to stall to
1038 * allow time for any pending HW events to complete.
1040 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1041 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1045 /* Store the permanent mac address */
1046 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1048 /* Store MAC address from RAR0, clear receive address registers, and
1049 * clear the multicast table. Also reset num_rar_entries to 128,
1050 * since we modify this value when programming the SAN MAC address.
1052 hw->mac.num_rar_entries = 128;
1053 hw->mac.ops.init_rx_addrs(hw);
1059 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1060 * @hw: pointer to hardware structure
1062 * Configures the integrated KR PHY.
1064 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1069 status = ixgbe_read_iosf_sb_reg_x550(hw,
1070 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1071 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1075 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1076 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1077 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1078 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1079 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1081 /* Advertise 10G support. */
1082 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1083 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1085 /* Advertise 1G support. */
1086 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1087 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1089 /* Restart auto-negotiation. */
1090 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1091 status = ixgbe_write_iosf_sb_reg_x550(hw,
1092 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1093 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1099 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
1100 * @hw: pointer to hardware structure
1102 * Configures the integrated KR PHY to use iXFI mode.
1104 s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
1109 /* Disable AN and force speed to 10G Serial. */
1110 status = ixgbe_read_iosf_sb_reg_x550(hw,
1111 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1112 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1113 if (status != IXGBE_SUCCESS)
1115 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1116 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1117 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1118 status = ixgbe_write_iosf_sb_reg_x550(hw,
1119 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1120 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1121 if (status != IXGBE_SUCCESS)
1124 /* Disable training protocol FSM. */
1125 status = ixgbe_read_iosf_sb_reg_x550(hw,
1126 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1127 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1128 if (status != IXGBE_SUCCESS)
1130 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1131 status = ixgbe_write_iosf_sb_reg_x550(hw,
1132 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1133 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1134 if (status != IXGBE_SUCCESS)
1137 /* Disable Flex from training TXFFE. */
1138 status = ixgbe_read_iosf_sb_reg_x550(hw,
1139 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1140 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1141 if (status != IXGBE_SUCCESS)
1143 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1144 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1145 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1146 status = ixgbe_write_iosf_sb_reg_x550(hw,
1147 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1148 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1149 if (status != IXGBE_SUCCESS)
1151 status = ixgbe_read_iosf_sb_reg_x550(hw,
1152 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1153 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1154 if (status != IXGBE_SUCCESS)
1156 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1157 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1158 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1159 status = ixgbe_write_iosf_sb_reg_x550(hw,
1160 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1161 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1162 if (status != IXGBE_SUCCESS)
1165 /* Enable override for coefficients. */
1166 status = ixgbe_read_iosf_sb_reg_x550(hw,
1167 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1168 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1169 if (status != IXGBE_SUCCESS)
1171 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1172 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1173 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1174 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1175 status = ixgbe_write_iosf_sb_reg_x550(hw,
1176 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1177 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1178 if (status != IXGBE_SUCCESS)
1181 /* Toggle port SW reset by AN reset. */
1182 status = ixgbe_read_iosf_sb_reg_x550(hw,
1183 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1184 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1185 if (status != IXGBE_SUCCESS)
1187 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1188 status = ixgbe_write_iosf_sb_reg_x550(hw,
1189 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1190 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1196 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1197 * @hw: pointer to hardware structure
1199 * Configures the integrated KR PHY to use internal loopback mode.
1201 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1206 /* Disable AN and force speed to 10G Serial. */
1207 status = ixgbe_read_iosf_sb_reg_x550(hw,
1208 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1209 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1210 if (status != IXGBE_SUCCESS)
1212 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1213 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1214 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1215 status = ixgbe_write_iosf_sb_reg_x550(hw,
1216 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1217 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1218 if (status != IXGBE_SUCCESS)
1221 /* Set near-end loopback clocks. */
1222 status = ixgbe_read_iosf_sb_reg_x550(hw,
1223 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1224 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1225 if (status != IXGBE_SUCCESS)
1227 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1228 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1229 status = ixgbe_write_iosf_sb_reg_x550(hw,
1230 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1231 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1232 if (status != IXGBE_SUCCESS)
1235 /* Set loopback enable. */
1236 status = ixgbe_read_iosf_sb_reg_x550(hw,
1237 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1238 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1239 if (status != IXGBE_SUCCESS)
1241 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1242 status = ixgbe_write_iosf_sb_reg_x550(hw,
1243 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1244 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1245 if (status != IXGBE_SUCCESS)
1248 /* Training bypass. */
1249 status = ixgbe_read_iosf_sb_reg_x550(hw,
1250 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1251 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1252 if (status != IXGBE_SUCCESS)
1254 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1255 status = ixgbe_write_iosf_sb_reg_x550(hw,
1256 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1257 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1263 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1264 * assuming that the semaphore is already obtained.
1265 * @hw: pointer to hardware structure
1266 * @offset: offset of word in the EEPROM to read
1267 * @data: word read from the EEPROM
1269 * Reads a 16 bit word from the EEPROM using the hostif.
1271 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1275 struct ixgbe_hic_read_shadow_ram buffer;
1277 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1278 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1279 buffer.hdr.buf_len1 = 0;
1280 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1281 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1283 /* convert offset from words to bytes */
1284 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1286 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1288 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1289 sizeof(buffer), false);
1294 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1295 FW_NVM_DATA_OFFSET);
1301 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1302 * @hw: pointer to hardware structure
1303 * @offset: offset of word in the EEPROM to read
1304 * @data: word read from the EEPROM
1306 * Reads a 16 bit word from the EEPROM using the hostif.
1308 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1311 s32 status = IXGBE_SUCCESS;
1313 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1315 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1317 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1318 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1320 status = IXGBE_ERR_SWFW_SYNC;
1327 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1328 * @hw: pointer to hardware structure
1329 * @offset: offset of word in the EEPROM to read
1330 * @words: number of words
1331 * @data: word(s) read from the EEPROM
1333 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1335 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1336 u16 offset, u16 words, u16 *data)
1338 struct ixgbe_hic_read_shadow_ram buffer;
1339 u32 current_word = 0;
1344 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1346 /* Take semaphore for the entire operation. */
1347 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1349 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1353 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1354 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1356 words_to_read = words;
1358 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1359 buffer.hdr.buf_len1 = 0;
1360 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1361 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1363 /* convert offset from words to bytes */
1364 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1365 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1367 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1368 sizeof(buffer), false);
1371 DEBUGOUT("Host interface command failed\n");
1375 for (i = 0; i < words_to_read; i++) {
1376 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1378 u32 value = IXGBE_READ_REG(hw, reg);
1380 data[current_word] = (u16)(value & 0xffff);
1383 if (i < words_to_read) {
1385 data[current_word] = (u16)(value & 0xffff);
1389 words -= words_to_read;
1393 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1398 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1399 * @hw: pointer to hardware structure
1400 * @offset: offset of word in the EEPROM to write
1401 * @data: word write to the EEPROM
1403 * Write a 16 bit word to the EEPROM using the hostif.
1405 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1409 struct ixgbe_hic_write_shadow_ram buffer;
1411 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1413 buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1414 buffer.hdr.buf_len1 = 0;
1415 buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1416 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1419 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1421 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1423 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1424 sizeof(buffer), false);
1430 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1431 * @hw: pointer to hardware structure
1432 * @offset: offset of word in the EEPROM to write
1433 * @data: word write to the EEPROM
1435 * Write a 16 bit word to the EEPROM using the hostif.
1437 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1440 s32 status = IXGBE_SUCCESS;
1442 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1444 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1446 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1447 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1449 DEBUGOUT("write ee hostif failed to get semaphore");
1450 status = IXGBE_ERR_SWFW_SYNC;
1457 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1458 * @hw: pointer to hardware structure
1459 * @offset: offset of word in the EEPROM to write
1460 * @words: number of words
1461 * @data: word(s) write to the EEPROM
1463 * Write a 16 bit word(s) to the EEPROM using the hostif.
1465 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1466 u16 offset, u16 words, u16 *data)
1468 s32 status = IXGBE_SUCCESS;
1471 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1473 /* Take semaphore for the entire operation. */
1474 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1475 if (status != IXGBE_SUCCESS) {
1476 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1480 for (i = 0; i < words; i++) {
1481 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1484 if (status != IXGBE_SUCCESS) {
1485 DEBUGOUT("Eeprom buffered write failed\n");
1490 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1497 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1498 * @hw: pointer to hardware structure
1499 * @ptr: pointer offset in eeprom
1500 * @size: size of section pointed by ptr, if 0 first word will be used as size
1501 * @csum: address of checksum to update
1503 * Returns error status for any failure
1505 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1506 u16 size, u16 *csum)
1510 u16 length, bufsz, i, start;
1512 bufsz = sizeof(buf) / sizeof(buf[0]);
1514 /* Read a chunk at the pointer location */
1515 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1517 DEBUGOUT("Failed to read EEPROM image\n");
1528 /* Skip pointer section if length is invalid. */
1529 if (length == 0xFFFF || length == 0 ||
1530 (ptr + length) >= hw->eeprom.word_size)
1531 return IXGBE_SUCCESS;
1534 for (i = start; length; i++, length--) {
1541 /* Read a chunk at the pointer location */
1542 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1545 DEBUGOUT("Failed to read EEPROM image\n");
1551 return IXGBE_SUCCESS;
1555 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1556 * @hw: pointer to hardware structure
1558 * Returns a negative error code on error, or the 16-bit checksum
1560 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1562 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1565 u16 pointer, i, size;
1567 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1569 hw->eeprom.ops.init_params(hw);
1571 /* Read pointer area */
1572 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1573 IXGBE_EEPROM_LAST_WORD + 1,
1576 DEBUGOUT("Failed to read EEPROM image\n");
1581 * For X550 hardware include 0x0-0x41 in the checksum, skip the
1582 * checksum word itself
1584 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1585 if (i != IXGBE_EEPROM_CHECKSUM)
1586 checksum += eeprom_ptrs[i];
1589 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
1590 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1592 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1593 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1596 pointer = eeprom_ptrs[i];
1598 /* Skip pointer section if the pointer is invalid. */
1599 if (pointer == 0xFFFF || pointer == 0 ||
1600 pointer >= hw->eeprom.word_size)
1604 case IXGBE_PCIE_GENERAL_PTR:
1605 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1607 case IXGBE_PCIE_CONFIG0_PTR:
1608 case IXGBE_PCIE_CONFIG1_PTR:
1609 size = IXGBE_PCIE_CONFIG_SIZE;
1616 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);
1621 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1623 return (s32)checksum;
1627 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1628 * @hw: pointer to hardware structure
1629 * @checksum_val: calculated checksum
1631 * Performs checksum calculation and validates the EEPROM checksum. If the
1632 * caller does not need checksum_val, the value can be NULL.
1634 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1638 u16 read_checksum = 0;
1640 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1642 /* Read the first word from the EEPROM. If this times out or fails, do
1643 * not continue or we could be in for a very long wait while every
1646 status = hw->eeprom.ops.read(hw, 0, &checksum);
1648 DEBUGOUT("EEPROM read failed\n");
1652 status = hw->eeprom.ops.calc_checksum(hw);
1656 checksum = (u16)(status & 0xffff);
1658 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1663 /* Verify read checksum from EEPROM is the same as
1664 * calculated checksum
1666 if (read_checksum != checksum) {
1667 status = IXGBE_ERR_EEPROM_CHECKSUM;
1668 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1669 "Invalid EEPROM checksum");
1672 /* If the user cares, return the calculated checksum */
1674 *checksum_val = checksum;
1680 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1681 * @hw: pointer to hardware structure
1683 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1684 * checksum and updates the EEPROM and instructs the hardware to update
1687 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1692 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1694 /* Read the first word from the EEPROM. If this times out or fails, do
1695 * not continue or we could be in for a very long wait while every
1698 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1700 DEBUGOUT("EEPROM read failed\n");
1704 status = ixgbe_calc_eeprom_checksum_X550(hw);
1708 checksum = (u16)(status & 0xffff);
1710 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1715 status = ixgbe_update_flash_X550(hw);
1721 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1722 * @hw: pointer to hardware structure
1724 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1726 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1728 s32 status = IXGBE_SUCCESS;
1729 struct ixgbe_hic_hdr2 buffer;
1731 DEBUGFUNC("ixgbe_update_flash_X550");
1733 buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1734 buffer.buf_len1 = 0;
1735 buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1736 buffer.checksum = FW_DEFAULT_CHECKSUM;
1738 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1739 sizeof(buffer), false);
1745 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
1746 * @hw: pointer to hardware structure
1748 * Determines physical layer capabilities of the current configuration.
1750 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
1752 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1754 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
1756 hw->phy.ops.identify(hw);
1758 switch (hw->phy.type) {
1759 case ixgbe_phy_x550em_kr:
1760 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
1761 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1763 case ixgbe_phy_x550em_kx4:
1764 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1765 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1771 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1772 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1774 return physical_layer;
1778 * ixgbe_get_bus_info_x550em - Set PCI bus info
1779 * @hw: pointer to hardware structure
1781 * Sets bus link width and speed to unknown because X550em is
1784 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1787 DEBUGFUNC("ixgbe_get_bus_info_x550em");
1789 hw->bus.width = ixgbe_bus_width_unknown;
1790 hw->bus.speed = ixgbe_bus_speed_unknown;
1792 return IXGBE_SUCCESS;
1796 * ixgbe_disable_rx_x550 - Disable RX unit
1798 * Enables the Rx DMA unit for x550
1800 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1802 u32 rxctrl, pfdtxgswc;
1804 struct ixgbe_hic_disable_rxen fw_cmd;
1806 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
1808 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1809 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1810 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1811 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1812 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1813 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1814 hw->mac.set_lben = true;
1816 hw->mac.set_lben = false;
1819 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1820 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1821 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1822 fw_cmd.port_number = hw->phy.lan_id;
1824 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1825 sizeof(struct ixgbe_hic_disable_rxen),
1828 /* If we fail - disable RX using register write */
1830 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1831 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1832 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1833 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);