1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
42 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
43 * @hw: pointer to hardware structure
45 * Initialize the function pointers and assign the MAC type for X550.
46 * Does not touch the hardware.
48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
50 struct ixgbe_mac_info *mac = &hw->mac;
51 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
54 DEBUGFUNC("ixgbe_init_ops_X550");
56 ret_val = ixgbe_init_ops_X540(hw);
57 mac->ops.dmac_config = ixgbe_dmac_config_X550;
58 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
59 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
60 mac->ops.setup_eee = ixgbe_setup_eee_X550;
61 mac->ops.set_source_address_pruning =
62 ixgbe_set_source_address_pruning_X550;
63 mac->ops.set_ethertype_anti_spoofing =
64 ixgbe_set_ethertype_anti_spoofing_X550;
66 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
67 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
68 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
69 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
70 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
71 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
72 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
73 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
74 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
76 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
77 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
78 mac->ops.mdd_event = ixgbe_mdd_event_X550;
79 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
80 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 * ixgbe_identify_phy_x550em - Get PHY type based on device id
86 * @hw: pointer to hardware structure
90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
92 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
94 switch (hw->device_id) {
95 case IXGBE_DEV_ID_X550EM_X_SFP:
96 /* set up for CS4227 usage */
97 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
98 IXGBE_STATUS_LAN_ID_1;
99 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
100 if (hw->phy.lan_id) {
102 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
103 esdp |= IXGBE_ESDP_SDP1_DIR;
105 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
106 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
108 return ixgbe_identify_module_generic(hw);
110 case IXGBE_DEV_ID_X550EM_X_KX4:
111 hw->phy.type = ixgbe_phy_x550em_kx4;
113 case IXGBE_DEV_ID_X550EM_X_KR:
114 case IXGBE_DEV_ID_X550EM_X:
115 hw->phy.type = ixgbe_phy_x550em_kr;
120 return IXGBE_SUCCESS;
123 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
124 u32 device_type, u16 *phy_data)
126 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
127 return IXGBE_NOT_IMPLEMENTED;
130 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
131 u32 device_type, u16 phy_data)
133 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
134 return IXGBE_NOT_IMPLEMENTED;
138 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
139 * @hw: pointer to hardware structure
141 * Initialize the function pointers and for MAC type X550EM.
142 * Does not touch the hardware.
144 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
146 struct ixgbe_mac_info *mac = &hw->mac;
147 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
148 struct ixgbe_phy_info *phy = &hw->phy;
151 DEBUGFUNC("ixgbe_init_ops_X550EM");
153 /* Similar to X550 so start there. */
154 ret_val = ixgbe_init_ops_X550(hw);
156 /* Since this function eventually calls
157 * ixgbe_init_ops_540 by design, we are setting
158 * the pointers to NULL explicitly here to overwrite
159 * the values being set in the x540 function.
161 /* Thermal sensor not supported in x550EM */
162 mac->ops.get_thermal_sensor_data = NULL;
163 mac->ops.init_thermal_sensor_thresh = NULL;
164 mac->thermal_sensor_enabled = false;
166 /* FCOE not supported in x550EM */
167 mac->ops.get_san_mac_addr = NULL;
168 mac->ops.set_san_mac_addr = NULL;
169 mac->ops.get_wwn_prefix = NULL;
170 mac->ops.get_fcoe_boot_status = NULL;
172 /* IPsec not supported in x550EM */
173 mac->ops.disable_sec_rx_path = NULL;
174 mac->ops.enable_sec_rx_path = NULL;
176 /* X550EM bus type is internal*/
177 hw->bus.type = ixgbe_bus_type_internal;
178 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
180 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
181 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
182 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
183 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
184 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
185 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
186 mac->ops.get_supported_physical_layer =
187 ixgbe_get_supported_physical_layer_X550em;
190 phy->ops.init = &ixgbe_init_phy_ops_X550em;
191 phy->ops.identify = &ixgbe_identify_phy_x550em;
192 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
193 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
194 phy->ops.setup_link = ixgbe_setup_kr_x550em;
198 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
199 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
200 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
201 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
202 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
203 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
204 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
205 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
211 * ixgbe_dmac_config_X550
212 * @hw: pointer to hardware structure
214 * Configure DMA coalescing. If enabling dmac, dmac is activated.
215 * When disabling dmac, dmac enable dmac bit is cleared.
217 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
219 u32 reg, high_pri_tc;
221 DEBUGFUNC("ixgbe_dmac_config_X550");
223 /* Disable DMA coalescing before configuring */
224 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
225 reg &= ~IXGBE_DMACR_DMAC_EN;
226 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
228 /* Disable DMA Coalescing if the watchdog timer is 0 */
229 if (!hw->mac.dmac_config.watchdog_timer)
232 ixgbe_dmac_config_tcs_X550(hw);
234 /* Configure DMA Coalescing Control Register */
235 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
237 /* Set the watchdog timer in units of 40.96 usec */
238 reg &= ~IXGBE_DMACR_DMACWT_MASK;
239 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
241 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
242 /* If fcoe is enabled, set high priority traffic class */
243 if (hw->mac.dmac_config.fcoe_en) {
244 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
245 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
246 IXGBE_DMACR_HIGH_PRI_TC_MASK);
248 reg |= IXGBE_DMACR_EN_MNG_IND;
250 /* Enable DMA coalescing after configuration */
251 reg |= IXGBE_DMACR_DMAC_EN;
252 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
255 return IXGBE_SUCCESS;
259 * ixgbe_dmac_config_tcs_X550
260 * @hw: pointer to hardware structure
262 * Configure DMA coalescing threshold per TC. The dmac enable bit must
263 * be cleared before configuring.
265 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
267 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
269 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
271 /* Configure DMA coalescing enabled */
272 switch (hw->mac.dmac_config.link_speed) {
273 case IXGBE_LINK_SPEED_100_FULL:
274 pb_headroom = IXGBE_DMACRXT_100M;
276 case IXGBE_LINK_SPEED_1GB_FULL:
277 pb_headroom = IXGBE_DMACRXT_1G;
280 pb_headroom = IXGBE_DMACRXT_10G;
284 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
285 IXGBE_MHADD_MFS_SHIFT) / 1024);
287 /* Set the per Rx packet buffer receive threshold */
288 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
289 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
290 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
292 if (tc < hw->mac.dmac_config.num_tcs) {
294 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
295 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
296 IXGBE_RXPBSIZE_SHIFT;
298 /* Calculate receive buffer threshold in kilobytes */
299 if (rx_pb_size > pb_headroom)
300 rx_pb_size = rx_pb_size - pb_headroom;
304 /* Minimum of MFS shall be set for DMCTH */
305 reg |= (rx_pb_size > maxframe_size_kb) ?
306 rx_pb_size : maxframe_size_kb;
308 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
310 return IXGBE_SUCCESS;
314 * ixgbe_dmac_update_tcs_X550
315 * @hw: pointer to hardware structure
317 * Disables dmac, updates per TC settings, and then enables dmac.
319 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
323 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
325 /* Disable DMA coalescing before configuring */
326 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
327 reg &= ~IXGBE_DMACR_DMAC_EN;
328 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
330 ixgbe_dmac_config_tcs_X550(hw);
332 /* Enable DMA coalescing after configuration */
333 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
334 reg |= IXGBE_DMACR_DMAC_EN;
335 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
337 return IXGBE_SUCCESS;
341 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
342 * @hw: pointer to hardware structure
344 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
345 * ixgbe_hw struct in order to set up EEPROM access.
347 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
349 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
353 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
355 if (eeprom->type == ixgbe_eeprom_uninitialized) {
356 eeprom->semaphore_delay = 10;
357 eeprom->type = ixgbe_flash;
359 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
360 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
361 IXGBE_EEC_SIZE_SHIFT);
362 eeprom->word_size = 1 << (eeprom_size +
363 IXGBE_EEPROM_WORD_SIZE_SHIFT);
365 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
366 eeprom->type, eeprom->word_size);
369 return IXGBE_SUCCESS;
373 * ixgbe_setup_eee_X550 - Enable/disable EEE support
374 * @hw: pointer to the HW structure
375 * @enable_eee: boolean flag to enable EEE
377 * Enable/disable EEE based on enable_eee flag.
378 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
382 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
389 DEBUGFUNC("ixgbe_setup_eee_X550");
391 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
392 /* Enable or disable EEE per flag */
394 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
396 if (hw->device_id == IXGBE_DEV_ID_X550T) {
397 /* Advertise EEE capability */
398 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
399 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
401 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
402 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
403 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
405 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
406 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
407 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
408 hw->device_id == IXGBE_DEV_ID_X550EM_X) {
409 status = ixgbe_read_iosf_sb_reg_x550(hw,
410 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
411 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
412 if (status != IXGBE_SUCCESS)
415 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
416 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
418 status = ixgbe_write_iosf_sb_reg_x550(hw,
419 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
420 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
421 if (status != IXGBE_SUCCESS)
425 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
427 if (hw->device_id == IXGBE_DEV_ID_X550T) {
428 /* Disable advertised EEE capability */
429 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
430 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
432 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
433 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
434 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
436 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
437 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
438 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
439 hw->device_id == IXGBE_DEV_ID_X550EM_X) {
440 status = ixgbe_read_iosf_sb_reg_x550(hw,
441 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
442 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
443 if (status != IXGBE_SUCCESS)
446 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
447 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
449 status = ixgbe_write_iosf_sb_reg_x550(hw,
450 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
451 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
452 if (status != IXGBE_SUCCESS)
456 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
458 return IXGBE_SUCCESS;
462 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
463 * @hw: pointer to hardware structure
464 * @enable: enable or disable source address pruning
465 * @pool: Rx pool to set source address pruning for
467 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
472 /* max rx pool is 63 */
476 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
477 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
480 pfflp |= (1ULL << pool);
482 pfflp &= ~(1ULL << pool);
484 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
485 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
489 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
490 * @hw: pointer to hardware structure
491 * @enable: enable or disable switch for Ethertype anti-spoofing
492 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
495 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
498 int vf_target_reg = vf >> 3;
499 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
502 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
504 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
506 pfvfspoof |= (1 << vf_target_shift);
508 pfvfspoof &= ~(1 << vf_target_shift);
510 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
514 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
516 * @hw: pointer to hardware structure
517 * @reg_addr: 32 bit PHY register to write
518 * @device_type: 3 bit device type
519 * @data: Data to write to the register
521 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
522 u32 device_type, u32 data)
524 u32 i, command, error;
526 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
527 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
529 /* Write IOSF control register */
530 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
532 /* Write IOSF data register */
533 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
535 * Check every 10 usec to see if the address cycle completed.
536 * The SB IOSF BUSY bit will clear when the operation is
539 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
542 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
543 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
547 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
548 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
549 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
550 ERROR_REPORT2(IXGBE_ERROR_POLLING,
551 "Failed to write, error %x\n", error);
552 return IXGBE_ERR_PHY;
555 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
556 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
557 return IXGBE_ERR_PHY;
560 return IXGBE_SUCCESS;
564 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
566 * @hw: pointer to hardware structure
567 * @reg_addr: 32 bit PHY register to write
568 * @device_type: 3 bit device type
569 * @phy_data: Pointer to read data from the register
571 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
572 u32 device_type, u32 *data)
574 u32 i, command, error;
576 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
577 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
579 /* Write IOSF control register */
580 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
583 * Check every 10 usec to see if the address cycle completed.
584 * The SB IOSF BUSY bit will clear when the operation is
587 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
590 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
591 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
595 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
596 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
597 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
598 ERROR_REPORT2(IXGBE_ERROR_POLLING,
599 "Failed to read, error %x\n", error);
600 return IXGBE_ERR_PHY;
603 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
604 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
605 return IXGBE_ERR_PHY;
608 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
610 return IXGBE_SUCCESS;
614 * ixgbe_disable_mdd_X550
615 * @hw: pointer to hardware structure
617 * Disable malicious driver detection
619 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
623 DEBUGFUNC("ixgbe_disable_mdd_X550");
625 /* Disable MDD for TX DMA and interrupt */
626 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
627 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
628 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
630 /* Disable MDD for RX and interrupt */
631 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
632 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
633 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
637 * ixgbe_enable_mdd_X550
638 * @hw: pointer to hardware structure
640 * Enable malicious driver detection
642 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
646 DEBUGFUNC("ixgbe_enable_mdd_X550");
648 /* Enable MDD for TX DMA and interrupt */
649 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
650 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
651 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
653 /* Enable MDD for RX and interrupt */
654 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
655 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
656 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
660 * ixgbe_restore_mdd_vf_X550
661 * @hw: pointer to hardware structure
664 * Restore VF that was disabled during malicious driver detection event
666 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
668 u32 idx, reg, num_qs, start_q, bitmask;
670 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
672 /* Map VF to queues */
673 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
674 switch (reg & IXGBE_MRQC_MRQE_MASK) {
675 case IXGBE_MRQC_VMDQRT8TCEN:
676 num_qs = 8; /* 16 VFs / pools */
677 bitmask = 0x000000FF;
679 case IXGBE_MRQC_VMDQRSS32EN:
680 case IXGBE_MRQC_VMDQRT4TCEN:
681 num_qs = 4; /* 32 VFs / pools */
682 bitmask = 0x0000000F;
684 default: /* 64 VFs / pools */
686 bitmask = 0x00000003;
689 start_q = vf * num_qs;
691 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
694 reg |= (bitmask << (start_q % 32));
695 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
696 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
700 * ixgbe_mdd_event_X550
701 * @hw: pointer to hardware structure
702 * @vf_bitmap: vf bitmap of malicious vfs
704 * Handle malicious driver detection event.
706 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
709 u32 i, j, reg, q, shift, vf, idx;
711 DEBUGFUNC("ixgbe_mdd_event_X550");
713 /* figure out pool size for mapping to vf's */
714 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
715 switch (reg & IXGBE_MRQC_MRQE_MASK) {
716 case IXGBE_MRQC_VMDQRT8TCEN:
717 shift = 3; /* 16 VFs / pools */
719 case IXGBE_MRQC_VMDQRSS32EN:
720 case IXGBE_MRQC_VMDQRT4TCEN:
721 shift = 2; /* 32 VFs / pools */
724 shift = 1; /* 64 VFs / pools */
728 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
729 for (i = 0; i < 4; i++) {
730 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
731 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
736 /* Get malicious queue */
737 for (j = 0; j < 32 && wqbr; j++) {
739 if (!(wqbr & (1 << j)))
742 /* Get queue from bitmask */
745 /* Map queue to vf */
748 /* Set vf bit in vf_bitmap */
750 vf_bitmap[idx] |= (1 << (vf % 32));
757 * ixgbe_get_media_type_X550em - Get media type
758 * @hw: pointer to hardware structure
760 * Returns the media type (fiber, copper, backplane)
762 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
764 enum ixgbe_media_type media_type;
766 DEBUGFUNC("ixgbe_get_media_type_X550em");
768 /* Detect if there is a copper PHY attached. */
769 switch (hw->device_id) {
770 case IXGBE_DEV_ID_X550EM_X:
771 case IXGBE_DEV_ID_X550EM_X_KR:
772 case IXGBE_DEV_ID_X550EM_X_KX4:
773 media_type = ixgbe_media_type_backplane;
775 case IXGBE_DEV_ID_X550EM_X_SFP:
776 media_type = ixgbe_media_type_fiber;
779 media_type = ixgbe_media_type_unknown;
786 * ixgbe_setup_sfp_modules_X550em - Setup SFP module
787 * @hw: pointer to hardware structure
789 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
792 u16 reg_slice, edc_mode;
795 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
797 switch (hw->phy.sfp_type) {
798 case ixgbe_sfp_type_unknown:
799 return IXGBE_SUCCESS;
800 case ixgbe_sfp_type_not_present:
801 return IXGBE_ERR_SFP_NOT_PRESENT;
802 case ixgbe_sfp_type_da_cu_core0:
803 case ixgbe_sfp_type_da_cu_core1:
806 case ixgbe_sfp_type_srlr_core0:
807 case ixgbe_sfp_type_srlr_core1:
808 case ixgbe_sfp_type_da_act_lmt_core0:
809 case ixgbe_sfp_type_da_act_lmt_core1:
810 case ixgbe_sfp_type_1g_sx_core0:
811 case ixgbe_sfp_type_1g_sx_core1:
812 case ixgbe_sfp_type_1g_lx_core0:
813 case ixgbe_sfp_type_1g_lx_core1:
814 setup_linear = false;
817 return IXGBE_ERR_SFP_NOT_SUPPORTED;
820 ixgbe_init_mac_link_ops_X550em(hw);
821 hw->phy.ops.reset = NULL;
823 /* The CS4227 slice address is the base address + the port-pair reg
824 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
826 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);
829 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
831 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
833 /* Configure CS4227 for connection type. */
834 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
837 if (ret_val != IXGBE_SUCCESS)
838 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
845 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
846 * @hw: pointer to hardware structure
848 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
850 struct ixgbe_mac_info *mac = &hw->mac;
852 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
854 /* CS4227 does not support autoneg, so disable the laser control
855 * functions for SFP+ fiber
857 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
858 mac->ops.disable_tx_laser = NULL;
859 mac->ops.enable_tx_laser = NULL;
860 mac->ops.flap_tx_laser = NULL;
865 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
866 * @hw: pointer to hardware structure
867 * @speed: pointer to link speed
868 * @autoneg: true when autoneg or autotry is enabled
870 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
871 ixgbe_link_speed *speed,
874 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
877 if (hw->phy.media_type == ixgbe_media_type_fiber) {
879 /* CS4227 SFP must not enable auto-negotiation */
882 /* Check if 1G SFP module. */
883 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
884 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
885 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
886 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
887 *speed = IXGBE_LINK_SPEED_1GB_FULL;
888 return IXGBE_SUCCESS;
891 /* Link capabilities are based on SFP */
892 if (hw->phy.multispeed_fiber)
893 *speed = IXGBE_LINK_SPEED_10GB_FULL |
894 IXGBE_LINK_SPEED_1GB_FULL;
896 *speed = IXGBE_LINK_SPEED_10GB_FULL;
898 *speed = IXGBE_LINK_SPEED_10GB_FULL |
899 IXGBE_LINK_SPEED_1GB_FULL;
903 return IXGBE_SUCCESS;
907 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
908 * @hw: pointer to hardware structure
910 * Initialize any function pointers that were not able to be
911 * set during init_shared_code because the PHY/SFP type was
912 * not known. Perform the SFP init if necessary.
914 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
916 struct ixgbe_phy_info *phy = &hw->phy;
920 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
922 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
923 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
924 phy->lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
925 IXGBE_STATUS_LAN_ID_1;
926 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
928 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
929 esdp |= IXGBE_ESDP_SDP1_DIR;
931 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
932 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
935 /* Identify the PHY or SFP module */
936 ret_val = phy->ops.identify(hw);
937 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
940 /* Setup function pointers based on detected SFP module and speeds */
941 ixgbe_init_mac_link_ops_X550em(hw);
942 if (phy->sfp_type != ixgbe_sfp_type_unknown)
943 phy->ops.reset = NULL;
945 /* Set functions pointers based on phy type */
946 switch (hw->phy.type) {
947 case ixgbe_phy_x550em_kr:
948 phy->ops.setup_link = ixgbe_setup_kr_x550em;
957 * ixgbe_reset_hw_X550em - Perform hardware reset
958 * @hw: pointer to hardware structure
960 * Resets the hardware by resetting the transmit and receive units, masks
961 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
964 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
966 ixgbe_link_speed link_speed;
970 bool link_up = false;
972 DEBUGFUNC("ixgbe_reset_hw_X550em");
974 /* Call adapter stop to disable Tx/Rx and clear interrupts */
975 status = hw->mac.ops.stop_adapter(hw);
976 if (status != IXGBE_SUCCESS)
979 /* flush pending Tx transactions */
980 ixgbe_clear_tx_pending(hw);
982 /* PHY ops must be identified and initialized prior to reset */
984 /* Identify PHY and related function pointers */
985 status = hw->phy.ops.init(hw);
987 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
990 /* Setup SFP module if there is one present. */
991 if (hw->phy.sfp_setup_needed) {
992 status = hw->mac.ops.setup_sfp(hw);
993 hw->phy.sfp_setup_needed = false;
996 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1000 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1001 hw->phy.ops.reset(hw);
1004 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1005 * If link reset is used when link is up, it might reset the PHY when
1006 * mng is using it. If link is down or the flag to force full link
1007 * reset is set, then perform link reset.
1009 ctrl = IXGBE_CTRL_LNK_RST;
1010 if (!hw->force_full_reset) {
1011 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1013 ctrl = IXGBE_CTRL_RST;
1016 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1017 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1018 IXGBE_WRITE_FLUSH(hw);
1020 /* Poll for reset bit to self-clear meaning reset is complete */
1021 for (i = 0; i < 10; i++) {
1023 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1024 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1028 if (ctrl & IXGBE_CTRL_RST_MASK) {
1029 status = IXGBE_ERR_RESET_FAILED;
1030 DEBUGOUT("Reset polling failed to complete.\n");
1035 /* Double resets are required for recovery from certain error
1036 * conditions. Between resets, it is necessary to stall to
1037 * allow time for any pending HW events to complete.
1039 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1040 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1044 /* Store the permanent mac address */
1045 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1047 /* Store MAC address from RAR0, clear receive address registers, and
1048 * clear the multicast table. Also reset num_rar_entries to 128,
1049 * since we modify this value when programming the SAN MAC address.
1051 hw->mac.num_rar_entries = 128;
1052 hw->mac.ops.init_rx_addrs(hw);
1058 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1059 * @hw: pointer to hardware structure
1061 * Configures the integrated KR PHY.
1063 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1068 status = ixgbe_read_iosf_sb_reg_x550(hw,
1069 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1070 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1074 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1075 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1076 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1077 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1078 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1080 /* Advertise 10G support. */
1081 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1082 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1084 /* Advertise 1G support. */
1085 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1086 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1088 /* Restart auto-negotiation. */
1089 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1090 status = ixgbe_write_iosf_sb_reg_x550(hw,
1091 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1092 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1098 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
1099 * @hw: pointer to hardware structure
1101 * Configures the integrated KR PHY to use iXFI mode.
1103 s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
1108 /* Disable AN and force speed to 10G Serial. */
1109 status = ixgbe_read_iosf_sb_reg_x550(hw,
1110 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1111 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1112 if (status != IXGBE_SUCCESS)
1114 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1115 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1116 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1117 status = ixgbe_write_iosf_sb_reg_x550(hw,
1118 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1119 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1120 if (status != IXGBE_SUCCESS)
1123 /* Disable training protocol FSM. */
1124 status = ixgbe_read_iosf_sb_reg_x550(hw,
1125 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1126 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1127 if (status != IXGBE_SUCCESS)
1129 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1130 status = ixgbe_write_iosf_sb_reg_x550(hw,
1131 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1132 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1133 if (status != IXGBE_SUCCESS)
1136 /* Disable Flex from training TXFFE. */
1137 status = ixgbe_read_iosf_sb_reg_x550(hw,
1138 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1139 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1140 if (status != IXGBE_SUCCESS)
1142 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1143 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1144 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1145 status = ixgbe_write_iosf_sb_reg_x550(hw,
1146 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1147 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1148 if (status != IXGBE_SUCCESS)
1150 status = ixgbe_read_iosf_sb_reg_x550(hw,
1151 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1152 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1153 if (status != IXGBE_SUCCESS)
1155 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1156 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1157 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1158 status = ixgbe_write_iosf_sb_reg_x550(hw,
1159 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1160 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1161 if (status != IXGBE_SUCCESS)
1164 /* Enable override for coefficients. */
1165 status = ixgbe_read_iosf_sb_reg_x550(hw,
1166 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1167 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1168 if (status != IXGBE_SUCCESS)
1170 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1171 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1172 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1173 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1174 status = ixgbe_write_iosf_sb_reg_x550(hw,
1175 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1176 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1177 if (status != IXGBE_SUCCESS)
1180 /* Toggle port SW reset by AN reset. */
1181 status = ixgbe_read_iosf_sb_reg_x550(hw,
1182 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1183 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1184 if (status != IXGBE_SUCCESS)
1186 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1187 status = ixgbe_write_iosf_sb_reg_x550(hw,
1188 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1189 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1195 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1196 * @hw: pointer to hardware structure
1198 * Configures the integrated KR PHY to use internal loopback mode.
1200 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1205 /* Disable AN and force speed to 10G Serial. */
1206 status = ixgbe_read_iosf_sb_reg_x550(hw,
1207 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1208 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1209 if (status != IXGBE_SUCCESS)
1211 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1212 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1213 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1214 status = ixgbe_write_iosf_sb_reg_x550(hw,
1215 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1216 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1217 if (status != IXGBE_SUCCESS)
1220 /* Set near-end loopback clocks. */
1221 status = ixgbe_read_iosf_sb_reg_x550(hw,
1222 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1223 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1224 if (status != IXGBE_SUCCESS)
1226 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1227 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1228 status = ixgbe_write_iosf_sb_reg_x550(hw,
1229 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1230 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1231 if (status != IXGBE_SUCCESS)
1234 /* Set loopback enable. */
1235 status = ixgbe_read_iosf_sb_reg_x550(hw,
1236 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1237 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1238 if (status != IXGBE_SUCCESS)
1240 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1241 status = ixgbe_write_iosf_sb_reg_x550(hw,
1242 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1243 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1244 if (status != IXGBE_SUCCESS)
1247 /* Training bypass. */
1248 status = ixgbe_read_iosf_sb_reg_x550(hw,
1249 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1250 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1251 if (status != IXGBE_SUCCESS)
1253 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1254 status = ixgbe_write_iosf_sb_reg_x550(hw,
1255 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1256 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1262 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1263 * assuming that the semaphore is already obtained.
1264 * @hw: pointer to hardware structure
1265 * @offset: offset of word in the EEPROM to read
1266 * @data: word read from the EEPROM
1268 * Reads a 16 bit word from the EEPROM using the hostif.
1270 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1274 struct ixgbe_hic_read_shadow_ram buffer;
1276 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1277 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1278 buffer.hdr.buf_len1 = 0;
1279 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1280 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1282 /* convert offset from words to bytes */
1283 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1285 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1287 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1288 sizeof(buffer), false);
1293 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1294 FW_NVM_DATA_OFFSET);
1300 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1301 * @hw: pointer to hardware structure
1302 * @offset: offset of word in the EEPROM to read
1303 * @data: word read from the EEPROM
1305 * Reads a 16 bit word from the EEPROM using the hostif.
1307 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1310 s32 status = IXGBE_SUCCESS;
1312 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1314 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1316 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1317 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1319 status = IXGBE_ERR_SWFW_SYNC;
1326 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1327 * @hw: pointer to hardware structure
1328 * @offset: offset of word in the EEPROM to read
1329 * @words: number of words
1330 * @data: word(s) read from the EEPROM
1332 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1334 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1335 u16 offset, u16 words, u16 *data)
1337 struct ixgbe_hic_read_shadow_ram buffer;
1338 u32 current_word = 0;
1343 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1345 /* Take semaphore for the entire operation. */
1346 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1348 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1352 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1353 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1355 words_to_read = words;
1357 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1358 buffer.hdr.buf_len1 = 0;
1359 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1360 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1362 /* convert offset from words to bytes */
1363 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1364 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1366 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1367 sizeof(buffer), false);
1370 DEBUGOUT("Host interface command failed\n");
1374 for (i = 0; i < words_to_read; i++) {
1375 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1377 u32 value = IXGBE_READ_REG(hw, reg);
1379 data[current_word] = (u16)(value & 0xffff);
1382 if (i < words_to_read) {
1384 data[current_word] = (u16)(value & 0xffff);
1388 words -= words_to_read;
1392 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1397 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1398 * @hw: pointer to hardware structure
1399 * @offset: offset of word in the EEPROM to write
1400 * @data: word write to the EEPROM
1402 * Write a 16 bit word to the EEPROM using the hostif.
1404 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1408 struct ixgbe_hic_write_shadow_ram buffer;
1410 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1412 buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1413 buffer.hdr.buf_len1 = 0;
1414 buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1415 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1418 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1420 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1422 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1423 sizeof(buffer), false);
1429 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1430 * @hw: pointer to hardware structure
1431 * @offset: offset of word in the EEPROM to write
1432 * @data: word write to the EEPROM
1434 * Write a 16 bit word to the EEPROM using the hostif.
1436 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1439 s32 status = IXGBE_SUCCESS;
1441 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1443 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1445 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1446 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1448 DEBUGOUT("write ee hostif failed to get semaphore");
1449 status = IXGBE_ERR_SWFW_SYNC;
1456 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1457 * @hw: pointer to hardware structure
1458 * @offset: offset of word in the EEPROM to write
1459 * @words: number of words
1460 * @data: word(s) write to the EEPROM
1462 * Write a 16 bit word(s) to the EEPROM using the hostif.
1464 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1465 u16 offset, u16 words, u16 *data)
1467 s32 status = IXGBE_SUCCESS;
1470 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1472 /* Take semaphore for the entire operation. */
1473 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1474 if (status != IXGBE_SUCCESS) {
1475 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1479 for (i = 0; i < words; i++) {
1480 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1483 if (status != IXGBE_SUCCESS) {
1484 DEBUGOUT("Eeprom buffered write failed\n");
1489 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1496 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1497 * @hw: pointer to hardware structure
1498 * @ptr: pointer offset in eeprom
1499 * @size: size of section pointed by ptr, if 0 first word will be used as size
1500 * @csum: address of checksum to update
1502 * Returns error status for any failure
1504 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1505 u16 size, u16 *csum)
1509 u16 length, bufsz, i, start;
1511 bufsz = sizeof(buf) / sizeof(buf[0]);
1513 /* Read a chunk at the pointer location */
1514 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1516 DEBUGOUT("Failed to read EEPROM image\n");
1527 /* Skip pointer section if length is invalid. */
1528 if (length == 0xFFFF || length == 0 ||
1529 (ptr + length) >= hw->eeprom.word_size)
1530 return IXGBE_SUCCESS;
1533 for (i = start; length; i++, length--) {
1540 /* Read a chunk at the pointer location */
1541 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1544 DEBUGOUT("Failed to read EEPROM image\n");
1550 return IXGBE_SUCCESS;
1554 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1555 * @hw: pointer to hardware structure
1557 * Returns a negative error code on error, or the 16-bit checksum
1559 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1561 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1564 u16 pointer, i, size;
1566 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1568 hw->eeprom.ops.init_params(hw);
1570 /* Read pointer area */
1571 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1572 IXGBE_EEPROM_LAST_WORD + 1,
1575 DEBUGOUT("Failed to read EEPROM image\n");
1580 * For X550 hardware include 0x0-0x41 in the checksum, skip the
1581 * checksum word itself
1583 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1584 if (i != IXGBE_EEPROM_CHECKSUM)
1585 checksum += eeprom_ptrs[i];
1588 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
1589 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1591 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1592 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1595 pointer = eeprom_ptrs[i];
1597 /* Skip pointer section if the pointer is invalid. */
1598 if (pointer == 0xFFFF || pointer == 0 ||
1599 pointer >= hw->eeprom.word_size)
1603 case IXGBE_PCIE_GENERAL_PTR:
1604 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1606 case IXGBE_PCIE_CONFIG0_PTR:
1607 case IXGBE_PCIE_CONFIG1_PTR:
1608 size = IXGBE_PCIE_CONFIG_SIZE;
1615 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);
1620 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1622 return (s32)checksum;
1626 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1627 * @hw: pointer to hardware structure
1628 * @checksum_val: calculated checksum
1630 * Performs checksum calculation and validates the EEPROM checksum. If the
1631 * caller does not need checksum_val, the value can be NULL.
1633 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1637 u16 read_checksum = 0;
1639 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1641 /* Read the first word from the EEPROM. If this times out or fails, do
1642 * not continue or we could be in for a very long wait while every
1645 status = hw->eeprom.ops.read(hw, 0, &checksum);
1647 DEBUGOUT("EEPROM read failed\n");
1651 status = hw->eeprom.ops.calc_checksum(hw);
1655 checksum = (u16)(status & 0xffff);
1657 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1662 /* Verify read checksum from EEPROM is the same as
1663 * calculated checksum
1665 if (read_checksum != checksum) {
1666 status = IXGBE_ERR_EEPROM_CHECKSUM;
1667 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1668 "Invalid EEPROM checksum");
1671 /* If the user cares, return the calculated checksum */
1673 *checksum_val = checksum;
1679 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1680 * @hw: pointer to hardware structure
1682 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1683 * checksum and updates the EEPROM and instructs the hardware to update
1686 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1691 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1693 /* Read the first word from the EEPROM. If this times out or fails, do
1694 * not continue or we could be in for a very long wait while every
1697 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1699 DEBUGOUT("EEPROM read failed\n");
1703 status = ixgbe_calc_eeprom_checksum_X550(hw);
1707 checksum = (u16)(status & 0xffff);
1709 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1714 status = ixgbe_update_flash_X550(hw);
1720 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1721 * @hw: pointer to hardware structure
1723 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1725 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1727 s32 status = IXGBE_SUCCESS;
1728 struct ixgbe_hic_hdr2 buffer;
1730 DEBUGFUNC("ixgbe_update_flash_X550");
1732 buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1733 buffer.buf_len1 = 0;
1734 buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1735 buffer.checksum = FW_DEFAULT_CHECKSUM;
1737 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1738 sizeof(buffer), false);
1744 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
1745 * @hw: pointer to hardware structure
1747 * Determines physical layer capabilities of the current configuration.
1749 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
1751 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1753 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
1755 hw->phy.ops.identify(hw);
1757 switch (hw->phy.type) {
1758 case ixgbe_phy_x550em_kr:
1759 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
1760 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1762 case ixgbe_phy_x550em_kx4:
1763 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1764 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1770 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1771 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1773 return physical_layer;
1777 * ixgbe_get_bus_info_x550em - Set PCI bus info
1778 * @hw: pointer to hardware structure
1780 * Sets bus link width and speed to unknown because X550em is
1783 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1786 DEBUGFUNC("ixgbe_get_bus_info_x550em");
1788 hw->bus.width = ixgbe_bus_width_unknown;
1789 hw->bus.speed = ixgbe_bus_speed_unknown;
1791 return IXGBE_SUCCESS;
1795 * ixgbe_disable_rx_x550 - Disable RX unit
1797 * Enables the Rx DMA unit for x550
1799 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1801 u32 rxctrl, pfdtxgswc;
1803 struct ixgbe_hic_disable_rxen fw_cmd;
1805 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
1807 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1808 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1809 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1810 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1811 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1812 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1813 hw->mac.set_lben = true;
1815 hw->mac.set_lben = false;
1818 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1819 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1820 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1821 fw_cmd.port_number = hw->phy.lan_id;
1823 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1824 sizeof(struct ixgbe_hic_disable_rxen),
1827 /* If we fail - disable RX using register write */
1829 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1830 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1831 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1832 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);