lib/librte_pmd_ixgbe/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 /**
  42  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  43  *  @hw: pointer to hardware structure
  44  *
  45  *  Initialize the function pointers and assign the MAC type for X550.
  46  *  Does not touch the hardware.
  47  **/
  48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  49 {
  50         struct ixgbe_mac_info *mac = &hw->mac;
  51         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  52         s32 ret_val;
  53
  54         DEBUGFUNC("ixgbe_init_ops_X550");
  55
  56         ret_val = ixgbe_init_ops_X540(hw);
  57         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  58         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  59         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  60         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  61         mac->ops.set_source_address_pruning =
  62                         ixgbe_set_source_address_pruning_X550;
  63         mac->ops.set_ethertype_anti_spoofing =
  64                         ixgbe_set_ethertype_anti_spoofing_X550;
  65
  66         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  67         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  68         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  69         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  70         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  71         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  72         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  73         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  74         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  75
  76         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  77         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  78         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  79         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  80         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  81         return ret_val;
  82 }
  83
  84 /**
  85  * ixgbe_identify_phy_x550em - Get PHY type based on device id
  86  * @hw: pointer to hardware structure
  87  *
  88  * Returns error code
  89  */
  90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
  91 {
  92         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  93
  94         switch (hw->device_id) {
  95         case IXGBE_DEV_ID_X550EM_X_SFP:
  96                 /* set up for CS4227 usage */
  97                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
  98                                  IXGBE_STATUS_LAN_ID_1;
  99                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 100                 if (hw->phy.lan_id) {
 101
 102                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 103                         esdp |= IXGBE_ESDP_SDP1_DIR;
 104                 }
 105                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 106                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 107
 108                 return ixgbe_identify_module_generic(hw);
 109                 break;
 110         case IXGBE_DEV_ID_X550EM_X_KX4:
 111                 hw->phy.type = ixgbe_phy_x550em_kx4;
 112                 break;
 113         case IXGBE_DEV_ID_X550EM_X_KR:
 114         case IXGBE_DEV_ID_X550EM_X:
 115                 hw->phy.type = ixgbe_phy_x550em_kr;
 116                 break;
 117         default:
 118                 break;
 119         }
 120         return IXGBE_SUCCESS;
 121 }
 122
 123 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 124                                      u32 device_type, u16 *phy_data)
 125 {
 126         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 127         return IXGBE_NOT_IMPLEMENTED;
 128 }
 129
 130 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 131                                       u32 device_type, u16 phy_data)
 132 {
 133         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 134         return IXGBE_NOT_IMPLEMENTED;
 135 }
 136
 137 /**
 138 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 139 *  @hw: pointer to hardware structure
 140 *
 141 *  Initialize the function pointers and for MAC type X550EM.
 142 *  Does not touch the hardware.
 143 **/
 144 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 145 {
 146         struct ixgbe_mac_info *mac = &hw->mac;
 147         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 148         struct ixgbe_phy_info *phy = &hw->phy;
 149         s32 ret_val;
 150
 151         DEBUGFUNC("ixgbe_init_ops_X550EM");
 152
 153         /* Similar to X550 so start there. */
 154         ret_val = ixgbe_init_ops_X550(hw);
 155
 156         /* Since this function eventually calls
 157          * ixgbe_init_ops_540 by design, we are setting
 158          * the pointers to NULL explicitly here to overwrite
 159          * the values being set in the x540 function.
 160          */
 161         /* Thermal sensor not supported in x550EM */
 162         mac->ops.get_thermal_sensor_data = NULL;
 163         mac->ops.init_thermal_sensor_thresh = NULL;
 164         mac->thermal_sensor_enabled = false;
 165
 166         /* FCOE not supported in x550EM */
 167         mac->ops.get_san_mac_addr = NULL;
 168         mac->ops.set_san_mac_addr = NULL;
 169         mac->ops.get_wwn_prefix = NULL;
 170         mac->ops.get_fcoe_boot_status = NULL;
 171
 172         /* IPsec not supported in x550EM */
 173         mac->ops.disable_sec_rx_path = NULL;
 174         mac->ops.enable_sec_rx_path = NULL;
 175
 176         /* X550EM bus type is internal*/
 177         hw->bus.type = ixgbe_bus_type_internal;
 178         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 179
 180         mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 181         mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 182         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 183         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 184         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 185         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 186         mac->ops.get_supported_physical_layer =
 187                                     ixgbe_get_supported_physical_layer_X550em;
 188
 189         /* PHY */
 190         phy->ops.init = &ixgbe_init_phy_ops_X550em;
 191         phy->ops.identify = &ixgbe_identify_phy_x550em;
 192         phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
 193         phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
 194         phy->ops.setup_link = ixgbe_setup_kr_x550em;
 195
 196
 197         /* EEPROM */
 198         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 199         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 200         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 201         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 202         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 203         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 204         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 205         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 206
 207         return ret_val;
 208 }
 209
 210 /**
 211  *  ixgbe_dmac_config_X550
 212  *  @hw: pointer to hardware structure
 213  *
 214  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 215  *  When disabling dmac, dmac enable dmac bit is cleared.
 216  **/
 217 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 218 {
 219         u32 reg, high_pri_tc;
 220
 221         DEBUGFUNC("ixgbe_dmac_config_X550");
 222
 223         /* Disable DMA coalescing before configuring */
 224         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 225         reg &= ~IXGBE_DMACR_DMAC_EN;
 226         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 227
 228         /* Disable DMA Coalescing if the watchdog timer is 0 */
 229         if (!hw->mac.dmac_config.watchdog_timer)
 230                 goto out;
 231
 232         ixgbe_dmac_config_tcs_X550(hw);
 233
 234         /* Configure DMA Coalescing Control Register */
 235         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 236
 237         /* Set the watchdog timer in units of 40.96 usec */
 238         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 239         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 240
 241         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 242         /* If fcoe is enabled, set high priority traffic class */
 243         if (hw->mac.dmac_config.fcoe_en) {
 244                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 245                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 246                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 247         }
 248         reg |= IXGBE_DMACR_EN_MNG_IND;
 249
 250         /* Enable DMA coalescing after configuration */
 251         reg |= IXGBE_DMACR_DMAC_EN;
 252         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 253
 254 out:
 255         return IXGBE_SUCCESS;
 256 }
 257
 258 /**
 259  *  ixgbe_dmac_config_tcs_X550
 260  *  @hw: pointer to hardware structure
 261  *
 262  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 263  *  be cleared before configuring.
 264  **/
 265 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 266 {
 267         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 268
 269         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 270
 271         /* Configure DMA coalescing enabled */
 272         switch (hw->mac.dmac_config.link_speed) {
 273         case IXGBE_LINK_SPEED_100_FULL:
 274                 pb_headroom = IXGBE_DMACRXT_100M;
 275                 break;
 276         case IXGBE_LINK_SPEED_1GB_FULL:
 277                 pb_headroom = IXGBE_DMACRXT_1G;
 278                 break;
 279         default:
 280                 pb_headroom = IXGBE_DMACRXT_10G;
 281                 break;
 282         }
 283
 284         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 285                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 286
 287         /* Set the per Rx packet buffer receive threshold */
 288         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 289                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 290                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 291
 292                 if (tc < hw->mac.dmac_config.num_tcs) {
 293                         /* Get Rx PB size */
 294                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 295                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 296                                 IXGBE_RXPBSIZE_SHIFT;
 297
 298                         /* Calculate receive buffer threshold in kilobytes */
 299                         if (rx_pb_size > pb_headroom)
 300                                 rx_pb_size = rx_pb_size - pb_headroom;
 301                         else
 302                                 rx_pb_size = 0;
 303
 304                         /* Minimum of MFS shall be set for DMCTH */
 305                         reg |= (rx_pb_size > maxframe_size_kb) ?
 306                                 rx_pb_size : maxframe_size_kb;
 307                 }
 308                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 309         }
 310         return IXGBE_SUCCESS;
 311 }
 312
 313 /**
 314  *  ixgbe_dmac_update_tcs_X550
 315  *  @hw: pointer to hardware structure
 316  *
 317  *  Disables dmac, updates per TC settings, and then enables dmac.
 318  **/
 319 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 320 {
 321         u32 reg;
 322
 323         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 324
 325         /* Disable DMA coalescing before configuring */
 326         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 327         reg &= ~IXGBE_DMACR_DMAC_EN;
 328         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 329
 330         ixgbe_dmac_config_tcs_X550(hw);
 331
 332         /* Enable DMA coalescing after configuration */
 333         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 334         reg |= IXGBE_DMACR_DMAC_EN;
 335         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 336
 337         return IXGBE_SUCCESS;
 338 }
 339
 340 /**
 341  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 342  *  @hw: pointer to hardware structure
 343  *
 344  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 345  *  ixgbe_hw struct in order to set up EEPROM access.
 346  **/
 347 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 348 {
 349         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 350         u32 eec;
 351         u16 eeprom_size;
 352
 353         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 354
 355         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 356                 eeprom->semaphore_delay = 10;
 357                 eeprom->type = ixgbe_flash;
 358
 359                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 360                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 361                                     IXGBE_EEC_SIZE_SHIFT);
 362                 eeprom->word_size = 1 << (eeprom_size +
 363                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 364
 365                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 366                           eeprom->type, eeprom->word_size);
 367         }
 368
 369         return IXGBE_SUCCESS;
 370 }
 371
 372 /**
 373  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 374  *  @hw: pointer to the HW structure
 375  *  @enable_eee: boolean flag to enable EEE
 376  *
 377  *  Enable/disable EEE based on enable_eee flag.
 378  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 379  *  are modified.
 380  *
 381  **/
 382 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 383 {
 384         u32 eeer;
 385         u16 autoneg_eee_reg;
 386         u32 link_reg;
 387         s32 status;
 388
 389         DEBUGFUNC("ixgbe_setup_eee_X550");
 390
 391         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 392         /* Enable or disable EEE per flag */
 393         if (enable_eee) {
 394                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 395
 396                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 397                         /* Advertise EEE capability */
 398                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 399                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 400
 401                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 402                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 403                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 404
 405                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 406                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 407                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 408                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 409                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 410                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 411                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 412                         if (status != IXGBE_SUCCESS)
 413                                 return status;
 414
 415                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 416                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 417
 418                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 419                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 420                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 421                         if (status != IXGBE_SUCCESS)
 422                                 return status;
 423                 }
 424         } else {
 425                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 426
 427                 if (hw->device_id == IXGBE_DEV_ID_X550T) {
 428                         /* Disable advertised EEE capability */
 429                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 430                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 431
 432                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 433                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 434                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 435
 436                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 437                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 438                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
 439                            hw->device_id == IXGBE_DEV_ID_X550EM_X) {
 440                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 441                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 442                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 443                         if (status != IXGBE_SUCCESS)
 444                                 return status;
 445
 446                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 447                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 448
 449                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 450                                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
 451                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 452                         if (status != IXGBE_SUCCESS)
 453                                 return status;
 454                 }
 455         }
 456         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 457
 458         return IXGBE_SUCCESS;
 459 }
 460
 461 /**
 462  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 463  * @hw: pointer to hardware structure
 464  * @enable: enable or disable source address pruning
 465  * @pool: Rx pool to set source address pruning for
 466  **/
 467 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 468                                            unsigned int pool)
 469 {
 470         u64 pfflp;
 471
 472         /* max rx pool is 63 */
 473         if (pool > 63)
 474                 return;
 475
 476         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 477         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 478
 479         if (enable)
 480                 pfflp |= (1ULL << pool);
 481         else
 482                 pfflp &= ~(1ULL << pool);
 483
 484         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 485         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 486 }
 487
 488 /**
 489  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 490  *  @hw: pointer to hardware structure
 491  *  @enable: enable or disable switch for Ethertype anti-spoofing
 492  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 493  *
 494  **/
 495 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 496                 bool enable, int vf)
 497 {
 498         int vf_target_reg = vf >> 3;
 499         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 500         u32 pfvfspoof;
 501
 502         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 503
 504         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 505         if (enable)
 506                 pfvfspoof |= (1 << vf_target_shift);
 507         else
 508                 pfvfspoof &= ~(1 << vf_target_shift);
 509
 510         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 511 }
 512
 513 /**
 514  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 515  *  device
 516  *  @hw: pointer to hardware structure
 517  *  @reg_addr: 32 bit PHY register to write
 518  *  @device_type: 3 bit device type
 519  *  @data: Data to write to the register
 520  **/
 521 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 522                             u32 device_type, u32 data)
 523 {
 524         u32 i, command, error;
 525
 526         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 527                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 528
 529         /* Write IOSF control register */
 530         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 531
 532         /* Write IOSF data register */
 533         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 534         /*
 535          * Check every 10 usec to see if the address cycle completed.
 536          * The SB IOSF BUSY bit will clear when the operation is
 537          * complete
 538          */
 539         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 540                 usec_delay(10);
 541
 542                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 543                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 544                         break;
 545         }
 546
 547         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 548                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 549                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 550                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 551                               "Failed to write, error %x\n", error);
 552                 return IXGBE_ERR_PHY;
 553         }
 554
 555         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 556                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
 557                 return IXGBE_ERR_PHY;
 558         }
 559
 560         return IXGBE_SUCCESS;
 561 }
 562
 563 /**
 564  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 565  *  device
 566  *  @hw: pointer to hardware structure
 567  *  @reg_addr: 32 bit PHY register to write
 568  *  @device_type: 3 bit device type
 569  *  @phy_data: Pointer to read data from the register
 570  **/
 571 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 572                            u32 device_type, u32 *data)
 573 {
 574         u32 i, command, error;
 575
 576         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 577                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 578
 579         /* Write IOSF control register */
 580         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 581
 582         /*
 583          * Check every 10 usec to see if the address cycle completed.
 584          * The SB IOSF BUSY bit will clear when the operation is
 585          * complete
 586          */
 587         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 588                 usec_delay(10);
 589
 590                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 591                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 592                         break;
 593         }
 594
 595         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 596                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 597                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 598                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 599                                 "Failed to read, error %x\n", error);
 600                 return IXGBE_ERR_PHY;
 601         }
 602
 603         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 604                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
 605                 return IXGBE_ERR_PHY;
 606         }
 607
 608         *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 609
 610         return IXGBE_SUCCESS;
 611 }
 612
 613 /**
 614  *  ixgbe_disable_mdd_X550
 615  *  @hw: pointer to hardware structure
 616  *
 617  *  Disable malicious driver detection
 618  **/
 619 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
 620 {
 621         u32 reg;
 622
 623         DEBUGFUNC("ixgbe_disable_mdd_X550");
 624
 625         /* Disable MDD for TX DMA and interrupt */
 626         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 627         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 628         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 629
 630         /* Disable MDD for RX and interrupt */
 631         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 632         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 633         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 634 }
 635
 636 /**
 637  *  ixgbe_enable_mdd_X550
 638  *  @hw: pointer to hardware structure
 639  *
 640  *  Enable malicious driver detection
 641  **/
 642 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
 643 {
 644         u32 reg;
 645
 646         DEBUGFUNC("ixgbe_enable_mdd_X550");
 647
 648         /* Enable MDD for TX DMA and interrupt */
 649         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
 650         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
 651         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
 652
 653         /* Enable MDD for RX and interrupt */
 654         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 655         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
 656         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
 657 }
 658
 659 /**
 660  *  ixgbe_restore_mdd_vf_X550
 661  *  @hw: pointer to hardware structure
 662  *  @vf: vf index
 663  *
 664  *  Restore VF that was disabled during malicious driver detection event
 665  **/
 666 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
 667 {
 668         u32 idx, reg, num_qs, start_q, bitmask;
 669
 670         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
 671
 672         /* Map VF to queues */
 673         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 674         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 675         case IXGBE_MRQC_VMDQRT8TCEN:
 676                 num_qs = 8;  /* 16 VFs / pools */
 677                 bitmask = 0x000000FF;
 678                 break;
 679         case IXGBE_MRQC_VMDQRSS32EN:
 680         case IXGBE_MRQC_VMDQRT4TCEN:
 681                 num_qs = 4;  /* 32 VFs / pools */
 682                 bitmask = 0x0000000F;
 683                 break;
 684         default:            /* 64 VFs / pools */
 685                 num_qs = 2;
 686                 bitmask = 0x00000003;
 687                 break;
 688         }
 689         start_q = vf * num_qs;
 690
 691         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
 692         idx = start_q / 32;
 693         reg = 0;
 694         reg |= (bitmask << (start_q % 32));
 695         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
 696         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
 697 }
 698
 699 /**
 700  *  ixgbe_mdd_event_X550
 701  *  @hw: pointer to hardware structure
 702  *  @vf_bitmap: vf bitmap of malicious vfs
 703  *
 704  *  Handle malicious driver detection event.
 705  **/
 706 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
 707 {
 708         u32 wqbr;
 709         u32 i, j, reg, q, shift, vf, idx;
 710
 711         DEBUGFUNC("ixgbe_mdd_event_X550");
 712
 713         /* figure out pool size for mapping to vf's */
 714         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
 715         switch (reg & IXGBE_MRQC_MRQE_MASK) {
 716         case IXGBE_MRQC_VMDQRT8TCEN:
 717                 shift = 3;  /* 16 VFs / pools */
 718                 break;
 719         case IXGBE_MRQC_VMDQRSS32EN:
 720         case IXGBE_MRQC_VMDQRT4TCEN:
 721                 shift = 2;  /* 32 VFs / pools */
 722                 break;
 723         default:
 724                 shift = 1;  /* 64 VFs / pools */
 725                 break;
 726         }
 727
 728         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
 729         for (i = 0; i < 4; i++) {
 730                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
 731                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
 732
 733                 if (!wqbr)
 734                         continue;
 735
 736                 /* Get malicious queue */
 737                 for (j = 0; j < 32 && wqbr; j++) {
 738
 739                         if (!(wqbr & (1 << j)))
 740                                 continue;
 741
 742                         /* Get queue from bitmask */
 743                         q = j + (i * 32);
 744
 745                         /* Map queue to vf */
 746                         vf = (q >> shift);
 747
 748                         /* Set vf bit in vf_bitmap */
 749                         idx = vf / 32;
 750                         vf_bitmap[idx] |= (1 << (vf % 32));
 751                         wqbr &= ~(1 << j);
 752                 }
 753         }
 754 }
 755
 756 /**
 757  *  ixgbe_get_media_type_X550em - Get media type
 758  *  @hw: pointer to hardware structure
 759  *
 760  *  Returns the media type (fiber, copper, backplane)
 761  */
 762 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
 763 {
 764         enum ixgbe_media_type media_type;
 765
 766         DEBUGFUNC("ixgbe_get_media_type_X550em");
 767
 768         /* Detect if there is a copper PHY attached. */
 769         switch (hw->device_id) {
 770         case IXGBE_DEV_ID_X550EM_X:
 771         case IXGBE_DEV_ID_X550EM_X_KR:
 772         case IXGBE_DEV_ID_X550EM_X_KX4:
 773                 media_type = ixgbe_media_type_backplane;
 774                 break;
 775         case IXGBE_DEV_ID_X550EM_X_SFP:
 776                 media_type = ixgbe_media_type_fiber;
 777                 break;
 778         default:
 779                 media_type = ixgbe_media_type_unknown;
 780                 break;
 781         }
 782         return media_type;
 783 }
 784
 785 /**
 786  *  ixgbe_setup_sfp_modules_X550em - Setup SFP module
 787  *  @hw: pointer to hardware structure
 788  */
 789 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
 790 {
 791         bool setup_linear;
 792         u16 reg_slice, edc_mode;
 793         s32 ret_val;
 794
 795         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
 796
 797         switch (hw->phy.sfp_type) {
 798         case ixgbe_sfp_type_unknown:
 799                 return IXGBE_SUCCESS;
 800         case ixgbe_sfp_type_not_present:
 801                 return IXGBE_ERR_SFP_NOT_PRESENT;
 802         case ixgbe_sfp_type_da_cu_core0:
 803         case ixgbe_sfp_type_da_cu_core1:
 804                 setup_linear = true;
 805                 break;
 806         case ixgbe_sfp_type_srlr_core0:
 807         case ixgbe_sfp_type_srlr_core1:
 808         case ixgbe_sfp_type_da_act_lmt_core0:
 809         case ixgbe_sfp_type_da_act_lmt_core1:
 810         case ixgbe_sfp_type_1g_sx_core0:
 811         case ixgbe_sfp_type_1g_sx_core1:
 812         case ixgbe_sfp_type_1g_lx_core0:
 813         case ixgbe_sfp_type_1g_lx_core1:
 814                 setup_linear = false;
 815                 break;
 816         default:
 817                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 818         }
 819
 820         ixgbe_init_mac_link_ops_X550em(hw);
 821         hw->phy.ops.reset = NULL;
 822
 823         /* The CS4227 slice address is the base address + the port-pair reg
 824          * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
 825          */
 826         reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);
 827
 828         if (setup_linear)
 829                 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
 830         else
 831                 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
 832
 833         /* Configure CS4227 for connection type. */
 834         ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
 835                                            edc_mode);
 836
 837         if (ret_val != IXGBE_SUCCESS)
 838                 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
 839                                                    edc_mode);
 840
 841         return ret_val;
 842 }
 843
 844 /**
 845  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
 846  *  @hw: pointer to hardware structure
 847  */
 848 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
 849 {
 850         struct ixgbe_mac_info *mac = &hw->mac;
 851
 852         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
 853
 854         /* CS4227 does not support autoneg, so disable the laser control
 855          * functions for SFP+ fiber
 856          */
 857          if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 858                 mac->ops.disable_tx_laser = NULL;
 859                 mac->ops.enable_tx_laser = NULL;
 860                 mac->ops.flap_tx_laser = NULL;
 861          }
 862 }
 863
 864 /**
 865  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
 866  *  @hw: pointer to hardware structure
 867  *  @speed: pointer to link speed
 868  *  @autoneg: true when autoneg or autotry is enabled
 869  */
 870 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
 871                                        ixgbe_link_speed *speed,
 872                                        bool *autoneg)
 873 {
 874         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
 875
 876         /* SFP */
 877         if (hw->phy.media_type == ixgbe_media_type_fiber) {
 878
 879                 /* CS4227 SFP must not enable auto-negotiation */
 880                 *autoneg = false;
 881
 882                 /* Check if 1G SFP module. */
 883                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 884                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
 885                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
 886                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
 887                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
 888                         return IXGBE_SUCCESS;
 889                 }
 890
 891                 /* Link capabilities are based on SFP */
 892                 if (hw->phy.multispeed_fiber)
 893                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
 894                                  IXGBE_LINK_SPEED_1GB_FULL;
 895                 else
 896                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 897         } else {
 898                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
 899                          IXGBE_LINK_SPEED_1GB_FULL;
 900                 *autoneg = true;
 901         }
 902
 903         return IXGBE_SUCCESS;
 904 }
 905
 906 /**
 907  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
 908  *  @hw: pointer to hardware structure
 909  *
 910  *  Initialize any function pointers that were not able to be
 911  *  set during init_shared_code because the PHY/SFP type was
 912  *  not known.  Perform the SFP init if necessary.
 913  */
 914 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
 915 {
 916         struct ixgbe_phy_info *phy = &hw->phy;
 917         s32 ret_val;
 918         u32 esdp;
 919
 920         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
 921
 922         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
 923                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 924                 phy->lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
 925                               IXGBE_STATUS_LAN_ID_1;
 926                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 927                 if (phy->lan_id) {
 928                         esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 929                         esdp |= IXGBE_ESDP_SDP1_DIR;
 930                 }
 931                 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 932                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 933         }
 934
 935         /* Identify the PHY or SFP module */
 936         ret_val = phy->ops.identify(hw);
 937         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
 938                 return ret_val;
 939
 940         /* Setup function pointers based on detected SFP module and speeds */
 941         ixgbe_init_mac_link_ops_X550em(hw);
 942         if (phy->sfp_type != ixgbe_sfp_type_unknown)
 943                 phy->ops.reset = NULL;
 944
 945         /* Set functions pointers based on phy type */
 946         switch (hw->phy.type) {
 947         case ixgbe_phy_x550em_kr:
 948                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
 949                 break;
 950         default:
 951                 break;
 952         }
 953         return ret_val;
 954 }
 955
 956 /**
 957  *  ixgbe_reset_hw_X550em - Perform hardware reset
 958  *  @hw: pointer to hardware structure
 959  *
 960  *  Resets the hardware by resetting the transmit and receive units, masks
 961  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 962  *  reset.
 963  */
 964 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
 965 {
 966         ixgbe_link_speed link_speed;
 967         s32 status;
 968         u32 ctrl = 0;
 969         u32 i;
 970         bool link_up = false;
 971
 972         DEBUGFUNC("ixgbe_reset_hw_X550em");
 973
 974         /* Call adapter stop to disable Tx/Rx and clear interrupts */
 975         status = hw->mac.ops.stop_adapter(hw);
 976         if (status != IXGBE_SUCCESS)
 977                 return status;
 978
 979         /* flush pending Tx transactions */
 980         ixgbe_clear_tx_pending(hw);
 981
 982         /* PHY ops must be identified and initialized prior to reset */
 983
 984         /* Identify PHY and related function pointers */
 985         status = hw->phy.ops.init(hw);
 986
 987         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 988                 return status;
 989
 990         /* Setup SFP module if there is one present. */
 991         if (hw->phy.sfp_setup_needed) {
 992                 status = hw->mac.ops.setup_sfp(hw);
 993                 hw->phy.sfp_setup_needed = false;
 994         }
 995
 996         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 997                 return status;
 998
 999         /* Reset PHY */
1000         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1001                 hw->phy.ops.reset(hw);
1002
1003 mac_reset_top:
1004         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1005          * If link reset is used when link is up, it might reset the PHY when
1006          * mng is using it.  If link is down or the flag to force full link
1007          * reset is set, then perform link reset.
1008          */
1009         ctrl = IXGBE_CTRL_LNK_RST;
1010         if (!hw->force_full_reset) {
1011                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1012                 if (link_up)
1013                         ctrl = IXGBE_CTRL_RST;
1014         }
1015
1016         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1017         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1018         IXGBE_WRITE_FLUSH(hw);
1019
1020         /* Poll for reset bit to self-clear meaning reset is complete */
1021         for (i = 0; i < 10; i++) {
1022                 usec_delay(1);
1023                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1024                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1025                         break;
1026         }
1027
1028         if (ctrl & IXGBE_CTRL_RST_MASK) {
1029                 status = IXGBE_ERR_RESET_FAILED;
1030                 DEBUGOUT("Reset polling failed to complete.\n");
1031         }
1032
1033         msec_delay(50);
1034
1035         /* Double resets are required for recovery from certain error
1036          * conditions.  Between resets, it is necessary to stall to
1037          * allow time for any pending HW events to complete.
1038          */
1039         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1040                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1041                 goto mac_reset_top;
1042         }
1043
1044         /* Store the permanent mac address */
1045         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1046
1047         /* Store MAC address from RAR0, clear receive address registers, and
1048          * clear the multicast table.  Also reset num_rar_entries to 128,
1049          * since we modify this value when programming the SAN MAC address.
1050          */
1051         hw->mac.num_rar_entries = 128;
1052         hw->mac.ops.init_rx_addrs(hw);
1053
1054         return status;
1055 }
1056
1057 /**
1058  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1059  *  @hw: pointer to hardware structure
1060  *
1061  *  Configures the integrated KR PHY.
1062  **/
1063 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1064 {
1065         s32 status;
1066         u32 reg_val;
1067
1068         status = ixgbe_read_iosf_sb_reg_x550(hw,
1069                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1070                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1071         if (status)
1072                 return status;
1073
1074         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1075         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1076         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1077         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1078                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1079
1080         /* Advertise 10G support. */
1081         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1082                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1083
1084         /* Advertise 1G support. */
1085         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1086                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1087
1088         /* Restart auto-negotiation. */
1089         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1090         status = ixgbe_write_iosf_sb_reg_x550(hw,
1091                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1092                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1093
1094         return status;
1095 }
1096
1097 /**
1098  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
1099  *  @hw: pointer to hardware structure
1100  *
1101  *  Configures the integrated KR PHY to use iXFI mode.
1102  **/
1103 s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
1104 {
1105         s32 status;
1106         u32 reg_val;
1107
1108         /* Disable AN and force speed to 10G Serial. */
1109         status = ixgbe_read_iosf_sb_reg_x550(hw,
1110                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1111                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1112         if (status != IXGBE_SUCCESS)
1113                 return status;
1114         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1115         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1116         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1117         status = ixgbe_write_iosf_sb_reg_x550(hw,
1118                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1119                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1120         if (status != IXGBE_SUCCESS)
1121                 return status;
1122
1123         /* Disable training protocol FSM. */
1124         status = ixgbe_read_iosf_sb_reg_x550(hw,
1125                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1126                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1127         if (status != IXGBE_SUCCESS)
1128                 return status;
1129         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1130         status = ixgbe_write_iosf_sb_reg_x550(hw,
1131                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1132                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1133         if (status != IXGBE_SUCCESS)
1134                 return status;
1135
1136         /* Disable Flex from training TXFFE. */
1137         status = ixgbe_read_iosf_sb_reg_x550(hw,
1138                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1139                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1140         if (status != IXGBE_SUCCESS)
1141                 return status;
1142         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1143         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1144         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1145         status = ixgbe_write_iosf_sb_reg_x550(hw,
1146                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1147                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1148         if (status != IXGBE_SUCCESS)
1149                 return status;
1150         status = ixgbe_read_iosf_sb_reg_x550(hw,
1151                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1152                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1153         if (status != IXGBE_SUCCESS)
1154                 return status;
1155         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1156         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1157         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1158         status = ixgbe_write_iosf_sb_reg_x550(hw,
1159                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1160                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1161         if (status != IXGBE_SUCCESS)
1162                 return status;
1163
1164         /* Enable override for coefficients. */
1165         status = ixgbe_read_iosf_sb_reg_x550(hw,
1166                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1167                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1168         if (status != IXGBE_SUCCESS)
1169                 return status;
1170         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1171         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1172         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1173         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1174         status = ixgbe_write_iosf_sb_reg_x550(hw,
1175                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1176                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1177         if (status != IXGBE_SUCCESS)
1178                 return status;
1179
1180         /* Toggle port SW reset by AN reset. */
1181         status = ixgbe_read_iosf_sb_reg_x550(hw,
1182                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1183                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1184         if (status != IXGBE_SUCCESS)
1185                 return status;
1186         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1187         status = ixgbe_write_iosf_sb_reg_x550(hw,
1188                                         IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1189                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1190
1191         return status;
1192 }
1193
1194 /**
1195  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1196  *  @hw: pointer to hardware structure
1197  *
1198  *  Configures the integrated KR PHY to use internal loopback mode.
1199  **/
1200 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1201 {
1202         s32 status;
1203         u32 reg_val;
1204
1205         /* Disable AN and force speed to 10G Serial. */
1206         status = ixgbe_read_iosf_sb_reg_x550(hw,
1207                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1208                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1209         if (status != IXGBE_SUCCESS)
1210                 return status;
1211         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1212         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1213         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1214         status = ixgbe_write_iosf_sb_reg_x550(hw,
1215                 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1216                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1217         if (status != IXGBE_SUCCESS)
1218                 return status;
1219
1220         /* Set near-end loopback clocks. */
1221         status = ixgbe_read_iosf_sb_reg_x550(hw,
1222                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1223                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1224         if (status != IXGBE_SUCCESS)
1225                 return status;
1226         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1227         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1228         status = ixgbe_write_iosf_sb_reg_x550(hw,
1229                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1230                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1231         if (status != IXGBE_SUCCESS)
1232                 return status;
1233
1234         /* Set loopback enable. */
1235         status = ixgbe_read_iosf_sb_reg_x550(hw,
1236                 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1237                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1238         if (status != IXGBE_SUCCESS)
1239                 return status;
1240         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1241         status = ixgbe_write_iosf_sb_reg_x550(hw,
1242                 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1243                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1244         if (status != IXGBE_SUCCESS)
1245                 return status;
1246
1247         /* Training bypass. */
1248         status = ixgbe_read_iosf_sb_reg_x550(hw,
1249                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1250                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1251         if (status != IXGBE_SUCCESS)
1252                 return status;
1253         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1254         status = ixgbe_write_iosf_sb_reg_x550(hw,
1255                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1256                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1257
1258         return status;
1259 }
1260
1261 /**
1262  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1263  *  assuming that the semaphore is already obtained.
1264  *  @hw: pointer to hardware structure
1265  *  @offset: offset of  word in the EEPROM to read
1266  *  @data: word read from the EEPROM
1267  *
1268  *  Reads a 16 bit word from the EEPROM using the hostif.
1269  **/
1270 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1271                                    u16 *data)
1272 {
1273         s32 status;
1274         struct ixgbe_hic_read_shadow_ram buffer;
1275
1276         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1277         buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1278         buffer.hdr.buf_len1 = 0;
1279         buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1280         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1281
1282         /* convert offset from words to bytes */
1283         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1284         /* one word */
1285         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1286
1287         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1288                                               sizeof(buffer), false);
1289
1290         if (status)
1291                 return status;
1292
1293         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1294                                           FW_NVM_DATA_OFFSET);
1295
1296         return 0;
1297 }
1298
1299 /**
1300  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1301  *  @hw: pointer to hardware structure
1302  *  @offset: offset of  word in the EEPROM to read
1303  *  @data: word read from the EEPROM
1304  *
1305  *  Reads a 16 bit word from the EEPROM using the hostif.
1306  **/
1307 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1308                               u16 *data)
1309 {
1310         s32 status = IXGBE_SUCCESS;
1311
1312         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1313
1314         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1315             IXGBE_SUCCESS) {
1316                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1317                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1318         } else {
1319                 status = IXGBE_ERR_SWFW_SYNC;
1320         }
1321
1322         return status;
1323 }
1324
1325 /**
1326  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1327  *  @hw: pointer to hardware structure
1328  *  @offset: offset of  word in the EEPROM to read
1329  *  @words: number of words
1330  *  @data: word(s) read from the EEPROM
1331  *
1332  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
1333  **/
1334 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1335                                      u16 offset, u16 words, u16 *data)
1336 {
1337         struct ixgbe_hic_read_shadow_ram buffer;
1338         u32 current_word = 0;
1339         u16 words_to_read;
1340         s32 status;
1341         u32 i;
1342
1343         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1344
1345         /* Take semaphore for the entire operation. */
1346         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1347         if (status) {
1348                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1349                 return status;
1350         }
1351         while (words) {
1352                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1353                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1354                 else
1355                         words_to_read = words;
1356
1357                 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1358                 buffer.hdr.buf_len1 = 0;
1359                 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1360                 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1361
1362                 /* convert offset from words to bytes */
1363                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1364                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1365
1366                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1367                                                       sizeof(buffer), false);
1368
1369                 if (status) {
1370                         DEBUGOUT("Host interface command failed\n");
1371                         goto out;
1372                 }
1373
1374                 for (i = 0; i < words_to_read; i++) {
1375                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1376                                   2 * i;
1377                         u32 value = IXGBE_READ_REG(hw, reg);
1378
1379                         data[current_word] = (u16)(value & 0xffff);
1380                         current_word++;
1381                         i++;
1382                         if (i < words_to_read) {
1383                                 value >>= 16;
1384                                 data[current_word] = (u16)(value & 0xffff);
1385                                 current_word++;
1386                         }
1387                 }
1388                 words -= words_to_read;
1389         }
1390
1391 out:
1392         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1393         return status;
1394 }
1395
1396 /**
1397  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1398  *  @hw: pointer to hardware structure
1399  *  @offset: offset of  word in the EEPROM to write
1400  *  @data: word write to the EEPROM
1401  *
1402  *  Write a 16 bit word to the EEPROM using the hostif.
1403  **/
1404 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1405                                     u16 data)
1406 {
1407         s32 status;
1408         struct ixgbe_hic_write_shadow_ram buffer;
1409
1410         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1411
1412         buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1413         buffer.hdr.buf_len1 = 0;
1414         buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1415         buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1416
1417          /* one word */
1418         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1419         buffer.data = data;
1420         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1421
1422         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1423                                               sizeof(buffer), false);
1424
1425         return status;
1426 }
1427
1428 /**
1429  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1430  *  @hw: pointer to hardware structure
1431  *  @offset: offset of  word in the EEPROM to write
1432  *  @data: word write to the EEPROM
1433  *
1434  *  Write a 16 bit word to the EEPROM using the hostif.
1435  **/
1436 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1437                                u16 data)
1438 {
1439         s32 status = IXGBE_SUCCESS;
1440
1441         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1442
1443         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1444             IXGBE_SUCCESS) {
1445                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1446                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1447         } else {
1448                 DEBUGOUT("write ee hostif failed to get semaphore");
1449                 status = IXGBE_ERR_SWFW_SYNC;
1450         }
1451
1452         return status;
1453 }
1454
1455 /**
1456  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1457  *  @hw: pointer to hardware structure
1458  *  @offset: offset of  word in the EEPROM to write
1459  *  @words: number of words
1460  *  @data: word(s) write to the EEPROM
1461  *
1462  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1463  **/
1464 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1465                                       u16 offset, u16 words, u16 *data)
1466 {
1467         s32 status = IXGBE_SUCCESS;
1468         u32 i = 0;
1469
1470         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1471
1472         /* Take semaphore for the entire operation. */
1473         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1474         if (status != IXGBE_SUCCESS) {
1475                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1476                 goto out;
1477         }
1478
1479         for (i = 0; i < words; i++) {
1480                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1481                                                          data[i]);
1482
1483                 if (status != IXGBE_SUCCESS) {
1484                         DEBUGOUT("Eeprom buffered write failed\n");
1485                         break;
1486                 }
1487         }
1488
1489         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1490 out:
1491
1492         return status;
1493 }
1494
1495 /**
1496  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1497  * @hw: pointer to hardware structure
1498  * @ptr: pointer offset in eeprom
1499  * @size: size of section pointed by ptr, if 0 first word will be used as size
1500  * @csum: address of checksum to update
1501  *
1502  * Returns error status for any failure
1503  */
1504 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1505                                    u16 size, u16 *csum)
1506 {
1507         u16 buf[256];
1508         s32 status;
1509         u16 length, bufsz, i, start;
1510
1511         bufsz = sizeof(buf) / sizeof(buf[0]);
1512
1513         /* Read a chunk at the pointer location */
1514         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1515         if (status) {
1516                 DEBUGOUT("Failed to read EEPROM image\n");
1517                 return status;
1518         }
1519
1520         if (size) {
1521                 start = 0;
1522                 length = size;
1523         } else {
1524                 start = 1;
1525                 length = buf[0];
1526
1527                 /* Skip pointer section if length is invalid. */
1528                 if (length == 0xFFFF || length == 0 ||
1529                     (ptr + length) >= hw->eeprom.word_size)
1530                         return IXGBE_SUCCESS;
1531         }
1532
1533         for (i = start; length; i++, length--) {
1534                 if (i == bufsz) {
1535                         ptr += bufsz;
1536                         i = 0;
1537                         if (length < bufsz)
1538                                 bufsz = length;
1539
1540                         /* Read a chunk at the pointer location */
1541                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1542                                                                   bufsz, buf);
1543                         if (status) {
1544                                 DEBUGOUT("Failed to read EEPROM image\n");
1545                                 return status;
1546                         }
1547                 }
1548                 *csum += buf[i];
1549         }
1550         return IXGBE_SUCCESS;
1551 }
1552
1553 /**
1554  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1555  *  @hw: pointer to hardware structure
1556  *
1557  *  Returns a negative error code on error, or the 16-bit checksum
1558  **/
1559 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1560 {
1561         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1562         s32 status;
1563         u16 checksum = 0;
1564         u16 pointer, i, size;
1565
1566         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1567
1568         hw->eeprom.ops.init_params(hw);
1569
1570         /* Read pointer area */
1571         status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1572                                                   IXGBE_EEPROM_LAST_WORD + 1,
1573                                                   eeprom_ptrs);
1574         if (status) {
1575                 DEBUGOUT("Failed to read EEPROM image\n");
1576                 return status;
1577         }
1578
1579         /*
1580          * For X550 hardware include 0x0-0x41 in the checksum, skip the
1581          * checksum word itself
1582          */
1583         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1584                 if (i != IXGBE_EEPROM_CHECKSUM)
1585                         checksum += eeprom_ptrs[i];
1586
1587         /*
1588          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
1589          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1590          */
1591         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1592                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1593                         continue;
1594
1595                 pointer = eeprom_ptrs[i];
1596
1597                 /* Skip pointer section if the pointer is invalid. */
1598                 if (pointer == 0xFFFF || pointer == 0 ||
1599                     pointer >= hw->eeprom.word_size)
1600                         continue;
1601
1602                 switch (i) {
1603                 case IXGBE_PCIE_GENERAL_PTR:
1604                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1605                         break;
1606                 case IXGBE_PCIE_CONFIG0_PTR:
1607                 case IXGBE_PCIE_CONFIG1_PTR:
1608                         size = IXGBE_PCIE_CONFIG_SIZE;
1609                         break;
1610                 default:
1611                         size = 0;
1612                         break;
1613                 }
1614
1615                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);
1616                 if (status)
1617                         return status;
1618         }
1619
1620         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1621
1622         return (s32)checksum;
1623 }
1624
1625 /**
1626  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1627  *  @hw: pointer to hardware structure
1628  *  @checksum_val: calculated checksum
1629  *
1630  *  Performs checksum calculation and validates the EEPROM checksum.  If the
1631  *  caller does not need checksum_val, the value can be NULL.
1632  **/
1633 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1634 {
1635         s32 status;
1636         u16 checksum;
1637         u16 read_checksum = 0;
1638
1639         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1640
1641         /* Read the first word from the EEPROM. If this times out or fails, do
1642          * not continue or we could be in for a very long wait while every
1643          * EEPROM read fails
1644          */
1645         status = hw->eeprom.ops.read(hw, 0, &checksum);
1646         if (status) {
1647                 DEBUGOUT("EEPROM read failed\n");
1648                 return status;
1649         }
1650
1651         status = hw->eeprom.ops.calc_checksum(hw);
1652         if (status < 0)
1653                 return status;
1654
1655         checksum = (u16)(status & 0xffff);
1656
1657         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1658                                            &read_checksum);
1659         if (status)
1660                 return status;
1661
1662         /* Verify read checksum from EEPROM is the same as
1663          * calculated checksum
1664          */
1665         if (read_checksum != checksum) {
1666                 status = IXGBE_ERR_EEPROM_CHECKSUM;
1667                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1668                              "Invalid EEPROM checksum");
1669         }
1670
1671         /* If the user cares, return the calculated checksum */
1672         if (checksum_val)
1673                 *checksum_val = checksum;
1674
1675         return status;
1676 }
1677
1678 /**
1679  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1680  * @hw: pointer to hardware structure
1681  *
1682  * After writing EEPROM to shadow RAM using EEWR register, software calculates
1683  * checksum and updates the EEPROM and instructs the hardware to update
1684  * the flash.
1685  **/
1686 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1687 {
1688         s32 status;
1689         u16 checksum = 0;
1690
1691         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1692
1693         /* Read the first word from the EEPROM. If this times out or fails, do
1694          * not continue or we could be in for a very long wait while every
1695          * EEPROM read fails
1696          */
1697         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1698         if (status) {
1699                 DEBUGOUT("EEPROM read failed\n");
1700                 return status;
1701         }
1702
1703         status = ixgbe_calc_eeprom_checksum_X550(hw);
1704         if (status < 0)
1705                 return status;
1706
1707         checksum = (u16)(status & 0xffff);
1708
1709         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1710                                             checksum);
1711         if (status)
1712                 return status;
1713
1714         status = ixgbe_update_flash_X550(hw);
1715
1716         return status;
1717 }
1718
1719 /**
1720  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1721  *  @hw: pointer to hardware structure
1722  *
1723  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1724  **/
1725 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1726 {
1727         s32 status = IXGBE_SUCCESS;
1728         struct ixgbe_hic_hdr2 buffer;
1729
1730         DEBUGFUNC("ixgbe_update_flash_X550");
1731
1732         buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1733         buffer.buf_len1 = 0;
1734         buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1735         buffer.checksum = FW_DEFAULT_CHECKSUM;
1736
1737         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1738                                               sizeof(buffer), false);
1739
1740         return status;
1741 }
1742
1743 /**
1744  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
1745  *  @hw: pointer to hardware structure
1746  *
1747  *  Determines physical layer capabilities of the current configuration.
1748  **/
1749 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
1750 {
1751         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1752
1753         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
1754
1755         hw->phy.ops.identify(hw);
1756
1757         switch (hw->phy.type) {
1758         case ixgbe_phy_x550em_kr:
1759                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
1760                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1761                 break;
1762         case ixgbe_phy_x550em_kx4:
1763                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1764                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1765                 break;
1766         default:
1767                 break;
1768         }
1769
1770         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1771                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1772
1773         return physical_layer;
1774 }
1775
1776 /**
1777  * ixgbe_get_bus_info_x550em - Set PCI bus info
1778  * @hw: pointer to hardware structure
1779  *
1780  * Sets bus link width and speed to unknown because X550em is
1781  * not a PCI device.
1782  **/
1783 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1784 {
1785
1786         DEBUGFUNC("ixgbe_get_bus_info_x550em");
1787
1788         hw->bus.width = ixgbe_bus_width_unknown;
1789         hw->bus.speed = ixgbe_bus_speed_unknown;
1790
1791         return IXGBE_SUCCESS;
1792 }
1793
1794 /**
1795  * ixgbe_disable_rx_x550 - Disable RX unit
1796  *
1797  * Enables the Rx DMA unit for x550
1798  **/
1799 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1800 {
1801         u32 rxctrl, pfdtxgswc;
1802         s32 status;
1803         struct ixgbe_hic_disable_rxen fw_cmd;
1804
1805         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
1806
1807         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1808         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1809                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1810                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1811                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1812                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1813                         hw->mac.set_lben = true;
1814                 } else {
1815                         hw->mac.set_lben = false;
1816                 }
1817
1818                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1819                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1820                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1821                 fw_cmd.port_number = hw->phy.lan_id;
1822
1823                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1824                                         sizeof(struct ixgbe_hic_disable_rxen),
1825                                         true);
1826
1827                 /* If we fail - disable RX using register write */
1828                 if (status) {
1829                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1830                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1831                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1832                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1833                         }
1834                 }
1835         }
1836 }