1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
42 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
43 * @hw: pointer to hardware structure
45 * Initialize the function pointers and assign the MAC type for X550.
46 * Does not touch the hardware.
48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
50 struct ixgbe_mac_info *mac = &hw->mac;
51 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
54 DEBUGFUNC("ixgbe_init_ops_X550");
56 ret_val = ixgbe_init_ops_X540(hw);
57 mac->ops.dmac_config = ixgbe_dmac_config_X550;
58 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
59 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
60 mac->ops.setup_eee = ixgbe_setup_eee_X550;
61 mac->ops.set_source_address_pruning =
62 ixgbe_set_source_address_pruning_X550;
63 mac->ops.set_ethertype_anti_spoofing =
64 ixgbe_set_ethertype_anti_spoofing_X550;
66 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
67 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
68 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
69 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
70 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
71 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
72 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
73 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
74 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
76 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
77 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
78 mac->ops.mdd_event = ixgbe_mdd_event_X550;
79 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
80 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 * ixgbe_identify_phy_x550em - Get PHY type based on device id
86 * @hw: pointer to hardware structure
90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
92 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
94 switch (hw->device_id) {
95 case IXGBE_DEV_ID_X550EM_X_SFP:
96 /* set up for CS4227 usage */
97 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
100 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
101 esdp |= IXGBE_ESDP_SDP1_DIR;
103 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
104 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
106 return ixgbe_identify_module_generic(hw);
108 case IXGBE_DEV_ID_X550EM_X_KX4:
109 hw->phy.type = ixgbe_phy_x550em_kx4;
111 case IXGBE_DEV_ID_X550EM_X_KR:
112 case IXGBE_DEV_ID_X550EM_X:
113 hw->phy.type = ixgbe_phy_x550em_kr;
118 return IXGBE_SUCCESS;
121 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
122 u32 device_type, u16 *phy_data)
124 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
125 return IXGBE_NOT_IMPLEMENTED;
128 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
129 u32 device_type, u16 phy_data)
131 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
132 return IXGBE_NOT_IMPLEMENTED;
136 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
137 * @hw: pointer to hardware structure
139 * Initialize the function pointers and for MAC type X550EM.
140 * Does not touch the hardware.
142 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
144 struct ixgbe_mac_info *mac = &hw->mac;
145 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
146 struct ixgbe_phy_info *phy = &hw->phy;
149 DEBUGFUNC("ixgbe_init_ops_X550EM");
151 /* Similar to X550 so start there. */
152 ret_val = ixgbe_init_ops_X550(hw);
154 /* Since this function eventually calls
155 * ixgbe_init_ops_540 by design, we are setting
156 * the pointers to NULL explicitly here to overwrite
157 * the values being set in the x540 function.
159 /* Thermal sensor not supported in x550EM */
160 mac->ops.get_thermal_sensor_data = NULL;
161 mac->ops.init_thermal_sensor_thresh = NULL;
162 mac->thermal_sensor_enabled = false;
164 /* FCOE not supported in x550EM */
165 mac->ops.get_san_mac_addr = NULL;
166 mac->ops.set_san_mac_addr = NULL;
167 mac->ops.get_wwn_prefix = NULL;
168 mac->ops.get_fcoe_boot_status = NULL;
170 /* IPsec not supported in x550EM */
171 mac->ops.disable_sec_rx_path = NULL;
172 mac->ops.enable_sec_rx_path = NULL;
174 /* X550EM bus type is internal*/
175 hw->bus.type = ixgbe_bus_type_internal;
176 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
178 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
179 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
180 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
181 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
182 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
183 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
184 mac->ops.get_supported_physical_layer =
185 ixgbe_get_supported_physical_layer_X550em;
188 phy->ops.init = ixgbe_init_phy_ops_X550em;
189 phy->ops.identify = ixgbe_identify_phy_x550em;
190 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
191 phy->ops.set_phy_power = NULL;
195 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
196 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
197 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
198 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
199 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
200 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
201 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
202 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
208 * ixgbe_dmac_config_X550
209 * @hw: pointer to hardware structure
211 * Configure DMA coalescing. If enabling dmac, dmac is activated.
212 * When disabling dmac, dmac enable dmac bit is cleared.
214 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
216 u32 reg, high_pri_tc;
218 DEBUGFUNC("ixgbe_dmac_config_X550");
220 /* Disable DMA coalescing before configuring */
221 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
222 reg &= ~IXGBE_DMACR_DMAC_EN;
223 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
225 /* Disable DMA Coalescing if the watchdog timer is 0 */
226 if (!hw->mac.dmac_config.watchdog_timer)
229 ixgbe_dmac_config_tcs_X550(hw);
231 /* Configure DMA Coalescing Control Register */
232 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
234 /* Set the watchdog timer in units of 40.96 usec */
235 reg &= ~IXGBE_DMACR_DMACWT_MASK;
236 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
238 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
239 /* If fcoe is enabled, set high priority traffic class */
240 if (hw->mac.dmac_config.fcoe_en) {
241 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
242 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
243 IXGBE_DMACR_HIGH_PRI_TC_MASK);
245 reg |= IXGBE_DMACR_EN_MNG_IND;
247 /* Enable DMA coalescing after configuration */
248 reg |= IXGBE_DMACR_DMAC_EN;
249 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
252 return IXGBE_SUCCESS;
256 * ixgbe_dmac_config_tcs_X550
257 * @hw: pointer to hardware structure
259 * Configure DMA coalescing threshold per TC. The dmac enable bit must
260 * be cleared before configuring.
262 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
264 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
266 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
268 /* Configure DMA coalescing enabled */
269 switch (hw->mac.dmac_config.link_speed) {
270 case IXGBE_LINK_SPEED_100_FULL:
271 pb_headroom = IXGBE_DMACRXT_100M;
273 case IXGBE_LINK_SPEED_1GB_FULL:
274 pb_headroom = IXGBE_DMACRXT_1G;
277 pb_headroom = IXGBE_DMACRXT_10G;
281 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
282 IXGBE_MHADD_MFS_SHIFT) / 1024);
284 /* Set the per Rx packet buffer receive threshold */
285 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
286 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
287 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
289 if (tc < hw->mac.dmac_config.num_tcs) {
291 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
292 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
293 IXGBE_RXPBSIZE_SHIFT;
295 /* Calculate receive buffer threshold in kilobytes */
296 if (rx_pb_size > pb_headroom)
297 rx_pb_size = rx_pb_size - pb_headroom;
301 /* Minimum of MFS shall be set for DMCTH */
302 reg |= (rx_pb_size > maxframe_size_kb) ?
303 rx_pb_size : maxframe_size_kb;
305 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
307 return IXGBE_SUCCESS;
311 * ixgbe_dmac_update_tcs_X550
312 * @hw: pointer to hardware structure
314 * Disables dmac, updates per TC settings, and then enables dmac.
316 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
320 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
322 /* Disable DMA coalescing before configuring */
323 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
324 reg &= ~IXGBE_DMACR_DMAC_EN;
325 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
327 ixgbe_dmac_config_tcs_X550(hw);
329 /* Enable DMA coalescing after configuration */
330 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
331 reg |= IXGBE_DMACR_DMAC_EN;
332 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
334 return IXGBE_SUCCESS;
338 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
339 * @hw: pointer to hardware structure
341 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
342 * ixgbe_hw struct in order to set up EEPROM access.
344 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
346 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
350 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
352 if (eeprom->type == ixgbe_eeprom_uninitialized) {
353 eeprom->semaphore_delay = 10;
354 eeprom->type = ixgbe_flash;
356 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
357 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
358 IXGBE_EEC_SIZE_SHIFT);
359 eeprom->word_size = 1 << (eeprom_size +
360 IXGBE_EEPROM_WORD_SIZE_SHIFT);
362 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
363 eeprom->type, eeprom->word_size);
366 return IXGBE_SUCCESS;
370 * ixgbe_setup_eee_X550 - Enable/disable EEE support
371 * @hw: pointer to the HW structure
372 * @enable_eee: boolean flag to enable EEE
374 * Enable/disable EEE based on enable_eee flag.
375 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
379 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
386 DEBUGFUNC("ixgbe_setup_eee_X550");
388 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
389 /* Enable or disable EEE per flag */
391 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
393 if (hw->device_id == IXGBE_DEV_ID_X550T) {
394 /* Advertise EEE capability */
395 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
396 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
398 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
399 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
400 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
402 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
403 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
404 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
405 hw->device_id == IXGBE_DEV_ID_X550EM_X) {
406 status = ixgbe_read_iosf_sb_reg_x550(hw,
407 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
408 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
409 if (status != IXGBE_SUCCESS)
412 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
413 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
415 status = ixgbe_write_iosf_sb_reg_x550(hw,
416 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
417 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
418 if (status != IXGBE_SUCCESS)
422 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
424 if (hw->device_id == IXGBE_DEV_ID_X550T) {
425 /* Disable advertised EEE capability */
426 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
427 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
429 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
430 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
431 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
433 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
434 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
435 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
436 hw->device_id == IXGBE_DEV_ID_X550EM_X) {
437 status = ixgbe_read_iosf_sb_reg_x550(hw,
438 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
439 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
440 if (status != IXGBE_SUCCESS)
443 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
444 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
446 status = ixgbe_write_iosf_sb_reg_x550(hw,
447 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
448 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
449 if (status != IXGBE_SUCCESS)
453 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
455 return IXGBE_SUCCESS;
459 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
460 * @hw: pointer to hardware structure
461 * @enable: enable or disable source address pruning
462 * @pool: Rx pool to set source address pruning for
464 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
469 /* max rx pool is 63 */
473 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
474 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
477 pfflp |= (1ULL << pool);
479 pfflp &= ~(1ULL << pool);
481 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
482 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
486 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
487 * @hw: pointer to hardware structure
488 * @enable: enable or disable switch for Ethertype anti-spoofing
489 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
492 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
495 int vf_target_reg = vf >> 3;
496 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
499 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
501 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
503 pfvfspoof |= (1 << vf_target_shift);
505 pfvfspoof &= ~(1 << vf_target_shift);
507 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
511 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
513 * @hw: pointer to hardware structure
514 * @reg_addr: 32 bit PHY register to write
515 * @device_type: 3 bit device type
516 * @data: Data to write to the register
518 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
519 u32 device_type, u32 data)
521 u32 i, command, error;
523 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
524 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
526 /* Write IOSF control register */
527 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
529 /* Write IOSF data register */
530 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
532 * Check every 10 usec to see if the address cycle completed.
533 * The SB IOSF BUSY bit will clear when the operation is
536 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
539 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
540 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
544 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
545 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
546 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
547 ERROR_REPORT2(IXGBE_ERROR_POLLING,
548 "Failed to write, error %x\n", error);
549 return IXGBE_ERR_PHY;
552 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
553 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
554 return IXGBE_ERR_PHY;
557 return IXGBE_SUCCESS;
561 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
563 * @hw: pointer to hardware structure
564 * @reg_addr: 32 bit PHY register to write
565 * @device_type: 3 bit device type
566 * @phy_data: Pointer to read data from the register
568 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
569 u32 device_type, u32 *data)
571 u32 i, command, error;
573 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
574 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
576 /* Write IOSF control register */
577 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
580 * Check every 10 usec to see if the address cycle completed.
581 * The SB IOSF BUSY bit will clear when the operation is
584 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
587 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
588 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
592 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
593 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
594 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
595 ERROR_REPORT2(IXGBE_ERROR_POLLING,
596 "Failed to read, error %x\n", error);
597 return IXGBE_ERR_PHY;
600 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
601 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
602 return IXGBE_ERR_PHY;
605 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
607 return IXGBE_SUCCESS;
611 * ixgbe_disable_mdd_X550
612 * @hw: pointer to hardware structure
614 * Disable malicious driver detection
616 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
620 DEBUGFUNC("ixgbe_disable_mdd_X550");
622 /* Disable MDD for TX DMA and interrupt */
623 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
624 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
625 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
627 /* Disable MDD for RX and interrupt */
628 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
629 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
630 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
634 * ixgbe_enable_mdd_X550
635 * @hw: pointer to hardware structure
637 * Enable malicious driver detection
639 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
643 DEBUGFUNC("ixgbe_enable_mdd_X550");
645 /* Enable MDD for TX DMA and interrupt */
646 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
647 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
648 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
650 /* Enable MDD for RX and interrupt */
651 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
652 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
653 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
657 * ixgbe_restore_mdd_vf_X550
658 * @hw: pointer to hardware structure
661 * Restore VF that was disabled during malicious driver detection event
663 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
665 u32 idx, reg, num_qs, start_q, bitmask;
667 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
669 /* Map VF to queues */
670 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
671 switch (reg & IXGBE_MRQC_MRQE_MASK) {
672 case IXGBE_MRQC_VMDQRT8TCEN:
673 num_qs = 8; /* 16 VFs / pools */
674 bitmask = 0x000000FF;
676 case IXGBE_MRQC_VMDQRSS32EN:
677 case IXGBE_MRQC_VMDQRT4TCEN:
678 num_qs = 4; /* 32 VFs / pools */
679 bitmask = 0x0000000F;
681 default: /* 64 VFs / pools */
683 bitmask = 0x00000003;
686 start_q = vf * num_qs;
688 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
691 reg |= (bitmask << (start_q % 32));
692 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
693 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
697 * ixgbe_mdd_event_X550
698 * @hw: pointer to hardware structure
699 * @vf_bitmap: vf bitmap of malicious vfs
701 * Handle malicious driver detection event.
703 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
706 u32 i, j, reg, q, shift, vf, idx;
708 DEBUGFUNC("ixgbe_mdd_event_X550");
710 /* figure out pool size for mapping to vf's */
711 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
712 switch (reg & IXGBE_MRQC_MRQE_MASK) {
713 case IXGBE_MRQC_VMDQRT8TCEN:
714 shift = 3; /* 16 VFs / pools */
716 case IXGBE_MRQC_VMDQRSS32EN:
717 case IXGBE_MRQC_VMDQRT4TCEN:
718 shift = 2; /* 32 VFs / pools */
721 shift = 1; /* 64 VFs / pools */
725 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
726 for (i = 0; i < 4; i++) {
727 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
728 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
733 /* Get malicious queue */
734 for (j = 0; j < 32 && wqbr; j++) {
736 if (!(wqbr & (1 << j)))
739 /* Get queue from bitmask */
742 /* Map queue to vf */
745 /* Set vf bit in vf_bitmap */
747 vf_bitmap[idx] |= (1 << (vf % 32));
754 * ixgbe_get_media_type_X550em - Get media type
755 * @hw: pointer to hardware structure
757 * Returns the media type (fiber, copper, backplane)
759 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
761 enum ixgbe_media_type media_type;
763 DEBUGFUNC("ixgbe_get_media_type_X550em");
765 /* Detect if there is a copper PHY attached. */
766 switch (hw->device_id) {
767 case IXGBE_DEV_ID_X550EM_X:
768 case IXGBE_DEV_ID_X550EM_X_KR:
769 case IXGBE_DEV_ID_X550EM_X_KX4:
770 media_type = ixgbe_media_type_backplane;
772 case IXGBE_DEV_ID_X550EM_X_SFP:
773 media_type = ixgbe_media_type_fiber;
776 media_type = ixgbe_media_type_unknown;
783 * ixgbe_setup_sfp_modules_X550em - Setup SFP module
784 * @hw: pointer to hardware structure
786 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
789 u16 reg_slice, edc_mode;
792 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
794 switch (hw->phy.sfp_type) {
795 case ixgbe_sfp_type_unknown:
796 return IXGBE_SUCCESS;
797 case ixgbe_sfp_type_not_present:
798 return IXGBE_ERR_SFP_NOT_PRESENT;
799 case ixgbe_sfp_type_da_cu_core0:
800 case ixgbe_sfp_type_da_cu_core1:
803 case ixgbe_sfp_type_srlr_core0:
804 case ixgbe_sfp_type_srlr_core1:
805 case ixgbe_sfp_type_da_act_lmt_core0:
806 case ixgbe_sfp_type_da_act_lmt_core1:
807 case ixgbe_sfp_type_1g_sx_core0:
808 case ixgbe_sfp_type_1g_sx_core1:
809 case ixgbe_sfp_type_1g_lx_core0:
810 case ixgbe_sfp_type_1g_lx_core1:
811 setup_linear = false;
814 return IXGBE_ERR_SFP_NOT_SUPPORTED;
817 ixgbe_init_mac_link_ops_X550em(hw);
818 hw->phy.ops.reset = NULL;
820 /* The CS4227 slice address is the base address + the port-pair reg
821 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
823 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12);
826 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
828 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
830 /* Configure CS4227 for connection type. */
831 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
834 if (ret_val != IXGBE_SUCCESS)
835 ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice,
842 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
843 * @hw: pointer to hardware structure
845 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
847 struct ixgbe_mac_info *mac = &hw->mac;
849 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
851 /* CS4227 does not support autoneg, so disable the laser control
852 * functions for SFP+ fiber
854 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
855 mac->ops.disable_tx_laser = NULL;
856 mac->ops.enable_tx_laser = NULL;
857 mac->ops.flap_tx_laser = NULL;
862 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
863 * @hw: pointer to hardware structure
864 * @speed: pointer to link speed
865 * @autoneg: true when autoneg or autotry is enabled
867 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
868 ixgbe_link_speed *speed,
871 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
874 if (hw->phy.media_type == ixgbe_media_type_fiber) {
876 /* CS4227 SFP must not enable auto-negotiation */
879 /* Check if 1G SFP module. */
880 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
881 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
882 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
883 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
884 *speed = IXGBE_LINK_SPEED_1GB_FULL;
885 return IXGBE_SUCCESS;
888 /* Link capabilities are based on SFP */
889 if (hw->phy.multispeed_fiber)
890 *speed = IXGBE_LINK_SPEED_10GB_FULL |
891 IXGBE_LINK_SPEED_1GB_FULL;
893 *speed = IXGBE_LINK_SPEED_10GB_FULL;
895 *speed = IXGBE_LINK_SPEED_10GB_FULL |
896 IXGBE_LINK_SPEED_1GB_FULL;
900 return IXGBE_SUCCESS;
904 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
905 * @hw: pointer to hardware structure
907 * Initialize any function pointers that were not able to be
908 * set during init_shared_code because the PHY/SFP type was
909 * not known. Perform the SFP init if necessary.
911 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
913 struct ixgbe_phy_info *phy = &hw->phy;
917 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
919 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
920 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
921 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
923 if (hw->bus.lan_id) {
924 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
925 esdp |= IXGBE_ESDP_SDP1_DIR;
927 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
928 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
931 /* Identify the PHY or SFP module */
932 ret_val = phy->ops.identify(hw);
933 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
936 /* Setup function pointers based on detected SFP module and speeds */
937 ixgbe_init_mac_link_ops_X550em(hw);
938 if (phy->sfp_type != ixgbe_sfp_type_unknown)
939 phy->ops.reset = NULL;
941 /* Set functions pointers based on phy type */
942 switch (hw->phy.type) {
943 case ixgbe_phy_x550em_kr:
944 phy->ops.setup_link = ixgbe_setup_kr_x550em;
945 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
946 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
948 case ixgbe_phy_x550em_ext_t:
949 phy->ops.setup_internal_link = ixgbe_setup_internal_phy_x550em;
958 * ixgbe_reset_hw_X550em - Perform hardware reset
959 * @hw: pointer to hardware structure
961 * Resets the hardware by resetting the transmit and receive units, masks
962 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
965 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
967 ixgbe_link_speed link_speed;
971 bool link_up = false;
973 DEBUGFUNC("ixgbe_reset_hw_X550em");
975 /* Call adapter stop to disable Tx/Rx and clear interrupts */
976 status = hw->mac.ops.stop_adapter(hw);
977 if (status != IXGBE_SUCCESS)
980 /* flush pending Tx transactions */
981 ixgbe_clear_tx_pending(hw);
983 /* PHY ops must be identified and initialized prior to reset */
985 /* Identify PHY and related function pointers */
986 status = hw->phy.ops.init(hw);
988 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
991 /* start the external PHY */
992 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
993 status = ixgbe_init_ext_t_x550em(hw);
998 /* Setup SFP module if there is one present. */
999 if (hw->phy.sfp_setup_needed) {
1000 status = hw->mac.ops.setup_sfp(hw);
1001 hw->phy.sfp_setup_needed = false;
1004 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1008 if (!hw->phy.reset_disable && hw->phy.ops.reset)
1009 hw->phy.ops.reset(hw);
1012 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1013 * If link reset is used when link is up, it might reset the PHY when
1014 * mng is using it. If link is down or the flag to force full link
1015 * reset is set, then perform link reset.
1017 ctrl = IXGBE_CTRL_LNK_RST;
1018 if (!hw->force_full_reset) {
1019 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1021 ctrl = IXGBE_CTRL_RST;
1024 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1025 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1026 IXGBE_WRITE_FLUSH(hw);
1028 /* Poll for reset bit to self-clear meaning reset is complete */
1029 for (i = 0; i < 10; i++) {
1031 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1032 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1036 if (ctrl & IXGBE_CTRL_RST_MASK) {
1037 status = IXGBE_ERR_RESET_FAILED;
1038 DEBUGOUT("Reset polling failed to complete.\n");
1043 /* Double resets are required for recovery from certain error
1044 * conditions. Between resets, it is necessary to stall to
1045 * allow time for any pending HW events to complete.
1047 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1048 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1052 /* Store the permanent mac address */
1053 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1055 /* Store MAC address from RAR0, clear receive address registers, and
1056 * clear the multicast table. Also reset num_rar_entries to 128,
1057 * since we modify this value when programming the SAN MAC address.
1059 hw->mac.num_rar_entries = 128;
1060 hw->mac.ops.init_rx_addrs(hw);
1067 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1068 * @hw: pointer to hardware structure
1070 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1076 /* TODO: The number of attempts and delay between attempts is undefined */
1078 /* decrement retries counter and exit if we hit 0 */
1080 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1081 "External PHY not yet finished resetting.");
1082 return IXGBE_ERR_PHY;
1088 status = hw->phy.ops.read_reg(hw,
1089 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1090 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1093 if (status != IXGBE_SUCCESS)
1096 /* Verify PHY FW reset has completed */
1097 } while ((reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) != 1);
1099 /* Set port to low power mode */
1100 status = hw->phy.ops.read_reg(hw,
1101 IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1102 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1105 if (status != IXGBE_SUCCESS)
1108 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
1110 status = hw->phy.ops.write_reg(hw,
1111 IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
1112 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1115 if (status != IXGBE_SUCCESS)
1118 /* Enable the transmitter */
1119 status = hw->phy.ops.read_reg(hw,
1120 IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1121 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1124 if (status != IXGBE_SUCCESS)
1127 reg &= ~IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE;
1129 status = hw->phy.ops.write_reg(hw,
1130 IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR,
1131 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1134 if (status != IXGBE_SUCCESS)
1137 /* Un-stall the PHY FW */
1138 status = hw->phy.ops.read_reg(hw,
1139 IXGBE_MDIO_GLOBAL_RES_PR_10,
1140 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1143 if (status != IXGBE_SUCCESS)
1146 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1148 status = hw->phy.ops.write_reg(hw,
1149 IXGBE_MDIO_GLOBAL_RES_PR_10,
1150 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1157 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1158 * @hw: pointer to hardware structure
1160 * Configures the integrated KR PHY.
1162 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1167 status = ixgbe_read_iosf_sb_reg_x550(hw,
1168 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1169 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1173 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1174 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1175 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1176 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1177 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1179 /* Advertise 10G support. */
1180 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1181 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1183 /* Advertise 1G support. */
1184 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1185 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1187 /* Restart auto-negotiation. */
1188 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1189 status = ixgbe_write_iosf_sb_reg_x550(hw,
1190 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1191 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1197 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
1198 * @hw: pointer to hardware structure
1199 * @speed: the link speed to force
1201 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1202 * internal and external PHY at a specific speed, without autonegotiation.
1204 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1209 /* Disable AN and force speed to 10G Serial. */
1210 status = ixgbe_read_iosf_sb_reg_x550(hw,
1211 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1212 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1213 if (status != IXGBE_SUCCESS)
1216 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1217 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1219 /* Select forced link speed for internal PHY. */
1221 case IXGBE_LINK_SPEED_10GB_FULL:
1222 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1224 case IXGBE_LINK_SPEED_1GB_FULL:
1225 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1228 /* Other link speeds are not supported by internal KR PHY. */
1229 return IXGBE_ERR_LINK_SETUP;
1232 status = ixgbe_write_iosf_sb_reg_x550(hw,
1233 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1234 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1235 if (status != IXGBE_SUCCESS)
1238 /* Disable training protocol FSM. */
1239 status = ixgbe_read_iosf_sb_reg_x550(hw,
1240 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1241 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1242 if (status != IXGBE_SUCCESS)
1244 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1245 status = ixgbe_write_iosf_sb_reg_x550(hw,
1246 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1247 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1248 if (status != IXGBE_SUCCESS)
1251 /* Disable Flex from training TXFFE. */
1252 status = ixgbe_read_iosf_sb_reg_x550(hw,
1253 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1254 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1255 if (status != IXGBE_SUCCESS)
1257 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1258 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1259 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1260 status = ixgbe_write_iosf_sb_reg_x550(hw,
1261 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1262 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1263 if (status != IXGBE_SUCCESS)
1265 status = ixgbe_read_iosf_sb_reg_x550(hw,
1266 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1267 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1268 if (status != IXGBE_SUCCESS)
1270 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1271 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1272 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1273 status = ixgbe_write_iosf_sb_reg_x550(hw,
1274 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1275 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1276 if (status != IXGBE_SUCCESS)
1279 /* Enable override for coefficients. */
1280 status = ixgbe_read_iosf_sb_reg_x550(hw,
1281 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1282 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1283 if (status != IXGBE_SUCCESS)
1285 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1286 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1287 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1288 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1289 status = ixgbe_write_iosf_sb_reg_x550(hw,
1290 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1291 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1292 if (status != IXGBE_SUCCESS)
1295 /* Toggle port SW reset by AN reset. */
1296 status = ixgbe_read_iosf_sb_reg_x550(hw,
1297 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1298 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1299 if (status != IXGBE_SUCCESS)
1301 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1302 status = ixgbe_write_iosf_sb_reg_x550(hw,
1303 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1304 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1310 * ixgbe_setup_internal_phy_x550em - Configure integrated KR PHY
1311 * @hw: point to hardware structure
1313 * Configures the integrated KR PHY to talk to the external PHY. The base
1314 * driver will call this function when it gets notification via interrupt from
1315 * the external PHY. This function forces the internal PHY into iXFI mode at
1316 * the correct speed.
1318 * A return of a non-zero value indicates an error, and the base driver should
1319 * not report link up.
1321 s32 ixgbe_setup_internal_phy_x550em(struct ixgbe_hw *hw)
1324 u16 lasi, autoneg_status, speed;
1325 ixgbe_link_speed force_speed;
1327 /* Verify that the external link status has changed */
1328 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_XENPAK_LASI_STATUS,
1329 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1331 if (status != IXGBE_SUCCESS)
1334 /* If there was no change in link status, we can just exit */
1335 if (!(lasi & IXGBE_XENPAK_LASI_LINK_STATUS_ALARM))
1336 return IXGBE_SUCCESS;
1338 /* we read this twice back to back to indicate current status */
1339 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1340 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1342 if (status != IXGBE_SUCCESS)
1345 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1346 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1348 if (status != IXGBE_SUCCESS)
1351 /* If link is not up return an error indicating treat link as down */
1352 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1353 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1355 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
1356 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1359 /* clear everything but the speed and duplex bits */
1360 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
1363 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
1364 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1366 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
1367 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1370 /* Internal PHY does not support anything else */
1371 return IXGBE_ERR_INVALID_LINK_SETTINGS;
1374 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
1378 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1379 * @hw: pointer to hardware structure
1381 * Configures the integrated KR PHY to use internal loopback mode.
1383 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1388 /* Disable AN and force speed to 10G Serial. */
1389 status = ixgbe_read_iosf_sb_reg_x550(hw,
1390 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1391 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1392 if (status != IXGBE_SUCCESS)
1394 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1395 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1396 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1397 status = ixgbe_write_iosf_sb_reg_x550(hw,
1398 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1399 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1400 if (status != IXGBE_SUCCESS)
1403 /* Set near-end loopback clocks. */
1404 status = ixgbe_read_iosf_sb_reg_x550(hw,
1405 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1406 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1407 if (status != IXGBE_SUCCESS)
1409 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1410 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1411 status = ixgbe_write_iosf_sb_reg_x550(hw,
1412 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
1413 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1414 if (status != IXGBE_SUCCESS)
1417 /* Set loopback enable. */
1418 status = ixgbe_read_iosf_sb_reg_x550(hw,
1419 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1420 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1421 if (status != IXGBE_SUCCESS)
1423 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1424 status = ixgbe_write_iosf_sb_reg_x550(hw,
1425 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
1426 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1427 if (status != IXGBE_SUCCESS)
1430 /* Training bypass. */
1431 status = ixgbe_read_iosf_sb_reg_x550(hw,
1432 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1433 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1434 if (status != IXGBE_SUCCESS)
1436 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1437 status = ixgbe_write_iosf_sb_reg_x550(hw,
1438 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1439 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1445 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1446 * assuming that the semaphore is already obtained.
1447 * @hw: pointer to hardware structure
1448 * @offset: offset of word in the EEPROM to read
1449 * @data: word read from the EEPROM
1451 * Reads a 16 bit word from the EEPROM using the hostif.
1453 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1457 struct ixgbe_hic_read_shadow_ram buffer;
1459 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1460 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1461 buffer.hdr.buf_len1 = 0;
1462 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1463 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1465 /* convert offset from words to bytes */
1466 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1468 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1470 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1471 sizeof(buffer), false);
1476 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1477 FW_NVM_DATA_OFFSET);
1483 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1484 * @hw: pointer to hardware structure
1485 * @offset: offset of word in the EEPROM to read
1486 * @data: word read from the EEPROM
1488 * Reads a 16 bit word from the EEPROM using the hostif.
1490 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1493 s32 status = IXGBE_SUCCESS;
1495 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1497 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1499 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1500 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1502 status = IXGBE_ERR_SWFW_SYNC;
1509 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1510 * @hw: pointer to hardware structure
1511 * @offset: offset of word in the EEPROM to read
1512 * @words: number of words
1513 * @data: word(s) read from the EEPROM
1515 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1517 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1518 u16 offset, u16 words, u16 *data)
1520 struct ixgbe_hic_read_shadow_ram buffer;
1521 u32 current_word = 0;
1526 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1528 /* Take semaphore for the entire operation. */
1529 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1531 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1535 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1536 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1538 words_to_read = words;
1540 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1541 buffer.hdr.buf_len1 = 0;
1542 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1543 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1545 /* convert offset from words to bytes */
1546 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1547 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1549 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1550 sizeof(buffer), false);
1553 DEBUGOUT("Host interface command failed\n");
1557 for (i = 0; i < words_to_read; i++) {
1558 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1560 u32 value = IXGBE_READ_REG(hw, reg);
1562 data[current_word] = (u16)(value & 0xffff);
1565 if (i < words_to_read) {
1567 data[current_word] = (u16)(value & 0xffff);
1571 words -= words_to_read;
1575 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1580 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1581 * @hw: pointer to hardware structure
1582 * @offset: offset of word in the EEPROM to write
1583 * @data: word write to the EEPROM
1585 * Write a 16 bit word to the EEPROM using the hostif.
1587 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1591 struct ixgbe_hic_write_shadow_ram buffer;
1593 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1595 buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1596 buffer.hdr.buf_len1 = 0;
1597 buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1598 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1601 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1603 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1605 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1606 sizeof(buffer), false);
1612 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1613 * @hw: pointer to hardware structure
1614 * @offset: offset of word in the EEPROM to write
1615 * @data: word write to the EEPROM
1617 * Write a 16 bit word to the EEPROM using the hostif.
1619 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1622 s32 status = IXGBE_SUCCESS;
1624 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1626 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1628 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1629 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1631 DEBUGOUT("write ee hostif failed to get semaphore");
1632 status = IXGBE_ERR_SWFW_SYNC;
1639 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1640 * @hw: pointer to hardware structure
1641 * @offset: offset of word in the EEPROM to write
1642 * @words: number of words
1643 * @data: word(s) write to the EEPROM
1645 * Write a 16 bit word(s) to the EEPROM using the hostif.
1647 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1648 u16 offset, u16 words, u16 *data)
1650 s32 status = IXGBE_SUCCESS;
1653 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1655 /* Take semaphore for the entire operation. */
1656 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1657 if (status != IXGBE_SUCCESS) {
1658 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1662 for (i = 0; i < words; i++) {
1663 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1666 if (status != IXGBE_SUCCESS) {
1667 DEBUGOUT("Eeprom buffered write failed\n");
1672 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1679 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1680 * @hw: pointer to hardware structure
1681 * @ptr: pointer offset in eeprom
1682 * @size: size of section pointed by ptr, if 0 first word will be used as size
1683 * @csum: address of checksum to update
1685 * Returns error status for any failure
1687 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1688 u16 size, u16 *csum)
1692 u16 length, bufsz, i, start;
1694 bufsz = sizeof(buf) / sizeof(buf[0]);
1696 /* Read a chunk at the pointer location */
1697 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1699 DEBUGOUT("Failed to read EEPROM image\n");
1710 /* Skip pointer section if length is invalid. */
1711 if (length == 0xFFFF || length == 0 ||
1712 (ptr + length) >= hw->eeprom.word_size)
1713 return IXGBE_SUCCESS;
1716 for (i = start; length; i++, length--) {
1723 /* Read a chunk at the pointer location */
1724 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1727 DEBUGOUT("Failed to read EEPROM image\n");
1733 return IXGBE_SUCCESS;
1737 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1738 * @hw: pointer to hardware structure
1740 * Returns a negative error code on error, or the 16-bit checksum
1742 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1744 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1747 u16 pointer, i, size;
1749 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1751 hw->eeprom.ops.init_params(hw);
1753 /* Read pointer area */
1754 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1755 IXGBE_EEPROM_LAST_WORD + 1,
1758 DEBUGOUT("Failed to read EEPROM image\n");
1763 * For X550 hardware include 0x0-0x41 in the checksum, skip the
1764 * checksum word itself
1766 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1767 if (i != IXGBE_EEPROM_CHECKSUM)
1768 checksum += eeprom_ptrs[i];
1771 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
1772 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1774 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1775 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1778 pointer = eeprom_ptrs[i];
1780 /* Skip pointer section if the pointer is invalid. */
1781 if (pointer == 0xFFFF || pointer == 0 ||
1782 pointer >= hw->eeprom.word_size)
1786 case IXGBE_PCIE_GENERAL_PTR:
1787 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1789 case IXGBE_PCIE_CONFIG0_PTR:
1790 case IXGBE_PCIE_CONFIG1_PTR:
1791 size = IXGBE_PCIE_CONFIG_SIZE;
1798 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);
1803 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1805 return (s32)checksum;
1809 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1810 * @hw: pointer to hardware structure
1811 * @checksum_val: calculated checksum
1813 * Performs checksum calculation and validates the EEPROM checksum. If the
1814 * caller does not need checksum_val, the value can be NULL.
1816 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1820 u16 read_checksum = 0;
1822 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1824 /* Read the first word from the EEPROM. If this times out or fails, do
1825 * not continue or we could be in for a very long wait while every
1828 status = hw->eeprom.ops.read(hw, 0, &checksum);
1830 DEBUGOUT("EEPROM read failed\n");
1834 status = hw->eeprom.ops.calc_checksum(hw);
1838 checksum = (u16)(status & 0xffff);
1840 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1845 /* Verify read checksum from EEPROM is the same as
1846 * calculated checksum
1848 if (read_checksum != checksum) {
1849 status = IXGBE_ERR_EEPROM_CHECKSUM;
1850 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1851 "Invalid EEPROM checksum");
1854 /* If the user cares, return the calculated checksum */
1856 *checksum_val = checksum;
1862 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1863 * @hw: pointer to hardware structure
1865 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1866 * checksum and updates the EEPROM and instructs the hardware to update
1869 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1874 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1876 /* Read the first word from the EEPROM. If this times out or fails, do
1877 * not continue or we could be in for a very long wait while every
1880 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1882 DEBUGOUT("EEPROM read failed\n");
1886 status = ixgbe_calc_eeprom_checksum_X550(hw);
1890 checksum = (u16)(status & 0xffff);
1892 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1897 status = ixgbe_update_flash_X550(hw);
1903 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1904 * @hw: pointer to hardware structure
1906 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1908 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1910 s32 status = IXGBE_SUCCESS;
1911 struct ixgbe_hic_hdr2 buffer;
1913 DEBUGFUNC("ixgbe_update_flash_X550");
1915 buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1916 buffer.buf_len1 = 0;
1917 buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1918 buffer.checksum = FW_DEFAULT_CHECKSUM;
1920 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1921 sizeof(buffer), false);
1927 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
1928 * @hw: pointer to hardware structure
1930 * Determines physical layer capabilities of the current configuration.
1932 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
1934 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1935 u16 ext_ability = 0;
1937 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
1939 hw->phy.ops.identify(hw);
1941 switch (hw->phy.type) {
1942 case ixgbe_phy_x550em_kr:
1943 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
1944 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1946 case ixgbe_phy_x550em_kx4:
1947 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1948 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1950 case ixgbe_phy_x550em_ext_t:
1951 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1952 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1954 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1955 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1956 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1957 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1963 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1964 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1966 return physical_layer;
1970 * ixgbe_get_bus_info_x550em - Set PCI bus info
1971 * @hw: pointer to hardware structure
1973 * Sets bus link width and speed to unknown because X550em is
1976 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1979 DEBUGFUNC("ixgbe_get_bus_info_x550em");
1981 hw->bus.width = ixgbe_bus_width_unknown;
1982 hw->bus.speed = ixgbe_bus_speed_unknown;
1984 return IXGBE_SUCCESS;
1988 * ixgbe_disable_rx_x550 - Disable RX unit
1990 * Enables the Rx DMA unit for x550
1992 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1994 u32 rxctrl, pfdtxgswc;
1996 struct ixgbe_hic_disable_rxen fw_cmd;
1998 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2000 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2001 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2002 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2003 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2004 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2005 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2006 hw->mac.set_lben = true;
2008 hw->mac.set_lben = false;
2011 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2012 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2013 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2014 fw_cmd.port_number = (u8)hw->bus.lan_id;
2016 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2017 sizeof(struct ixgbe_hic_disable_rxen),
2020 /* If we fail - disable RX using register write */
2022 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2023 if (rxctrl & IXGBE_RXCTRL_RXEN) {
2024 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2025 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);