1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x550.h"
35 #include "ixgbe_x540.h"
36 #include "ixgbe_type.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
42 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type
43 * @hw: pointer to hardware structure
45 * Initialize the function pointers and assign the MAC type for X550.
46 * Does not touch the hardware.
48 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
50 struct ixgbe_mac_info *mac = &hw->mac;
51 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
54 DEBUGFUNC("ixgbe_init_ops_X550");
56 ret_val = ixgbe_init_ops_X540(hw);
57 mac->ops.dmac_config = ixgbe_dmac_config_X550;
58 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
59 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
60 mac->ops.setup_eee = ixgbe_setup_eee_X550;
61 mac->ops.set_source_address_pruning =
62 ixgbe_set_source_address_pruning_X550;
63 mac->ops.set_ethertype_anti_spoofing =
64 ixgbe_set_ethertype_anti_spoofing_X550;
66 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
67 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
68 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
69 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
70 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
71 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
72 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
73 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
74 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
76 mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
77 mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
78 mac->ops.mdd_event = ixgbe_mdd_event_X550;
79 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
80 mac->ops.disable_rx = ixgbe_disable_rx_x550;
85 * ixgbe_identify_phy_x550em - Get PHY type based on device id
86 * @hw: pointer to hardware structure
90 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
92 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
94 switch (hw->device_id) {
95 case IXGBE_DEV_ID_X550EM_X_SFP:
96 /* set up for CS4227 usage */
97 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
98 IXGBE_STATUS_LAN_ID_1;
99 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
100 if (hw->phy.lan_id) {
102 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
103 esdp |= IXGBE_ESDP_SDP1_DIR;
105 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
106 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
108 return ixgbe_identify_module_generic(hw);
110 case IXGBE_DEV_ID_X550EM_X_KX4:
111 hw->phy.type = ixgbe_phy_x550em_kx4;
113 case IXGBE_DEV_ID_X550EM_X_KR:
114 case IXGBE_DEV_ID_X550EM_X:
115 hw->phy.type = ixgbe_phy_x550em_kr;
120 return IXGBE_SUCCESS;
123 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
124 u32 device_type, u16 *phy_data)
126 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
127 return IXGBE_NOT_IMPLEMENTED;
130 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
131 u32 device_type, u16 phy_data)
133 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
134 return IXGBE_NOT_IMPLEMENTED;
138 * ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
139 * @hw: pointer to hardware structure
141 * Initialize the function pointers and for MAC type X550EM.
142 * Does not touch the hardware.
144 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
146 struct ixgbe_mac_info *mac = &hw->mac;
147 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
148 struct ixgbe_phy_info *phy = &hw->phy;
151 DEBUGFUNC("ixgbe_init_ops_X550EM");
153 /* Similar to X550 so start there. */
154 ret_val = ixgbe_init_ops_X550(hw);
156 /* Since this function eventually calls
157 * ixgbe_init_ops_540 by design, we are setting
158 * the pointers to NULL explicitly here to overwrite
159 * the values being set in the x540 function.
161 /* Thermal sensor not supported in x550EM */
162 mac->ops.get_thermal_sensor_data = NULL;
163 mac->ops.init_thermal_sensor_thresh = NULL;
164 mac->thermal_sensor_enabled = false;
166 /* FCOE not supported in x550EM */
167 mac->ops.get_san_mac_addr = NULL;
168 mac->ops.set_san_mac_addr = NULL;
169 mac->ops.get_wwn_prefix = NULL;
170 mac->ops.get_fcoe_boot_status = NULL;
172 /* IPsec not supported in x550EM */
173 mac->ops.disable_sec_rx_path = NULL;
174 mac->ops.enable_sec_rx_path = NULL;
176 /* PCIe bus info not supported in X550EM */
177 mac->ops.get_bus_info = NULL;
179 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
180 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
181 mac->ops.get_media_type = ixgbe_get_media_type_X550em;
182 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
183 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
184 mac->ops.reset_hw = ixgbe_reset_hw_X550em;
185 mac->ops.get_supported_physical_layer =
186 ixgbe_get_supported_physical_layer_X550em;
189 phy->ops.init = &ixgbe_init_phy_ops_X550em;
190 phy->ops.identify = &ixgbe_identify_phy_x550em;
191 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
192 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
193 phy->ops.setup_link = ixgbe_setup_kr_x550em;
197 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
198 eeprom->ops.read = ixgbe_read_ee_hostif_X550;
199 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
200 eeprom->ops.write = ixgbe_write_ee_hostif_X550;
201 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
202 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
203 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
204 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
210 * ixgbe_dmac_config_X550
211 * @hw: pointer to hardware structure
213 * Configure DMA coalescing. If enabling dmac, dmac is activated.
214 * When disabling dmac, dmac enable dmac bit is cleared.
216 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
218 u32 reg, high_pri_tc;
220 DEBUGFUNC("ixgbe_dmac_config_X550");
222 /* Disable DMA coalescing before configuring */
223 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
224 reg &= ~IXGBE_DMACR_DMAC_EN;
225 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
227 /* Disable DMA Coalescing if the watchdog timer is 0 */
228 if (!hw->mac.dmac_config.watchdog_timer)
231 ixgbe_dmac_config_tcs_X550(hw);
233 /* Configure DMA Coalescing Control Register */
234 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
236 /* Set the watchdog timer in units of 40.96 usec */
237 reg &= ~IXGBE_DMACR_DMACWT_MASK;
238 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
240 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
241 /* If fcoe is enabled, set high priority traffic class */
242 if (hw->mac.dmac_config.fcoe_en) {
243 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
244 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
245 IXGBE_DMACR_HIGH_PRI_TC_MASK);
247 reg |= IXGBE_DMACR_EN_MNG_IND;
249 /* Enable DMA coalescing after configuration */
250 reg |= IXGBE_DMACR_DMAC_EN;
251 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
254 return IXGBE_SUCCESS;
258 * ixgbe_dmac_config_tcs_X550
259 * @hw: pointer to hardware structure
261 * Configure DMA coalescing threshold per TC. The dmac enable bit must
262 * be cleared before configuring.
264 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
266 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
268 DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
270 /* Configure DMA coalescing enabled */
271 switch (hw->mac.dmac_config.link_speed) {
272 case IXGBE_LINK_SPEED_100_FULL:
273 pb_headroom = IXGBE_DMACRXT_100M;
275 case IXGBE_LINK_SPEED_1GB_FULL:
276 pb_headroom = IXGBE_DMACRXT_1G;
279 pb_headroom = IXGBE_DMACRXT_10G;
283 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
284 IXGBE_MHADD_MFS_SHIFT) / 1024);
286 /* Set the per Rx packet buffer receive threshold */
287 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
288 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
289 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
291 if (tc < hw->mac.dmac_config.num_tcs) {
293 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
294 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
295 IXGBE_RXPBSIZE_SHIFT;
297 /* Calculate receive buffer threshold in kilobytes */
298 if (rx_pb_size > pb_headroom)
299 rx_pb_size = rx_pb_size - pb_headroom;
303 /* Minimum of MFS shall be set for DMCTH */
304 reg |= (rx_pb_size > maxframe_size_kb) ?
305 rx_pb_size : maxframe_size_kb;
307 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
309 return IXGBE_SUCCESS;
313 * ixgbe_dmac_update_tcs_X550
314 * @hw: pointer to hardware structure
316 * Disables dmac, updates per TC settings, and then enables dmac.
318 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
322 DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
324 /* Disable DMA coalescing before configuring */
325 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
326 reg &= ~IXGBE_DMACR_DMAC_EN;
327 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
329 ixgbe_dmac_config_tcs_X550(hw);
331 /* Enable DMA coalescing after configuration */
332 reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
333 reg |= IXGBE_DMACR_DMAC_EN;
334 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
336 return IXGBE_SUCCESS;
340 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
341 * @hw: pointer to hardware structure
343 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
344 * ixgbe_hw struct in order to set up EEPROM access.
346 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
348 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
352 DEBUGFUNC("ixgbe_init_eeprom_params_X550");
354 if (eeprom->type == ixgbe_eeprom_uninitialized) {
355 eeprom->semaphore_delay = 10;
356 eeprom->type = ixgbe_flash;
358 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
359 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
360 IXGBE_EEC_SIZE_SHIFT);
361 eeprom->word_size = 1 << (eeprom_size +
362 IXGBE_EEPROM_WORD_SIZE_SHIFT);
364 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
365 eeprom->type, eeprom->word_size);
368 return IXGBE_SUCCESS;
372 * ixgbe_setup_eee_X550 - Enable/disable EEE support
373 * @hw: pointer to the HW structure
374 * @enable_eee: boolean flag to enable EEE
376 * Enable/disable EEE based on enable_eee flag.
377 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
381 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
388 DEBUGFUNC("ixgbe_setup_eee_X550");
390 eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
391 /* Enable or disable EEE per flag */
393 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
395 if (hw->device_id == IXGBE_DEV_ID_X550T) {
396 /* Advertise EEE capability */
397 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
398 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
400 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
401 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
402 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
404 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
405 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
406 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
407 hw->device_id == IXGBE_DEV_ID_X550EM_X) {
408 status = ixgbe_read_iosf_sb_reg_x550(hw,
409 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
410 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
411 if (status != IXGBE_SUCCESS)
414 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
415 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
417 status = ixgbe_write_iosf_sb_reg_x550(hw,
418 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
419 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
420 if (status != IXGBE_SUCCESS)
424 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
426 if (hw->device_id == IXGBE_DEV_ID_X550T) {
427 /* Disable advertised EEE capability */
428 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
429 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
431 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
432 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
433 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
435 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
436 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
437 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR ||
438 hw->device_id == IXGBE_DEV_ID_X550EM_X) {
439 status = ixgbe_read_iosf_sb_reg_x550(hw,
440 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
441 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
442 if (status != IXGBE_SUCCESS)
445 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
446 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
448 status = ixgbe_write_iosf_sb_reg_x550(hw,
449 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
450 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
451 if (status != IXGBE_SUCCESS)
455 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
457 return IXGBE_SUCCESS;
461 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
462 * @hw: pointer to hardware structure
463 * @enable: enable or disable source address pruning
464 * @pool: Rx pool to set source address pruning for
466 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
471 /* max rx pool is 63 */
475 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
476 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
479 pfflp |= (1ULL << pool);
481 pfflp &= ~(1ULL << pool);
483 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
484 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
488 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
489 * @hw: pointer to hardware structure
490 * @enable: enable or disable switch for Ethertype anti-spoofing
491 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
494 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
497 int vf_target_reg = vf >> 3;
498 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
501 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
503 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
505 pfvfspoof |= (1 << vf_target_shift);
507 pfvfspoof &= ~(1 << vf_target_shift);
509 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
513 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
515 * @hw: pointer to hardware structure
516 * @reg_addr: 32 bit PHY register to write
517 * @device_type: 3 bit device type
518 * @data: Data to write to the register
520 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
521 u32 device_type, u32 data)
523 u32 i, command, error;
525 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
526 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
528 /* Write IOSF control register */
529 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
531 /* Write IOSF data register */
532 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
534 * Check every 10 usec to see if the address cycle completed.
535 * The SB IOSF BUSY bit will clear when the operation is
538 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
541 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
542 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
546 if ((command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) != 0) {
547 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
548 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
549 ERROR_REPORT2(IXGBE_ERROR_POLLING,
550 "Failed to write, error %x\n", error);
551 return IXGBE_ERR_PHY;
554 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
555 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n");
556 return IXGBE_ERR_PHY;
559 return IXGBE_SUCCESS;
563 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
565 * @hw: pointer to hardware structure
566 * @reg_addr: 32 bit PHY register to write
567 * @device_type: 3 bit device type
568 * @phy_data: Pointer to read data from the register
570 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
571 u32 device_type, u32 *data)
573 u32 i, command, error;
575 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
576 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
578 /* Write IOSF control register */
579 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
582 * Check every 10 usec to see if the address cycle completed.
583 * The SB IOSF BUSY bit will clear when the operation is
586 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
589 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
590 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
594 if ((command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) != 0) {
595 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
596 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
597 ERROR_REPORT2(IXGBE_ERROR_POLLING,
598 "Failed to read, error %x\n", error);
599 return IXGBE_ERR_PHY;
602 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
603 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n");
604 return IXGBE_ERR_PHY;
607 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
609 return IXGBE_SUCCESS;
613 * ixgbe_disable_mdd_X550
614 * @hw: pointer to hardware structure
616 * Disable malicious driver detection
618 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
622 DEBUGFUNC("ixgbe_disable_mdd_X550");
624 /* Disable MDD for TX DMA and interrupt */
625 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
626 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
627 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
629 /* Disable MDD for RX and interrupt */
630 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
631 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
632 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
636 * ixgbe_enable_mdd_X550
637 * @hw: pointer to hardware structure
639 * Enable malicious driver detection
641 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
645 DEBUGFUNC("ixgbe_enable_mdd_X550");
647 /* Enable MDD for TX DMA and interrupt */
648 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
649 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
650 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
652 /* Enable MDD for RX and interrupt */
653 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
654 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
655 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
659 * ixgbe_restore_mdd_vf_X550
660 * @hw: pointer to hardware structure
663 * Restore VF that was disabled during malicious driver detection event
665 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
667 u32 idx, reg, num_qs, start_q, bitmask;
669 DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
671 /* Map VF to queues */
672 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
673 switch (reg & IXGBE_MRQC_MRQE_MASK) {
674 case IXGBE_MRQC_VMDQRT8TCEN:
675 num_qs = 8; /* 16 VFs / pools */
676 bitmask = 0x000000FF;
678 case IXGBE_MRQC_VMDQRSS32EN:
679 case IXGBE_MRQC_VMDQRT4TCEN:
680 num_qs = 4; /* 32 VFs / pools */
681 bitmask = 0x0000000F;
683 default: /* 64 VFs / pools */
685 bitmask = 0x00000003;
688 start_q = vf * num_qs;
690 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
693 reg |= (bitmask << (start_q % 32));
694 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
695 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
699 * ixgbe_mdd_event_X550
700 * @hw: pointer to hardware structure
701 * @vf_bitmap: vf bitmap of malicious vfs
703 * Handle malicious driver detection event.
705 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
708 u32 i, j, reg, q, shift, vf, idx;
710 DEBUGFUNC("ixgbe_mdd_event_X550");
712 /* figure out pool size for mapping to vf's */
713 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
714 switch (reg & IXGBE_MRQC_MRQE_MASK) {
715 case IXGBE_MRQC_VMDQRT8TCEN:
716 shift = 3; /* 16 VFs / pools */
718 case IXGBE_MRQC_VMDQRSS32EN:
719 case IXGBE_MRQC_VMDQRT4TCEN:
720 shift = 2; /* 32 VFs / pools */
723 shift = 1; /* 64 VFs / pools */
727 /* Read WQBR_TX and WQBR_RX and check for malicious queues */
728 for (i = 0; i < 4; i++) {
729 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
730 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
735 /* Get malicious queue */
736 for (j = 0; j < 32 && wqbr; j++) {
738 if (!(wqbr & (1 << j)))
741 /* Get queue from bitmask */
744 /* Map queue to vf */
747 /* Set vf bit in vf_bitmap */
749 vf_bitmap[idx] |= (1 << (vf % 32));
756 * ixgbe_get_media_type_X550em - Get media type
757 * @hw: pointer to hardware structure
759 * Returns the media type (fiber, copper, backplane)
761 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
763 enum ixgbe_media_type media_type;
765 DEBUGFUNC("ixgbe_get_media_type_X550em");
767 /* Detect if there is a copper PHY attached. */
768 switch (hw->device_id) {
769 case IXGBE_DEV_ID_X550EM_X:
770 case IXGBE_DEV_ID_X550EM_X_KR:
771 case IXGBE_DEV_ID_X550EM_X_KX4:
772 media_type = ixgbe_media_type_backplane;
774 case IXGBE_DEV_ID_X550EM_X_SFP:
775 media_type = ixgbe_media_type_fiber;
778 media_type = ixgbe_media_type_unknown;
785 * ixgbe_setup_sfp_modules_X550em - Setup SFP module
786 * @hw: pointer to hardware structure
788 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
791 u16 reg_slice, edc_mode;
794 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
796 switch (hw->phy.sfp_type) {
797 case ixgbe_sfp_type_unknown:
798 return IXGBE_SUCCESS;
799 case ixgbe_sfp_type_not_present:
800 return IXGBE_ERR_SFP_NOT_PRESENT;
801 case ixgbe_sfp_type_da_cu_core0:
802 case ixgbe_sfp_type_da_cu_core1:
805 case ixgbe_sfp_type_srlr_core0:
806 case ixgbe_sfp_type_srlr_core1:
807 case ixgbe_sfp_type_da_act_lmt_core0:
808 case ixgbe_sfp_type_da_act_lmt_core1:
809 case ixgbe_sfp_type_1g_sx_core0:
810 case ixgbe_sfp_type_1g_sx_core1:
811 case ixgbe_sfp_type_1g_lx_core0:
812 case ixgbe_sfp_type_1g_lx_core1:
813 setup_linear = false;
816 return IXGBE_ERR_SFP_NOT_SUPPORTED;
819 ixgbe_init_mac_link_ops_X550em(hw);
820 hw->phy.ops.reset = NULL;
822 /* The CS4227 slice address is the base address + the port-pair reg
823 * offset. I.e. Slice 0 = 0x0000 and slice 1 = 0x1000.
825 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->phy.lan_id << 12);
828 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
830 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
832 /* Configure CS4227 for connection type. */
833 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,
840 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers
841 * @hw: pointer to hardware structure
843 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
845 struct ixgbe_mac_info *mac = &hw->mac;
847 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
849 /* CS4227 does not support autoneg, so disable the laser control
850 * functions for SFP+ fiber
852 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
853 mac->ops.disable_tx_laser = NULL;
854 mac->ops.enable_tx_laser = NULL;
855 mac->ops.flap_tx_laser = NULL;
860 * ixgbe_get_link_capabilities_x550em - Determines link capabilities
861 * @hw: pointer to hardware structure
862 * @speed: pointer to link speed
863 * @autoneg: true when autoneg or autotry is enabled
865 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
866 ixgbe_link_speed *speed,
869 DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
872 if (hw->phy.media_type == ixgbe_media_type_fiber) {
874 /* CS4227 SFP must not enable auto-negotiation */
877 /* Check if 1G SFP module. */
878 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
879 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
880 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
881 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
882 *speed = IXGBE_LINK_SPEED_1GB_FULL;
883 return IXGBE_SUCCESS;
886 /* Link capabilities are based on SFP */
887 if (hw->phy.multispeed_fiber)
888 *speed = IXGBE_LINK_SPEED_10GB_FULL |
889 IXGBE_LINK_SPEED_1GB_FULL;
891 *speed = IXGBE_LINK_SPEED_10GB_FULL;
893 *speed = IXGBE_LINK_SPEED_10GB_FULL |
894 IXGBE_LINK_SPEED_1GB_FULL;
898 return IXGBE_SUCCESS;
902 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init
903 * @hw: pointer to hardware structure
905 * Initialize any function pointers that were not able to be
906 * set during init_shared_code because the PHY/SFP type was
907 * not known. Perform the SFP init if necessary.
909 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
911 struct ixgbe_phy_info *phy = &hw->phy;
915 DEBUGFUNC("ixgbe_init_phy_ops_X550em");
917 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
918 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
919 phy->lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
920 IXGBE_STATUS_LAN_ID_1;
921 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
923 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
924 esdp |= IXGBE_ESDP_SDP1_DIR;
926 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
927 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
930 /* Identify the PHY or SFP module */
931 ret_val = phy->ops.identify(hw);
932 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
935 /* Setup function pointers based on detected SFP module and speeds */
936 ixgbe_init_mac_link_ops_X550em(hw);
937 if (phy->sfp_type != ixgbe_sfp_type_unknown)
938 phy->ops.reset = NULL;
940 /* Set functions pointers based on phy type */
941 switch (hw->phy.type) {
942 case ixgbe_phy_x550em_kr:
943 phy->ops.setup_link = ixgbe_setup_kr_x550em;
952 * ixgbe_reset_hw_X550em - Perform hardware reset
953 * @hw: pointer to hardware structure
955 * Resets the hardware by resetting the transmit and receive units, masks
956 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
959 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
961 ixgbe_link_speed link_speed;
965 bool link_up = false;
967 DEBUGFUNC("ixgbe_reset_hw_X550em");
969 /* Call adapter stop to disable Tx/Rx and clear interrupts */
970 status = hw->mac.ops.stop_adapter(hw);
971 if (status != IXGBE_SUCCESS)
974 /* flush pending Tx transactions */
975 ixgbe_clear_tx_pending(hw);
977 /* PHY ops must be identified and initialized prior to reset */
979 /* Identify PHY and related function pointers */
980 status = hw->phy.ops.init(hw);
982 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
985 /* Setup SFP module if there is one present. */
986 if (hw->phy.sfp_setup_needed) {
987 status = hw->mac.ops.setup_sfp(hw);
988 hw->phy.sfp_setup_needed = false;
991 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
995 if (!hw->phy.reset_disable && hw->phy.ops.reset)
996 hw->phy.ops.reset(hw);
999 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1000 * If link reset is used when link is up, it might reset the PHY when
1001 * mng is using it. If link is down or the flag to force full link
1002 * reset is set, then perform link reset.
1004 ctrl = IXGBE_CTRL_LNK_RST;
1005 if (!hw->force_full_reset) {
1006 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1008 ctrl = IXGBE_CTRL_RST;
1011 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1012 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1013 IXGBE_WRITE_FLUSH(hw);
1015 /* Poll for reset bit to self-clear meaning reset is complete */
1016 for (i = 0; i < 10; i++) {
1018 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1019 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1023 if (ctrl & IXGBE_CTRL_RST_MASK) {
1024 status = IXGBE_ERR_RESET_FAILED;
1025 DEBUGOUT("Reset polling failed to complete.\n");
1030 /* Double resets are required for recovery from certain error
1031 * conditions. Between resets, it is necessary to stall to
1032 * allow time for any pending HW events to complete.
1034 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1035 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1039 /* Store the permanent mac address */
1040 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1042 /* Store MAC address from RAR0, clear receive address registers, and
1043 * clear the multicast table. Also reset num_rar_entries to 128,
1044 * since we modify this value when programming the SAN MAC address.
1046 hw->mac.num_rar_entries = 128;
1047 hw->mac.ops.init_rx_addrs(hw);
1053 * ixgbe_setup_kr_x550em - Configure the KR PHY.
1054 * @hw: pointer to hardware structure
1056 * Configures the integrated KR PHY.
1058 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1063 status = ixgbe_read_iosf_sb_reg_x550(hw,
1064 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1065 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1067 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1068 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ;
1069 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
1070 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1071 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1073 /* Advertise 10G support. */
1074 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1075 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1077 /* Advertise 1G support. */
1078 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1079 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1081 /* Restart auto-negotiation. */
1082 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1083 status = ixgbe_write_iosf_sb_reg_x550(hw,
1084 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1085 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1091 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI.
1092 * @hw: pointer to hardware structure
1094 * Configures the integrated KR PHY to use iXFI mode.
1096 s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw)
1101 /* Disable AN and force speed to 10G Serial. */
1102 status = ixgbe_read_iosf_sb_reg_x550(hw,
1103 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1104 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1105 if (status != IXGBE_SUCCESS)
1107 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1108 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1109 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1110 status = ixgbe_write_iosf_sb_reg_x550(hw,
1111 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1112 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1113 if (status != IXGBE_SUCCESS)
1116 /* Disable training protocol FSM. */
1117 status = ixgbe_read_iosf_sb_reg_x550(hw,
1118 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1119 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1120 if (status != IXGBE_SUCCESS)
1122 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1123 status = ixgbe_write_iosf_sb_reg_x550(hw,
1124 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1125 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1126 if (status != IXGBE_SUCCESS)
1129 /* Disable Flex from training TXFFE. */
1130 status = ixgbe_read_iosf_sb_reg_x550(hw,
1131 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1132 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1133 if (status != IXGBE_SUCCESS)
1135 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1136 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1137 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1138 status = ixgbe_write_iosf_sb_reg_x550(hw,
1139 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->phy.lan_id),
1140 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1141 if (status != IXGBE_SUCCESS)
1143 status = ixgbe_read_iosf_sb_reg_x550(hw,
1144 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1145 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1146 if (status != IXGBE_SUCCESS)
1148 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1149 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1150 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1151 status = ixgbe_write_iosf_sb_reg_x550(hw,
1152 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->phy.lan_id),
1153 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1154 if (status != IXGBE_SUCCESS)
1157 /* Enable override for coefficients. */
1158 status = ixgbe_read_iosf_sb_reg_x550(hw,
1159 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1160 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1161 if (status != IXGBE_SUCCESS)
1163 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1164 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1165 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1166 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1167 status = ixgbe_write_iosf_sb_reg_x550(hw,
1168 IXGBE_KRM_TX_COEFF_CTRL_1(hw->phy.lan_id),
1169 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1170 if (status != IXGBE_SUCCESS)
1173 /* Toggle port SW reset by AN reset. */
1174 status = ixgbe_read_iosf_sb_reg_x550(hw,
1175 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1176 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1177 if (status != IXGBE_SUCCESS)
1179 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1180 status = ixgbe_write_iosf_sb_reg_x550(hw,
1181 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1182 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1188 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
1189 * @hw: pointer to hardware structure
1191 * Configures the integrated KR PHY to use internal loopback mode.
1193 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
1198 /* Disable AN and force speed to 10G Serial. */
1199 status = ixgbe_read_iosf_sb_reg_x550(hw,
1200 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1201 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1202 if (status != IXGBE_SUCCESS)
1204 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1205 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1206 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1207 status = ixgbe_write_iosf_sb_reg_x550(hw,
1208 IXGBE_KRM_LINK_CTRL_1(hw->phy.lan_id),
1209 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1210 if (status != IXGBE_SUCCESS)
1213 /* Set near-end loopback clocks. */
1214 status = ixgbe_read_iosf_sb_reg_x550(hw,
1215 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1216 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1217 if (status != IXGBE_SUCCESS)
1219 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
1220 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
1221 status = ixgbe_write_iosf_sb_reg_x550(hw,
1222 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->phy.lan_id),
1223 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1224 if (status != IXGBE_SUCCESS)
1227 /* Set loopback enable. */
1228 status = ixgbe_read_iosf_sb_reg_x550(hw,
1229 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1230 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1231 if (status != IXGBE_SUCCESS)
1233 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
1234 status = ixgbe_write_iosf_sb_reg_x550(hw,
1235 IXGBE_KRM_PMD_DFX_BURNIN(hw->phy.lan_id),
1236 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1237 if (status != IXGBE_SUCCESS)
1240 /* Training bypass. */
1241 status = ixgbe_read_iosf_sb_reg_x550(hw,
1242 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1243 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1244 if (status != IXGBE_SUCCESS)
1246 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
1247 status = ixgbe_write_iosf_sb_reg_x550(hw,
1248 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->phy.lan_id),
1249 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1255 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1256 * assuming that the semaphore is already obtained.
1257 * @hw: pointer to hardware structure
1258 * @offset: offset of word in the EEPROM to read
1259 * @data: word read from the EEPROM
1261 * Reads a 16 bit word from the EEPROM using the hostif.
1263 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1267 struct ixgbe_hic_read_shadow_ram buffer;
1269 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
1270 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1271 buffer.hdr.buf_len1 = 0;
1272 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1273 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1275 /* convert offset from words to bytes */
1276 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1278 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1280 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1281 sizeof(buffer), false);
1286 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1287 FW_NVM_DATA_OFFSET);
1293 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1294 * @hw: pointer to hardware structure
1295 * @offset: offset of word in the EEPROM to read
1296 * @data: word read from the EEPROM
1298 * Reads a 16 bit word from the EEPROM using the hostif.
1300 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1303 s32 status = IXGBE_SUCCESS;
1305 DEBUGFUNC("ixgbe_read_ee_hostif_X550");
1307 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1309 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
1310 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1312 status = IXGBE_ERR_SWFW_SYNC;
1319 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
1320 * @hw: pointer to hardware structure
1321 * @offset: offset of word in the EEPROM to read
1322 * @words: number of words
1323 * @data: word(s) read from the EEPROM
1325 * Reads a 16 bit word(s) from the EEPROM using the hostif.
1327 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1328 u16 offset, u16 words, u16 *data)
1330 struct ixgbe_hic_read_shadow_ram buffer;
1331 u32 current_word = 0;
1336 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
1338 /* Take semaphore for the entire operation. */
1339 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1341 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
1345 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
1346 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
1348 words_to_read = words;
1350 buffer.hdr.cmd = FW_READ_SHADOW_RAM_CMD;
1351 buffer.hdr.buf_len1 = 0;
1352 buffer.hdr.buf_len2 = FW_READ_SHADOW_RAM_LEN;
1353 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1355 /* convert offset from words to bytes */
1356 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
1357 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
1359 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1360 sizeof(buffer), false);
1363 DEBUGOUT("Host interface command failed\n");
1367 for (i = 0; i < words_to_read; i++) {
1368 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
1370 u32 value = IXGBE_READ_REG(hw, reg);
1372 data[current_word] = (u16)(value & 0xffff);
1375 if (i < words_to_read) {
1377 data[current_word] = (u16)(value & 0xffff);
1381 words -= words_to_read;
1385 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1390 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1391 * @hw: pointer to hardware structure
1392 * @offset: offset of word in the EEPROM to write
1393 * @data: word write to the EEPROM
1395 * Write a 16 bit word to the EEPROM using the hostif.
1397 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1401 struct ixgbe_hic_write_shadow_ram buffer;
1403 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
1405 buffer.hdr.cmd = FW_WRITE_SHADOW_RAM_CMD;
1406 buffer.hdr.buf_len1 = 0;
1407 buffer.hdr.buf_len2 = FW_WRITE_SHADOW_RAM_LEN;
1408 buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
1411 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
1413 buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
1415 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1416 sizeof(buffer), false);
1422 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1423 * @hw: pointer to hardware structure
1424 * @offset: offset of word in the EEPROM to write
1425 * @data: word write to the EEPROM
1427 * Write a 16 bit word to the EEPROM using the hostif.
1429 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
1432 s32 status = IXGBE_SUCCESS;
1434 DEBUGFUNC("ixgbe_write_ee_hostif_X550");
1436 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
1438 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1439 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1441 DEBUGOUT("write ee hostif failed to get semaphore");
1442 status = IXGBE_ERR_SWFW_SYNC;
1449 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1450 * @hw: pointer to hardware structure
1451 * @offset: offset of word in the EEPROM to write
1452 * @words: number of words
1453 * @data: word(s) write to the EEPROM
1455 * Write a 16 bit word(s) to the EEPROM using the hostif.
1457 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1458 u16 offset, u16 words, u16 *data)
1460 s32 status = IXGBE_SUCCESS;
1463 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
1465 /* Take semaphore for the entire operation. */
1466 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1467 if (status != IXGBE_SUCCESS) {
1468 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
1472 for (i = 0; i < words; i++) {
1473 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1476 if (status != IXGBE_SUCCESS) {
1477 DEBUGOUT("Eeprom buffered write failed\n");
1482 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1489 * ixgbe_checksum_ptr_x550 - Checksum one pointer region
1490 * @hw: pointer to hardware structure
1491 * @ptr: pointer offset in eeprom
1492 * @size: size of section pointed by ptr, if 0 first word will be used as size
1493 * @csum: address of checksum to update
1495 * Returns error status for any failure
1497 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
1498 u16 size, u16 *csum)
1502 u16 length, bufsz, i, start;
1504 bufsz = sizeof(buf) / sizeof(buf[0]);
1506 /* Read a chunk at the pointer location */
1507 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
1509 DEBUGOUT("Failed to read EEPROM image\n");
1520 /* Skip pointer section if length is invalid. */
1521 if (length == 0xFFFF || length == 0 ||
1522 (ptr + length) >= hw->eeprom.word_size)
1523 return IXGBE_SUCCESS;
1526 for (i = start; length; i++, length--) {
1533 /* Read a chunk at the pointer location */
1534 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
1537 DEBUGOUT("Failed to read EEPROM image\n");
1543 return IXGBE_SUCCESS;
1547 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1548 * @hw: pointer to hardware structure
1550 * Returns a negative error code on error, or the 16-bit checksum
1552 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1554 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
1557 u16 pointer, i, size;
1559 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
1561 hw->eeprom.ops.init_params(hw);
1563 /* Read pointer area */
1564 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1565 IXGBE_EEPROM_LAST_WORD + 1,
1568 DEBUGOUT("Failed to read EEPROM image\n");
1573 * For X550 hardware include 0x0-0x41 in the checksum, skip the
1574 * checksum word itself
1576 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1577 if (i != IXGBE_EEPROM_CHECKSUM)
1578 checksum += eeprom_ptrs[i];
1581 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
1582 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1584 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1585 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1588 pointer = eeprom_ptrs[i];
1590 /* Skip pointer section if the pointer is invalid. */
1591 if (pointer == 0xFFFF || pointer == 0 ||
1592 pointer >= hw->eeprom.word_size)
1596 case IXGBE_PCIE_GENERAL_PTR:
1597 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1599 case IXGBE_PCIE_CONFIG0_PTR:
1600 case IXGBE_PCIE_CONFIG1_PTR:
1601 size = IXGBE_PCIE_CONFIG_SIZE;
1608 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum);
1613 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1615 return (s32)checksum;
1619 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1620 * @hw: pointer to hardware structure
1621 * @checksum_val: calculated checksum
1623 * Performs checksum calculation and validates the EEPROM checksum. If the
1624 * caller does not need checksum_val, the value can be NULL.
1626 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
1630 u16 read_checksum = 0;
1632 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
1634 /* Read the first word from the EEPROM. If this times out or fails, do
1635 * not continue or we could be in for a very long wait while every
1638 status = hw->eeprom.ops.read(hw, 0, &checksum);
1640 DEBUGOUT("EEPROM read failed\n");
1644 status = hw->eeprom.ops.calc_checksum(hw);
1648 checksum = (u16)(status & 0xffff);
1650 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1655 /* Verify read checksum from EEPROM is the same as
1656 * calculated checksum
1658 if (read_checksum != checksum) {
1659 status = IXGBE_ERR_EEPROM_CHECKSUM;
1660 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
1661 "Invalid EEPROM checksum");
1664 /* If the user cares, return the calculated checksum */
1666 *checksum_val = checksum;
1672 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1673 * @hw: pointer to hardware structure
1675 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1676 * checksum and updates the EEPROM and instructs the hardware to update
1679 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1684 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
1686 /* Read the first word from the EEPROM. If this times out or fails, do
1687 * not continue or we could be in for a very long wait while every
1690 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1692 DEBUGOUT("EEPROM read failed\n");
1696 status = ixgbe_calc_eeprom_checksum_X550(hw);
1700 checksum = (u16)(status & 0xffff);
1702 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1707 status = ixgbe_update_flash_X550(hw);
1713 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1714 * @hw: pointer to hardware structure
1716 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1718 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1720 s32 status = IXGBE_SUCCESS;
1721 struct ixgbe_hic_hdr2 buffer;
1723 DEBUGFUNC("ixgbe_update_flash_X550");
1725 buffer.cmd = FW_SHADOW_RAM_DUMP_CMD;
1726 buffer.buf_len1 = 0;
1727 buffer.buf_len2 = FW_SHADOW_RAM_DUMP_LEN;
1728 buffer.checksum = FW_DEFAULT_CHECKSUM;
1730 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
1731 sizeof(buffer), false);
1737 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
1738 * @hw: pointer to hardware structure
1740 * Determines physical layer capabilities of the current configuration.
1742 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
1744 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1746 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
1748 hw->phy.ops.identify(hw);
1750 switch (hw->phy.type) {
1751 case ixgbe_phy_x550em_kr:
1752 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
1753 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1755 case ixgbe_phy_x550em_kx4:
1756 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1757 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1763 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
1764 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1766 return physical_layer;
1770 * ixgbe_disable_rx_x550 - Disable RX unit
1772 * Enables the Rx DMA unit for x550
1774 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1776 u32 rxctrl, pfdtxgswc;
1778 struct ixgbe_hic_disable_rxen fw_cmd;
1780 DEBUGFUNC("ixgbe_enable_rx_dma_x550");
1782 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1783 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1784 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1785 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1786 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1787 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1788 hw->mac.set_lben = true;
1790 hw->mac.set_lben = false;
1793 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1794 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1795 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1796 fw_cmd.port_number = hw->phy.lan_id;
1798 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
1799 sizeof(struct ixgbe_hic_disable_rxen),
1802 /* If we fail - disable RX using register write */
1804 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1805 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1806 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1807 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);