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34 #ifndef _IXGBE_BYPASS_API_H_
35 #define _IXGBE_BYPASS_API_H_
39 #include "ixgbe_bypass_defines.h"
41 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW
43 * @hw: pointer to hardware structure
44 * @cmd: Command we send to the FW
45 * @status: The reply from the FW
47 * Bit-bangs the cmd to the by_pass FW status points to what is returned.
49 #define IXGBE_BYPASS_BB_WAIT 1
50 static s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)
53 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo;
57 return IXGBE_ERR_PARAM;
61 /* SDP vary by MAC type */
62 switch (hw->mac.type) {
63 case ixgbe_mac_82599EB:
64 sck = IXGBE_ESDP_SDP7;
65 sdi = IXGBE_ESDP_SDP0;
66 sdo = IXGBE_ESDP_SDP6;
67 dir_sck = IXGBE_ESDP_SDP7_DIR;
68 dir_sdi = IXGBE_ESDP_SDP0_DIR;
69 dir_sdo = IXGBE_ESDP_SDP6_DIR;
72 sck = IXGBE_ESDP_SDP2;
73 sdi = IXGBE_ESDP_SDP0;
74 sdo = IXGBE_ESDP_SDP1;
75 dir_sck = IXGBE_ESDP_SDP2_DIR;
76 dir_sdi = IXGBE_ESDP_SDP0_DIR;
77 dir_sdo = IXGBE_ESDP_SDP1_DIR;
80 return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
83 /* Set SDP pins direction */
84 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
85 esdp |= dir_sck; /* SCK as output */
86 esdp |= dir_sdi; /* SDI as output */
87 esdp &= ~dir_sdo; /* SDO as input */
90 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
91 IXGBE_WRITE_FLUSH(hw);
93 msleep(IXGBE_BYPASS_BB_WAIT);
95 /* Generate start condition */
97 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
98 IXGBE_WRITE_FLUSH(hw);
99 msleep(IXGBE_BYPASS_BB_WAIT);
102 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
103 IXGBE_WRITE_FLUSH(hw);
104 msleep(IXGBE_BYPASS_BB_WAIT);
106 /* Clock out the new control word and clock in the status */
107 for (i = 0; i < 32; i++) {
108 if ((cmd >> (31 - i)) & 0x01) {
110 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
113 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
115 IXGBE_WRITE_FLUSH(hw);
116 msleep(IXGBE_BYPASS_BB_WAIT);
119 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
120 IXGBE_WRITE_FLUSH(hw);
121 msleep(IXGBE_BYPASS_BB_WAIT);
124 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
125 IXGBE_WRITE_FLUSH(hw);
126 msleep(IXGBE_BYPASS_BB_WAIT);
128 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
130 *status = (*status << 1) | 0x01;
132 *status = (*status << 1) | 0x00;
133 msleep(IXGBE_BYPASS_BB_WAIT);
139 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
140 IXGBE_WRITE_FLUSH(hw);
141 msleep(IXGBE_BYPASS_BB_WAIT);
144 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
145 IXGBE_WRITE_FLUSH(hw);
147 /* set the page bits to match the cmd that the status it belongs to */
148 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000);
154 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang.
156 * If we send a write we can't be sure it took until we can read back
157 * that same register. It can be a problem as some of the feilds may
158 * for valid reasons change between the time wrote the register and
159 * we read it again to verify. So this function check everything we
160 * can check and then assumes it worked.
162 * @u32 in_reg - The register cmd for the bit-bang read.
163 * @u32 out_reg - The register returned from a bit-bang read.
165 static bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg)
169 /* Page must match for all control pages */
170 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M))
173 switch (in_reg & BYPASS_PAGE_M) {
174 case BYPASS_PAGE_CTL0:
175 /* All the following can't change since the last write
176 * - All the event actions
177 * - The timeout value
179 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M |
180 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M |
183 if ((out_reg & mask) != (in_reg & mask))
186 /* 0x0 is never a valid value for bypass status */
187 if (!(out_reg & BYPASS_STATUS_OFF_M))
190 case BYPASS_PAGE_CTL1:
191 /* All the following can't change since the last write
193 * - time we last sent
195 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M;
196 if ((out_reg & mask) != (in_reg & mask))
199 case BYPASS_PAGE_CTL2:
200 /* All we can check in this page is control number
201 * which is already done above.
206 /* We are as sure as we can be return true */
211 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter.
213 * @hw: pointer to hardware structure
214 * @cmd: The control word we are setting.
215 * @event: The event we are setting in the FW. This also happens to
216 * be the mask for the event we are setting (handy)
217 * @action: The action we set the event to in the FW. This is in a
218 * bit field that happens to be what we want to put in
219 * the event spot (also handy)
221 static s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
228 /* Get current values */
229 cmd = ctrl; /* just reading only need control number */
230 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
231 return IXGBE_ERR_INVALID_ARGUMENT;
233 /* Set to new action */
234 cmd = (by_ctl & ~event) | BYPASS_WE | action;
235 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
236 return IXGBE_ERR_INVALID_ARGUMENT;
238 /* Page 0 force a FW eeprom write which is slow so verify */
239 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) {
240 verify = BYPASS_PAGE_CTL0;
243 return IXGBE_BYPASS_FW_WRITE_FAILURE;
245 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl))
246 return IXGBE_ERR_INVALID_ARGUMENT;
247 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl));
249 /* We have give the FW time for the write to stick */
257 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom address.
259 * @hw: pointer to hardware structure
260 * @addr: The bypass eeprom address to read.
261 * @value: The 8b of data at the address above.
263 static s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)
269 /* send the request */
270 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE;
271 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M;
272 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
273 return IXGBE_ERR_INVALID_ARGUMENT;
275 /* We have give the FW time for the write to stick */
278 /* now read the results */
280 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
281 return IXGBE_ERR_INVALID_ARGUMENT;
283 *value = status & BYPASS_CTL2_DATA_M;
288 #endif /* RTE_NIC_BYPASS */
290 #endif /* _IXGBE_BYPASS_API_H_ */