4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
65 #include "ixgbe_logs.h"
66 #include "ixgbe/ixgbe_api.h"
67 #include "ixgbe/ixgbe_vf.h"
68 #include "ixgbe/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
74 * High threshold controlling when to start sending XOFF frames. Must be at
75 * least 8 bytes less than receive packet buffer size. This value is in units
78 #define IXGBE_FC_HI 0x80
81 * Low threshold controlling when to start sending XON frames. This value is
82 * in units of 1024 bytes.
84 #define IXGBE_FC_LO 0x40
86 /* Timer value included in XOFF frames. */
87 #define IXGBE_FC_PAUSE 0x680
89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
90 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
91 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
93 #define IXGBE_MMW_SIZE_DEFAULT 0x4
94 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
97 * Default values for RX/TX configuration
99 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
100 #define IXGBE_DEFAULT_RX_PTHRESH 8
101 #define IXGBE_DEFAULT_RX_HTHRESH 8
102 #define IXGBE_DEFAULT_RX_WTHRESH 0
104 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
105 #define IXGBE_DEFAULT_TX_PTHRESH 32
106 #define IXGBE_DEFAULT_TX_HTHRESH 0
107 #define IXGBE_DEFAULT_TX_WTHRESH 0
108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
110 /* Bit shift and mask */
111 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
112 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
113 #define IXGBE_8_BIT_WIDTH CHAR_BIT
114 #define IXGBE_8_BIT_MASK UINT8_MAX
116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
121 struct rte_eth_dev *eth_dev);
122 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
123 static int ixgbe_dev_start(struct rte_eth_dev *dev);
124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
125 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
126 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
133 int wait_to_complete);
134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
135 struct rte_eth_stats *stats);
136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
142 struct rte_eth_dev_info *dev_info);
143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
144 struct rte_eth_dev_info *dev_info);
145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
148 uint16_t vlan_id, int on);
149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
151 uint16_t queue, bool on);
152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
163 struct rte_eth_fc_conf *fc_conf);
164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
165 struct rte_eth_fc_conf *fc_conf);
166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
167 struct rte_eth_pfc_conf *pfc_conf);
168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
169 struct rte_eth_rss_reta_entry64 *reta_conf,
171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
172 struct rte_eth_rss_reta_entry64 *reta_conf,
174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
182 uint32_t index, uint32_t pool);
183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
186 /* For Virtual Function support */
187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
188 struct rte_eth_dev *eth_dev);
189 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
190 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
195 struct rte_eth_stats *stats);
196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
198 uint16_t vlan_id, int on);
199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
200 uint16_t queue, int on);
201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
204 /* For Eth VMDQ APIs support */
205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
206 ether_addr* mac_addr,uint8_t on);
207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
208 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
209 uint16_t rx_mask, uint8_t on);
210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
213 uint64_t pool_mask,uint8_t vlan_on);
214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
215 struct rte_eth_vmdq_mirror_conf *mirror_conf,
216 uint8_t rule_id, uint8_t on);
217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
221 uint16_t queue_idx, uint16_t tx_rate);
222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
223 uint16_t tx_rate, uint64_t q_msk);
225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
226 struct ether_addr *mac_addr,
227 uint32_t index, uint32_t pool);
228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
229 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
230 struct rte_syn_filter *filter, uint16_t rx_queue);
231 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
232 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
233 struct rte_syn_filter *filter, uint16_t *rx_queue);
234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
235 struct rte_5tuple_filter *filter, uint16_t rx_queue);
236 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
238 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
239 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
241 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
242 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
243 struct rte_eth_ethertype_filter *filter,
245 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
246 enum rte_filter_op filter_op,
248 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
249 struct rte_eth_ethertype_filter *filter);
250 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
251 enum rte_filter_type filter_type,
252 enum rte_filter_op filter_op,
256 * Define VF Stats MACRO for Non "cleared on read" register
258 #define UPDATE_VF_STAT(reg, last, cur) \
260 u32 latest = IXGBE_READ_REG(hw, reg); \
261 cur += latest - last; \
265 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
267 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
268 u64 new_msb = IXGBE_READ_REG(hw, msb); \
269 u64 latest = ((new_msb << 32) | new_lsb); \
270 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
274 #define IXGBE_SET_HWSTRIP(h, q) do{\
275 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
276 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
277 (h)->bitmap[idx] |= 1 << bit;\
280 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
281 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
282 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
283 (h)->bitmap[idx] &= ~(1 << bit);\
286 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
287 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
288 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
289 (r) = (h)->bitmap[idx] >> bit & 1;\
293 * The set of PCI devices this driver supports
295 static struct rte_pci_id pci_id_ixgbe_map[] = {
297 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
298 #include "rte_pci_dev_ids.h"
300 { .vendor_id = 0, /* sentinel */ },
305 * The set of PCI devices this driver supports (for 82599 VF)
307 static struct rte_pci_id pci_id_ixgbevf_map[] = {
309 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
310 #include "rte_pci_dev_ids.h"
311 { .vendor_id = 0, /* sentinel */ },
315 static struct eth_dev_ops ixgbe_eth_dev_ops = {
316 .dev_configure = ixgbe_dev_configure,
317 .dev_start = ixgbe_dev_start,
318 .dev_stop = ixgbe_dev_stop,
319 .dev_set_link_up = ixgbe_dev_set_link_up,
320 .dev_set_link_down = ixgbe_dev_set_link_down,
321 .dev_close = ixgbe_dev_close,
322 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
323 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
324 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
325 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
326 .link_update = ixgbe_dev_link_update,
327 .stats_get = ixgbe_dev_stats_get,
328 .stats_reset = ixgbe_dev_stats_reset,
329 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
330 .dev_infos_get = ixgbe_dev_info_get,
331 .mtu_set = ixgbe_dev_mtu_set,
332 .vlan_filter_set = ixgbe_vlan_filter_set,
333 .vlan_tpid_set = ixgbe_vlan_tpid_set,
334 .vlan_offload_set = ixgbe_vlan_offload_set,
335 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
336 .rx_queue_start = ixgbe_dev_rx_queue_start,
337 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
338 .tx_queue_start = ixgbe_dev_tx_queue_start,
339 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
340 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
341 .rx_queue_release = ixgbe_dev_rx_queue_release,
342 .rx_queue_count = ixgbe_dev_rx_queue_count,
343 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
344 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
345 .tx_queue_release = ixgbe_dev_tx_queue_release,
346 .dev_led_on = ixgbe_dev_led_on,
347 .dev_led_off = ixgbe_dev_led_off,
348 .flow_ctrl_get = ixgbe_flow_ctrl_get,
349 .flow_ctrl_set = ixgbe_flow_ctrl_set,
350 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
351 .mac_addr_add = ixgbe_add_rar,
352 .mac_addr_remove = ixgbe_remove_rar,
353 .uc_hash_table_set = ixgbe_uc_hash_table_set,
354 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
355 .mirror_rule_set = ixgbe_mirror_rule_set,
356 .mirror_rule_reset = ixgbe_mirror_rule_reset,
357 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
358 .set_vf_rx = ixgbe_set_pool_rx,
359 .set_vf_tx = ixgbe_set_pool_tx,
360 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
361 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
362 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
363 .reta_update = ixgbe_dev_rss_reta_update,
364 .reta_query = ixgbe_dev_rss_reta_query,
365 #ifdef RTE_NIC_BYPASS
366 .bypass_init = ixgbe_bypass_init,
367 .bypass_state_set = ixgbe_bypass_state_store,
368 .bypass_state_show = ixgbe_bypass_state_show,
369 .bypass_event_set = ixgbe_bypass_event_store,
370 .bypass_event_show = ixgbe_bypass_event_show,
371 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
372 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
373 .bypass_ver_show = ixgbe_bypass_ver_show,
374 .bypass_wd_reset = ixgbe_bypass_wd_reset,
375 #endif /* RTE_NIC_BYPASS */
376 .rss_hash_update = ixgbe_dev_rss_hash_update,
377 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
378 .add_syn_filter = ixgbe_add_syn_filter,
379 .remove_syn_filter = ixgbe_remove_syn_filter,
380 .get_syn_filter = ixgbe_get_syn_filter,
381 .add_5tuple_filter = ixgbe_add_5tuple_filter,
382 .remove_5tuple_filter = ixgbe_remove_5tuple_filter,
383 .get_5tuple_filter = ixgbe_get_5tuple_filter,
384 .filter_ctrl = ixgbe_dev_filter_ctrl,
388 * dev_ops for virtual function, bare necessities for basic vf
389 * operation have been implemented
391 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
393 .dev_configure = ixgbevf_dev_configure,
394 .dev_start = ixgbevf_dev_start,
395 .dev_stop = ixgbevf_dev_stop,
396 .link_update = ixgbe_dev_link_update,
397 .stats_get = ixgbevf_dev_stats_get,
398 .stats_reset = ixgbevf_dev_stats_reset,
399 .dev_close = ixgbevf_dev_close,
400 .dev_infos_get = ixgbevf_dev_info_get,
401 .mtu_set = ixgbevf_dev_set_mtu,
402 .vlan_filter_set = ixgbevf_vlan_filter_set,
403 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
404 .vlan_offload_set = ixgbevf_vlan_offload_set,
405 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
406 .rx_queue_release = ixgbe_dev_rx_queue_release,
407 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
408 .tx_queue_release = ixgbe_dev_tx_queue_release,
409 .mac_addr_add = ixgbevf_add_mac_addr,
410 .mac_addr_remove = ixgbevf_remove_mac_addr,
414 * Atomically reads the link status information from global
415 * structure rte_eth_dev.
418 * - Pointer to the structure rte_eth_dev to read from.
419 * - Pointer to the buffer to be saved with the link status.
422 * - On success, zero.
423 * - On failure, negative value.
426 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
427 struct rte_eth_link *link)
429 struct rte_eth_link *dst = link;
430 struct rte_eth_link *src = &(dev->data->dev_link);
432 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
433 *(uint64_t *)src) == 0)
440 * Atomically writes the link status information into global
441 * structure rte_eth_dev.
444 * - Pointer to the structure rte_eth_dev to read from.
445 * - Pointer to the buffer to be saved with the link status.
448 * - On success, zero.
449 * - On failure, negative value.
452 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
453 struct rte_eth_link *link)
455 struct rte_eth_link *dst = &(dev->data->dev_link);
456 struct rte_eth_link *src = link;
458 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
459 *(uint64_t *)src) == 0)
466 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
469 ixgbe_is_sfp(struct ixgbe_hw *hw)
471 switch (hw->phy.type) {
472 case ixgbe_phy_sfp_avago:
473 case ixgbe_phy_sfp_ftl:
474 case ixgbe_phy_sfp_intel:
475 case ixgbe_phy_sfp_unknown:
476 case ixgbe_phy_sfp_passive_tyco:
477 case ixgbe_phy_sfp_passive_unknown:
484 static inline int32_t
485 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
490 status = ixgbe_reset_hw(hw);
492 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
493 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
494 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
495 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
496 IXGBE_WRITE_FLUSH(hw);
502 ixgbe_enable_intr(struct rte_eth_dev *dev)
504 struct ixgbe_interrupt *intr =
505 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
506 struct ixgbe_hw *hw =
507 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
509 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
510 IXGBE_WRITE_FLUSH(hw);
514 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
517 ixgbe_disable_intr(struct ixgbe_hw *hw)
519 PMD_INIT_FUNC_TRACE();
521 if (hw->mac.type == ixgbe_mac_82598EB) {
522 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
524 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
525 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
526 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
528 IXGBE_WRITE_FLUSH(hw);
532 * This function resets queue statistics mapping registers.
533 * From Niantic datasheet, Initialization of Statistics section:
534 * "...if software requires the queue counters, the RQSMR and TQSM registers
535 * must be re-programmed following a device reset.
538 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
542 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
543 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
544 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
550 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
555 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
556 #define NB_QMAP_FIELDS_PER_QSM_REG 4
557 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
559 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
560 struct ixgbe_stat_mapping_registers *stat_mappings =
561 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
562 uint32_t qsmr_mask = 0;
563 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
567 if ((hw->mac.type != ixgbe_mac_82599EB) &&
568 (hw->mac.type != ixgbe_mac_X540) &&
569 (hw->mac.type != ixgbe_mac_X550) &&
570 (hw->mac.type != ixgbe_mac_X550EM_x))
573 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
574 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
577 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
578 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
579 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
582 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
584 /* Now clear any previous stat_idx set */
585 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
587 stat_mappings->tqsm[n] &= ~clearing_mask;
589 stat_mappings->rqsmr[n] &= ~clearing_mask;
591 q_map = (uint32_t)stat_idx;
592 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
593 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
595 stat_mappings->tqsm[n] |= qsmr_mask;
597 stat_mappings->rqsmr[n] |= qsmr_mask;
599 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
600 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
602 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
603 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
605 /* Now write the mapping in the appropriate register */
607 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
608 stat_mappings->rqsmr[n], n);
609 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
612 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
613 stat_mappings->tqsm[n], n);
614 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
620 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
622 struct ixgbe_stat_mapping_registers *stat_mappings =
623 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
624 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
627 /* write whatever was in stat mapping table to the NIC */
628 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
630 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
633 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
638 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
641 struct ixgbe_dcb_tc_config *tc;
642 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
644 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
645 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
646 for (i = 0; i < dcb_max_tc; i++) {
647 tc = &dcb_config->tc_config[i];
648 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
649 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
650 (uint8_t)(100/dcb_max_tc + (i & 1));
651 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
652 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
653 (uint8_t)(100/dcb_max_tc + (i & 1));
654 tc->pfc = ixgbe_dcb_pfc_disabled;
657 /* Initialize default user to priority mapping, UPx->TC0 */
658 tc = &dcb_config->tc_config[0];
659 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
660 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
661 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
662 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
663 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
665 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
666 dcb_config->pfc_mode_enable = false;
667 dcb_config->vt_mode = true;
668 dcb_config->round_robin_enable = false;
669 /* support all DCB capabilities in 82599 */
670 dcb_config->support.capabilities = 0xFF;
672 /*we only support 4 Tcs for X540, X550 */
673 if (hw->mac.type == ixgbe_mac_X540 ||
674 hw->mac.type == ixgbe_mac_X550 ||
675 hw->mac.type == ixgbe_mac_X550EM_x) {
676 dcb_config->num_tcs.pg_tcs = 4;
677 dcb_config->num_tcs.pfc_tcs = 4;
682 * Ensure that all locks are released before first NVM or PHY access
685 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
690 * Phy lock should not fail in this early stage. If this is the case,
691 * it is due to an improper exit of the application.
692 * So force the release of the faulty lock. Release of common lock
693 * is done automatically by swfw_sync function.
695 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
696 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
697 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
699 ixgbe_release_swfw_semaphore(hw, mask);
702 * These ones are more tricky since they are common to all ports; but
703 * swfw_sync retries last long enough (1s) to be almost sure that if
704 * lock can not be taken it is due to an improper lock of the
707 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
708 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
709 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
711 ixgbe_release_swfw_semaphore(hw, mask);
715 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
716 * It returns 0 on success.
719 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
720 struct rte_eth_dev *eth_dev)
722 struct rte_pci_device *pci_dev;
723 struct ixgbe_hw *hw =
724 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
725 struct ixgbe_vfta * shadow_vfta =
726 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
727 struct ixgbe_hwstrip *hwstrip =
728 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
729 struct ixgbe_dcb_config *dcb_config =
730 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
735 PMD_INIT_FUNC_TRACE();
737 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
738 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
739 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
742 * For secondary processes, we don't initialise any further as primary
743 * has already done this work. Only check we don't need a different
744 * RX and TX function.
746 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
747 struct igb_tx_queue *txq;
748 /* TX queue function in primary, set by last queue initialized
749 * Tx queue may not initialized by primary process */
750 if (eth_dev->data->tx_queues) {
751 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
752 set_tx_function(eth_dev, txq);
754 /* Use default TX function if we get here */
755 PMD_INIT_LOG(INFO, "No TX queues configured yet. "
756 "Using default TX function.");
759 if (eth_dev->data->scattered_rx)
760 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
763 pci_dev = eth_dev->pci_dev;
765 /* Vendor and Device ID need to be set before init of shared code */
766 hw->device_id = pci_dev->id.device_id;
767 hw->vendor_id = pci_dev->id.vendor_id;
768 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
769 hw->allow_unsupported_sfp = 1;
771 /* Initialize the shared code (base driver) */
772 #ifdef RTE_NIC_BYPASS
773 diag = ixgbe_bypass_init_shared_code(hw);
775 diag = ixgbe_init_shared_code(hw);
776 #endif /* RTE_NIC_BYPASS */
778 if (diag != IXGBE_SUCCESS) {
779 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
783 /* pick up the PCI bus settings for reporting later */
784 ixgbe_get_bus_info(hw);
786 /* Unlock any pending hardware semaphore */
787 ixgbe_swfw_lock_reset(hw);
789 /* Initialize DCB configuration*/
790 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
791 ixgbe_dcb_init(hw,dcb_config);
792 /* Get Hardware Flow Control setting */
793 hw->fc.requested_mode = ixgbe_fc_full;
794 hw->fc.current_mode = ixgbe_fc_full;
795 hw->fc.pause_time = IXGBE_FC_PAUSE;
796 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
797 hw->fc.low_water[i] = IXGBE_FC_LO;
798 hw->fc.high_water[i] = IXGBE_FC_HI;
802 /* Make sure we have a good EEPROM before we read from it */
803 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
804 if (diag != IXGBE_SUCCESS) {
805 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
809 #ifdef RTE_NIC_BYPASS
810 diag = ixgbe_bypass_init_hw(hw);
812 diag = ixgbe_init_hw(hw);
813 #endif /* RTE_NIC_BYPASS */
816 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
817 * is called too soon after the kernel driver unbinding/binding occurs.
818 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
819 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
820 * also called. See ixgbe_identify_phy_82599(). The reason for the
821 * failure is not known, and only occuts when virtualisation features
822 * are disabled in the bios. A delay of 100ms was found to be enough by
823 * trial-and-error, and is doubled to be safe.
825 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
827 diag = ixgbe_init_hw(hw);
830 if (diag == IXGBE_ERR_EEPROM_VERSION) {
831 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
832 "LOM. Please be aware there may be issues associated "
833 "with your hardware.");
834 PMD_INIT_LOG(ERR, "If you are experiencing problems "
835 "please contact your Intel or hardware representative "
836 "who provided you with this hardware.");
837 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
838 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
840 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
844 /* disable interrupt */
845 ixgbe_disable_intr(hw);
847 /* reset mappings for queue statistics hw counters*/
848 ixgbe_reset_qstat_mappings(hw);
850 /* Allocate memory for storing MAC addresses */
851 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
852 hw->mac.num_rar_entries, 0);
853 if (eth_dev->data->mac_addrs == NULL) {
855 "Failed to allocate %u bytes needed to store "
857 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
860 /* Copy the permanent MAC address */
861 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
862 ð_dev->data->mac_addrs[0]);
864 /* Allocate memory for storing hash filter MAC addresses */
865 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
866 IXGBE_VMDQ_NUM_UC_MAC, 0);
867 if (eth_dev->data->hash_mac_addrs == NULL) {
869 "Failed to allocate %d bytes needed to store MAC addresses",
870 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
874 /* initialize the vfta */
875 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
877 /* initialize the hw strip bitmap*/
878 memset(hwstrip, 0, sizeof(*hwstrip));
880 /* initialize PF if max_vfs not zero */
881 ixgbe_pf_host_init(eth_dev);
883 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
884 /* let hardware know driver is loaded */
885 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
886 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
887 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
888 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
889 IXGBE_WRITE_FLUSH(hw);
891 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
892 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
893 (int) hw->mac.type, (int) hw->phy.type,
894 (int) hw->phy.sfp_type);
896 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
897 (int) hw->mac.type, (int) hw->phy.type);
899 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
900 eth_dev->data->port_id, pci_dev->id.vendor_id,
901 pci_dev->id.device_id);
903 rte_intr_callback_register(&(pci_dev->intr_handle),
904 ixgbe_dev_interrupt_handler, (void *)eth_dev);
906 /* enable uio intr after callback register */
907 rte_intr_enable(&(pci_dev->intr_handle));
909 /* enable support intr */
910 ixgbe_enable_intr(eth_dev);
917 * Negotiate mailbox API version with the PF.
918 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
919 * Then we try to negotiate starting with the most recent one.
920 * If all negotiation attempts fail, then we will proceed with
921 * the default one (ixgbe_mbox_api_10).
924 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
928 /* start with highest supported, proceed down */
929 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
935 i != RTE_DIM(sup_ver) &&
936 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
942 generate_random_mac_addr(struct ether_addr *mac_addr)
946 /* Set Organizationally Unique Identifier (OUI) prefix. */
947 mac_addr->addr_bytes[0] = 0x00;
948 mac_addr->addr_bytes[1] = 0x09;
949 mac_addr->addr_bytes[2] = 0xC0;
950 /* Force indication of locally assigned MAC address. */
951 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
952 /* Generate the last 3 bytes of the MAC address with a random number. */
954 memcpy(&mac_addr->addr_bytes[3], &random, 3);
958 * Virtual Function device init
961 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
962 struct rte_eth_dev *eth_dev)
966 struct rte_pci_device *pci_dev;
967 struct ixgbe_hw *hw =
968 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
969 struct ixgbe_vfta * shadow_vfta =
970 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
971 struct ixgbe_hwstrip *hwstrip =
972 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
973 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
975 PMD_INIT_FUNC_TRACE();
977 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
978 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
979 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
981 /* for secondary processes, we don't initialise any further as primary
982 * has already done this work. Only check we don't need a different
984 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
985 if (eth_dev->data->scattered_rx)
986 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
990 pci_dev = eth_dev->pci_dev;
992 hw->device_id = pci_dev->id.device_id;
993 hw->vendor_id = pci_dev->id.vendor_id;
994 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
996 /* initialize the vfta */
997 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
999 /* initialize the hw strip bitmap*/
1000 memset(hwstrip, 0, sizeof(*hwstrip));
1002 /* Initialize the shared code (base driver) */
1003 diag = ixgbe_init_shared_code(hw);
1004 if (diag != IXGBE_SUCCESS) {
1005 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1009 /* init_mailbox_params */
1010 hw->mbx.ops.init_params(hw);
1012 /* Disable the interrupts for VF */
1013 ixgbevf_intr_disable(hw);
1015 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1016 diag = hw->mac.ops.reset_hw(hw);
1019 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1020 * the underlying PF driver has not assigned a MAC address to the VF.
1021 * In this case, assign a random MAC address.
1023 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1024 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1028 /* negotiate mailbox API version to use with the PF. */
1029 ixgbevf_negotiate_api(hw);
1031 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1032 ixgbevf_get_queues(hw, &tcs, &tc);
1034 /* Allocate memory for storing MAC addresses */
1035 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1036 hw->mac.num_rar_entries, 0);
1037 if (eth_dev->data->mac_addrs == NULL) {
1039 "Failed to allocate %u bytes needed to store "
1041 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1045 /* Generate a random MAC address, if none was assigned by PF. */
1046 if (is_zero_ether_addr(perm_addr)) {
1047 generate_random_mac_addr(perm_addr);
1048 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1050 rte_free(eth_dev->data->mac_addrs);
1051 eth_dev->data->mac_addrs = NULL;
1054 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1055 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1056 "%02x:%02x:%02x:%02x:%02x:%02x",
1057 perm_addr->addr_bytes[0],
1058 perm_addr->addr_bytes[1],
1059 perm_addr->addr_bytes[2],
1060 perm_addr->addr_bytes[3],
1061 perm_addr->addr_bytes[4],
1062 perm_addr->addr_bytes[5]);
1065 /* Copy the permanent MAC address */
1066 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1068 /* reset the hardware with the new settings */
1069 diag = hw->mac.ops.start_hw(hw);
1075 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1079 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1080 eth_dev->data->port_id, pci_dev->id.vendor_id,
1081 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1086 static struct eth_driver rte_ixgbe_pmd = {
1088 .name = "rte_ixgbe_pmd",
1089 .id_table = pci_id_ixgbe_map,
1090 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1092 .eth_dev_init = eth_ixgbe_dev_init,
1093 .dev_private_size = sizeof(struct ixgbe_adapter),
1097 * virtual function driver struct
1099 static struct eth_driver rte_ixgbevf_pmd = {
1101 .name = "rte_ixgbevf_pmd",
1102 .id_table = pci_id_ixgbevf_map,
1103 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1105 .eth_dev_init = eth_ixgbevf_dev_init,
1106 .dev_private_size = sizeof(struct ixgbe_adapter),
1110 * Driver initialization routine.
1111 * Invoked once at EAL init time.
1112 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1115 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1117 PMD_INIT_FUNC_TRACE();
1119 rte_eth_driver_register(&rte_ixgbe_pmd);
1124 * VF Driver initialization routine.
1125 * Invoked one at EAL init time.
1126 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1129 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1131 PMD_INIT_FUNC_TRACE();
1133 rte_eth_driver_register(&rte_ixgbevf_pmd);
1138 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1140 struct ixgbe_hw *hw =
1141 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1142 struct ixgbe_vfta * shadow_vfta =
1143 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1148 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1149 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1150 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1155 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1157 /* update local VFTA copy */
1158 shadow_vfta->vfta[vid_idx] = vfta;
1164 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1167 ixgbe_vlan_hw_strip_enable(dev, queue);
1169 ixgbe_vlan_hw_strip_disable(dev, queue);
1173 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1175 struct ixgbe_hw *hw =
1176 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178 /* Only the high 16-bits is valid */
1179 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1183 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1185 struct ixgbe_hw *hw =
1186 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189 PMD_INIT_FUNC_TRACE();
1191 /* Filter Table Disable */
1192 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1193 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1195 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1199 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1201 struct ixgbe_hw *hw =
1202 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203 struct ixgbe_vfta * shadow_vfta =
1204 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1208 PMD_INIT_FUNC_TRACE();
1210 /* Filter Table Enable */
1211 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1212 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1213 vlnctrl |= IXGBE_VLNCTRL_VFE;
1215 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1217 /* write whatever is in local vfta copy */
1218 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1219 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1223 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1225 struct ixgbe_hwstrip *hwstrip =
1226 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1228 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1232 IXGBE_SET_HWSTRIP(hwstrip, queue);
1234 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1238 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1240 struct ixgbe_hw *hw =
1241 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1244 PMD_INIT_FUNC_TRACE();
1246 if (hw->mac.type == ixgbe_mac_82598EB) {
1247 /* No queue level support */
1248 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1252 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1253 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1254 ctrl &= ~IXGBE_RXDCTL_VME;
1255 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1257 /* record those setting for HW strip per queue */
1258 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1262 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1264 struct ixgbe_hw *hw =
1265 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1268 PMD_INIT_FUNC_TRACE();
1270 if (hw->mac.type == ixgbe_mac_82598EB) {
1271 /* No queue level supported */
1272 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1276 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1277 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1278 ctrl |= IXGBE_RXDCTL_VME;
1279 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1281 /* record those setting for HW strip per queue */
1282 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1286 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1288 struct ixgbe_hw *hw =
1289 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293 PMD_INIT_FUNC_TRACE();
1295 if (hw->mac.type == ixgbe_mac_82598EB) {
1296 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1297 ctrl &= ~IXGBE_VLNCTRL_VME;
1298 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1301 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1302 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1303 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1304 ctrl &= ~IXGBE_RXDCTL_VME;
1305 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1307 /* record those setting for HW strip per queue */
1308 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1314 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1316 struct ixgbe_hw *hw =
1317 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1321 PMD_INIT_FUNC_TRACE();
1323 if (hw->mac.type == ixgbe_mac_82598EB) {
1324 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1325 ctrl |= IXGBE_VLNCTRL_VME;
1326 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1329 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1330 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1331 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1332 ctrl |= IXGBE_RXDCTL_VME;
1333 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1335 /* record those setting for HW strip per queue */
1336 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1342 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1344 struct ixgbe_hw *hw =
1345 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348 PMD_INIT_FUNC_TRACE();
1350 /* DMATXCTRL: Geric Double VLAN Disable */
1351 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1352 ctrl &= ~IXGBE_DMATXCTL_GDV;
1353 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1355 /* CTRL_EXT: Global Double VLAN Disable */
1356 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1357 ctrl &= ~IXGBE_EXTENDED_VLAN;
1358 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1363 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1365 struct ixgbe_hw *hw =
1366 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1369 PMD_INIT_FUNC_TRACE();
1371 /* DMATXCTRL: Geric Double VLAN Enable */
1372 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1373 ctrl |= IXGBE_DMATXCTL_GDV;
1374 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1376 /* CTRL_EXT: Global Double VLAN Enable */
1377 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1378 ctrl |= IXGBE_EXTENDED_VLAN;
1379 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1382 * VET EXT field in the EXVET register = 0x8100 by default
1383 * So no need to change. Same to VT field of DMATXCTL register
1388 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1390 if(mask & ETH_VLAN_STRIP_MASK){
1391 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1392 ixgbe_vlan_hw_strip_enable_all(dev);
1394 ixgbe_vlan_hw_strip_disable_all(dev);
1397 if(mask & ETH_VLAN_FILTER_MASK){
1398 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1399 ixgbe_vlan_hw_filter_enable(dev);
1401 ixgbe_vlan_hw_filter_disable(dev);
1404 if(mask & ETH_VLAN_EXTEND_MASK){
1405 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1406 ixgbe_vlan_hw_extend_enable(dev);
1408 ixgbe_vlan_hw_extend_disable(dev);
1413 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1415 struct ixgbe_hw *hw =
1416 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1418 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1419 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1420 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1424 ixgbe_dev_configure(struct rte_eth_dev *dev)
1426 struct ixgbe_interrupt *intr =
1427 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1429 PMD_INIT_FUNC_TRACE();
1431 /* set flag to update link status after init */
1432 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1438 * Configure device link speed and setup link.
1439 * It returns 0 on success.
1442 ixgbe_dev_start(struct rte_eth_dev *dev)
1444 struct ixgbe_hw *hw =
1445 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1446 struct ixgbe_vf_info *vfinfo =
1447 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1448 int err, link_up = 0, negotiate = 0;
1454 PMD_INIT_FUNC_TRACE();
1456 /* IXGBE devices don't support half duplex */
1457 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1458 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1459 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1460 dev->data->dev_conf.link_duplex,
1461 dev->data->port_id);
1466 hw->adapter_stopped = FALSE;
1467 ixgbe_stop_adapter(hw);
1469 /* reinitialize adapter
1470 * this calls reset and start */
1471 status = ixgbe_pf_reset_hw(hw);
1474 hw->mac.ops.start_hw(hw);
1475 hw->mac.get_link_status = true;
1477 /* configure PF module if SRIOV enabled */
1478 ixgbe_pf_host_configure(dev);
1480 /* initialize transmission unit */
1481 ixgbe_dev_tx_init(dev);
1483 /* This can fail when allocating mbufs for descriptor rings */
1484 err = ixgbe_dev_rx_init(dev);
1486 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1490 err = ixgbe_dev_rxtx_start(dev);
1492 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1496 /* Skip link setup if loopback mode is enabled for 82599. */
1497 if (hw->mac.type == ixgbe_mac_82599EB &&
1498 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1499 goto skip_link_setup;
1501 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1502 err = hw->mac.ops.setup_sfp(hw);
1507 /* Turn on the laser */
1508 ixgbe_enable_tx_laser(hw);
1510 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1513 dev->data->dev_link.link_status = link_up;
1515 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1519 switch(dev->data->dev_conf.link_speed) {
1520 case ETH_LINK_SPEED_AUTONEG:
1521 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1522 IXGBE_LINK_SPEED_82599_AUTONEG :
1523 IXGBE_LINK_SPEED_82598_AUTONEG;
1525 case ETH_LINK_SPEED_100:
1527 * Invalid for 82598 but error will be detected by
1528 * ixgbe_setup_link()
1530 speed = IXGBE_LINK_SPEED_100_FULL;
1532 case ETH_LINK_SPEED_1000:
1533 speed = IXGBE_LINK_SPEED_1GB_FULL;
1535 case ETH_LINK_SPEED_10000:
1536 speed = IXGBE_LINK_SPEED_10GB_FULL;
1539 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1540 dev->data->dev_conf.link_speed,
1541 dev->data->port_id);
1545 err = ixgbe_setup_link(hw, speed, link_up);
1551 /* check if lsc interrupt is enabled */
1552 if (dev->data->dev_conf.intr_conf.lsc != 0)
1553 ixgbe_dev_lsc_interrupt_setup(dev);
1555 /* resume enabled intr since hw reset */
1556 ixgbe_enable_intr(dev);
1558 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1559 ETH_VLAN_EXTEND_MASK;
1560 ixgbe_vlan_offload_set(dev, mask);
1562 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1563 /* Enable vlan filtering for VMDq */
1564 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1567 /* Configure DCB hw */
1568 ixgbe_configure_dcb(dev);
1570 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1571 err = ixgbe_fdir_configure(dev);
1576 /* Restore vf rate limit */
1577 if (vfinfo != NULL) {
1578 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1579 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1580 if (vfinfo[vf].tx_rate[idx] != 0)
1581 ixgbe_set_vf_rate_limit(dev, vf,
1582 vfinfo[vf].tx_rate[idx],
1586 ixgbe_restore_statistics_mapping(dev);
1591 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1592 ixgbe_dev_clear_queues(dev);
1597 * Stop device: disable rx and tx functions to allow for reconfiguring.
1600 ixgbe_dev_stop(struct rte_eth_dev *dev)
1602 struct rte_eth_link link;
1603 struct ixgbe_hw *hw =
1604 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1605 struct ixgbe_vf_info *vfinfo =
1606 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1609 PMD_INIT_FUNC_TRACE();
1611 /* disable interrupts */
1612 ixgbe_disable_intr(hw);
1615 ixgbe_pf_reset_hw(hw);
1616 hw->adapter_stopped = FALSE;
1619 ixgbe_stop_adapter(hw);
1621 for (vf = 0; vfinfo != NULL &&
1622 vf < dev->pci_dev->max_vfs; vf++)
1623 vfinfo[vf].clear_to_send = false;
1625 /* Turn off the laser */
1626 ixgbe_disable_tx_laser(hw);
1628 ixgbe_dev_clear_queues(dev);
1630 /* Clear stored conf */
1631 dev->data->scattered_rx = 0;
1633 /* Clear recorded link status */
1634 memset(&link, 0, sizeof(link));
1635 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1639 * Set device link up: enable tx laser.
1642 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1644 struct ixgbe_hw *hw =
1645 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646 if (hw->mac.type == ixgbe_mac_82599EB) {
1647 #ifdef RTE_NIC_BYPASS
1648 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1649 /* Not suported in bypass mode */
1650 PMD_INIT_LOG(ERR, "Set link up is not supported "
1651 "by device id 0x%x", hw->device_id);
1655 /* Turn on the laser */
1656 ixgbe_enable_tx_laser(hw);
1660 PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1666 * Set device link down: disable tx laser.
1669 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1671 struct ixgbe_hw *hw =
1672 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673 if (hw->mac.type == ixgbe_mac_82599EB) {
1674 #ifdef RTE_NIC_BYPASS
1675 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1676 /* Not suported in bypass mode */
1677 PMD_INIT_LOG(ERR, "Set link down is not supported "
1678 "by device id 0x%x", hw->device_id);
1682 /* Turn off the laser */
1683 ixgbe_disable_tx_laser(hw);
1687 PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1693 * Reest and stop device.
1696 ixgbe_dev_close(struct rte_eth_dev *dev)
1698 struct ixgbe_hw *hw =
1699 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701 PMD_INIT_FUNC_TRACE();
1703 ixgbe_pf_reset_hw(hw);
1705 ixgbe_dev_stop(dev);
1706 hw->adapter_stopped = 1;
1708 ixgbe_disable_pcie_master(hw);
1710 /* reprogram the RAR[0] in case user changed it. */
1711 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1715 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1718 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1720 struct ixgbe_hw *hw =
1721 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1722 struct ixgbe_hw_stats *hw_stats =
1723 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1724 uint32_t bprc, lxon, lxoff, total;
1725 uint64_t total_missed_rx, total_qbrc, total_qprc;
1728 total_missed_rx = 0;
1732 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1733 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1734 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1735 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1737 for (i = 0; i < 8; i++) {
1739 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1740 /* global total per queue */
1741 hw_stats->mpc[i] += mp;
1742 /* Running comprehensive total for stats display */
1743 total_missed_rx += hw_stats->mpc[i];
1744 if (hw->mac.type == ixgbe_mac_82598EB)
1745 hw_stats->rnbc[i] +=
1746 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1747 hw_stats->pxontxc[i] +=
1748 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1749 hw_stats->pxonrxc[i] +=
1750 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1751 hw_stats->pxofftxc[i] +=
1752 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1753 hw_stats->pxoffrxc[i] +=
1754 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1755 hw_stats->pxon2offc[i] +=
1756 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1758 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1759 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1760 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1761 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1762 hw_stats->qbrc[i] +=
1763 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1764 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1765 hw_stats->qbtc[i] +=
1766 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1767 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1769 total_qprc += hw_stats->qprc[i];
1770 total_qbrc += hw_stats->qbrc[i];
1772 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1773 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1774 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1776 /* Note that gprc counts missed packets */
1777 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1779 if (hw->mac.type != ixgbe_mac_82598EB) {
1780 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1781 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1782 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1783 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1784 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1785 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1786 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1787 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1789 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1790 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1791 /* 82598 only has a counter in the high register */
1792 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1793 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1794 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1798 * Workaround: mprc hardware is incorrectly counting
1799 * broadcasts, so for now we subtract those.
1801 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1802 hw_stats->bprc += bprc;
1803 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1804 if (hw->mac.type == ixgbe_mac_82598EB)
1805 hw_stats->mprc -= bprc;
1807 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1808 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1809 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1810 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1811 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1812 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1814 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1815 hw_stats->lxontxc += lxon;
1816 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1817 hw_stats->lxofftxc += lxoff;
1818 total = lxon + lxoff;
1820 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1821 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1822 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1823 hw_stats->gptc -= total;
1824 hw_stats->mptc -= total;
1825 hw_stats->ptc64 -= total;
1826 hw_stats->gotc -= total * ETHER_MIN_LEN;
1828 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1829 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1830 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1831 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1832 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1833 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1834 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1835 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1836 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1837 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1838 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1839 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1840 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1841 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1842 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1843 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1844 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1845 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1846 /* Only read FCOE on 82599 */
1847 if (hw->mac.type != ixgbe_mac_82598EB) {
1848 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1849 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1850 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1851 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1852 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1858 /* Fill out the rte_eth_stats statistics structure */
1859 stats->ipackets = total_qprc;
1860 stats->ibytes = total_qbrc;
1861 stats->opackets = hw_stats->gptc;
1862 stats->obytes = hw_stats->gotc;
1863 stats->imcasts = hw_stats->mprc;
1865 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1866 stats->q_ipackets[i] = hw_stats->qprc[i];
1867 stats->q_opackets[i] = hw_stats->qptc[i];
1868 stats->q_ibytes[i] = hw_stats->qbrc[i];
1869 stats->q_obytes[i] = hw_stats->qbtc[i];
1870 stats->q_errors[i] = hw_stats->qprdc[i];
1874 stats->ibadcrc = hw_stats->crcerrs;
1875 stats->ibadlen = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1876 stats->imissed = total_missed_rx;
1877 stats->ierrors = stats->ibadcrc +
1880 hw_stats->illerrc + hw_stats->errbc;
1885 /* XON/XOFF pause frames */
1886 stats->tx_pause_xon = hw_stats->lxontxc;
1887 stats->rx_pause_xon = hw_stats->lxonrxc;
1888 stats->tx_pause_xoff = hw_stats->lxofftxc;
1889 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1891 /* Flow Director Stats registers */
1892 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1893 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1894 stats->fdirmatch = hw_stats->fdirmatch;
1895 stats->fdirmiss = hw_stats->fdirmiss;
1899 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1901 struct ixgbe_hw_stats *stats =
1902 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1904 /* HW registers are cleared on read */
1905 ixgbe_dev_stats_get(dev, NULL);
1907 /* Reset software totals */
1908 memset(stats, 0, sizeof(*stats));
1912 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1914 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1915 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1916 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1918 /* Good Rx packet, include VF loopback */
1919 UPDATE_VF_STAT(IXGBE_VFGPRC,
1920 hw_stats->last_vfgprc, hw_stats->vfgprc);
1922 /* Good Rx octets, include VF loopback */
1923 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1924 hw_stats->last_vfgorc, hw_stats->vfgorc);
1926 /* Good Tx packet, include VF loopback */
1927 UPDATE_VF_STAT(IXGBE_VFGPTC,
1928 hw_stats->last_vfgptc, hw_stats->vfgptc);
1930 /* Good Tx octets, include VF loopback */
1931 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1932 hw_stats->last_vfgotc, hw_stats->vfgotc);
1934 /* Rx Multicst Packet */
1935 UPDATE_VF_STAT(IXGBE_VFMPRC,
1936 hw_stats->last_vfmprc, hw_stats->vfmprc);
1941 stats->ipackets = hw_stats->vfgprc;
1942 stats->ibytes = hw_stats->vfgorc;
1943 stats->opackets = hw_stats->vfgptc;
1944 stats->obytes = hw_stats->vfgotc;
1945 stats->imcasts = hw_stats->vfmprc;
1949 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1951 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1952 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1954 /* Sync HW register to the last stats */
1955 ixgbevf_dev_stats_get(dev, NULL);
1957 /* reset HW current stats*/
1958 hw_stats->vfgprc = 0;
1959 hw_stats->vfgorc = 0;
1960 hw_stats->vfgptc = 0;
1961 hw_stats->vfgotc = 0;
1962 hw_stats->vfmprc = 0;
1967 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1971 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1972 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1973 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1974 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1975 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1976 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1977 dev_info->max_vfs = dev->pci_dev->max_vfs;
1978 if (hw->mac.type == ixgbe_mac_82598EB)
1979 dev_info->max_vmdq_pools = ETH_16_POOLS;
1981 dev_info->max_vmdq_pools = ETH_64_POOLS;
1982 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1983 dev_info->rx_offload_capa =
1984 DEV_RX_OFFLOAD_VLAN_STRIP |
1985 DEV_RX_OFFLOAD_IPV4_CKSUM |
1986 DEV_RX_OFFLOAD_UDP_CKSUM |
1987 DEV_RX_OFFLOAD_TCP_CKSUM;
1988 dev_info->tx_offload_capa =
1989 DEV_TX_OFFLOAD_VLAN_INSERT |
1990 DEV_TX_OFFLOAD_IPV4_CKSUM |
1991 DEV_TX_OFFLOAD_UDP_CKSUM |
1992 DEV_TX_OFFLOAD_TCP_CKSUM |
1993 DEV_TX_OFFLOAD_SCTP_CKSUM |
1994 DEV_TX_OFFLOAD_TCP_TSO;
1996 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1998 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
1999 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2000 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2002 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2006 dev_info->default_txconf = (struct rte_eth_txconf) {
2008 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2009 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2010 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2012 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2013 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2014 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2015 ETH_TXQ_FLAGS_NOOFFLOADS,
2017 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2021 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2022 struct rte_eth_dev_info *dev_info)
2024 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2026 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2027 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2028 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2029 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2030 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2031 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2032 dev_info->max_vfs = dev->pci_dev->max_vfs;
2033 if (hw->mac.type == ixgbe_mac_82598EB)
2034 dev_info->max_vmdq_pools = ETH_16_POOLS;
2036 dev_info->max_vmdq_pools = ETH_64_POOLS;
2037 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2038 DEV_RX_OFFLOAD_IPV4_CKSUM |
2039 DEV_RX_OFFLOAD_UDP_CKSUM |
2040 DEV_RX_OFFLOAD_TCP_CKSUM;
2041 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2042 DEV_TX_OFFLOAD_IPV4_CKSUM |
2043 DEV_TX_OFFLOAD_UDP_CKSUM |
2044 DEV_TX_OFFLOAD_TCP_CKSUM |
2045 DEV_TX_OFFLOAD_SCTP_CKSUM;
2047 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2049 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2050 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2051 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2053 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2057 dev_info->default_txconf = (struct rte_eth_txconf) {
2059 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2060 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2061 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2063 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2064 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2065 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2066 ETH_TXQ_FLAGS_NOOFFLOADS,
2070 /* return 0 means link status changed, -1 means not changed */
2072 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2074 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075 struct rte_eth_link link, old;
2076 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2080 link.link_status = 0;
2081 link.link_speed = 0;
2082 link.link_duplex = 0;
2083 memset(&old, 0, sizeof(old));
2084 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2086 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2087 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2088 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2090 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2092 link.link_speed = ETH_LINK_SPEED_100;
2093 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2094 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2095 if (link.link_status == old.link_status)
2100 if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2101 !hw->mac.get_link_status) {
2102 memcpy(&link, &old, sizeof(link));
2107 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2108 if (link.link_status == old.link_status)
2112 link.link_status = 1;
2113 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2115 switch (link_speed) {
2117 case IXGBE_LINK_SPEED_UNKNOWN:
2118 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2119 link.link_speed = ETH_LINK_SPEED_100;
2122 case IXGBE_LINK_SPEED_100_FULL:
2123 link.link_speed = ETH_LINK_SPEED_100;
2126 case IXGBE_LINK_SPEED_1GB_FULL:
2127 link.link_speed = ETH_LINK_SPEED_1000;
2130 case IXGBE_LINK_SPEED_10GB_FULL:
2131 link.link_speed = ETH_LINK_SPEED_10000;
2134 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2136 if (link.link_status == old.link_status)
2143 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2145 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2149 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2150 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2154 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2156 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2160 fctrl &= (~IXGBE_FCTRL_UPE);
2161 if (dev->data->all_multicast == 1)
2162 fctrl |= IXGBE_FCTRL_MPE;
2164 fctrl &= (~IXGBE_FCTRL_MPE);
2165 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2169 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2171 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2175 fctrl |= IXGBE_FCTRL_MPE;
2176 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2180 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2182 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185 if (dev->data->promiscuous == 1)
2186 return; /* must remain in all_multicast mode */
2188 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2189 fctrl &= (~IXGBE_FCTRL_MPE);
2190 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2194 * It clears the interrupt causes and enables the interrupt.
2195 * It will be called once only during nic initialized.
2198 * Pointer to struct rte_eth_dev.
2201 * - On success, zero.
2202 * - On failure, a negative value.
2205 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2207 struct ixgbe_interrupt *intr =
2208 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2210 ixgbe_dev_link_status_print(dev);
2211 intr->mask |= IXGBE_EICR_LSC;
2217 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2220 * Pointer to struct rte_eth_dev.
2223 * - On success, zero.
2224 * - On failure, a negative value.
2227 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2230 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2231 struct ixgbe_interrupt *intr =
2232 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2234 /* clear all cause mask */
2235 ixgbe_disable_intr(hw);
2237 /* read-on-clear nic registers here */
2238 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2239 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2242 if (eicr & IXGBE_EICR_LSC) {
2243 /* set flag for async link update */
2244 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2247 if (eicr & IXGBE_EICR_MAILBOX)
2248 intr->flags |= IXGBE_FLAG_MAILBOX;
2254 * It gets and then prints the link status.
2257 * Pointer to struct rte_eth_dev.
2260 * - On success, zero.
2261 * - On failure, a negative value.
2264 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2266 struct rte_eth_link link;
2268 memset(&link, 0, sizeof(link));
2269 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2270 if (link.link_status) {
2271 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2272 (int)(dev->data->port_id),
2273 (unsigned)link.link_speed,
2274 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2275 "full-duplex" : "half-duplex");
2277 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2278 (int)(dev->data->port_id));
2280 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2281 dev->pci_dev->addr.domain,
2282 dev->pci_dev->addr.bus,
2283 dev->pci_dev->addr.devid,
2284 dev->pci_dev->addr.function);
2288 * It executes link_update after knowing an interrupt occurred.
2291 * Pointer to struct rte_eth_dev.
2294 * - On success, zero.
2295 * - On failure, a negative value.
2298 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2300 struct ixgbe_interrupt *intr =
2301 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2303 struct rte_eth_link link;
2304 int intr_enable_delay = false;
2306 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2308 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2309 ixgbe_pf_mbx_process(dev);
2310 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2313 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2314 /* get the link status before link update, for predicting later */
2315 memset(&link, 0, sizeof(link));
2316 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2318 ixgbe_dev_link_update(dev, 0);
2321 if (!link.link_status)
2322 /* handle it 1 sec later, wait it being stable */
2323 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2324 /* likely to down */
2326 /* handle it 4 sec later, wait it being stable */
2327 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2329 ixgbe_dev_link_status_print(dev);
2331 intr_enable_delay = true;
2334 if (intr_enable_delay) {
2335 if (rte_eal_alarm_set(timeout * 1000,
2336 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2337 PMD_DRV_LOG(ERR, "Error setting alarm");
2339 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2340 ixgbe_enable_intr(dev);
2341 rte_intr_enable(&(dev->pci_dev->intr_handle));
2349 * Interrupt handler which shall be registered for alarm callback for delayed
2350 * handling specific interrupt to wait for the stable nic state. As the
2351 * NIC interrupt state is not stable for ixgbe after link is just down,
2352 * it needs to wait 4 seconds to get the stable status.
2355 * Pointer to interrupt handle.
2357 * The address of parameter (struct rte_eth_dev *) regsitered before.
2363 ixgbe_dev_interrupt_delayed_handler(void *param)
2365 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2366 struct ixgbe_interrupt *intr =
2367 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2368 struct ixgbe_hw *hw =
2369 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2373 if (eicr & IXGBE_EICR_MAILBOX)
2374 ixgbe_pf_mbx_process(dev);
2376 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2377 ixgbe_dev_link_update(dev, 0);
2378 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2379 ixgbe_dev_link_status_print(dev);
2380 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2383 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2384 ixgbe_enable_intr(dev);
2385 rte_intr_enable(&(dev->pci_dev->intr_handle));
2389 * Interrupt handler triggered by NIC for handling
2390 * specific interrupt.
2393 * Pointer to interrupt handle.
2395 * The address of parameter (struct rte_eth_dev *) regsitered before.
2401 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2404 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2405 ixgbe_dev_interrupt_get_status(dev);
2406 ixgbe_dev_interrupt_action(dev);
2410 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2412 struct ixgbe_hw *hw;
2414 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2415 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2419 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2421 struct ixgbe_hw *hw;
2423 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2428 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2430 struct ixgbe_hw *hw;
2436 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2438 fc_conf->pause_time = hw->fc.pause_time;
2439 fc_conf->high_water = hw->fc.high_water[0];
2440 fc_conf->low_water = hw->fc.low_water[0];
2441 fc_conf->send_xon = hw->fc.send_xon;
2442 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2445 * Return rx_pause status according to actual setting of
2448 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2449 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2455 * Return tx_pause status according to actual setting of
2458 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2459 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2464 if (rx_pause && tx_pause)
2465 fc_conf->mode = RTE_FC_FULL;
2467 fc_conf->mode = RTE_FC_RX_PAUSE;
2469 fc_conf->mode = RTE_FC_TX_PAUSE;
2471 fc_conf->mode = RTE_FC_NONE;
2477 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2479 struct ixgbe_hw *hw;
2481 uint32_t rx_buf_size;
2482 uint32_t max_high_water;
2484 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2491 PMD_INIT_FUNC_TRACE();
2493 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494 if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2496 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2497 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2500 * At least reserve one Ethernet frame for watermark
2501 * high_water/low_water in kilo bytes for ixgbe
2503 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2504 if ((fc_conf->high_water > max_high_water) ||
2505 (fc_conf->high_water < fc_conf->low_water)) {
2506 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2507 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2511 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2512 hw->fc.pause_time = fc_conf->pause_time;
2513 hw->fc.high_water[0] = fc_conf->high_water;
2514 hw->fc.low_water[0] = fc_conf->low_water;
2515 hw->fc.send_xon = fc_conf->send_xon;
2517 err = ixgbe_fc_enable(hw);
2519 /* Not negotiated is not an error case */
2520 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2522 /* check if we want to forward MAC frames - driver doesn't have native
2523 * capability to do that, so we'll write the registers ourselves */
2525 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2527 /* set or clear MFLCN.PMCF bit depending on configuration */
2528 if (fc_conf->mac_ctrl_frame_fwd != 0)
2529 mflcn |= IXGBE_MFLCN_PMCF;
2531 mflcn &= ~IXGBE_MFLCN_PMCF;
2533 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2534 IXGBE_WRITE_FLUSH(hw);
2539 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2544 * ixgbe_pfc_enable_generic - Enable flow control
2545 * @hw: pointer to hardware structure
2546 * @tc_num: traffic class number
2547 * Enable flow control according to the current settings.
2550 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2553 uint32_t mflcn_reg, fccfg_reg;
2555 uint32_t fcrtl, fcrth;
2559 /* Validate the water mark configuration */
2560 if (!hw->fc.pause_time) {
2561 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2565 /* Low water mark of zero causes XOFF floods */
2566 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2567 /* High/Low water can not be 0 */
2568 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2569 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2570 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2574 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2575 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2576 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2580 /* Negotiate the fc mode to use */
2581 ixgbe_fc_autoneg(hw);
2583 /* Disable any previous flow control settings */
2584 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2585 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2587 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2588 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2590 switch (hw->fc.current_mode) {
2593 * If the count of enabled RX Priority Flow control >1,
2594 * and the TX pause can not be disabled
2597 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2598 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2599 if (reg & IXGBE_FCRTH_FCEN)
2603 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2605 case ixgbe_fc_rx_pause:
2607 * Rx Flow control is enabled and Tx Flow control is
2608 * disabled by software override. Since there really
2609 * isn't a way to advertise that we are capable of RX
2610 * Pause ONLY, we will advertise that we support both
2611 * symmetric and asymmetric Rx PAUSE. Later, we will
2612 * disable the adapter's ability to send PAUSE frames.
2614 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2616 * If the count of enabled RX Priority Flow control >1,
2617 * and the TX pause can not be disabled
2620 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2621 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2622 if (reg & IXGBE_FCRTH_FCEN)
2626 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2628 case ixgbe_fc_tx_pause:
2630 * Tx Flow control is enabled, and Rx Flow control is
2631 * disabled by software override.
2633 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2636 /* Flow control (both Rx and Tx) is enabled by SW override. */
2637 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2638 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2641 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2642 ret_val = IXGBE_ERR_CONFIG;
2647 /* Set 802.3x based flow control settings. */
2648 mflcn_reg |= IXGBE_MFLCN_DPF;
2649 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2650 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2652 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2653 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2654 hw->fc.high_water[tc_num]) {
2655 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2656 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2657 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2659 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2661 * In order to prevent Tx hangs when the internal Tx
2662 * switch is enabled we must set the high water mark
2663 * to the maximum FCRTH value. This allows the Tx
2664 * switch to function even under heavy Rx workloads.
2666 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2668 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2670 /* Configure pause time (2 TCs per register) */
2671 reg = hw->fc.pause_time * 0x00010001;
2672 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2673 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2675 /* Configure flow control refresh threshold value */
2676 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2683 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2685 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2686 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2688 if(hw->mac.type != ixgbe_mac_82598EB) {
2689 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2695 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2698 uint32_t rx_buf_size;
2699 uint32_t max_high_water;
2701 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2702 struct ixgbe_hw *hw =
2703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704 struct ixgbe_dcb_config *dcb_config =
2705 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2707 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2714 PMD_INIT_FUNC_TRACE();
2716 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2717 tc_num = map[pfc_conf->priority];
2718 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2719 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2721 * At least reserve one Ethernet frame for watermark
2722 * high_water/low_water in kilo bytes for ixgbe
2724 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2725 if ((pfc_conf->fc.high_water > max_high_water) ||
2726 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2727 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2728 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2732 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2733 hw->fc.pause_time = pfc_conf->fc.pause_time;
2734 hw->fc.send_xon = pfc_conf->fc.send_xon;
2735 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2736 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2738 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2740 /* Not negotiated is not an error case */
2741 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2744 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2749 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2750 struct rte_eth_rss_reta_entry64 *reta_conf,
2755 uint16_t idx, shift;
2756 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2758 PMD_INIT_FUNC_TRACE();
2759 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2760 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2761 "(%d) doesn't match the number hardware can supported "
2762 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2766 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2767 idx = i / RTE_RETA_GROUP_SIZE;
2768 shift = i % RTE_RETA_GROUP_SIZE;
2769 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2773 if (mask == IXGBE_4_BIT_MASK)
2776 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2777 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2778 if (mask & (0x1 << j))
2779 reta |= reta_conf[idx].reta[shift + j] <<
2782 reta |= r & (IXGBE_8_BIT_MASK <<
2785 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2792 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2793 struct rte_eth_rss_reta_entry64 *reta_conf,
2798 uint16_t idx, shift;
2799 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801 PMD_INIT_FUNC_TRACE();
2802 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2803 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2804 "(%d) doesn't match the number hardware can supported "
2805 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2809 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2810 idx = i / RTE_RETA_GROUP_SIZE;
2811 shift = i % RTE_RETA_GROUP_SIZE;
2812 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2817 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2818 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2819 if (mask & (0x1 << j))
2820 reta_conf[idx].reta[shift + j] =
2821 ((reta >> (CHAR_BIT * j)) &
2830 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2831 uint32_t index, uint32_t pool)
2833 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2834 uint32_t enable_addr = 1;
2836 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2840 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2842 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844 ixgbe_clear_rar(hw, index);
2848 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2852 struct ixgbe_hw *hw;
2853 struct rte_eth_dev_info dev_info;
2854 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2856 ixgbe_dev_info_get(dev, &dev_info);
2858 /* check that mtu is within the allowed range */
2859 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2862 /* refuse mtu that requires the support of scattered packets when this
2863 * feature has not been enabled before. */
2864 if (!dev->data->scattered_rx &&
2865 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2866 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2869 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2872 /* switch to jumbo mode if needed */
2873 if (frame_size > ETHER_MAX_LEN) {
2874 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2875 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2877 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2878 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2880 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2882 /* update max frame size */
2883 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2885 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2886 maxfrs &= 0x0000FFFF;
2887 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2888 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2894 * Virtual Function operations
2897 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2899 PMD_INIT_FUNC_TRACE();
2901 /* Clear interrupt mask to stop from interrupts being generated */
2902 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2904 IXGBE_WRITE_FLUSH(hw);
2908 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2910 struct rte_eth_conf* conf = &dev->data->dev_conf;
2912 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2913 dev->data->port_id);
2916 * VF has no ability to enable/disable HW CRC
2917 * Keep the persistent behavior the same as Host PF
2919 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2920 if (!conf->rxmode.hw_strip_crc) {
2921 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2922 conf->rxmode.hw_strip_crc = 1;
2925 if (conf->rxmode.hw_strip_crc) {
2926 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2927 conf->rxmode.hw_strip_crc = 0;
2935 ixgbevf_dev_start(struct rte_eth_dev *dev)
2937 struct ixgbe_hw *hw =
2938 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941 PMD_INIT_FUNC_TRACE();
2943 hw->mac.ops.reset_hw(hw);
2944 hw->mac.get_link_status = true;
2946 /* negotiate mailbox API version to use with the PF. */
2947 ixgbevf_negotiate_api(hw);
2949 ixgbevf_dev_tx_init(dev);
2951 /* This can fail when allocating mbufs for descriptor rings */
2952 err = ixgbevf_dev_rx_init(dev);
2954 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2955 ixgbe_dev_clear_queues(dev);
2960 ixgbevf_set_vfta_all(dev,1);
2963 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2964 ETH_VLAN_EXTEND_MASK;
2965 ixgbevf_vlan_offload_set(dev, mask);
2967 ixgbevf_dev_rxtx_start(dev);
2973 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2975 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2977 PMD_INIT_FUNC_TRACE();
2979 hw->adapter_stopped = TRUE;
2980 ixgbe_stop_adapter(hw);
2983 * Clear what we set, but we still keep shadow_vfta to
2984 * restore after device starts
2986 ixgbevf_set_vfta_all(dev,0);
2988 /* Clear stored conf */
2989 dev->data->scattered_rx = 0;
2991 ixgbe_dev_clear_queues(dev);
2995 ixgbevf_dev_close(struct rte_eth_dev *dev)
2997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999 PMD_INIT_FUNC_TRACE();
3003 ixgbevf_dev_stop(dev);
3005 /* reprogram the RAR[0] in case user changed it. */
3006 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3009 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3011 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3012 struct ixgbe_vfta * shadow_vfta =
3013 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3014 int i = 0, j = 0, vfta = 0, mask = 1;
3016 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3017 vfta = shadow_vfta->vfta[i];
3020 for (j = 0; j < 32; j++){
3022 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3031 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3033 struct ixgbe_hw *hw =
3034 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3035 struct ixgbe_vfta * shadow_vfta =
3036 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3037 uint32_t vid_idx = 0;
3038 uint32_t vid_bit = 0;
3041 PMD_INIT_FUNC_TRACE();
3043 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3044 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3046 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3049 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3050 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3052 /* Save what we set and retore it after device reset */
3054 shadow_vfta->vfta[vid_idx] |= vid_bit;
3056 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3062 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3064 struct ixgbe_hw *hw =
3065 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068 PMD_INIT_FUNC_TRACE();
3070 if(queue >= hw->mac.max_rx_queues)
3073 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3075 ctrl |= IXGBE_RXDCTL_VME;
3077 ctrl &= ~IXGBE_RXDCTL_VME;
3078 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3080 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3084 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3086 struct ixgbe_hw *hw =
3087 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091 /* VF function only support hw strip feature, others are not support */
3092 if(mask & ETH_VLAN_STRIP_MASK){
3093 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3095 for(i=0; i < hw->mac.max_rx_queues; i++)
3096 ixgbevf_vlan_strip_queue_set(dev,i,on);
3101 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3105 /* we only need to do this if VMDq is enabled */
3106 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3107 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3108 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3116 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3118 uint32_t vector = 0;
3119 switch (hw->mac.mc_filter_type) {
3120 case 0: /* use bits [47:36] of the address */
3121 vector = ((uc_addr->addr_bytes[4] >> 4) |
3122 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3124 case 1: /* use bits [46:35] of the address */
3125 vector = ((uc_addr->addr_bytes[4] >> 3) |
3126 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3128 case 2: /* use bits [45:34] of the address */
3129 vector = ((uc_addr->addr_bytes[4] >> 2) |
3130 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3132 case 3: /* use bits [43:32] of the address */
3133 vector = ((uc_addr->addr_bytes[4]) |
3134 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3136 default: /* Invalid mc_filter_type */
3140 /* vector can only be 12-bits or boundary will be exceeded */
3146 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3154 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3155 const uint32_t ixgbe_uta_bit_shift = 5;
3156 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3157 const uint32_t bit1 = 0x1;
3159 struct ixgbe_hw *hw =
3160 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161 struct ixgbe_uta_info *uta_info =
3162 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3164 /* The UTA table only exists on 82599 hardware and newer */
3165 if (hw->mac.type < ixgbe_mac_82599EB)
3168 vector = ixgbe_uta_vector(hw,mac_addr);
3169 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3170 uta_shift = vector & ixgbe_uta_bit_mask;
3172 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3176 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3178 uta_info->uta_in_use++;
3179 reg_val |= (bit1 << uta_shift);
3180 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3182 uta_info->uta_in_use--;
3183 reg_val &= ~(bit1 << uta_shift);
3184 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3187 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3189 if (uta_info->uta_in_use > 0)
3190 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3191 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3193 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3199 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3202 struct ixgbe_hw *hw =
3203 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3204 struct ixgbe_uta_info *uta_info =
3205 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3207 /* The UTA table only exists on 82599 hardware and newer */
3208 if (hw->mac.type < ixgbe_mac_82599EB)
3212 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3213 uta_info->uta_shadow[i] = ~0;
3214 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3217 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3218 uta_info->uta_shadow[i] = 0;
3219 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3227 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3229 uint32_t new_val = orig_val;
3231 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3232 new_val |= IXGBE_VMOLR_AUPE;
3233 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3234 new_val |= IXGBE_VMOLR_ROMPE;
3235 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3236 new_val |= IXGBE_VMOLR_ROPE;
3237 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3238 new_val |= IXGBE_VMOLR_BAM;
3239 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3240 new_val |= IXGBE_VMOLR_MPE;
3246 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3247 uint16_t rx_mask, uint8_t on)
3251 struct ixgbe_hw *hw =
3252 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3253 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3255 if (hw->mac.type == ixgbe_mac_82598EB) {
3256 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3257 " on 82599 hardware and newer");
3260 if (ixgbe_vmdq_mode_check(hw) < 0)
3263 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3270 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3276 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3280 const uint8_t bit1 = 0x1;
3282 struct ixgbe_hw *hw =
3283 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3285 if (ixgbe_vmdq_mode_check(hw) < 0)
3288 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3289 reg = IXGBE_READ_REG(hw, addr);
3297 IXGBE_WRITE_REG(hw, addr,reg);
3303 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3307 const uint8_t bit1 = 0x1;
3309 struct ixgbe_hw *hw =
3310 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312 if (ixgbe_vmdq_mode_check(hw) < 0)
3315 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3316 reg = IXGBE_READ_REG(hw, addr);
3324 IXGBE_WRITE_REG(hw, addr,reg);
3330 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3331 uint64_t pool_mask, uint8_t vlan_on)
3335 struct ixgbe_hw *hw =
3336 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3338 if (ixgbe_vmdq_mode_check(hw) < 0)
3340 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3341 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3342 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3351 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3352 struct rte_eth_vmdq_mirror_conf *mirror_conf,
3353 uint8_t rule_id, uint8_t on)
3355 uint32_t mr_ctl,vlvf;
3356 uint32_t mp_lsb = 0;
3357 uint32_t mv_msb = 0;
3358 uint32_t mv_lsb = 0;
3359 uint32_t mp_msb = 0;
3362 uint64_t vlan_mask = 0;
3364 const uint8_t pool_mask_offset = 32;
3365 const uint8_t vlan_mask_offset = 32;
3366 const uint8_t dst_pool_offset = 8;
3367 const uint8_t rule_mr_offset = 4;
3368 const uint8_t mirror_rule_mask= 0x0F;
3370 struct ixgbe_mirror_info *mr_info =
3371 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3372 struct ixgbe_hw *hw =
3373 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3375 if (ixgbe_vmdq_mode_check(hw) < 0)
3378 /* Check if vlan mask is valid */
3379 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3380 if (mirror_conf->vlan.vlan_mask == 0)
3384 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3385 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3386 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3387 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3388 /* search vlan id related pool vlan filter index */
3389 reg_index = ixgbe_find_vlvf_slot(hw,
3390 mirror_conf->vlan.vlan_id[i]);
3393 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3394 if ((vlvf & IXGBE_VLVF_VIEN) &&
3395 ((vlvf & IXGBE_VLVF_VLANID_MASK)
3396 == mirror_conf->vlan.vlan_id[i]))
3397 vlan_mask |= (1ULL << reg_index);
3404 mv_lsb = vlan_mask & 0xFFFFFFFF;
3405 mv_msb = vlan_mask >> vlan_mask_offset;
3407 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3408 mirror_conf->vlan.vlan_mask;
3409 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3410 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3411 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3412 mirror_conf->vlan.vlan_id[i];
3417 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3418 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3419 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3424 * if enable pool mirror, write related pool mask register,if disable
3425 * pool mirror, clear PFMRVM register
3427 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3429 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3430 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3431 mr_info->mr_conf[rule_id].pool_mask =
3432 mirror_conf->pool_mask;
3437 mr_info->mr_conf[rule_id].pool_mask = 0;
3441 /* read mirror control register and recalculate it */
3442 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3445 mr_ctl |= mirror_conf->rule_type_mask;
3446 mr_ctl &= mirror_rule_mask;
3447 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3449 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3451 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3452 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3454 /* write mirrror control register */
3455 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3457 /* write pool mirrror control register */
3458 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3459 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3460 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3463 /* write VLAN mirrror control register */
3464 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3465 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3466 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3474 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3477 uint32_t lsb_val = 0;
3478 uint32_t msb_val = 0;
3479 const uint8_t rule_mr_offset = 4;
3481 struct ixgbe_hw *hw =
3482 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483 struct ixgbe_mirror_info *mr_info =
3484 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3486 if (ixgbe_vmdq_mode_check(hw) < 0)
3489 memset(&mr_info->mr_conf[rule_id], 0,
3490 sizeof(struct rte_eth_vmdq_mirror_conf));
3492 /* clear PFVMCTL register */
3493 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3495 /* clear pool mask register */
3496 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3497 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3499 /* clear vlan mask register */
3500 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3501 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3506 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3507 uint16_t queue_idx, uint16_t tx_rate)
3509 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510 uint32_t rf_dec, rf_int;
3512 uint16_t link_speed = dev->data->dev_link.link_speed;
3514 if (queue_idx >= hw->mac.max_tx_queues)
3518 /* Calculate the rate factor values to set */
3519 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3520 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3521 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3523 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3524 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3525 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3526 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3532 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3533 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3536 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3537 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3538 IXGBE_MAX_JUMBO_FRAME_SIZE))
3539 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3540 IXGBE_MMW_SIZE_JUMBO_FRAME);
3542 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3543 IXGBE_MMW_SIZE_DEFAULT);
3545 /* Set RTTBCNRC of queue X */
3546 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3547 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3548 IXGBE_WRITE_FLUSH(hw);
3553 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3554 uint16_t tx_rate, uint64_t q_msk)
3556 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3557 struct ixgbe_vf_info *vfinfo =
3558 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3559 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3560 uint32_t queue_stride =
3561 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3562 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3563 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3564 uint16_t total_rate = 0;
3566 if (queue_end >= hw->mac.max_tx_queues)
3569 if (vfinfo != NULL) {
3570 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3573 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3575 total_rate += vfinfo[vf_idx].tx_rate[idx];
3580 /* Store tx_rate for this vf. */
3581 for (idx = 0; idx < nb_q_per_pool; idx++) {
3582 if (((uint64_t)0x1 << idx) & q_msk) {
3583 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3584 vfinfo[vf].tx_rate[idx] = tx_rate;
3585 total_rate += tx_rate;
3589 if (total_rate > dev->data->dev_link.link_speed) {
3591 * Reset stored TX rate of the VF if it causes exceed
3594 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3598 /* Set RTTBCNRC of each queue/pool for vf X */
3599 for (; queue_idx <= queue_end; queue_idx++) {
3601 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3609 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3610 __attribute__((unused)) uint32_t index,
3611 __attribute__((unused)) uint32_t pool)
3613 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3618 * operation. Trap this case to avoid exhausting the [very limited]
3619 * set of PF resources used to store VF MAC addresses.
3621 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3623 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3626 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3630 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3632 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3633 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3634 struct ether_addr *mac_addr;
3639 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3640 * not support the deletion of a given MAC address.
3641 * Instead, it imposes to delete all MAC addresses, then to add again
3642 * all MAC addresses with the exception of the one to be deleted.
3644 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3647 * Add again all MAC addresses, with the exception of the deleted one
3648 * and of the permanent MAC address.
3650 for (i = 0, mac_addr = dev->data->mac_addrs;
3651 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3652 /* Skip the deleted MAC address */
3655 /* Skip NULL MAC addresses */
3656 if (is_zero_ether_addr(mac_addr))
3658 /* Skip the permanent MAC address */
3659 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3661 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3664 "Adding again MAC address "
3665 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3667 mac_addr->addr_bytes[0],
3668 mac_addr->addr_bytes[1],
3669 mac_addr->addr_bytes[2],
3670 mac_addr->addr_bytes[3],
3671 mac_addr->addr_bytes[4],
3672 mac_addr->addr_bytes[5],
3681 * dev: Pointer to struct rte_eth_dev.
3682 * filter: ponter to the filter that will be added.
3683 * rx_queue: the queue id the filter assigned to.
3686 * - On success, zero.
3687 * - On failure, a negative value.
3690 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3691 struct rte_syn_filter *filter, uint16_t rx_queue)
3693 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3696 if (hw->mac.type != ixgbe_mac_82599EB)
3699 if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3702 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3704 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3707 synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3708 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3710 if (filter->hig_pri)
3711 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3713 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3715 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3723 * dev: Pointer to struct rte_eth_dev.
3726 * - On success, zero.
3727 * - On failure, a negative value.
3730 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3732 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3735 if (hw->mac.type != ixgbe_mac_82599EB)
3738 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3740 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3742 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3747 * get the syn filter's info
3750 * dev: Pointer to struct rte_eth_dev.
3751 * filter: ponter to the filter that returns.
3752 * *rx_queue: pointer to the queue id the filter assigned to.
3755 * - On success, zero.
3756 * - On failure, a negative value.
3759 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3760 struct rte_syn_filter *filter, uint16_t *rx_queue)
3763 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3766 if (hw->mac.type != ixgbe_mac_82599EB)
3769 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3770 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3771 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3772 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3778 static inline enum ixgbe_5tuple_protocol
3779 convert_protocol_type(uint8_t protocol_value)
3781 if (protocol_value == IPPROTO_TCP)
3782 return IXGBE_FILTER_PROTOCOL_TCP;
3783 else if (protocol_value == IPPROTO_UDP)
3784 return IXGBE_FILTER_PROTOCOL_UDP;
3785 else if (protocol_value == IPPROTO_SCTP)
3786 return IXGBE_FILTER_PROTOCOL_SCTP;
3788 return IXGBE_FILTER_PROTOCOL_NONE;
3791 static inline uint8_t
3792 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3794 if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3796 else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3798 else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3799 return IPPROTO_SCTP;
3805 * add a 5tuple filter
3808 * dev: Pointer to struct rte_eth_dev.
3809 * index: the index the filter allocates.
3810 * filter: ponter to the filter that will be added.
3811 * rx_queue: the queue id the filter assigned to.
3814 * - On success, zero.
3815 * - On failure, a negative value.
3818 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3819 struct rte_5tuple_filter *filter, uint16_t rx_queue)
3821 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3822 uint32_t ftqf, sdpqf = 0;
3823 uint32_t l34timir = 0;
3824 uint8_t mask = 0xff;
3826 if (hw->mac.type != ixgbe_mac_82599EB)
3829 if (index >= IXGBE_MAX_FTQF_FILTERS ||
3830 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3831 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3832 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3833 return -EINVAL; /* filter index is out of range. */
3835 if (filter->tcp_flags) {
3836 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3840 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3841 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3842 return -EINVAL; /* filter index is in use. */
3845 sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3846 sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3848 ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3849 IXGBE_FTQF_PROTOCOL_MASK);
3850 ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3851 IXGBE_FTQF_PRIORITY_SHIFT);
3852 if (filter->src_ip_mask == 0) /* 0 means compare. */
3853 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3854 if (filter->dst_ip_mask == 0)
3855 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3856 if (filter->src_port_mask == 0)
3857 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3858 if (filter->dst_port_mask == 0)
3859 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3860 if (filter->protocol_mask == 0)
3861 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3862 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3863 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3864 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3866 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3867 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3868 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3869 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3871 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3872 l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3873 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3878 * remove a 5tuple filter
3881 * dev: Pointer to struct rte_eth_dev.
3882 * index: the index the filter allocates.
3885 * - On success, zero.
3886 * - On failure, a negative value.
3889 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3892 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3894 if (hw->mac.type != ixgbe_mac_82599EB)
3897 if (index >= IXGBE_MAX_FTQF_FILTERS)
3898 return -EINVAL; /* filter index is out of range. */
3900 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3901 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3902 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3903 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3904 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3909 * get a 5tuple filter
3912 * dev: Pointer to struct rte_eth_dev.
3913 * index: the index the filter allocates
3914 * filter: ponter to the filter that returns.
3915 * *rx_queue: pointer of the queue id the filter assigned to.
3918 * - On success, zero.
3919 * - On failure, a negative value.
3922 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3923 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3925 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3926 uint32_t sdpqf, ftqf, l34timir;
3928 enum ixgbe_5tuple_protocol proto;
3930 if (hw->mac.type != ixgbe_mac_82599EB)
3933 if (index >= IXGBE_MAX_FTQF_FILTERS)
3934 return -EINVAL; /* filter index is out of range. */
3936 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3937 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3938 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3939 filter->protocol = revert_protocol_type(proto);
3940 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3941 IXGBE_FTQF_PRIORITY_MASK;
3942 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3943 IXGBE_FTQF_5TUPLE_MASK_MASK);
3944 filter->src_ip_mask =
3945 (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3946 filter->dst_ip_mask =
3947 (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3948 filter->src_port_mask =
3949 (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3950 filter->dst_port_mask =
3951 (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3952 filter->protocol_mask =
3953 (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3955 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3956 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3957 IXGBE_SDPQF_DSTPORT_SHIFT;
3958 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3959 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3960 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3962 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3963 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3964 IXGBE_L34T_IMIR_QUEUE_SHIFT;
3971 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3973 struct ixgbe_hw *hw;
3974 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3976 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3978 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3981 /* refuse mtu that requires the support of scattered packets when this
3982 * feature has not been enabled before. */
3983 if (!dev->data->scattered_rx &&
3984 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3985 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3989 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3990 * request of the version 2.0 of the mailbox API.
3991 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3992 * of the mailbox API.
3993 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3994 * prior to 3.11.33 which contains the following change:
3995 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3997 ixgbevf_rlpml_set_vf(hw, max_frame);
3999 /* update max frame size */
4000 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4004 #define MAC_TYPE_FILTER_SUP(type) do {\
4005 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4006 (type) != ixgbe_mac_X550)\
4011 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4016 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4017 if (filter_info->ethertype_filters[i] == ethertype &&
4018 (filter_info->ethertype_mask & (1 << i)))
4025 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4030 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4031 if (!(filter_info->ethertype_mask & (1 << i))) {
4032 filter_info->ethertype_mask |= 1 << i;
4033 filter_info->ethertype_filters[i] = ethertype;
4041 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4044 if (idx >= IXGBE_MAX_ETQF_FILTERS)
4046 filter_info->ethertype_mask &= ~(1 << idx);
4047 filter_info->ethertype_filters[idx] = 0;
4052 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4053 struct rte_eth_ethertype_filter *filter,
4056 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4057 struct ixgbe_filter_info *filter_info =
4058 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4063 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4066 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4067 filter->ether_type == ETHER_TYPE_IPv6) {
4068 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4069 " ethertype filter.", filter->ether_type);
4073 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4074 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4077 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4078 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4082 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4083 if (ret >= 0 && add) {
4084 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4085 filter->ether_type);
4088 if (ret < 0 && !add) {
4089 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4090 filter->ether_type);
4095 ret = ixgbe_ethertype_filter_insert(filter_info,
4096 filter->ether_type);
4098 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4101 etqf = IXGBE_ETQF_FILTER_EN;
4102 etqf |= (uint32_t)filter->ether_type;
4103 etqs |= (uint32_t)((filter->queue <<
4104 IXGBE_ETQS_RX_QUEUE_SHIFT) &
4105 IXGBE_ETQS_RX_QUEUE);
4106 etqs |= IXGBE_ETQS_QUEUE_EN;
4108 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4112 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4113 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4114 IXGBE_WRITE_FLUSH(hw);
4120 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4121 struct rte_eth_ethertype_filter *filter)
4123 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4124 struct ixgbe_filter_info *filter_info =
4125 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4126 uint32_t etqf, etqs;
4129 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4131 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4132 filter->ether_type);
4136 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4137 if (etqf & IXGBE_ETQF_FILTER_EN) {
4138 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4139 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4141 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4142 IXGBE_ETQS_RX_QUEUE_SHIFT;
4149 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4150 * @dev: pointer to rte_eth_dev structure
4151 * @filter_op:operation will be taken.
4152 * @arg: a pointer to specific structure corresponding to the filter_op
4155 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4156 enum rte_filter_op filter_op,
4159 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4162 MAC_TYPE_FILTER_SUP(hw->mac.type);
4164 if (filter_op == RTE_ETH_FILTER_NOP)
4168 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4173 switch (filter_op) {
4174 case RTE_ETH_FILTER_ADD:
4175 ret = ixgbe_add_del_ethertype_filter(dev,
4176 (struct rte_eth_ethertype_filter *)arg,
4179 case RTE_ETH_FILTER_DELETE:
4180 ret = ixgbe_add_del_ethertype_filter(dev,
4181 (struct rte_eth_ethertype_filter *)arg,
4184 case RTE_ETH_FILTER_GET:
4185 ret = ixgbe_get_ethertype_filter(dev,
4186 (struct rte_eth_ethertype_filter *)arg);
4189 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4197 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4198 enum rte_filter_type filter_type,
4199 enum rte_filter_op filter_op,
4204 switch (filter_type) {
4205 case RTE_ETH_FILTER_ETHERTYPE:
4206 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4208 case RTE_ETH_FILTER_FDIR:
4209 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4212 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4220 static struct rte_driver rte_ixgbe_driver = {
4222 .init = rte_ixgbe_pmd_init,
4225 static struct rte_driver rte_ixgbevf_driver = {
4227 .init = rte_ixgbevf_pmd_init,
4230 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4231 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);