lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 110
 111 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 112
 113 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 114                 struct rte_eth_dev *eth_dev);
 115 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 116 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 117 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 118 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 119 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 120 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 121 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 122 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 123 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 124 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 125 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 126                                 int wait_to_complete);
 127 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 128                                 struct rte_eth_stats *stats);
 129 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 130 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 131                                              uint16_t queue_id,
 132                                              uint8_t stat_idx,
 133                                              uint8_t is_rx);
 134 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 135                                 struct rte_eth_dev_info *dev_info);
 136
 137 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 138
 139 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 140                 uint16_t vlan_id, int on);
 141 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 142 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 143                 uint16_t queue, bool on);
 144 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 145                 int on);
 146 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 147 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 148 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 149 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 151
 152 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 154 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 155                                struct rte_eth_fc_conf *fc_conf);
 156 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 157                                struct rte_eth_fc_conf *fc_conf);
 158 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 159                 struct rte_eth_pfc_conf *pfc_conf);
 160 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 161                 struct rte_eth_rss_reta *reta_conf);
 162 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 163                 struct rte_eth_rss_reta *reta_conf);
 164 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 165 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 167 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 169                 void *param);
 170 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 171 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 172                 uint32_t index, uint32_t pool);
 173 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 174 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 175
 176 /* For Virtual Function support */
 177 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 178                 struct rte_eth_dev *eth_dev);
 179 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 180 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 181 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 182 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 183 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 184 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 185                 struct rte_eth_stats *stats);
 186 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 187 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 188                 uint16_t vlan_id, int on);
 189 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 190                 uint16_t queue, int on);
 191 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 192 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 193
 194 /* For Eth VMDQ APIs support */
 195 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 196                 ether_addr* mac_addr,uint8_t on);
 197 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 198 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 199                 uint16_t rx_mask, uint8_t on);
 200 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 201 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 202 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 203                 uint64_t pool_mask,uint8_t vlan_on);
 204 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 205                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 206                 uint8_t rule_id, uint8_t on);
 207 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 208                 uint8_t rule_id);
 209
 210 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 211                 uint16_t queue_idx, uint16_t tx_rate);
 212 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 213                 uint16_t tx_rate, uint64_t q_msk);
 214
 215 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 216                                  struct ether_addr *mac_addr,
 217                                  uint32_t index, uint32_t pool);
 218 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 219 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 220                         struct rte_syn_filter *filter, uint16_t rx_queue);
 221 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 222 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 223                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 224 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 225                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 226 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 227                         uint16_t index);
 228 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 229                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 230 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 231                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 232 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 233                         uint16_t index);
 234 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 235                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 236
 237 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 238
 239 /*
 240  * Define VF Stats MACRO for Non "cleared on read" register
 241  */
 242 #define UPDATE_VF_STAT(reg, last, cur)                          \
 243 {                                                               \
 244         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 245         cur += latest - last;                                   \
 246         last = latest;                                          \
 247 }
 248
 249 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 250 {                                                                \
 251         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 252         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 253         u64 latest = ((new_msb << 32) | new_lsb);                \
 254         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 255         last = latest;                                           \
 256 }
 257
 258 #define IXGBE_SET_HWSTRIP(h, q) do{\
 259                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 260                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 261                 (h)->bitmap[idx] |= 1 << bit;\
 262         }while(0)
 263
 264 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 265                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 266                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 267                 (h)->bitmap[idx] &= ~(1 << bit);\
 268         }while(0)
 269
 270 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 271                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 272                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 273                 (r) = (h)->bitmap[idx] >> bit & 1;\
 274         }while(0)
 275
 276 /*
 277  * The set of PCI devices this driver supports
 278  */
 279 static struct rte_pci_id pci_id_ixgbe_map[] = {
 280
 281 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 282 #include "rte_pci_dev_ids.h"
 283
 284 { .vendor_id = 0, /* sentinel */ },
 285 };
 286
 287
 288 /*
 289  * The set of PCI devices this driver supports (for 82599 VF)
 290  */
 291 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 292
 293 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 294 #include "rte_pci_dev_ids.h"
 295 { .vendor_id = 0, /* sentinel */ },
 296
 297 };
 298
 299 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 300         .dev_configure        = ixgbe_dev_configure,
 301         .dev_start            = ixgbe_dev_start,
 302         .dev_stop             = ixgbe_dev_stop,
 303         .dev_set_link_up    = ixgbe_dev_set_link_up,
 304         .dev_set_link_down  = ixgbe_dev_set_link_down,
 305         .dev_close            = ixgbe_dev_close,
 306         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 307         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 308         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 309         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 310         .link_update          = ixgbe_dev_link_update,
 311         .stats_get            = ixgbe_dev_stats_get,
 312         .stats_reset          = ixgbe_dev_stats_reset,
 313         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 314         .dev_infos_get        = ixgbe_dev_info_get,
 315         .mtu_set              = ixgbe_dev_mtu_set,
 316         .vlan_filter_set      = ixgbe_vlan_filter_set,
 317         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 318         .vlan_offload_set     = ixgbe_vlan_offload_set,
 319         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 320         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 321         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 322         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 323         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 324         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 325         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 326         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 327         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 328         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 329         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 330         .dev_led_on           = ixgbe_dev_led_on,
 331         .dev_led_off          = ixgbe_dev_led_off,
 332         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 333         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 334         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 335         .mac_addr_add         = ixgbe_add_rar,
 336         .mac_addr_remove      = ixgbe_remove_rar,
 337         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 338         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 339         .mirror_rule_set      = ixgbe_mirror_rule_set,
 340         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 341         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 342         .set_vf_rx            = ixgbe_set_pool_rx,
 343         .set_vf_tx            = ixgbe_set_pool_tx,
 344         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 345         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 346         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 347         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 348         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 349         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 350         .fdir_infos_get               = ixgbe_fdir_info_get,
 351         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 352         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 353         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 354         .fdir_set_masks               = ixgbe_fdir_set_masks,
 355         .reta_update          = ixgbe_dev_rss_reta_update,
 356         .reta_query           = ixgbe_dev_rss_reta_query,
 357 #ifdef RTE_NIC_BYPASS
 358         .bypass_init          = ixgbe_bypass_init,
 359         .bypass_state_set     = ixgbe_bypass_state_store,
 360         .bypass_state_show    = ixgbe_bypass_state_show,
 361         .bypass_event_set     = ixgbe_bypass_event_store,
 362         .bypass_event_show    = ixgbe_bypass_event_show,
 363         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 364         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 365         .bypass_ver_show      = ixgbe_bypass_ver_show,
 366         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 367 #endif /* RTE_NIC_BYPASS */
 368         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 369         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 370         .add_syn_filter          = ixgbe_add_syn_filter,
 371         .remove_syn_filter       = ixgbe_remove_syn_filter,
 372         .get_syn_filter          = ixgbe_get_syn_filter,
 373         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 374         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 375         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 376         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 377         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 378         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 379 };
 380
 381 /*
 382  * dev_ops for virtual function, bare necessities for basic vf
 383  * operation have been implemented
 384  */
 385 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 386
 387         .dev_configure        = ixgbevf_dev_configure,
 388         .dev_start            = ixgbevf_dev_start,
 389         .dev_stop             = ixgbevf_dev_stop,
 390         .link_update          = ixgbe_dev_link_update,
 391         .stats_get            = ixgbevf_dev_stats_get,
 392         .stats_reset          = ixgbevf_dev_stats_reset,
 393         .dev_close            = ixgbevf_dev_close,
 394         .dev_infos_get        = ixgbe_dev_info_get,
 395         .mtu_set              = ixgbevf_dev_set_mtu,
 396         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 397         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 398         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 399         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 400         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 401         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 402         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 403         .mac_addr_add         = ixgbevf_add_mac_addr,
 404         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 405 };
 406
 407 /**
 408  * Atomically reads the link status information from global
 409  * structure rte_eth_dev.
 410  *
 411  * @param dev
 412  *   - Pointer to the structure rte_eth_dev to read from.
 413  *   - Pointer to the buffer to be saved with the link status.
 414  *
 415  * @return
 416  *   - On success, zero.
 417  *   - On failure, negative value.
 418  */
 419 static inline int
 420 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 421                                 struct rte_eth_link *link)
 422 {
 423         struct rte_eth_link *dst = link;
 424         struct rte_eth_link *src = &(dev->data->dev_link);
 425
 426         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 427                                         *(uint64_t *)src) == 0)
 428                 return -1;
 429
 430         return 0;
 431 }
 432
 433 /**
 434  * Atomically writes the link status information into global
 435  * structure rte_eth_dev.
 436  *
 437  * @param dev
 438  *   - Pointer to the structure rte_eth_dev to read from.
 439  *   - Pointer to the buffer to be saved with the link status.
 440  *
 441  * @return
 442  *   - On success, zero.
 443  *   - On failure, negative value.
 444  */
 445 static inline int
 446 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 447                                 struct rte_eth_link *link)
 448 {
 449         struct rte_eth_link *dst = &(dev->data->dev_link);
 450         struct rte_eth_link *src = link;
 451
 452         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 453                                         *(uint64_t *)src) == 0)
 454                 return -1;
 455
 456         return 0;
 457 }
 458
 459 /*
 460  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 461  */
 462 static inline int
 463 ixgbe_is_sfp(struct ixgbe_hw *hw)
 464 {
 465         switch (hw->phy.type) {
 466         case ixgbe_phy_sfp_avago:
 467         case ixgbe_phy_sfp_ftl:
 468         case ixgbe_phy_sfp_intel:
 469         case ixgbe_phy_sfp_unknown:
 470         case ixgbe_phy_sfp_passive_tyco:
 471         case ixgbe_phy_sfp_passive_unknown:
 472                 return 1;
 473         default:
 474                 return 0;
 475         }
 476 }
 477
 478 static inline int32_t
 479 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 480 {
 481         uint32_t ctrl_ext;
 482         int32_t status;
 483
 484         status = ixgbe_reset_hw(hw);
 485
 486         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 487         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 488         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 489         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 490         IXGBE_WRITE_FLUSH(hw);
 491
 492         return status;
 493 }
 494
 495 static inline void
 496 ixgbe_enable_intr(struct rte_eth_dev *dev)
 497 {
 498         struct ixgbe_interrupt *intr =
 499                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 500         struct ixgbe_hw *hw =
 501                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 502
 503         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 504         IXGBE_WRITE_FLUSH(hw);
 505 }
 506
 507 /*
 508  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 509  */
 510 static void
 511 ixgbe_disable_intr(struct ixgbe_hw *hw)
 512 {
 513         PMD_INIT_FUNC_TRACE();
 514
 515         if (hw->mac.type == ixgbe_mac_82598EB) {
 516                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 517         } else {
 518                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 519                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 520                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 521         }
 522         IXGBE_WRITE_FLUSH(hw);
 523 }
 524
 525 /*
 526  * This function resets queue statistics mapping registers.
 527  * From Niantic datasheet, Initialization of Statistics section:
 528  * "...if software requires the queue counters, the RQSMR and TQSM registers
 529  * must be re-programmed following a device reset.
 530  */
 531 static void
 532 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 533 {
 534         uint32_t i;
 535
 536         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 537                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 538                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 539         }
 540 }
 541
 542
 543 static int
 544 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 545                                   uint16_t queue_id,
 546                                   uint8_t stat_idx,
 547                                   uint8_t is_rx)
 548 {
 549 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 550 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 551 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 552
 553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 554         struct ixgbe_stat_mapping_registers *stat_mappings =
 555                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 556         uint32_t qsmr_mask = 0;
 557         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 558         uint32_t q_map;
 559         uint8_t n, offset;
 560
 561         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 562                 (hw->mac.type != ixgbe_mac_X540) &&
 563                 (hw->mac.type != ixgbe_mac_X550) &&
 564                 (hw->mac.type != ixgbe_mac_X550EM_x))
 565                 return -ENOSYS;
 566
 567         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 568                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 569                      queue_id, stat_idx);
 570
 571         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 572         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 573                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 574                 return -EIO;
 575         }
 576         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 577
 578         /* Now clear any previous stat_idx set */
 579         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 580         if (!is_rx)
 581                 stat_mappings->tqsm[n] &= ~clearing_mask;
 582         else
 583                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 584
 585         q_map = (uint32_t)stat_idx;
 586         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 587         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 588         if (!is_rx)
 589                 stat_mappings->tqsm[n] |= qsmr_mask;
 590         else
 591                 stat_mappings->rqsmr[n] |= qsmr_mask;
 592
 593         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 594                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 595                      queue_id, stat_idx);
 596         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 597                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 598
 599         /* Now write the mapping in the appropriate register */
 600         if (is_rx) {
 601                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 602                              stat_mappings->rqsmr[n], n);
 603                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 604         }
 605         else {
 606                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 607                              stat_mappings->tqsm[n], n);
 608                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 609         }
 610         return 0;
 611 }
 612
 613 static void
 614 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 615 {
 616         struct ixgbe_stat_mapping_registers *stat_mappings =
 617                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 618         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 619         int i;
 620
 621         /* write whatever was in stat mapping table to the NIC */
 622         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 623                 /* rx */
 624                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 625
 626                 /* tx */
 627                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 628         }
 629 }
 630
 631 static void
 632 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 633 {
 634         uint8_t i;
 635         struct ixgbe_dcb_tc_config *tc;
 636         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 637
 638         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 639         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 640         for (i = 0; i < dcb_max_tc; i++) {
 641                 tc = &dcb_config->tc_config[i];
 642                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 643                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 644                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 645                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 646                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 647                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 648                 tc->pfc = ixgbe_dcb_pfc_disabled;
 649         }
 650
 651         /* Initialize default user to priority mapping, UPx->TC0 */
 652         tc = &dcb_config->tc_config[0];
 653         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 654         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 655         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 656                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 657                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 658         }
 659         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 660         dcb_config->pfc_mode_enable = false;
 661         dcb_config->vt_mode = true;
 662         dcb_config->round_robin_enable = false;
 663         /* support all DCB capabilities in 82599 */
 664         dcb_config->support.capabilities = 0xFF;
 665
 666         /*we only support 4 Tcs for X540, X550 */
 667         if (hw->mac.type == ixgbe_mac_X540 ||
 668                 hw->mac.type == ixgbe_mac_X550 ||
 669                 hw->mac.type == ixgbe_mac_X550EM_x) {
 670                 dcb_config->num_tcs.pg_tcs = 4;
 671                 dcb_config->num_tcs.pfc_tcs = 4;
 672         }
 673 }
 674
 675 /*
 676  * Ensure that all locks are released before first NVM or PHY access
 677  */
 678 static void
 679 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 680 {
 681         uint16_t mask;
 682
 683         /*
 684          * Phy lock should not fail in this early stage. If this is the case,
 685          * it is due to an improper exit of the application.
 686          * So force the release of the faulty lock. Release of common lock
 687          * is done automatically by swfw_sync function.
 688          */
 689         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 690         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 691                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 692         }
 693         ixgbe_release_swfw_semaphore(hw, mask);
 694
 695         /*
 696          * These ones are more tricky since they are common to all ports; but
 697          * swfw_sync retries last long enough (1s) to be almost sure that if
 698          * lock can not be taken it is due to an improper lock of the
 699          * semaphore.
 700          */
 701         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 702         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 703                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 704         }
 705         ixgbe_release_swfw_semaphore(hw, mask);
 706 }
 707
 708 /*
 709  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 710  * It returns 0 on success.
 711  */
 712 static int
 713 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 714                      struct rte_eth_dev *eth_dev)
 715 {
 716         struct rte_pci_device *pci_dev;
 717         struct ixgbe_hw *hw =
 718                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 719         struct ixgbe_vfta * shadow_vfta =
 720                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 721         struct ixgbe_hwstrip *hwstrip =
 722                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 723         struct ixgbe_dcb_config *dcb_config =
 724                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 725         uint32_t ctrl_ext;
 726         uint16_t csum;
 727         int diag, i;
 728
 729         PMD_INIT_FUNC_TRACE();
 730
 731         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 732         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 733         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 734
 735         /* for secondary processes, we don't initialise any further as primary
 736          * has already done this work. Only check we don't need a different
 737          * RX function */
 738         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 739                 if (eth_dev->data->scattered_rx)
 740                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 741                 return 0;
 742         }
 743         pci_dev = eth_dev->pci_dev;
 744
 745         /* Vendor and Device ID need to be set before init of shared code */
 746         hw->device_id = pci_dev->id.device_id;
 747         hw->vendor_id = pci_dev->id.vendor_id;
 748         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 749         hw->allow_unsupported_sfp = 1;
 750
 751         /* Initialize the shared code (base driver) */
 752 #ifdef RTE_NIC_BYPASS
 753         diag = ixgbe_bypass_init_shared_code(hw);
 754 #else
 755         diag = ixgbe_init_shared_code(hw);
 756 #endif /* RTE_NIC_BYPASS */
 757
 758         if (diag != IXGBE_SUCCESS) {
 759                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 760                 return -EIO;
 761         }
 762
 763         /* pick up the PCI bus settings for reporting later */
 764         ixgbe_get_bus_info(hw);
 765
 766         /* Unlock any pending hardware semaphore */
 767         ixgbe_swfw_lock_reset(hw);
 768
 769         /* Initialize DCB configuration*/
 770         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 771         ixgbe_dcb_init(hw,dcb_config);
 772         /* Get Hardware Flow Control setting */
 773         hw->fc.requested_mode = ixgbe_fc_full;
 774         hw->fc.current_mode = ixgbe_fc_full;
 775         hw->fc.pause_time = IXGBE_FC_PAUSE;
 776         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 777                 hw->fc.low_water[i] = IXGBE_FC_LO;
 778                 hw->fc.high_water[i] = IXGBE_FC_HI;
 779         }
 780         hw->fc.send_xon = 1;
 781
 782         /* Make sure we have a good EEPROM before we read from it */
 783         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 784         if (diag != IXGBE_SUCCESS) {
 785                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 786                 return -EIO;
 787         }
 788
 789 #ifdef RTE_NIC_BYPASS
 790         diag = ixgbe_bypass_init_hw(hw);
 791 #else
 792         diag = ixgbe_init_hw(hw);
 793 #endif /* RTE_NIC_BYPASS */
 794
 795         /*
 796          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 797          * is called too soon after the kernel driver unbinding/binding occurs.
 798          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 799          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 800          * also called. See ixgbe_identify_phy_82599(). The reason for the
 801          * failure is not known, and only occuts when virtualisation features
 802          * are disabled in the bios. A delay of 100ms  was found to be enough by
 803          * trial-and-error, and is doubled to be safe.
 804          */
 805         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 806                 rte_delay_ms(200);
 807                 diag = ixgbe_init_hw(hw);
 808         }
 809
 810         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 811                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 812                     "LOM.  Please be aware there may be issues associated "
 813                     "with your hardware.");
 814                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 815                     "please contact your Intel or hardware representative "
 816                     "who provided you with this hardware.");
 817         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 818                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 819         if (diag) {
 820                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 821                 return -EIO;
 822         }
 823
 824         /* disable interrupt */
 825         ixgbe_disable_intr(hw);
 826
 827         /* reset mappings for queue statistics hw counters*/
 828         ixgbe_reset_qstat_mappings(hw);
 829
 830         /* Allocate memory for storing MAC addresses */
 831         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 832                         hw->mac.num_rar_entries, 0);
 833         if (eth_dev->data->mac_addrs == NULL) {
 834                 PMD_INIT_LOG(ERR,
 835                         "Failed to allocate %u bytes needed to store "
 836                         "MAC addresses",
 837                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 838                 return -ENOMEM;
 839         }
 840         /* Copy the permanent MAC address */
 841         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 842                         &eth_dev->data->mac_addrs[0]);
 843
 844         /* Allocate memory for storing hash filter MAC addresses */
 845         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 846                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 847         if (eth_dev->data->hash_mac_addrs == NULL) {
 848                 PMD_INIT_LOG(ERR,
 849                         "Failed to allocate %d bytes needed to store MAC addresses",
 850                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 851                 return -ENOMEM;
 852         }
 853
 854         /* initialize the vfta */
 855         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 856
 857         /* initialize the hw strip bitmap*/
 858         memset(hwstrip, 0, sizeof(*hwstrip));
 859
 860         /* initialize PF if max_vfs not zero */
 861         ixgbe_pf_host_init(eth_dev);
 862
 863         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 864         /* let hardware know driver is loaded */
 865         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 866         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 867         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 868         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 869         IXGBE_WRITE_FLUSH(hw);
 870
 871         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 872                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 873                              (int) hw->mac.type, (int) hw->phy.type,
 874                              (int) hw->phy.sfp_type);
 875         else
 876                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 877                              (int) hw->mac.type, (int) hw->phy.type);
 878
 879         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 880                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 881                         pci_dev->id.device_id);
 882
 883         rte_intr_callback_register(&(pci_dev->intr_handle),
 884                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 885
 886         /* enable uio intr after callback register */
 887         rte_intr_enable(&(pci_dev->intr_handle));
 888
 889         /* enable support intr */
 890         ixgbe_enable_intr(eth_dev);
 891
 892         return 0;
 893 }
 894
 895
 896 /*
 897  * Negotiate mailbox API version with the PF.
 898  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 899  * Then we try to negotiate starting with the most recent one.
 900  * If all negotiation attempts fail, then we will proceed with
 901  * the default one (ixgbe_mbox_api_10).
 902  */
 903 static void
 904 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 905 {
 906         int32_t i;
 907
 908         /* start with highest supported, proceed down */
 909         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 910                 ixgbe_mbox_api_11,
 911                 ixgbe_mbox_api_10,
 912         };
 913
 914         for (i = 0;
 915                         i != RTE_DIM(sup_ver) &&
 916                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 917                         i++)
 918                 ;
 919 }
 920
 921 static void
 922 generate_random_mac_addr(struct ether_addr *mac_addr)
 923 {
 924         uint64_t random;
 925
 926         /* Set Organizationally Unique Identifier (OUI) prefix. */
 927         mac_addr->addr_bytes[0] = 0x00;
 928         mac_addr->addr_bytes[1] = 0x09;
 929         mac_addr->addr_bytes[2] = 0xC0;
 930         /* Force indication of locally assigned MAC address. */
 931         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 932         /* Generate the last 3 bytes of the MAC address with a random number. */
 933         random = rte_rand();
 934         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 935 }
 936
 937 /*
 938  * Virtual Function device init
 939  */
 940 static int
 941 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 942                      struct rte_eth_dev *eth_dev)
 943 {
 944         int diag;
 945         uint32_t tc, tcs;
 946         struct rte_pci_device *pci_dev;
 947         struct ixgbe_hw *hw =
 948                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 949         struct ixgbe_vfta * shadow_vfta =
 950                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 951         struct ixgbe_hwstrip *hwstrip =
 952                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 953         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 954
 955         PMD_INIT_FUNC_TRACE();
 956
 957         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 958         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 959         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 960
 961         /* for secondary processes, we don't initialise any further as primary
 962          * has already done this work. Only check we don't need a different
 963          * RX function */
 964         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 965                 if (eth_dev->data->scattered_rx)
 966                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 967                 return 0;
 968         }
 969
 970         pci_dev = eth_dev->pci_dev;
 971
 972         hw->device_id = pci_dev->id.device_id;
 973         hw->vendor_id = pci_dev->id.vendor_id;
 974         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 975
 976         /* initialize the vfta */
 977         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 978
 979         /* initialize the hw strip bitmap*/
 980         memset(hwstrip, 0, sizeof(*hwstrip));
 981
 982         /* Initialize the shared code (base driver) */
 983         diag = ixgbe_init_shared_code(hw);
 984         if (diag != IXGBE_SUCCESS) {
 985                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 986                 return -EIO;
 987         }
 988
 989         /* init_mailbox_params */
 990         hw->mbx.ops.init_params(hw);
 991
 992         /* Disable the interrupts for VF */
 993         ixgbevf_intr_disable(hw);
 994
 995         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
 996         diag = hw->mac.ops.reset_hw(hw);
 997
 998         /*
 999          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1000          * the underlying PF driver has not assigned a MAC address to the VF.
1001          * In this case, assign a random MAC address.
1002          */
1003         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1004                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1005                 return (diag);
1006         }
1007
1008         /* negotiate mailbox API version to use with the PF. */
1009         ixgbevf_negotiate_api(hw);
1010
1011         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1012         ixgbevf_get_queues(hw, &tcs, &tc);
1013
1014         /* Allocate memory for storing MAC addresses */
1015         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1016                         hw->mac.num_rar_entries, 0);
1017         if (eth_dev->data->mac_addrs == NULL) {
1018                 PMD_INIT_LOG(ERR,
1019                         "Failed to allocate %u bytes needed to store "
1020                         "MAC addresses",
1021                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1022                 return -ENOMEM;
1023         }
1024
1025         /* Generate a random MAC address, if none was assigned by PF. */
1026         if (is_zero_ether_addr(perm_addr)) {
1027                 generate_random_mac_addr(perm_addr);
1028                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1029                 if (diag) {
1030                         rte_free(eth_dev->data->mac_addrs);
1031                         eth_dev->data->mac_addrs = NULL;
1032                         return diag;
1033                 }
1034                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1035                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1036                              "%02x:%02x:%02x:%02x:%02x:%02x",
1037                              perm_addr->addr_bytes[0],
1038                              perm_addr->addr_bytes[1],
1039                              perm_addr->addr_bytes[2],
1040                              perm_addr->addr_bytes[3],
1041                              perm_addr->addr_bytes[4],
1042                              perm_addr->addr_bytes[5]);
1043         }
1044
1045         /* Copy the permanent MAC address */
1046         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1047
1048         /* reset the hardware with the new settings */
1049         diag = hw->mac.ops.start_hw(hw);
1050         switch (diag) {
1051                 case  0:
1052                         break;
1053
1054                 default:
1055                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1056                         return (-EIO);
1057         }
1058
1059         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1060                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1061                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1062
1063         return 0;
1064 }
1065
1066 static struct eth_driver rte_ixgbe_pmd = {
1067         {
1068                 .name = "rte_ixgbe_pmd",
1069                 .id_table = pci_id_ixgbe_map,
1070                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1071         },
1072         .eth_dev_init = eth_ixgbe_dev_init,
1073         .dev_private_size = sizeof(struct ixgbe_adapter),
1074 };
1075
1076 /*
1077  * virtual function driver struct
1078  */
1079 static struct eth_driver rte_ixgbevf_pmd = {
1080         {
1081                 .name = "rte_ixgbevf_pmd",
1082                 .id_table = pci_id_ixgbevf_map,
1083                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1084         },
1085         .eth_dev_init = eth_ixgbevf_dev_init,
1086         .dev_private_size = sizeof(struct ixgbe_adapter),
1087 };
1088
1089 /*
1090  * Driver initialization routine.
1091  * Invoked once at EAL init time.
1092  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1093  */
1094 static int
1095 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1096 {
1097         PMD_INIT_FUNC_TRACE();
1098
1099         rte_eth_driver_register(&rte_ixgbe_pmd);
1100         return 0;
1101 }
1102
1103 /*
1104  * VF Driver initialization routine.
1105  * Invoked one at EAL init time.
1106  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1107  */
1108 static int
1109 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1110 {
1111         PMD_INIT_FUNC_TRACE();
1112
1113         rte_eth_driver_register(&rte_ixgbevf_pmd);
1114         return (0);
1115 }
1116
1117 static int
1118 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1119 {
1120         struct ixgbe_hw *hw =
1121                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1122         struct ixgbe_vfta * shadow_vfta =
1123                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1124         uint32_t vfta;
1125         uint32_t vid_idx;
1126         uint32_t vid_bit;
1127
1128         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1129         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1130         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1131         if (on)
1132                 vfta |= vid_bit;
1133         else
1134                 vfta &= ~vid_bit;
1135         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1136
1137         /* update local VFTA copy */
1138         shadow_vfta->vfta[vid_idx] = vfta;
1139
1140         return 0;
1141 }
1142
1143 static void
1144 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1145 {
1146         if (on)
1147                 ixgbe_vlan_hw_strip_enable(dev, queue);
1148         else
1149                 ixgbe_vlan_hw_strip_disable(dev, queue);
1150 }
1151
1152 static void
1153 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1154 {
1155         struct ixgbe_hw *hw =
1156                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1157
1158         /* Only the high 16-bits is valid */
1159         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1160 }
1161
1162 void
1163 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1164 {
1165         struct ixgbe_hw *hw =
1166                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1167         uint32_t vlnctrl;
1168
1169         PMD_INIT_FUNC_TRACE();
1170
1171         /* Filter Table Disable */
1172         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1173         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1174
1175         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1176 }
1177
1178 void
1179 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1180 {
1181         struct ixgbe_hw *hw =
1182                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183         struct ixgbe_vfta * shadow_vfta =
1184                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1185         uint32_t vlnctrl;
1186         uint16_t i;
1187
1188         PMD_INIT_FUNC_TRACE();
1189
1190         /* Filter Table Enable */
1191         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1192         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1193         vlnctrl |= IXGBE_VLNCTRL_VFE;
1194
1195         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1196
1197         /* write whatever is in local vfta copy */
1198         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1199                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1200 }
1201
1202 static void
1203 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1204 {
1205         struct ixgbe_hwstrip *hwstrip =
1206                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1207
1208         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1209                 return;
1210
1211         if (on)
1212                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1213         else
1214                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1215 }
1216
1217 static void
1218 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1219 {
1220         struct ixgbe_hw *hw =
1221                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1222         uint32_t ctrl;
1223
1224         PMD_INIT_FUNC_TRACE();
1225
1226         if (hw->mac.type == ixgbe_mac_82598EB) {
1227                 /* No queue level support */
1228                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1229                 return;
1230         }
1231         else {
1232                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1233                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1234                 ctrl &= ~IXGBE_RXDCTL_VME;
1235                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1236         }
1237         /* record those setting for HW strip per queue */
1238         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1239 }
1240
1241 static void
1242 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1243 {
1244         struct ixgbe_hw *hw =
1245                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246         uint32_t ctrl;
1247
1248         PMD_INIT_FUNC_TRACE();
1249
1250         if (hw->mac.type == ixgbe_mac_82598EB) {
1251                 /* No queue level supported */
1252                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1253                 return;
1254         }
1255         else {
1256                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1257                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1258                 ctrl |= IXGBE_RXDCTL_VME;
1259                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1260         }
1261         /* record those setting for HW strip per queue */
1262         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1263 }
1264
1265 void
1266 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1267 {
1268         struct ixgbe_hw *hw =
1269                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1270         uint32_t ctrl;
1271         uint16_t i;
1272
1273         PMD_INIT_FUNC_TRACE();
1274
1275         if (hw->mac.type == ixgbe_mac_82598EB) {
1276                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1277                 ctrl &= ~IXGBE_VLNCTRL_VME;
1278                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1279         }
1280         else {
1281                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1282                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1283                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1284                         ctrl &= ~IXGBE_RXDCTL_VME;
1285                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1286
1287                         /* record those setting for HW strip per queue */
1288                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1289                 }
1290         }
1291 }
1292
1293 void
1294 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1295 {
1296         struct ixgbe_hw *hw =
1297                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1298         uint32_t ctrl;
1299         uint16_t i;
1300
1301         PMD_INIT_FUNC_TRACE();
1302
1303         if (hw->mac.type == ixgbe_mac_82598EB) {
1304                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1305                 ctrl |= IXGBE_VLNCTRL_VME;
1306                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1307         }
1308         else {
1309                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1310                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1311                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1312                         ctrl |= IXGBE_RXDCTL_VME;
1313                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1314
1315                         /* record those setting for HW strip per queue */
1316                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1317                 }
1318         }
1319 }
1320
1321 static void
1322 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1323 {
1324         struct ixgbe_hw *hw =
1325                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         uint32_t ctrl;
1327
1328         PMD_INIT_FUNC_TRACE();
1329
1330         /* DMATXCTRL: Geric Double VLAN Disable */
1331         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1332         ctrl &= ~IXGBE_DMATXCTL_GDV;
1333         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1334
1335         /* CTRL_EXT: Global Double VLAN Disable */
1336         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1337         ctrl &= ~IXGBE_EXTENDED_VLAN;
1338         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1339
1340 }
1341
1342 static void
1343 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1344 {
1345         struct ixgbe_hw *hw =
1346                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347         uint32_t ctrl;
1348
1349         PMD_INIT_FUNC_TRACE();
1350
1351         /* DMATXCTRL: Geric Double VLAN Enable */
1352         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1353         ctrl |= IXGBE_DMATXCTL_GDV;
1354         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1355
1356         /* CTRL_EXT: Global Double VLAN Enable */
1357         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1358         ctrl |= IXGBE_EXTENDED_VLAN;
1359         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1360
1361         /*
1362          * VET EXT field in the EXVET register = 0x8100 by default
1363          * So no need to change. Same to VT field of DMATXCTL register
1364          */
1365 }
1366
1367 static void
1368 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1369 {
1370         if(mask & ETH_VLAN_STRIP_MASK){
1371                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1372                         ixgbe_vlan_hw_strip_enable_all(dev);
1373                 else
1374                         ixgbe_vlan_hw_strip_disable_all(dev);
1375         }
1376
1377         if(mask & ETH_VLAN_FILTER_MASK){
1378                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1379                         ixgbe_vlan_hw_filter_enable(dev);
1380                 else
1381                         ixgbe_vlan_hw_filter_disable(dev);
1382         }
1383
1384         if(mask & ETH_VLAN_EXTEND_MASK){
1385                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1386                         ixgbe_vlan_hw_extend_enable(dev);
1387                 else
1388                         ixgbe_vlan_hw_extend_disable(dev);
1389         }
1390 }
1391
1392 static void
1393 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1394 {
1395         struct ixgbe_hw *hw =
1396                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1398         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1399         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1400         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1401 }
1402
1403 static int
1404 ixgbe_dev_configure(struct rte_eth_dev *dev)
1405 {
1406         struct ixgbe_interrupt *intr =
1407                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1408
1409         PMD_INIT_FUNC_TRACE();
1410
1411         /* set flag to update link status after init */
1412         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1413
1414         return 0;
1415 }
1416
1417 /*
1418  * Configure device link speed and setup link.
1419  * It returns 0 on success.
1420  */
1421 static int
1422 ixgbe_dev_start(struct rte_eth_dev *dev)
1423 {
1424         struct ixgbe_hw *hw =
1425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         struct ixgbe_vf_info *vfinfo =
1427                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1428         int err, link_up = 0, negotiate = 0;
1429         uint32_t speed = 0;
1430         int mask = 0;
1431         int status;
1432         uint16_t vf, idx;
1433
1434         PMD_INIT_FUNC_TRACE();
1435
1436         /* IXGBE devices don't support half duplex */
1437         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1438                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1439                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1440                              dev->data->dev_conf.link_duplex,
1441                              dev->data->port_id);
1442                 return -EINVAL;
1443         }
1444
1445         /* stop adapter */
1446         hw->adapter_stopped = FALSE;
1447         ixgbe_stop_adapter(hw);
1448
1449         /* reinitialize adapter
1450          * this calls reset and start */
1451         status = ixgbe_pf_reset_hw(hw);
1452         if (status != 0)
1453                 return -1;
1454         hw->mac.ops.start_hw(hw);
1455
1456         /* configure PF module if SRIOV enabled */
1457         ixgbe_pf_host_configure(dev);
1458
1459         /* initialize transmission unit */
1460         ixgbe_dev_tx_init(dev);
1461
1462         /* This can fail when allocating mbufs for descriptor rings */
1463         err = ixgbe_dev_rx_init(dev);
1464         if (err) {
1465                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1466                 goto error;
1467         }
1468
1469         ixgbe_dev_rxtx_start(dev);
1470
1471         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1472                 err = hw->mac.ops.setup_sfp(hw);
1473                 if (err)
1474                         goto error;
1475         }
1476
1477         /* Turn on the laser */
1478         ixgbe_enable_tx_laser(hw);
1479
1480         /* Skip link setup if loopback mode is enabled for 82599. */
1481         if (hw->mac.type == ixgbe_mac_82599EB &&
1482                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1483                 goto skip_link_setup;
1484
1485         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1486         if (err)
1487                 goto error;
1488         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1489         if (err)
1490                 goto error;
1491
1492         switch(dev->data->dev_conf.link_speed) {
1493         case ETH_LINK_SPEED_AUTONEG:
1494                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1495                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1496                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1497                 break;
1498         case ETH_LINK_SPEED_100:
1499                 /*
1500                  * Invalid for 82598 but error will be detected by
1501                  * ixgbe_setup_link()
1502                  */
1503                 speed = IXGBE_LINK_SPEED_100_FULL;
1504                 break;
1505         case ETH_LINK_SPEED_1000:
1506                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1507                 break;
1508         case ETH_LINK_SPEED_10000:
1509                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1510                 break;
1511         default:
1512                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1513                              dev->data->dev_conf.link_speed,
1514                              dev->data->port_id);
1515                 goto error;
1516         }
1517
1518         err = ixgbe_setup_link(hw, speed, link_up);
1519         if (err)
1520                 goto error;
1521
1522 skip_link_setup:
1523
1524         /* check if lsc interrupt is enabled */
1525         if (dev->data->dev_conf.intr_conf.lsc != 0)
1526                 ixgbe_dev_lsc_interrupt_setup(dev);
1527
1528         /* resume enabled intr since hw reset */
1529         ixgbe_enable_intr(dev);
1530
1531         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1532                 ETH_VLAN_EXTEND_MASK;
1533         ixgbe_vlan_offload_set(dev, mask);
1534
1535         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1536                 /* Enable vlan filtering for VMDq */
1537                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1538         }
1539
1540         /* Configure DCB hw */
1541         ixgbe_configure_dcb(dev);
1542
1543         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1544                 err = ixgbe_fdir_configure(dev);
1545                 if (err)
1546                         goto error;
1547         }
1548
1549         /* Restore vf rate limit */
1550         if (vfinfo != NULL) {
1551                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1552                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1553                                 if (vfinfo[vf].tx_rate[idx] != 0)
1554                                         ixgbe_set_vf_rate_limit(dev, vf,
1555                                                 vfinfo[vf].tx_rate[idx],
1556                                                 1 << idx);
1557         }
1558
1559         ixgbe_restore_statistics_mapping(dev);
1560
1561         return (0);
1562
1563 error:
1564         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1565         ixgbe_dev_clear_queues(dev);
1566         return -EIO;
1567 }
1568
1569 /*
1570  * Stop device: disable rx and tx functions to allow for reconfiguring.
1571  */
1572 static void
1573 ixgbe_dev_stop(struct rte_eth_dev *dev)
1574 {
1575         struct rte_eth_link link;
1576         struct ixgbe_hw *hw =
1577                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578         struct ixgbe_vf_info *vfinfo =
1579                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1580         int vf;
1581
1582         PMD_INIT_FUNC_TRACE();
1583
1584         /* disable interrupts */
1585         ixgbe_disable_intr(hw);
1586
1587         /* reset the NIC */
1588         ixgbe_pf_reset_hw(hw);
1589         hw->adapter_stopped = FALSE;
1590
1591         /* stop adapter */
1592         ixgbe_stop_adapter(hw);
1593
1594         for (vf = 0; vfinfo != NULL &&
1595                      vf < dev->pci_dev->max_vfs; vf++)
1596                 vfinfo[vf].clear_to_send = false;
1597
1598         /* Turn off the laser */
1599         ixgbe_disable_tx_laser(hw);
1600
1601         ixgbe_dev_clear_queues(dev);
1602
1603         /* Clear stored conf */
1604         dev->data->scattered_rx = 0;
1605
1606         /* Clear recorded link status */
1607         memset(&link, 0, sizeof(link));
1608         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1609 }
1610
1611 /*
1612  * Set device link up: enable tx laser.
1613  */
1614 static int
1615 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1616 {
1617         struct ixgbe_hw *hw =
1618                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619         if (hw->mac.type == ixgbe_mac_82599EB) {
1620 #ifdef RTE_NIC_BYPASS
1621                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1622                         /* Not suported in bypass mode */
1623                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1624                                      "by device id 0x%x", hw->device_id);
1625                         return -ENOTSUP;
1626                 }
1627 #endif
1628                 /* Turn on the laser */
1629                 ixgbe_enable_tx_laser(hw);
1630                 return 0;
1631         }
1632
1633         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1634                      hw->device_id);
1635         return -ENOTSUP;
1636 }
1637
1638 /*
1639  * Set device link down: disable tx laser.
1640  */
1641 static int
1642 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1643 {
1644         struct ixgbe_hw *hw =
1645                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646         if (hw->mac.type == ixgbe_mac_82599EB) {
1647 #ifdef RTE_NIC_BYPASS
1648                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1649                         /* Not suported in bypass mode */
1650                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1651                                      "by device id 0x%x", hw->device_id);
1652                         return -ENOTSUP;
1653                 }
1654 #endif
1655                 /* Turn off the laser */
1656                 ixgbe_disable_tx_laser(hw);
1657                 return 0;
1658         }
1659
1660         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1661                      hw->device_id);
1662         return -ENOTSUP;
1663 }
1664
1665 /*
1666  * Reest and stop device.
1667  */
1668 static void
1669 ixgbe_dev_close(struct rte_eth_dev *dev)
1670 {
1671         struct ixgbe_hw *hw =
1672                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673
1674         PMD_INIT_FUNC_TRACE();
1675
1676         ixgbe_pf_reset_hw(hw);
1677
1678         ixgbe_dev_stop(dev);
1679         hw->adapter_stopped = 1;
1680
1681         ixgbe_disable_pcie_master(hw);
1682
1683         /* reprogram the RAR[0] in case user changed it. */
1684         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1685 }
1686
1687 /*
1688  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1689  */
1690 static void
1691 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1692 {
1693         struct ixgbe_hw *hw =
1694                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695         struct ixgbe_hw_stats *hw_stats =
1696                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1697         uint32_t bprc, lxon, lxoff, total;
1698         uint64_t total_missed_rx, total_qbrc, total_qprc;
1699         unsigned i;
1700
1701         total_missed_rx = 0;
1702         total_qbrc = 0;
1703         total_qprc = 0;
1704
1705         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1706         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1707         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1708         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1709
1710         for (i = 0; i < 8; i++) {
1711                 uint32_t mp;
1712                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1713                 /* global total per queue */
1714                 hw_stats->mpc[i] += mp;
1715                 /* Running comprehensive total for stats display */
1716                 total_missed_rx += hw_stats->mpc[i];
1717                 if (hw->mac.type == ixgbe_mac_82598EB)
1718                         hw_stats->rnbc[i] +=
1719                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1720                 hw_stats->pxontxc[i] +=
1721                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1722                 hw_stats->pxonrxc[i] +=
1723                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1724                 hw_stats->pxofftxc[i] +=
1725                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1726                 hw_stats->pxoffrxc[i] +=
1727                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1728                 hw_stats->pxon2offc[i] +=
1729                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1730         }
1731         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1732                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1733                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1734                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1735                 hw_stats->qbrc[i] +=
1736                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1737                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1738                 hw_stats->qbtc[i] +=
1739                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1740                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1741
1742                 total_qprc += hw_stats->qprc[i];
1743                 total_qbrc += hw_stats->qbrc[i];
1744         }
1745         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1746         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1747         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1748
1749         /* Note that gprc counts missed packets */
1750         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1751
1752         if (hw->mac.type != ixgbe_mac_82598EB) {
1753                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1754                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1755                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1756                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1757                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1758                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1759                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1760                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1761         } else {
1762                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1763                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1764                 /* 82598 only has a counter in the high register */
1765                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1766                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1767                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1768         }
1769
1770         /*
1771          * Workaround: mprc hardware is incorrectly counting
1772          * broadcasts, so for now we subtract those.
1773          */
1774         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1775         hw_stats->bprc += bprc;
1776         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1777         if (hw->mac.type == ixgbe_mac_82598EB)
1778                 hw_stats->mprc -= bprc;
1779
1780         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1781         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1782         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1783         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1784         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1785         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1786
1787         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1788         hw_stats->lxontxc += lxon;
1789         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1790         hw_stats->lxofftxc += lxoff;
1791         total = lxon + lxoff;
1792
1793         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1794         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1795         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1796         hw_stats->gptc -= total;
1797         hw_stats->mptc -= total;
1798         hw_stats->ptc64 -= total;
1799         hw_stats->gotc -= total * ETHER_MIN_LEN;
1800
1801         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1802         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1803         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1804         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1805         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1806         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1807         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1808         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1809         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1810         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1811         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1812         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1813         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1814         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1815         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1816         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1817         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1818         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1819         /* Only read FCOE on 82599 */
1820         if (hw->mac.type != ixgbe_mac_82598EB) {
1821                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1822                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1823                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1824                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1825                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1826         }
1827
1828         if (stats == NULL)
1829                 return;
1830
1831         /* Fill out the rte_eth_stats statistics structure */
1832         stats->ipackets = total_qprc;
1833         stats->ibytes = total_qbrc;
1834         stats->opackets = hw_stats->gptc;
1835         stats->obytes = hw_stats->gotc;
1836         stats->imcasts = hw_stats->mprc;
1837
1838         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1839                 stats->q_ipackets[i] = hw_stats->qprc[i];
1840                 stats->q_opackets[i] = hw_stats->qptc[i];
1841                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1842                 stats->q_obytes[i] = hw_stats->qbtc[i];
1843                 stats->q_errors[i] = hw_stats->qprdc[i];
1844         }
1845
1846         /* Rx Errors */
1847         stats->ibadcrc  = hw_stats->crcerrs;
1848         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1849         stats->imissed  = total_missed_rx;
1850         stats->ierrors  = stats->ibadcrc +
1851                           stats->ibadlen +
1852                           stats->imissed +
1853                           hw_stats->illerrc + hw_stats->errbc;
1854
1855         /* Tx Errors */
1856         stats->oerrors  = 0;
1857
1858         /* XON/XOFF pause frames */
1859         stats->tx_pause_xon  = hw_stats->lxontxc;
1860         stats->rx_pause_xon  = hw_stats->lxonrxc;
1861         stats->tx_pause_xoff = hw_stats->lxofftxc;
1862         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1863
1864         /* Flow Director Stats registers */
1865         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1866         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1867         stats->fdirmatch = hw_stats->fdirmatch;
1868         stats->fdirmiss = hw_stats->fdirmiss;
1869 }
1870
1871 static void
1872 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1873 {
1874         struct ixgbe_hw_stats *stats =
1875                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1876
1877         /* HW registers are cleared on read */
1878         ixgbe_dev_stats_get(dev, NULL);
1879
1880         /* Reset software totals */
1881         memset(stats, 0, sizeof(*stats));
1882 }
1883
1884 static void
1885 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1886 {
1887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1888         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1889                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1890
1891         /* Good Rx packet, include VF loopback */
1892         UPDATE_VF_STAT(IXGBE_VFGPRC,
1893             hw_stats->last_vfgprc, hw_stats->vfgprc);
1894
1895         /* Good Rx octets, include VF loopback */
1896         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1897             hw_stats->last_vfgorc, hw_stats->vfgorc);
1898
1899         /* Good Tx packet, include VF loopback */
1900         UPDATE_VF_STAT(IXGBE_VFGPTC,
1901             hw_stats->last_vfgptc, hw_stats->vfgptc);
1902
1903         /* Good Tx octets, include VF loopback */
1904         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1905             hw_stats->last_vfgotc, hw_stats->vfgotc);
1906
1907         /* Rx Multicst Packet */
1908         UPDATE_VF_STAT(IXGBE_VFMPRC,
1909             hw_stats->last_vfmprc, hw_stats->vfmprc);
1910
1911         if (stats == NULL)
1912                 return;
1913
1914         memset(stats, 0, sizeof(*stats));
1915         stats->ipackets = hw_stats->vfgprc;
1916         stats->ibytes = hw_stats->vfgorc;
1917         stats->opackets = hw_stats->vfgptc;
1918         stats->obytes = hw_stats->vfgotc;
1919         stats->imcasts = hw_stats->vfmprc;
1920 }
1921
1922 static void
1923 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1924 {
1925         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1926                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1927
1928         /* Sync HW register to the last stats */
1929         ixgbevf_dev_stats_get(dev, NULL);
1930
1931         /* reset HW current stats*/
1932         hw_stats->vfgprc = 0;
1933         hw_stats->vfgorc = 0;
1934         hw_stats->vfgptc = 0;
1935         hw_stats->vfgotc = 0;
1936         hw_stats->vfmprc = 0;
1937
1938 }
1939
1940 static void
1941 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1942 {
1943         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944
1945         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1946         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1947         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1948         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1949         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1950         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1951         dev_info->max_vfs = dev->pci_dev->max_vfs;
1952         if (hw->mac.type == ixgbe_mac_82598EB)
1953                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1954         else
1955                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1956         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1957         dev_info->rx_offload_capa =
1958                 DEV_RX_OFFLOAD_VLAN_STRIP |
1959                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1960                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1961                 DEV_RX_OFFLOAD_TCP_CKSUM;
1962         dev_info->tx_offload_capa =
1963                 DEV_TX_OFFLOAD_VLAN_INSERT |
1964                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1965                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1966                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1967                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1968
1969         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1970                         .rx_thresh = {
1971                                 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
1972                                 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
1973                                 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
1974                         },
1975                         .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
1976                         .rx_drop_en = 0,
1977         };
1978
1979
1980          dev_info->default_txconf = (struct rte_eth_txconf) {
1981                         .tx_thresh = {
1982                                 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
1983                                 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
1984                                 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
1985                         },
1986                         .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
1987                         .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
1988                         .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1989         };
1990 }
1991
1992 /* return 0 means link status changed, -1 means not changed */
1993 static int
1994 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1995 {
1996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997         struct rte_eth_link link, old;
1998         ixgbe_link_speed link_speed;
1999         int link_up;
2000         int diag;
2001
2002         link.link_status = 0;
2003         link.link_speed = 0;
2004         link.link_duplex = 0;
2005         memset(&old, 0, sizeof(old));
2006         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2007
2008         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2009         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2010                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2011         else
2012                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2013         if (diag != 0) {
2014                 link.link_speed = ETH_LINK_SPEED_100;
2015                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2016                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2017                 if (link.link_status == old.link_status)
2018                         return -1;
2019                 return 0;
2020         }
2021
2022         if (link_up == 0) {
2023                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2024                 if (link.link_status == old.link_status)
2025                         return -1;
2026                 return 0;
2027         }
2028         link.link_status = 1;
2029         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2030
2031         switch (link_speed) {
2032         default:
2033         case IXGBE_LINK_SPEED_UNKNOWN:
2034                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2035                 link.link_speed = ETH_LINK_SPEED_100;
2036                 break;
2037
2038         case IXGBE_LINK_SPEED_100_FULL:
2039                 link.link_speed = ETH_LINK_SPEED_100;
2040                 break;
2041
2042         case IXGBE_LINK_SPEED_1GB_FULL:
2043                 link.link_speed = ETH_LINK_SPEED_1000;
2044                 break;
2045
2046         case IXGBE_LINK_SPEED_10GB_FULL:
2047                 link.link_speed = ETH_LINK_SPEED_10000;
2048                 break;
2049         }
2050         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2051
2052         if (link.link_status == old.link_status)
2053                 return -1;
2054
2055         return 0;
2056 }
2057
2058 static void
2059 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2060 {
2061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         uint32_t fctrl;
2063
2064         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2065         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2066         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2067 }
2068
2069 static void
2070 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2071 {
2072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073         uint32_t fctrl;
2074
2075         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2076         fctrl &= (~IXGBE_FCTRL_UPE);
2077         if (dev->data->all_multicast == 1)
2078                 fctrl |= IXGBE_FCTRL_MPE;
2079         else
2080                 fctrl &= (~IXGBE_FCTRL_MPE);
2081         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2082 }
2083
2084 static void
2085 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2086 {
2087         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         uint32_t fctrl;
2089
2090         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2091         fctrl |= IXGBE_FCTRL_MPE;
2092         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2093 }
2094
2095 static void
2096 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2097 {
2098         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         uint32_t fctrl;
2100
2101         if (dev->data->promiscuous == 1)
2102                 return; /* must remain in all_multicast mode */
2103
2104         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2105         fctrl &= (~IXGBE_FCTRL_MPE);
2106         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2107 }
2108
2109 /**
2110  * It clears the interrupt causes and enables the interrupt.
2111  * It will be called once only during nic initialized.
2112  *
2113  * @param dev
2114  *  Pointer to struct rte_eth_dev.
2115  *
2116  * @return
2117  *  - On success, zero.
2118  *  - On failure, a negative value.
2119  */
2120 static int
2121 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2122 {
2123         struct ixgbe_interrupt *intr =
2124                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2125
2126         ixgbe_dev_link_status_print(dev);
2127         intr->mask |= IXGBE_EICR_LSC;
2128
2129         return 0;
2130 }
2131
2132 /*
2133  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2134  *
2135  * @param dev
2136  *  Pointer to struct rte_eth_dev.
2137  *
2138  * @return
2139  *  - On success, zero.
2140  *  - On failure, a negative value.
2141  */
2142 static int
2143 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2144 {
2145         uint32_t eicr;
2146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2147         struct ixgbe_interrupt *intr =
2148                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2149
2150         /* clear all cause mask */
2151         ixgbe_disable_intr(hw);
2152
2153         /* read-on-clear nic registers here */
2154         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2155         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2156
2157         intr->flags = 0;
2158         if (eicr & IXGBE_EICR_LSC) {
2159                 /* set flag for async link update */
2160                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2161         }
2162
2163         if (eicr & IXGBE_EICR_MAILBOX)
2164                 intr->flags |= IXGBE_FLAG_MAILBOX;
2165
2166         return 0;
2167 }
2168
2169 /**
2170  * It gets and then prints the link status.
2171  *
2172  * @param dev
2173  *  Pointer to struct rte_eth_dev.
2174  *
2175  * @return
2176  *  - On success, zero.
2177  *  - On failure, a negative value.
2178  */
2179 static void
2180 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2181 {
2182         struct rte_eth_link link;
2183
2184         memset(&link, 0, sizeof(link));
2185         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2186         if (link.link_status) {
2187                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2188                                         (int)(dev->data->port_id),
2189                                         (unsigned)link.link_speed,
2190                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2191                                         "full-duplex" : "half-duplex");
2192         } else {
2193                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2194                                 (int)(dev->data->port_id));
2195         }
2196         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2197                                 dev->pci_dev->addr.domain,
2198                                 dev->pci_dev->addr.bus,
2199                                 dev->pci_dev->addr.devid,
2200                                 dev->pci_dev->addr.function);
2201 }
2202
2203 /*
2204  * It executes link_update after knowing an interrupt occurred.
2205  *
2206  * @param dev
2207  *  Pointer to struct rte_eth_dev.
2208  *
2209  * @return
2210  *  - On success, zero.
2211  *  - On failure, a negative value.
2212  */
2213 static int
2214 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2215 {
2216         struct ixgbe_interrupt *intr =
2217                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2218         int64_t timeout;
2219         struct rte_eth_link link;
2220         int intr_enable_delay = false;
2221
2222         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2223
2224         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2225                 ixgbe_pf_mbx_process(dev);
2226                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2227         }
2228
2229         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2230                 /* get the link status before link update, for predicting later */
2231                 memset(&link, 0, sizeof(link));
2232                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2233
2234                 ixgbe_dev_link_update(dev, 0);
2235
2236                 /* likely to up */
2237                 if (!link.link_status)
2238                         /* handle it 1 sec later, wait it being stable */
2239                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2240                 /* likely to down */
2241                 else
2242                         /* handle it 4 sec later, wait it being stable */
2243                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2244
2245                 ixgbe_dev_link_status_print(dev);
2246
2247                 intr_enable_delay = true;
2248         }
2249
2250         if (intr_enable_delay) {
2251                 if (rte_eal_alarm_set(timeout * 1000,
2252                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2253                         PMD_DRV_LOG(ERR, "Error setting alarm");
2254         } else {
2255                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2256                 ixgbe_enable_intr(dev);
2257                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2258         }
2259
2260
2261         return 0;
2262 }
2263
2264 /**
2265  * Interrupt handler which shall be registered for alarm callback for delayed
2266  * handling specific interrupt to wait for the stable nic state. As the
2267  * NIC interrupt state is not stable for ixgbe after link is just down,
2268  * it needs to wait 4 seconds to get the stable status.
2269  *
2270  * @param handle
2271  *  Pointer to interrupt handle.
2272  * @param param
2273  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2274  *
2275  * @return
2276  *  void
2277  */
2278 static void
2279 ixgbe_dev_interrupt_delayed_handler(void *param)
2280 {
2281         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2282         struct ixgbe_interrupt *intr =
2283                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2284         struct ixgbe_hw *hw =
2285                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2286         uint32_t eicr;
2287
2288         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2289         if (eicr & IXGBE_EICR_MAILBOX)
2290                 ixgbe_pf_mbx_process(dev);
2291
2292         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2293                 ixgbe_dev_link_update(dev, 0);
2294                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2295                 ixgbe_dev_link_status_print(dev);
2296                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2297         }
2298
2299         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2300         ixgbe_enable_intr(dev);
2301         rte_intr_enable(&(dev->pci_dev->intr_handle));
2302 }
2303
2304 /**
2305  * Interrupt handler triggered by NIC  for handling
2306  * specific interrupt.
2307  *
2308  * @param handle
2309  *  Pointer to interrupt handle.
2310  * @param param
2311  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2312  *
2313  * @return
2314  *  void
2315  */
2316 static void
2317 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2318                                                         void *param)
2319 {
2320         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2321         ixgbe_dev_interrupt_get_status(dev);
2322         ixgbe_dev_interrupt_action(dev);
2323 }
2324
2325 static int
2326 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2327 {
2328         struct ixgbe_hw *hw;
2329
2330         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2332 }
2333
2334 static int
2335 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2336 {
2337         struct ixgbe_hw *hw;
2338
2339         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2341 }
2342
2343 static int
2344 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2345 {
2346         struct ixgbe_hw *hw;
2347         uint32_t mflcn_reg;
2348         uint32_t fccfg_reg;
2349         int rx_pause;
2350         int tx_pause;
2351
2352         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2353
2354         fc_conf->pause_time = hw->fc.pause_time;
2355         fc_conf->high_water = hw->fc.high_water[0];
2356         fc_conf->low_water = hw->fc.low_water[0];
2357         fc_conf->send_xon = hw->fc.send_xon;
2358         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2359
2360         /*
2361          * Return rx_pause status according to actual setting of
2362          * MFLCN register.
2363          */
2364         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2365         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2366                 rx_pause = 1;
2367         else
2368                 rx_pause = 0;
2369
2370         /*
2371          * Return tx_pause status according to actual setting of
2372          * FCCFG register.
2373          */
2374         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2375         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2376                 tx_pause = 1;
2377         else
2378                 tx_pause = 0;
2379
2380         if (rx_pause && tx_pause)
2381                 fc_conf->mode = RTE_FC_FULL;
2382         else if (rx_pause)
2383                 fc_conf->mode = RTE_FC_RX_PAUSE;
2384         else if (tx_pause)
2385                 fc_conf->mode = RTE_FC_TX_PAUSE;
2386         else
2387                 fc_conf->mode = RTE_FC_NONE;
2388
2389         return 0;
2390 }
2391
2392 static int
2393 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2394 {
2395         struct ixgbe_hw *hw;
2396         int err;
2397         uint32_t rx_buf_size;
2398         uint32_t max_high_water;
2399         uint32_t mflcn;
2400         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2401                 ixgbe_fc_none,
2402                 ixgbe_fc_rx_pause,
2403                 ixgbe_fc_tx_pause,
2404                 ixgbe_fc_full
2405         };
2406
2407         PMD_INIT_FUNC_TRACE();
2408
2409         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2410         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2411                 return -ENOTSUP;
2412         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2413         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2414
2415         /*
2416          * At least reserve one Ethernet frame for watermark
2417          * high_water/low_water in kilo bytes for ixgbe
2418          */
2419         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2420         if ((fc_conf->high_water > max_high_water) ||
2421                 (fc_conf->high_water < fc_conf->low_water)) {
2422                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2423                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2424                 return (-EINVAL);
2425         }
2426
2427         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2428         hw->fc.pause_time     = fc_conf->pause_time;
2429         hw->fc.high_water[0]  = fc_conf->high_water;
2430         hw->fc.low_water[0]   = fc_conf->low_water;
2431         hw->fc.send_xon       = fc_conf->send_xon;
2432
2433         err = ixgbe_fc_enable(hw);
2434
2435         /* Not negotiated is not an error case */
2436         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2437
2438                 /* check if we want to forward MAC frames - driver doesn't have native
2439                  * capability to do that, so we'll write the registers ourselves */
2440
2441                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2442
2443                 /* set or clear MFLCN.PMCF bit depending on configuration */
2444                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2445                         mflcn |= IXGBE_MFLCN_PMCF;
2446                 else
2447                         mflcn &= ~IXGBE_MFLCN_PMCF;
2448
2449                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2450                 IXGBE_WRITE_FLUSH(hw);
2451
2452                 return 0;
2453         }
2454
2455         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2456         return -EIO;
2457 }
2458
2459 /**
2460  *  ixgbe_pfc_enable_generic - Enable flow control
2461  *  @hw: pointer to hardware structure
2462  *  @tc_num: traffic class number
2463  *  Enable flow control according to the current settings.
2464  */
2465 static int
2466 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2467 {
2468         int ret_val = 0;
2469         uint32_t mflcn_reg, fccfg_reg;
2470         uint32_t reg;
2471         uint32_t fcrtl, fcrth;
2472         uint8_t i;
2473         uint8_t nb_rx_en;
2474
2475         /* Validate the water mark configuration */
2476         if (!hw->fc.pause_time) {
2477                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2478                 goto out;
2479         }
2480
2481         /* Low water mark of zero causes XOFF floods */
2482         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2483                  /* High/Low water can not be 0 */
2484                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2485                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2486                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2487                         goto out;
2488                 }
2489
2490                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2491                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2492                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2493                         goto out;
2494                 }
2495         }
2496         /* Negotiate the fc mode to use */
2497         ixgbe_fc_autoneg(hw);
2498
2499         /* Disable any previous flow control settings */
2500         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2501         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2502
2503         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2504         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2505
2506         switch (hw->fc.current_mode) {
2507         case ixgbe_fc_none:
2508                 /*
2509                  * If the count of enabled RX Priority Flow control >1,
2510                  * and the TX pause can not be disabled
2511                  */
2512                 nb_rx_en = 0;
2513                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2514                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2515                         if (reg & IXGBE_FCRTH_FCEN)
2516                                 nb_rx_en++;
2517                 }
2518                 if (nb_rx_en > 1)
2519                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2520                 break;
2521         case ixgbe_fc_rx_pause:
2522                 /*
2523                  * Rx Flow control is enabled and Tx Flow control is
2524                  * disabled by software override. Since there really
2525                  * isn't a way to advertise that we are capable of RX
2526                  * Pause ONLY, we will advertise that we support both
2527                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2528                  * disable the adapter's ability to send PAUSE frames.
2529                  */
2530                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2531                 /*
2532                  * If the count of enabled RX Priority Flow control >1,
2533                  * and the TX pause can not be disabled
2534                  */
2535                 nb_rx_en = 0;
2536                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2537                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2538                         if (reg & IXGBE_FCRTH_FCEN)
2539                                 nb_rx_en++;
2540                 }
2541                 if (nb_rx_en > 1)
2542                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2543                 break;
2544         case ixgbe_fc_tx_pause:
2545                 /*
2546                  * Tx Flow control is enabled, and Rx Flow control is
2547                  * disabled by software override.
2548                  */
2549                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2550                 break;
2551         case ixgbe_fc_full:
2552                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2553                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2554                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2555                 break;
2556         default:
2557                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2558                 ret_val = IXGBE_ERR_CONFIG;
2559                 goto out;
2560                 break;
2561         }
2562
2563         /* Set 802.3x based flow control settings. */
2564         mflcn_reg |= IXGBE_MFLCN_DPF;
2565         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2566         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2567
2568         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2569         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2570                 hw->fc.high_water[tc_num]) {
2571                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2572                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2573                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2574         } else {
2575                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2576                 /*
2577                  * In order to prevent Tx hangs when the internal Tx
2578                  * switch is enabled we must set the high water mark
2579                  * to the maximum FCRTH value.  This allows the Tx
2580                  * switch to function even under heavy Rx workloads.
2581                  */
2582                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2583         }
2584         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2585
2586         /* Configure pause time (2 TCs per register) */
2587         reg = hw->fc.pause_time * 0x00010001;
2588         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2589                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2590
2591         /* Configure flow control refresh threshold value */
2592         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2593
2594 out:
2595         return ret_val;
2596 }
2597
2598 static int
2599 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2600 {
2601         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2602         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2603
2604         if(hw->mac.type != ixgbe_mac_82598EB) {
2605                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2606         }
2607         return ret_val;
2608 }
2609
2610 static int
2611 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2612 {
2613         int err;
2614         uint32_t rx_buf_size;
2615         uint32_t max_high_water;
2616         uint8_t tc_num;
2617         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2618         struct ixgbe_hw *hw =
2619                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2620         struct ixgbe_dcb_config *dcb_config =
2621                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2622
2623         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2624                 ixgbe_fc_none,
2625                 ixgbe_fc_rx_pause,
2626                 ixgbe_fc_tx_pause,
2627                 ixgbe_fc_full
2628         };
2629
2630         PMD_INIT_FUNC_TRACE();
2631
2632         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2633         tc_num = map[pfc_conf->priority];
2634         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2635         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2636         /*
2637          * At least reserve one Ethernet frame for watermark
2638          * high_water/low_water in kilo bytes for ixgbe
2639          */
2640         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2641         if ((pfc_conf->fc.high_water > max_high_water) ||
2642             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2643                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2644                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2645                 return (-EINVAL);
2646         }
2647
2648         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2649         hw->fc.pause_time = pfc_conf->fc.pause_time;
2650         hw->fc.send_xon = pfc_conf->fc.send_xon;
2651         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2652         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2653
2654         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2655
2656         /* Not negotiated is not an error case */
2657         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2658                 return 0;
2659
2660         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2661         return -EIO;
2662 }
2663
2664 static int
2665 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2666                                 struct rte_eth_rss_reta *reta_conf)
2667 {
2668         uint8_t i,j,mask;
2669         uint32_t reta;
2670         struct ixgbe_hw *hw =
2671                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2672
2673         PMD_INIT_FUNC_TRACE();
2674         /*
2675         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2676         * 128-entries in 32 registers
2677          */
2678         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2679                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2680                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2681                 else
2682                         mask = (uint8_t)((reta_conf->mask_hi >>
2683                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2684                 if (mask != 0) {
2685                         reta = 0;
2686                         if (mask != 0xF)
2687                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2688
2689                         for (j = 0; j < 4; j++) {
2690                                 if (mask & (0x1 << j)) {
2691                                         if (mask != 0xF)
2692                                                 reta &= ~(0xFF << 8 * j);
2693                                         reta |= reta_conf->reta[i + j] << 8*j;
2694                                 }
2695                         }
2696                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2697                 }
2698         }
2699
2700         return 0;
2701 }
2702
2703 static int
2704 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2705                                 struct rte_eth_rss_reta *reta_conf)
2706 {
2707         uint8_t i,j,mask;
2708         uint32_t reta;
2709         struct ixgbe_hw *hw =
2710                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2711
2712         PMD_INIT_FUNC_TRACE();
2713         /*
2714          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2715          * 128-entries in 32 registers
2716          */
2717         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2718                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2719                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2720                 else
2721                         mask = (uint8_t)((reta_conf->mask_hi >>
2722                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2723
2724                 if (mask != 0) {
2725                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2726                         for (j = 0; j < 4; j++) {
2727                                 if (mask & (0x1 << j))
2728                                         reta_conf->reta[i + j] =
2729                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2730                         }
2731                 }
2732         }
2733
2734         return 0;
2735 }
2736
2737 static void
2738 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2739                                 uint32_t index, uint32_t pool)
2740 {
2741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2742         uint32_t enable_addr = 1;
2743
2744         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2745 }
2746
2747 static void
2748 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2749 {
2750         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2751
2752         ixgbe_clear_rar(hw, index);
2753 }
2754
2755 static int
2756 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2757 {
2758         uint32_t hlreg0;
2759         uint32_t maxfrs;
2760         struct ixgbe_hw *hw;
2761         struct rte_eth_dev_info dev_info;
2762         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2763
2764         ixgbe_dev_info_get(dev, &dev_info);
2765
2766         /* check that mtu is within the allowed range */
2767         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2768                 return -EINVAL;
2769
2770         /* refuse mtu that requires the support of scattered packets when this
2771          * feature has not been enabled before. */
2772         if (!dev->data->scattered_rx &&
2773             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2774              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2775                 return -EINVAL;
2776
2777         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2779
2780         /* switch to jumbo mode if needed */
2781         if (frame_size > ETHER_MAX_LEN) {
2782                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2783                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2784         } else {
2785                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2786                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2787         }
2788         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2789
2790         /* update max frame size */
2791         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2792
2793         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2794         maxfrs &= 0x0000FFFF;
2795         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2796         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2797
2798         return 0;
2799 }
2800
2801 /*
2802  * Virtual Function operations
2803  */
2804 static void
2805 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2806 {
2807         PMD_INIT_FUNC_TRACE();
2808
2809         /* Clear interrupt mask to stop from interrupts being generated */
2810         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2811
2812         IXGBE_WRITE_FLUSH(hw);
2813 }
2814
2815 static int
2816 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2817 {
2818         struct rte_eth_conf* conf = &dev->data->dev_conf;
2819
2820         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2821                      dev->data->port_id);
2822
2823         /*
2824          * VF has no ability to enable/disable HW CRC
2825          * Keep the persistent behavior the same as Host PF
2826          */
2827 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2828         if (!conf->rxmode.hw_strip_crc) {
2829                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2830                 conf->rxmode.hw_strip_crc = 1;
2831         }
2832 #else
2833         if (conf->rxmode.hw_strip_crc) {
2834                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2835                 conf->rxmode.hw_strip_crc = 0;
2836         }
2837 #endif
2838
2839         return 0;
2840 }
2841
2842 static int
2843 ixgbevf_dev_start(struct rte_eth_dev *dev)
2844 {
2845         struct ixgbe_hw *hw =
2846                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847         int err, mask = 0;
2848
2849         PMD_INIT_FUNC_TRACE();
2850
2851         hw->mac.ops.reset_hw(hw);
2852
2853         /* negotiate mailbox API version to use with the PF. */
2854         ixgbevf_negotiate_api(hw);
2855
2856         ixgbevf_dev_tx_init(dev);
2857
2858         /* This can fail when allocating mbufs for descriptor rings */
2859         err = ixgbevf_dev_rx_init(dev);
2860         if (err) {
2861                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2862                 ixgbe_dev_clear_queues(dev);
2863                 return err;
2864         }
2865
2866         /* Set vfta */
2867         ixgbevf_set_vfta_all(dev,1);
2868
2869         /* Set HW strip */
2870         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2871                 ETH_VLAN_EXTEND_MASK;
2872         ixgbevf_vlan_offload_set(dev, mask);
2873
2874         ixgbevf_dev_rxtx_start(dev);
2875
2876         return 0;
2877 }
2878
2879 static void
2880 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2881 {
2882         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2883
2884         PMD_INIT_FUNC_TRACE();
2885
2886         hw->adapter_stopped = TRUE;
2887         ixgbe_stop_adapter(hw);
2888
2889         /*
2890           * Clear what we set, but we still keep shadow_vfta to
2891           * restore after device starts
2892           */
2893         ixgbevf_set_vfta_all(dev,0);
2894
2895         /* Clear stored conf */
2896         dev->data->scattered_rx = 0;
2897
2898         ixgbe_dev_clear_queues(dev);
2899 }
2900
2901 static void
2902 ixgbevf_dev_close(struct rte_eth_dev *dev)
2903 {
2904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2905
2906         PMD_INIT_FUNC_TRACE();
2907
2908         ixgbe_reset_hw(hw);
2909
2910         ixgbevf_dev_stop(dev);
2911
2912         /* reprogram the RAR[0] in case user changed it. */
2913         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2914 }
2915
2916 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2917 {
2918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2919         struct ixgbe_vfta * shadow_vfta =
2920                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2921         int i = 0, j = 0, vfta = 0, mask = 1;
2922
2923         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2924                 vfta = shadow_vfta->vfta[i];
2925                 if(vfta){
2926                         mask = 1;
2927                         for (j = 0; j < 32; j++){
2928                                 if(vfta & mask)
2929                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2930                                 mask<<=1;
2931                         }
2932                 }
2933         }
2934
2935 }
2936
2937 static int
2938 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2939 {
2940         struct ixgbe_hw *hw =
2941                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942         struct ixgbe_vfta * shadow_vfta =
2943                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2944         uint32_t vid_idx = 0;
2945         uint32_t vid_bit = 0;
2946         int ret = 0;
2947
2948         PMD_INIT_FUNC_TRACE();
2949
2950         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2951         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2952         if(ret){
2953                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2954                 return ret;
2955         }
2956         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2957         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2958
2959         /* Save what we set and retore it after device reset */
2960         if (on)
2961                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2962         else
2963                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2964
2965         return 0;
2966 }
2967
2968 static void
2969 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2970 {
2971         struct ixgbe_hw *hw =
2972                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2973         uint32_t ctrl;
2974
2975         PMD_INIT_FUNC_TRACE();
2976
2977         if(queue >= hw->mac.max_rx_queues)
2978                 return;
2979
2980         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2981         if(on)
2982                 ctrl |= IXGBE_RXDCTL_VME;
2983         else
2984                 ctrl &= ~IXGBE_RXDCTL_VME;
2985         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2986
2987         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2988 }
2989
2990 static void
2991 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2992 {
2993         struct ixgbe_hw *hw =
2994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2995         uint16_t i;
2996         int on = 0;
2997
2998         /* VF function only support hw strip feature, others are not support */
2999         if(mask & ETH_VLAN_STRIP_MASK){
3000                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3001
3002                 for(i=0; i < hw->mac.max_rx_queues; i++)
3003                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3004         }
3005 }
3006
3007 static int
3008 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3009 {
3010         uint32_t reg_val;
3011
3012         /* we only need to do this if VMDq is enabled */
3013         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3014         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3015                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3016                 return (-1);
3017         }
3018
3019         return 0;
3020 }
3021
3022 static uint32_t
3023 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3024 {
3025         uint32_t vector = 0;
3026         switch (hw->mac.mc_filter_type) {
3027         case 0:   /* use bits [47:36] of the address */
3028                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3029                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3030                 break;
3031         case 1:   /* use bits [46:35] of the address */
3032                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3033                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3034                 break;
3035         case 2:   /* use bits [45:34] of the address */
3036                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3037                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3038                 break;
3039         case 3:   /* use bits [43:32] of the address */
3040                 vector = ((uc_addr->addr_bytes[4]) |
3041                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3042                 break;
3043         default:  /* Invalid mc_filter_type */
3044                 break;
3045         }
3046
3047         /* vector can only be 12-bits or boundary will be exceeded */
3048         vector &= 0xFFF;
3049         return vector;
3050 }
3051
3052 static int
3053 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3054                                uint8_t on)
3055 {
3056         uint32_t vector;
3057         uint32_t uta_idx;
3058         uint32_t reg_val;
3059         uint32_t uta_shift;
3060         uint32_t rc;
3061         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3062         const uint32_t ixgbe_uta_bit_shift = 5;
3063         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3064         const uint32_t bit1 = 0x1;
3065
3066         struct ixgbe_hw *hw =
3067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         struct ixgbe_uta_info *uta_info =
3069                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3070
3071         /* The UTA table only exists on 82599 hardware and newer */
3072         if (hw->mac.type < ixgbe_mac_82599EB)
3073                 return (-ENOTSUP);
3074
3075         vector = ixgbe_uta_vector(hw,mac_addr);
3076         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3077         uta_shift = vector & ixgbe_uta_bit_mask;
3078
3079         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3080         if(rc == on)
3081                 return 0;
3082
3083         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3084         if (on) {
3085                 uta_info->uta_in_use++;
3086                 reg_val |= (bit1 << uta_shift);
3087                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3088         } else {
3089                 uta_info->uta_in_use--;
3090                 reg_val &= ~(bit1 << uta_shift);
3091                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3092         }
3093
3094         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3095
3096         if (uta_info->uta_in_use > 0)
3097                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3098                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3099         else
3100                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3101
3102         return 0;
3103 }
3104
3105 static int
3106 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3107 {
3108         int i;
3109         struct ixgbe_hw *hw =
3110                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3111         struct ixgbe_uta_info *uta_info =
3112                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3113
3114         /* The UTA table only exists on 82599 hardware and newer */
3115         if (hw->mac.type < ixgbe_mac_82599EB)
3116                 return (-ENOTSUP);
3117
3118         if(on) {
3119                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3120                         uta_info->uta_shadow[i] = ~0;
3121                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3122                 }
3123         } else {
3124                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3125                         uta_info->uta_shadow[i] = 0;
3126                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3127                 }
3128         }
3129         return 0;
3130
3131 }
3132
3133 uint32_t
3134 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3135 {
3136         uint32_t new_val = orig_val;
3137
3138         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3139                 new_val |= IXGBE_VMOLR_AUPE;
3140         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3141                 new_val |= IXGBE_VMOLR_ROMPE;
3142         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3143                 new_val |= IXGBE_VMOLR_ROPE;
3144         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3145                 new_val |= IXGBE_VMOLR_BAM;
3146         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3147                 new_val |= IXGBE_VMOLR_MPE;
3148
3149         return new_val;
3150 }
3151
3152 static int
3153 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3154                                uint16_t rx_mask, uint8_t on)
3155 {
3156         int val = 0;
3157
3158         struct ixgbe_hw *hw =
3159                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3160         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3161
3162         if (hw->mac.type == ixgbe_mac_82598EB) {
3163                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3164                              " on 82599 hardware and newer");
3165                 return (-ENOTSUP);
3166         }
3167         if (ixgbe_vmdq_mode_check(hw) < 0)
3168                 return (-ENOTSUP);
3169
3170         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3171
3172         if (on)
3173                 vmolr |= val;
3174         else
3175                 vmolr &= ~val;
3176
3177         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3178
3179         return 0;
3180 }
3181
3182 static int
3183 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3184 {
3185         uint32_t reg,addr;
3186         uint32_t val;
3187         const uint8_t bit1 = 0x1;
3188
3189         struct ixgbe_hw *hw =
3190                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3191
3192         if (ixgbe_vmdq_mode_check(hw) < 0)
3193                 return (-ENOTSUP);
3194
3195         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3196         reg = IXGBE_READ_REG(hw, addr);
3197         val = bit1 << pool;
3198
3199         if (on)
3200                 reg |= val;
3201         else
3202                 reg &= ~val;
3203
3204         IXGBE_WRITE_REG(hw, addr,reg);
3205
3206         return 0;
3207 }
3208
3209 static int
3210 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3211 {
3212         uint32_t reg,addr;
3213         uint32_t val;
3214         const uint8_t bit1 = 0x1;
3215
3216         struct ixgbe_hw *hw =
3217                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3218
3219         if (ixgbe_vmdq_mode_check(hw) < 0)
3220                 return (-ENOTSUP);
3221
3222         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3223         reg = IXGBE_READ_REG(hw, addr);
3224         val = bit1 << pool;
3225
3226         if (on)
3227                 reg |= val;
3228         else
3229                 reg &= ~val;
3230
3231         IXGBE_WRITE_REG(hw, addr,reg);
3232
3233         return 0;
3234 }
3235
3236 static int
3237 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3238                         uint64_t pool_mask, uint8_t vlan_on)
3239 {
3240         int ret = 0;
3241         uint16_t pool_idx;
3242         struct ixgbe_hw *hw =
3243                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3244
3245         if (ixgbe_vmdq_mode_check(hw) < 0)
3246                 return (-ENOTSUP);
3247         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3248                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3249                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3250                         if (ret < 0)
3251                                 return ret;
3252         }
3253
3254         return ret;
3255 }
3256
3257 static int
3258 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3259                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3260                         uint8_t rule_id, uint8_t on)
3261 {
3262         uint32_t mr_ctl,vlvf;
3263         uint32_t mp_lsb = 0;
3264         uint32_t mv_msb = 0;
3265         uint32_t mv_lsb = 0;
3266         uint32_t mp_msb = 0;
3267         uint8_t i = 0;
3268         int reg_index = 0;
3269         uint64_t vlan_mask = 0;
3270
3271         const uint8_t pool_mask_offset = 32;
3272         const uint8_t vlan_mask_offset = 32;
3273         const uint8_t dst_pool_offset = 8;
3274         const uint8_t rule_mr_offset  = 4;
3275         const uint8_t mirror_rule_mask= 0x0F;
3276
3277         struct ixgbe_mirror_info *mr_info =
3278                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3279         struct ixgbe_hw *hw =
3280                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3281
3282         if (ixgbe_vmdq_mode_check(hw) < 0)
3283                 return (-ENOTSUP);
3284
3285         /* Check if vlan mask is valid */
3286         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3287                 if (mirror_conf->vlan.vlan_mask == 0)
3288                         return (-EINVAL);
3289         }
3290
3291         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3292         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3293                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3294                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3295                                 /* search vlan id related pool vlan filter index */
3296                                 reg_index = ixgbe_find_vlvf_slot(hw,
3297                                                 mirror_conf->vlan.vlan_id[i]);
3298                                 if(reg_index < 0)
3299                                         return (-EINVAL);
3300                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3301                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3302                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3303                                                 == mirror_conf->vlan.vlan_id[i]))
3304                                         vlan_mask |= (1ULL << reg_index);
3305                                 else
3306                                         return (-EINVAL);
3307                         }
3308                 }
3309
3310                 if (on) {
3311                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3312                         mv_msb = vlan_mask >> vlan_mask_offset;
3313
3314                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3315                                                 mirror_conf->vlan.vlan_mask;
3316                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3317                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3318                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3319                                                 mirror_conf->vlan.vlan_id[i];
3320                         }
3321                 } else {
3322                         mv_lsb = 0;
3323                         mv_msb = 0;
3324                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3325                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3326                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3327                 }
3328         }
3329
3330         /*
3331          * if enable pool mirror, write related pool mask register,if disable
3332          * pool mirror, clear PFMRVM register
3333          */
3334         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3335                 if (on) {
3336                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3337                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3338                         mr_info->mr_conf[rule_id].pool_mask =
3339                                         mirror_conf->pool_mask;
3340
3341                 } else {
3342                         mp_lsb = 0;
3343                         mp_msb = 0;
3344                         mr_info->mr_conf[rule_id].pool_mask = 0;
3345                 }
3346         }
3347
3348         /* read  mirror control register and recalculate it */
3349         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3350
3351         if (on) {
3352                 mr_ctl |= mirror_conf->rule_type_mask;
3353                 mr_ctl &= mirror_rule_mask;
3354                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3355         } else
3356                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3357
3358         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3359         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3360
3361         /* write mirrror control  register */
3362         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3363
3364         /* write pool mirrror control  register */
3365         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3366                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3367                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3368                                 mp_msb);
3369         }
3370         /* write VLAN mirrror control  register */
3371         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3372                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3373                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3374                                 mv_msb);
3375         }
3376
3377         return 0;
3378 }
3379
3380 static int
3381 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3382 {
3383         int mr_ctl = 0;
3384         uint32_t lsb_val = 0;
3385         uint32_t msb_val = 0;
3386         const uint8_t rule_mr_offset = 4;
3387
3388         struct ixgbe_hw *hw =
3389                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390         struct ixgbe_mirror_info *mr_info =
3391                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3392
3393         if (ixgbe_vmdq_mode_check(hw) < 0)
3394                 return (-ENOTSUP);
3395
3396         memset(&mr_info->mr_conf[rule_id], 0,
3397                 sizeof(struct rte_eth_vmdq_mirror_conf));
3398
3399         /* clear PFVMCTL register */
3400         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3401
3402         /* clear pool mask register */
3403         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3404         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3405
3406         /* clear vlan mask register */
3407         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3408         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3409
3410         return 0;
3411 }
3412
3413 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3414         uint16_t queue_idx, uint16_t tx_rate)
3415 {
3416         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417         uint32_t rf_dec, rf_int;
3418         uint32_t bcnrc_val;
3419         uint16_t link_speed = dev->data->dev_link.link_speed;
3420
3421         if (queue_idx >= hw->mac.max_tx_queues)
3422                 return -EINVAL;
3423
3424         if (tx_rate != 0) {
3425                 /* Calculate the rate factor values to set */
3426                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3427                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3428                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3429
3430                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3431                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3432                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3433                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3434         } else {
3435                 bcnrc_val = 0;
3436         }
3437
3438         /*
3439          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3440          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3441          * set as 0x4.
3442          */
3443         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3444                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3445                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3446                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3447                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3448         else
3449                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3450                         IXGBE_MMW_SIZE_DEFAULT);
3451
3452         /* Set RTTBCNRC of queue X */
3453         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3454         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3455         IXGBE_WRITE_FLUSH(hw);
3456
3457         return 0;
3458 }
3459
3460 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3461         uint16_t tx_rate, uint64_t q_msk)
3462 {
3463         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3464         struct ixgbe_vf_info *vfinfo =
3465                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3466         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3467         uint32_t queue_stride =
3468                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3469         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3470         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3471         uint16_t total_rate = 0;
3472
3473         if (queue_end >= hw->mac.max_tx_queues)
3474                 return -EINVAL;
3475
3476         if (vfinfo != NULL) {
3477                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3478                         if (vf_idx == vf)
3479                                 continue;
3480                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3481                                 idx++)
3482                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3483                 }
3484         } else
3485                 return -EINVAL;
3486
3487         /* Store tx_rate for this vf. */
3488         for (idx = 0; idx < nb_q_per_pool; idx++) {
3489                 if (((uint64_t)0x1 << idx) & q_msk) {
3490                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3491                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3492                         total_rate += tx_rate;
3493                 }
3494         }
3495
3496         if (total_rate > dev->data->dev_link.link_speed) {
3497                 /*
3498                  * Reset stored TX rate of the VF if it causes exceed
3499                  * link speed.
3500                  */
3501                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3502                 return -EINVAL;
3503         }
3504
3505         /* Set RTTBCNRC of each queue/pool for vf X  */
3506         for (; queue_idx <= queue_end; queue_idx++) {
3507                 if (0x1 & q_msk)
3508                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3509                 q_msk = q_msk >> 1;
3510         }
3511
3512         return 0;
3513 }
3514
3515 static void
3516 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3517                      __attribute__((unused)) uint32_t index,
3518                      __attribute__((unused)) uint32_t pool)
3519 {
3520         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3521         int diag;
3522
3523         /*
3524          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3525          * operation. Trap this case to avoid exhausting the [very limited]
3526          * set of PF resources used to store VF MAC addresses.
3527          */
3528         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3529                 return;
3530         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3531         if (diag == 0)
3532                 return;
3533         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3534 }
3535
3536 static void
3537 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3538 {
3539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3540         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3541         struct ether_addr *mac_addr;
3542         uint32_t i;
3543         int diag;
3544
3545         /*
3546          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3547          * not support the deletion of a given MAC address.
3548          * Instead, it imposes to delete all MAC addresses, then to add again
3549          * all MAC addresses with the exception of the one to be deleted.
3550          */
3551         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3552
3553         /*
3554          * Add again all MAC addresses, with the exception of the deleted one
3555          * and of the permanent MAC address.
3556          */
3557         for (i = 0, mac_addr = dev->data->mac_addrs;
3558              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3559                 /* Skip the deleted MAC address */
3560                 if (i == index)
3561                         continue;
3562                 /* Skip NULL MAC addresses */
3563                 if (is_zero_ether_addr(mac_addr))
3564                         continue;
3565                 /* Skip the permanent MAC address */
3566                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3567                         continue;
3568                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3569                 if (diag != 0)
3570                         PMD_DRV_LOG(ERR,
3571                                     "Adding again MAC address "
3572                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3573                                     "diag=%d",
3574                                     mac_addr->addr_bytes[0],
3575                                     mac_addr->addr_bytes[1],
3576                                     mac_addr->addr_bytes[2],
3577                                     mac_addr->addr_bytes[3],
3578                                     mac_addr->addr_bytes[4],
3579                                     mac_addr->addr_bytes[5],
3580                                     diag);
3581         }
3582 }
3583
3584 /*
3585  * add syn filter
3586  *
3587  * @param
3588  * dev: Pointer to struct rte_eth_dev.
3589  * filter: ponter to the filter that will be added.
3590  * rx_queue: the queue id the filter assigned to.
3591  *
3592  * @return
3593  *    - On success, zero.
3594  *    - On failure, a negative value.
3595  */
3596 static int
3597 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3598                         struct rte_syn_filter *filter, uint16_t rx_queue)
3599 {
3600         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601         uint32_t synqf;
3602
3603         if (hw->mac.type != ixgbe_mac_82599EB)
3604                 return -ENOSYS;
3605
3606         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3607                 return -EINVAL;
3608
3609         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3610
3611         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3612                 return -EINVAL;
3613
3614         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3615                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3616
3617         if (filter->hig_pri)
3618                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3619         else
3620                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3621
3622         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3623         return 0;
3624 }
3625
3626 /*
3627  * remove syn filter
3628  *
3629  * @param
3630  * dev: Pointer to struct rte_eth_dev.
3631  *
3632  * @return
3633  *    - On success, zero.
3634  *    - On failure, a negative value.
3635  */
3636 static int
3637 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3638 {
3639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640         uint32_t synqf;
3641
3642         if (hw->mac.type != ixgbe_mac_82599EB)
3643                 return -ENOSYS;
3644
3645         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3646
3647         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3648
3649         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3650         return 0;
3651 }
3652
3653 /*
3654  * get the syn filter's info
3655  *
3656  * @param
3657  * dev: Pointer to struct rte_eth_dev.
3658  * filter: ponter to the filter that returns.
3659  * *rx_queue: pointer to the queue id the filter assigned to.
3660  *
3661  * @return
3662  *    - On success, zero.
3663  *    - On failure, a negative value.
3664  */
3665 static int
3666 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3667                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3668
3669 {
3670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3671         uint32_t synqf;
3672
3673         if (hw->mac.type != ixgbe_mac_82599EB)
3674                 return -ENOSYS;
3675
3676         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3677         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3678                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3679                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3680                 return 0;
3681         }
3682         return -ENOENT;
3683 }
3684
3685 /*
3686  * add an ethertype filter
3687  *
3688  * @param
3689  * dev: Pointer to struct rte_eth_dev.
3690  * index: the index the filter allocates.
3691  * filter: ponter to the filter that will be added.
3692  * rx_queue: the queue id the filter assigned to.
3693  *
3694  * @return
3695  *    - On success, zero.
3696  *    - On failure, a negative value.
3697  */
3698 static int
3699 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3700                         uint16_t index, struct rte_ethertype_filter *filter,
3701                         uint16_t rx_queue)
3702 {
3703         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704         uint32_t etqf, etqs = 0;
3705
3706         if (hw->mac.type != ixgbe_mac_82599EB)
3707                 return -ENOSYS;
3708
3709         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3710                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3711                 return -EINVAL;
3712
3713         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3714         if (etqf & IXGBE_ETQF_FILTER_EN)
3715                 return -EINVAL;  /* filter index is in use. */
3716
3717         etqf = 0;
3718         etqf |= IXGBE_ETQF_FILTER_EN;
3719         etqf |= (uint32_t)filter->ethertype;
3720
3721         if (filter->priority_en) {
3722                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3723                         return -EINVAL;
3724                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3725                 etqf |= IXGBE_ETQF_UP_EN;
3726         }
3727         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3728         etqs |= IXGBE_ETQS_QUEUE_EN;
3729
3730         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3731         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3732         return 0;
3733 }
3734
3735 /*
3736  * remove an ethertype filter
3737  *
3738  * @param
3739  * dev: Pointer to struct rte_eth_dev.
3740  * index: the index the filter allocates.
3741  *
3742  * @return
3743  *    - On success, zero.
3744  *    - On failure, a negative value.
3745  */
3746 static int
3747 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3748                         uint16_t index)
3749 {
3750         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3751
3752         if (hw->mac.type != ixgbe_mac_82599EB)
3753                 return -ENOSYS;
3754
3755         if (index >= IXGBE_MAX_ETQF_FILTERS)
3756                 return -EINVAL;
3757
3758         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3759         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3760
3761         return 0;
3762 }
3763
3764 /*
3765  * get an ethertype filter
3766  *
3767  * @param
3768  * dev: Pointer to struct rte_eth_dev.
3769  * index: the index the filter allocates.
3770  * filter: ponter to the filter that will be gotten.
3771  * *rx_queue: the ponited of the queue id the filter assigned to.
3772  *
3773  * @return
3774  *    - On success, zero.
3775  *    - On failure, a negative value.
3776  */
3777 static int
3778 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3779                         uint16_t index, struct rte_ethertype_filter *filter,
3780                         uint16_t *rx_queue)
3781 {
3782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783         uint32_t etqf, etqs;
3784
3785         if (hw->mac.type != ixgbe_mac_82599EB)
3786                 return -ENOSYS;
3787
3788         if (index >= IXGBE_MAX_ETQF_FILTERS)
3789                 return -EINVAL;
3790
3791         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3792         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3793         if (etqf & IXGBE_ETQF_FILTER_EN) {
3794                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3795                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3796                 if (filter->priority_en)
3797                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3798                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3799                 return 0;
3800         }
3801         return -ENOENT;
3802 }
3803
3804 static inline enum ixgbe_5tuple_protocol
3805 convert_protocol_type(uint8_t protocol_value)
3806 {
3807         if (protocol_value == IPPROTO_TCP)
3808                 return IXGBE_FILTER_PROTOCOL_TCP;
3809         else if (protocol_value == IPPROTO_UDP)
3810                 return IXGBE_FILTER_PROTOCOL_UDP;
3811         else if (protocol_value == IPPROTO_SCTP)
3812                 return IXGBE_FILTER_PROTOCOL_SCTP;
3813         else
3814                 return IXGBE_FILTER_PROTOCOL_NONE;
3815 }
3816
3817 static inline uint8_t
3818 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3819 {
3820         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3821                 return IPPROTO_TCP;
3822         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3823                 return IPPROTO_UDP;
3824         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3825                 return IPPROTO_SCTP;
3826         else
3827                 return 0;
3828 }
3829
3830 /*
3831  * add a 5tuple filter
3832  *
3833  * @param
3834  * dev: Pointer to struct rte_eth_dev.
3835  * index: the index the filter allocates.
3836  * filter: ponter to the filter that will be added.
3837  * rx_queue: the queue id the filter assigned to.
3838  *
3839  * @return
3840  *    - On success, zero.
3841  *    - On failure, a negative value.
3842  */
3843 static int
3844 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3845                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3846 {
3847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3848         uint32_t ftqf, sdpqf = 0;
3849         uint32_t l34timir = 0;
3850         uint8_t mask = 0xff;
3851
3852         if (hw->mac.type != ixgbe_mac_82599EB)
3853                 return -ENOSYS;
3854
3855         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3856                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3857                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3858                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3859                 return -EINVAL;  /* filter index is out of range. */
3860
3861         if (filter->tcp_flags) {
3862                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3863                 return -EINVAL;
3864         }
3865
3866         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3867         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3868                 return -EINVAL;  /* filter index is in use. */
3869
3870         ftqf = 0;
3871         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3872         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3873
3874         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3875                 IXGBE_FTQF_PROTOCOL_MASK);
3876         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3877                 IXGBE_FTQF_PRIORITY_SHIFT);
3878         if (filter->src_ip_mask == 0) /* 0 means compare. */
3879                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3880         if (filter->dst_ip_mask == 0)
3881                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3882         if (filter->src_port_mask == 0)
3883                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3884         if (filter->dst_port_mask == 0)
3885                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3886         if (filter->protocol_mask == 0)
3887                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3888         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3889         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3890         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3891
3892         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3893         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3894         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3895         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3896
3897         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3898         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3899         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3900         return 0;
3901 }
3902
3903 /*
3904  * remove a 5tuple filter
3905  *
3906  * @param
3907  * dev: Pointer to struct rte_eth_dev.
3908  * index: the index the filter allocates.
3909  *
3910  * @return
3911  *    - On success, zero.
3912  *    - On failure, a negative value.
3913  */
3914 static int
3915 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3916                         uint16_t index)
3917 {
3918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3919
3920         if (hw->mac.type != ixgbe_mac_82599EB)
3921                 return -ENOSYS;
3922
3923         if (index >= IXGBE_MAX_FTQF_FILTERS)
3924                 return -EINVAL;  /* filter index is out of range. */
3925
3926         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3927         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3928         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3929         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3930         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3931         return 0;
3932 }
3933
3934 /*
3935  * get a 5tuple filter
3936  *
3937  * @param
3938  * dev: Pointer to struct rte_eth_dev.
3939  * index: the index the filter allocates
3940  * filter: ponter to the filter that returns.
3941  * *rx_queue: pointer of the queue id the filter assigned to.
3942  *
3943  * @return
3944  *    - On success, zero.
3945  *    - On failure, a negative value.
3946  */
3947 static int
3948 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3949                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3950 {
3951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3952         uint32_t sdpqf, ftqf, l34timir;
3953         uint8_t mask;
3954         enum ixgbe_5tuple_protocol proto;
3955
3956         if (hw->mac.type != ixgbe_mac_82599EB)
3957                 return -ENOSYS;
3958
3959         if (index >= IXGBE_MAX_FTQF_FILTERS)
3960                 return -EINVAL;  /* filter index is out of range. */
3961
3962         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3963         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3964                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3965                 filter->protocol = revert_protocol_type(proto);
3966                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3967                                         IXGBE_FTQF_PRIORITY_MASK;
3968                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3969                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3970                 filter->src_ip_mask =
3971                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3972                 filter->dst_ip_mask =
3973                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3974                 filter->src_port_mask =
3975                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3976                 filter->dst_port_mask =
3977                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3978                 filter->protocol_mask =
3979                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3980
3981                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3982                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3983                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3984                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3985                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3986                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3987
3988                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3989                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3990                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3991                 return 0;
3992         }
3993         return -ENOENT;
3994 }
3995
3996 static int
3997 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3998 {
3999         struct ixgbe_hw *hw;
4000         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4001
4002         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4003
4004         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4005                 return -EINVAL;
4006
4007         /* refuse mtu that requires the support of scattered packets when this
4008          * feature has not been enabled before. */
4009         if (!dev->data->scattered_rx &&
4010             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4011              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4012                 return -EINVAL;
4013
4014         /*
4015          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4016          * request of the version 2.0 of the mailbox API.
4017          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4018          * of the mailbox API.
4019          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4020          * prior to 3.11.33 which contains the following change:
4021          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4022          */
4023         ixgbevf_rlpml_set_vf(hw, max_frame);
4024
4025         /* update max frame size */
4026         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4027         return 0;
4028 }
4029
4030 static struct rte_driver rte_ixgbe_driver = {
4031         .type = PMD_PDEV,
4032         .init = rte_ixgbe_pmd_init,
4033 };
4034
4035 static struct rte_driver rte_ixgbevf_driver = {
4036         .type = PMD_PDEV,
4037         .init = rte_ixgbevf_pmd_init,
4038 };
4039
4040 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4041 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);