lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72
  73 /*
  74  * High threshold controlling when to start sending XOFF frames. Must be at
  75  * least 8 bytes less than receive packet buffer size. This value is in units
  76  * of 1024 bytes.
  77  */
  78 #define IXGBE_FC_HI    0x80
  79
  80 /*
  81  * Low threshold controlling when to start sending XON frames. This value is
  82  * in units of 1024 bytes.
  83  */
  84 #define IXGBE_FC_LO    0x40
  85
  86 /* Timer value included in XOFF frames. */
  87 #define IXGBE_FC_PAUSE 0x680
  88
  89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  90 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  91 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  92
  93 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  94 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  95
  96 /*
  97  *  Default values for RX/TX configuration
  98  */
  99 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 100 #define IXGBE_DEFAULT_RX_PTHRESH      8
 101 #define IXGBE_DEFAULT_RX_HTHRESH      8
 102 #define IXGBE_DEFAULT_RX_WTHRESH      0
 103
 104 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 105 #define IXGBE_DEFAULT_TX_PTHRESH      32
 106 #define IXGBE_DEFAULT_TX_HTHRESH      0
 107 #define IXGBE_DEFAULT_TX_WTHRESH      0
 108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 109
 110 /* Bit shift and mask */
 111 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 112 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 113 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 114 #define IXGBE_8_BIT_MASK   UINT8_MAX
 115
 116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 117
 118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 119
 120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 121                 struct rte_eth_dev *eth_dev);
 122 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 125 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 126 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 133                                 int wait_to_complete);
 134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 135                                 struct rte_eth_stats *stats);
 136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 138                                              uint16_t queue_id,
 139                                              uint8_t stat_idx,
 140                                              uint8_t is_rx);
 141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 142                                struct rte_eth_dev_info *dev_info);
 143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 144                                  struct rte_eth_dev_info *dev_info);
 145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 151                 uint16_t queue, bool on);
 152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 153                 int on);
 154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 165                                struct rte_eth_fc_conf *fc_conf);
 166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 167                 struct rte_eth_pfc_conf *pfc_conf);
 168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 169                         struct rte_eth_rss_reta_entry64 *reta_conf,
 170                         uint16_t reta_size);
 171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 172                         struct rte_eth_rss_reta_entry64 *reta_conf,
 173                         uint16_t reta_size);
 174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 179                 void *param);
 180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 182                 uint32_t index, uint32_t pool);
 183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 185
 186 /* For Virtual Function support */
 187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 188                 struct rte_eth_dev *eth_dev);
 189 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 190 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 195                 struct rte_eth_stats *stats);
 196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 198                 uint16_t vlan_id, int on);
 199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 200                 uint16_t queue, int on);
 201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203
 204 /* For Eth VMDQ APIs support */
 205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 206                 ether_addr* mac_addr,uint8_t on);
 207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 208 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 209                 uint16_t rx_mask, uint8_t on);
 210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 213                 uint64_t pool_mask,uint8_t vlan_on);
 214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 216                 uint8_t rule_id, uint8_t on);
 217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 218                 uint8_t rule_id);
 219
 220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 221                 uint16_t queue_idx, uint16_t tx_rate);
 222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 223                 uint16_t tx_rate, uint64_t q_msk);
 224
 225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 226                                  struct ether_addr *mac_addr,
 227                                  uint32_t index, uint32_t pool);
 228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 229 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 230                         struct rte_syn_filter *filter, uint16_t rx_queue);
 231 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 232 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 233                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 235                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 236 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 237                         uint16_t index);
 238 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 239                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 240
 241 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 242 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter,
 244                         bool add);
 245 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter);
 250 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 251                      enum rte_filter_type filter_type,
 252                      enum rte_filter_op filter_op,
 253                      void *arg);
 254
 255 /*
 256  * Define VF Stats MACRO for Non "cleared on read" register
 257  */
 258 #define UPDATE_VF_STAT(reg, last, cur)                          \
 259 {                                                               \
 260         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 261         cur += latest - last;                                   \
 262         last = latest;                                          \
 263 }
 264
 265 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 266 {                                                                \
 267         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 268         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 269         u64 latest = ((new_msb << 32) | new_lsb);                \
 270         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 271         last = latest;                                           \
 272 }
 273
 274 #define IXGBE_SET_HWSTRIP(h, q) do{\
 275                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 276                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 277                 (h)->bitmap[idx] |= 1 << bit;\
 278         }while(0)
 279
 280 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 281                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 283                 (h)->bitmap[idx] &= ~(1 << bit);\
 284         }while(0)
 285
 286 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 287                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 288                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 289                 (r) = (h)->bitmap[idx] >> bit & 1;\
 290         }while(0)
 291
 292 /*
 293  * The set of PCI devices this driver supports
 294  */
 295 static struct rte_pci_id pci_id_ixgbe_map[] = {
 296
 297 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 298 #include "rte_pci_dev_ids.h"
 299
 300 { .vendor_id = 0, /* sentinel */ },
 301 };
 302
 303
 304 /*
 305  * The set of PCI devices this driver supports (for 82599 VF)
 306  */
 307 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 308
 309 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 310 #include "rte_pci_dev_ids.h"
 311 { .vendor_id = 0, /* sentinel */ },
 312
 313 };
 314
 315 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 316         .dev_configure        = ixgbe_dev_configure,
 317         .dev_start            = ixgbe_dev_start,
 318         .dev_stop             = ixgbe_dev_stop,
 319         .dev_set_link_up    = ixgbe_dev_set_link_up,
 320         .dev_set_link_down  = ixgbe_dev_set_link_down,
 321         .dev_close            = ixgbe_dev_close,
 322         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 323         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 324         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 325         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 326         .link_update          = ixgbe_dev_link_update,
 327         .stats_get            = ixgbe_dev_stats_get,
 328         .stats_reset          = ixgbe_dev_stats_reset,
 329         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 330         .dev_infos_get        = ixgbe_dev_info_get,
 331         .mtu_set              = ixgbe_dev_mtu_set,
 332         .vlan_filter_set      = ixgbe_vlan_filter_set,
 333         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 334         .vlan_offload_set     = ixgbe_vlan_offload_set,
 335         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 336         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 337         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 338         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 339         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 340         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 341         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 342         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 343         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 344         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 345         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 346         .dev_led_on           = ixgbe_dev_led_on,
 347         .dev_led_off          = ixgbe_dev_led_off,
 348         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 349         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 350         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 351         .mac_addr_add         = ixgbe_add_rar,
 352         .mac_addr_remove      = ixgbe_remove_rar,
 353         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 354         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 355         .mirror_rule_set      = ixgbe_mirror_rule_set,
 356         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 357         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 358         .set_vf_rx            = ixgbe_set_pool_rx,
 359         .set_vf_tx            = ixgbe_set_pool_tx,
 360         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 361         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 362         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 363         .fdir_infos_get               = ixgbe_fdir_info_get,
 364         .reta_update          = ixgbe_dev_rss_reta_update,
 365         .reta_query           = ixgbe_dev_rss_reta_query,
 366 #ifdef RTE_NIC_BYPASS
 367         .bypass_init          = ixgbe_bypass_init,
 368         .bypass_state_set     = ixgbe_bypass_state_store,
 369         .bypass_state_show    = ixgbe_bypass_state_show,
 370         .bypass_event_set     = ixgbe_bypass_event_store,
 371         .bypass_event_show    = ixgbe_bypass_event_show,
 372         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 373         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 374         .bypass_ver_show      = ixgbe_bypass_ver_show,
 375         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 376 #endif /* RTE_NIC_BYPASS */
 377         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 378         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 379         .add_syn_filter          = ixgbe_add_syn_filter,
 380         .remove_syn_filter       = ixgbe_remove_syn_filter,
 381         .get_syn_filter          = ixgbe_get_syn_filter,
 382         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 383         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 384         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 385         .filter_ctrl             = ixgbe_dev_filter_ctrl,
 386 };
 387
 388 /*
 389  * dev_ops for virtual function, bare necessities for basic vf
 390  * operation have been implemented
 391  */
 392 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 393
 394         .dev_configure        = ixgbevf_dev_configure,
 395         .dev_start            = ixgbevf_dev_start,
 396         .dev_stop             = ixgbevf_dev_stop,
 397         .link_update          = ixgbe_dev_link_update,
 398         .stats_get            = ixgbevf_dev_stats_get,
 399         .stats_reset          = ixgbevf_dev_stats_reset,
 400         .dev_close            = ixgbevf_dev_close,
 401         .dev_infos_get        = ixgbevf_dev_info_get,
 402         .mtu_set              = ixgbevf_dev_set_mtu,
 403         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 404         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 405         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 406         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 407         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 408         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 409         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 410         .mac_addr_add         = ixgbevf_add_mac_addr,
 411         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 412 };
 413
 414 /**
 415  * Atomically reads the link status information from global
 416  * structure rte_eth_dev.
 417  *
 418  * @param dev
 419  *   - Pointer to the structure rte_eth_dev to read from.
 420  *   - Pointer to the buffer to be saved with the link status.
 421  *
 422  * @return
 423  *   - On success, zero.
 424  *   - On failure, negative value.
 425  */
 426 static inline int
 427 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 428                                 struct rte_eth_link *link)
 429 {
 430         struct rte_eth_link *dst = link;
 431         struct rte_eth_link *src = &(dev->data->dev_link);
 432
 433         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 434                                         *(uint64_t *)src) == 0)
 435                 return -1;
 436
 437         return 0;
 438 }
 439
 440 /**
 441  * Atomically writes the link status information into global
 442  * structure rte_eth_dev.
 443  *
 444  * @param dev
 445  *   - Pointer to the structure rte_eth_dev to read from.
 446  *   - Pointer to the buffer to be saved with the link status.
 447  *
 448  * @return
 449  *   - On success, zero.
 450  *   - On failure, negative value.
 451  */
 452 static inline int
 453 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 454                                 struct rte_eth_link *link)
 455 {
 456         struct rte_eth_link *dst = &(dev->data->dev_link);
 457         struct rte_eth_link *src = link;
 458
 459         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 460                                         *(uint64_t *)src) == 0)
 461                 return -1;
 462
 463         return 0;
 464 }
 465
 466 /*
 467  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 468  */
 469 static inline int
 470 ixgbe_is_sfp(struct ixgbe_hw *hw)
 471 {
 472         switch (hw->phy.type) {
 473         case ixgbe_phy_sfp_avago:
 474         case ixgbe_phy_sfp_ftl:
 475         case ixgbe_phy_sfp_intel:
 476         case ixgbe_phy_sfp_unknown:
 477         case ixgbe_phy_sfp_passive_tyco:
 478         case ixgbe_phy_sfp_passive_unknown:
 479                 return 1;
 480         default:
 481                 return 0;
 482         }
 483 }
 484
 485 static inline int32_t
 486 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 487 {
 488         uint32_t ctrl_ext;
 489         int32_t status;
 490
 491         status = ixgbe_reset_hw(hw);
 492
 493         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 494         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 495         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 496         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 497         IXGBE_WRITE_FLUSH(hw);
 498
 499         return status;
 500 }
 501
 502 static inline void
 503 ixgbe_enable_intr(struct rte_eth_dev *dev)
 504 {
 505         struct ixgbe_interrupt *intr =
 506                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 507         struct ixgbe_hw *hw =
 508                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 509
 510         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 511         IXGBE_WRITE_FLUSH(hw);
 512 }
 513
 514 /*
 515  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 516  */
 517 static void
 518 ixgbe_disable_intr(struct ixgbe_hw *hw)
 519 {
 520         PMD_INIT_FUNC_TRACE();
 521
 522         if (hw->mac.type == ixgbe_mac_82598EB) {
 523                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 524         } else {
 525                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 526                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 527                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 528         }
 529         IXGBE_WRITE_FLUSH(hw);
 530 }
 531
 532 /*
 533  * This function resets queue statistics mapping registers.
 534  * From Niantic datasheet, Initialization of Statistics section:
 535  * "...if software requires the queue counters, the RQSMR and TQSM registers
 536  * must be re-programmed following a device reset.
 537  */
 538 static void
 539 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 540 {
 541         uint32_t i;
 542
 543         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 544                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 545                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 546         }
 547 }
 548
 549
 550 static int
 551 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 552                                   uint16_t queue_id,
 553                                   uint8_t stat_idx,
 554                                   uint8_t is_rx)
 555 {
 556 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 557 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 558 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 559
 560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 561         struct ixgbe_stat_mapping_registers *stat_mappings =
 562                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 563         uint32_t qsmr_mask = 0;
 564         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 565         uint32_t q_map;
 566         uint8_t n, offset;
 567
 568         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 569                 (hw->mac.type != ixgbe_mac_X540) &&
 570                 (hw->mac.type != ixgbe_mac_X550) &&
 571                 (hw->mac.type != ixgbe_mac_X550EM_x))
 572                 return -ENOSYS;
 573
 574         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 575                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 576                      queue_id, stat_idx);
 577
 578         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 579         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 580                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 581                 return -EIO;
 582         }
 583         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 584
 585         /* Now clear any previous stat_idx set */
 586         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 587         if (!is_rx)
 588                 stat_mappings->tqsm[n] &= ~clearing_mask;
 589         else
 590                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 591
 592         q_map = (uint32_t)stat_idx;
 593         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 594         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 595         if (!is_rx)
 596                 stat_mappings->tqsm[n] |= qsmr_mask;
 597         else
 598                 stat_mappings->rqsmr[n] |= qsmr_mask;
 599
 600         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 601                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 602                      queue_id, stat_idx);
 603         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 604                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 605
 606         /* Now write the mapping in the appropriate register */
 607         if (is_rx) {
 608                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 609                              stat_mappings->rqsmr[n], n);
 610                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 611         }
 612         else {
 613                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 614                              stat_mappings->tqsm[n], n);
 615                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 616         }
 617         return 0;
 618 }
 619
 620 static void
 621 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 622 {
 623         struct ixgbe_stat_mapping_registers *stat_mappings =
 624                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 626         int i;
 627
 628         /* write whatever was in stat mapping table to the NIC */
 629         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 630                 /* rx */
 631                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 632
 633                 /* tx */
 634                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 635         }
 636 }
 637
 638 static void
 639 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 640 {
 641         uint8_t i;
 642         struct ixgbe_dcb_tc_config *tc;
 643         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 644
 645         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 646         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 647         for (i = 0; i < dcb_max_tc; i++) {
 648                 tc = &dcb_config->tc_config[i];
 649                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 650                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 651                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 652                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 653                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 654                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 655                 tc->pfc = ixgbe_dcb_pfc_disabled;
 656         }
 657
 658         /* Initialize default user to priority mapping, UPx->TC0 */
 659         tc = &dcb_config->tc_config[0];
 660         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 661         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 662         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 663                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 664                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 665         }
 666         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 667         dcb_config->pfc_mode_enable = false;
 668         dcb_config->vt_mode = true;
 669         dcb_config->round_robin_enable = false;
 670         /* support all DCB capabilities in 82599 */
 671         dcb_config->support.capabilities = 0xFF;
 672
 673         /*we only support 4 Tcs for X540, X550 */
 674         if (hw->mac.type == ixgbe_mac_X540 ||
 675                 hw->mac.type == ixgbe_mac_X550 ||
 676                 hw->mac.type == ixgbe_mac_X550EM_x) {
 677                 dcb_config->num_tcs.pg_tcs = 4;
 678                 dcb_config->num_tcs.pfc_tcs = 4;
 679         }
 680 }
 681
 682 /*
 683  * Ensure that all locks are released before first NVM or PHY access
 684  */
 685 static void
 686 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 687 {
 688         uint16_t mask;
 689
 690         /*
 691          * Phy lock should not fail in this early stage. If this is the case,
 692          * it is due to an improper exit of the application.
 693          * So force the release of the faulty lock. Release of common lock
 694          * is done automatically by swfw_sync function.
 695          */
 696         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 697         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 698                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 699         }
 700         ixgbe_release_swfw_semaphore(hw, mask);
 701
 702         /*
 703          * These ones are more tricky since they are common to all ports; but
 704          * swfw_sync retries last long enough (1s) to be almost sure that if
 705          * lock can not be taken it is due to an improper lock of the
 706          * semaphore.
 707          */
 708         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 709         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 710                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 711         }
 712         ixgbe_release_swfw_semaphore(hw, mask);
 713 }
 714
 715 /*
 716  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 717  * It returns 0 on success.
 718  */
 719 static int
 720 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 721                      struct rte_eth_dev *eth_dev)
 722 {
 723         struct rte_pci_device *pci_dev;
 724         struct ixgbe_hw *hw =
 725                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 726         struct ixgbe_vfta * shadow_vfta =
 727                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 728         struct ixgbe_hwstrip *hwstrip =
 729                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 730         struct ixgbe_dcb_config *dcb_config =
 731                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 732         uint32_t ctrl_ext;
 733         uint16_t csum;
 734         int diag, i;
 735
 736         PMD_INIT_FUNC_TRACE();
 737
 738         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 739         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 740         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 741
 742         /*
 743          * For secondary processes, we don't initialise any further as primary
 744          * has already done this work. Only check we don't need a different
 745          * RX and TX function.
 746          */
 747         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 748                 struct igb_tx_queue *txq;
 749                 /* TX queue function in primary, set by last queue initialized
 750                  * Tx queue may not initialized by primary process */
 751                 if (eth_dev->data->tx_queues) {
 752                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 753                         set_tx_function(eth_dev, txq);
 754                 } else {
 755                         /* Use default TX function if we get here */
 756                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 757                                            "Using default TX function.");
 758                 }
 759
 760                 if (eth_dev->data->scattered_rx)
 761                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 762                 return 0;
 763         }
 764         pci_dev = eth_dev->pci_dev;
 765
 766         /* Vendor and Device ID need to be set before init of shared code */
 767         hw->device_id = pci_dev->id.device_id;
 768         hw->vendor_id = pci_dev->id.vendor_id;
 769         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 770         hw->allow_unsupported_sfp = 1;
 771
 772         /* Initialize the shared code (base driver) */
 773 #ifdef RTE_NIC_BYPASS
 774         diag = ixgbe_bypass_init_shared_code(hw);
 775 #else
 776         diag = ixgbe_init_shared_code(hw);
 777 #endif /* RTE_NIC_BYPASS */
 778
 779         if (diag != IXGBE_SUCCESS) {
 780                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 781                 return -EIO;
 782         }
 783
 784         /* pick up the PCI bus settings for reporting later */
 785         ixgbe_get_bus_info(hw);
 786
 787         /* Unlock any pending hardware semaphore */
 788         ixgbe_swfw_lock_reset(hw);
 789
 790         /* Initialize DCB configuration*/
 791         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 792         ixgbe_dcb_init(hw,dcb_config);
 793         /* Get Hardware Flow Control setting */
 794         hw->fc.requested_mode = ixgbe_fc_full;
 795         hw->fc.current_mode = ixgbe_fc_full;
 796         hw->fc.pause_time = IXGBE_FC_PAUSE;
 797         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 798                 hw->fc.low_water[i] = IXGBE_FC_LO;
 799                 hw->fc.high_water[i] = IXGBE_FC_HI;
 800         }
 801         hw->fc.send_xon = 1;
 802
 803         /* Make sure we have a good EEPROM before we read from it */
 804         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 805         if (diag != IXGBE_SUCCESS) {
 806                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 807                 return -EIO;
 808         }
 809
 810 #ifdef RTE_NIC_BYPASS
 811         diag = ixgbe_bypass_init_hw(hw);
 812 #else
 813         diag = ixgbe_init_hw(hw);
 814 #endif /* RTE_NIC_BYPASS */
 815
 816         /*
 817          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 818          * is called too soon after the kernel driver unbinding/binding occurs.
 819          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 820          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 821          * also called. See ixgbe_identify_phy_82599(). The reason for the
 822          * failure is not known, and only occuts when virtualisation features
 823          * are disabled in the bios. A delay of 100ms  was found to be enough by
 824          * trial-and-error, and is doubled to be safe.
 825          */
 826         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 827                 rte_delay_ms(200);
 828                 diag = ixgbe_init_hw(hw);
 829         }
 830
 831         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 832                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 833                     "LOM.  Please be aware there may be issues associated "
 834                     "with your hardware.");
 835                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 836                     "please contact your Intel or hardware representative "
 837                     "who provided you with this hardware.");
 838         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 839                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 840         if (diag) {
 841                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 842                 return -EIO;
 843         }
 844
 845         /* disable interrupt */
 846         ixgbe_disable_intr(hw);
 847
 848         /* reset mappings for queue statistics hw counters*/
 849         ixgbe_reset_qstat_mappings(hw);
 850
 851         /* Allocate memory for storing MAC addresses */
 852         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 853                         hw->mac.num_rar_entries, 0);
 854         if (eth_dev->data->mac_addrs == NULL) {
 855                 PMD_INIT_LOG(ERR,
 856                         "Failed to allocate %u bytes needed to store "
 857                         "MAC addresses",
 858                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 859                 return -ENOMEM;
 860         }
 861         /* Copy the permanent MAC address */
 862         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 863                         &eth_dev->data->mac_addrs[0]);
 864
 865         /* Allocate memory for storing hash filter MAC addresses */
 866         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 867                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 868         if (eth_dev->data->hash_mac_addrs == NULL) {
 869                 PMD_INIT_LOG(ERR,
 870                         "Failed to allocate %d bytes needed to store MAC addresses",
 871                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 872                 return -ENOMEM;
 873         }
 874
 875         /* initialize the vfta */
 876         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 877
 878         /* initialize the hw strip bitmap*/
 879         memset(hwstrip, 0, sizeof(*hwstrip));
 880
 881         /* initialize PF if max_vfs not zero */
 882         ixgbe_pf_host_init(eth_dev);
 883
 884         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 885         /* let hardware know driver is loaded */
 886         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 887         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 888         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 889         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 890         IXGBE_WRITE_FLUSH(hw);
 891
 892         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 893                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 894                              (int) hw->mac.type, (int) hw->phy.type,
 895                              (int) hw->phy.sfp_type);
 896         else
 897                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 898                              (int) hw->mac.type, (int) hw->phy.type);
 899
 900         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 901                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 902                         pci_dev->id.device_id);
 903
 904         rte_intr_callback_register(&(pci_dev->intr_handle),
 905                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 906
 907         /* enable uio intr after callback register */
 908         rte_intr_enable(&(pci_dev->intr_handle));
 909
 910         /* enable support intr */
 911         ixgbe_enable_intr(eth_dev);
 912
 913         return 0;
 914 }
 915
 916
 917 /*
 918  * Negotiate mailbox API version with the PF.
 919  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 920  * Then we try to negotiate starting with the most recent one.
 921  * If all negotiation attempts fail, then we will proceed with
 922  * the default one (ixgbe_mbox_api_10).
 923  */
 924 static void
 925 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 926 {
 927         int32_t i;
 928
 929         /* start with highest supported, proceed down */
 930         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 931                 ixgbe_mbox_api_11,
 932                 ixgbe_mbox_api_10,
 933         };
 934
 935         for (i = 0;
 936                         i != RTE_DIM(sup_ver) &&
 937                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 938                         i++)
 939                 ;
 940 }
 941
 942 static void
 943 generate_random_mac_addr(struct ether_addr *mac_addr)
 944 {
 945         uint64_t random;
 946
 947         /* Set Organizationally Unique Identifier (OUI) prefix. */
 948         mac_addr->addr_bytes[0] = 0x00;
 949         mac_addr->addr_bytes[1] = 0x09;
 950         mac_addr->addr_bytes[2] = 0xC0;
 951         /* Force indication of locally assigned MAC address. */
 952         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 953         /* Generate the last 3 bytes of the MAC address with a random number. */
 954         random = rte_rand();
 955         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 956 }
 957
 958 /*
 959  * Virtual Function device init
 960  */
 961 static int
 962 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 963                      struct rte_eth_dev *eth_dev)
 964 {
 965         int diag;
 966         uint32_t tc, tcs;
 967         struct rte_pci_device *pci_dev;
 968         struct ixgbe_hw *hw =
 969                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 970         struct ixgbe_vfta * shadow_vfta =
 971                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 972         struct ixgbe_hwstrip *hwstrip =
 973                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 974         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 975
 976         PMD_INIT_FUNC_TRACE();
 977
 978         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 979         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 980         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 981
 982         /* for secondary processes, we don't initialise any further as primary
 983          * has already done this work. Only check we don't need a different
 984          * RX function */
 985         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 986                 if (eth_dev->data->scattered_rx)
 987                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 988                 return 0;
 989         }
 990
 991         pci_dev = eth_dev->pci_dev;
 992
 993         hw->device_id = pci_dev->id.device_id;
 994         hw->vendor_id = pci_dev->id.vendor_id;
 995         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 996
 997         /* initialize the vfta */
 998         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 999
1000         /* initialize the hw strip bitmap*/
1001         memset(hwstrip, 0, sizeof(*hwstrip));
1002
1003         /* Initialize the shared code (base driver) */
1004         diag = ixgbe_init_shared_code(hw);
1005         if (diag != IXGBE_SUCCESS) {
1006                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1007                 return -EIO;
1008         }
1009
1010         /* init_mailbox_params */
1011         hw->mbx.ops.init_params(hw);
1012
1013         /* Disable the interrupts for VF */
1014         ixgbevf_intr_disable(hw);
1015
1016         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1017         diag = hw->mac.ops.reset_hw(hw);
1018
1019         /*
1020          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1021          * the underlying PF driver has not assigned a MAC address to the VF.
1022          * In this case, assign a random MAC address.
1023          */
1024         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1025                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1026                 return (diag);
1027         }
1028
1029         /* negotiate mailbox API version to use with the PF. */
1030         ixgbevf_negotiate_api(hw);
1031
1032         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1033         ixgbevf_get_queues(hw, &tcs, &tc);
1034
1035         /* Allocate memory for storing MAC addresses */
1036         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1037                         hw->mac.num_rar_entries, 0);
1038         if (eth_dev->data->mac_addrs == NULL) {
1039                 PMD_INIT_LOG(ERR,
1040                         "Failed to allocate %u bytes needed to store "
1041                         "MAC addresses",
1042                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1043                 return -ENOMEM;
1044         }
1045
1046         /* Generate a random MAC address, if none was assigned by PF. */
1047         if (is_zero_ether_addr(perm_addr)) {
1048                 generate_random_mac_addr(perm_addr);
1049                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1050                 if (diag) {
1051                         rte_free(eth_dev->data->mac_addrs);
1052                         eth_dev->data->mac_addrs = NULL;
1053                         return diag;
1054                 }
1055                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1056                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1057                              "%02x:%02x:%02x:%02x:%02x:%02x",
1058                              perm_addr->addr_bytes[0],
1059                              perm_addr->addr_bytes[1],
1060                              perm_addr->addr_bytes[2],
1061                              perm_addr->addr_bytes[3],
1062                              perm_addr->addr_bytes[4],
1063                              perm_addr->addr_bytes[5]);
1064         }
1065
1066         /* Copy the permanent MAC address */
1067         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1068
1069         /* reset the hardware with the new settings */
1070         diag = hw->mac.ops.start_hw(hw);
1071         switch (diag) {
1072                 case  0:
1073                         break;
1074
1075                 default:
1076                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1077                         return (-EIO);
1078         }
1079
1080         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1081                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1082                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1083
1084         return 0;
1085 }
1086
1087 static struct eth_driver rte_ixgbe_pmd = {
1088         {
1089                 .name = "rte_ixgbe_pmd",
1090                 .id_table = pci_id_ixgbe_map,
1091                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1092         },
1093         .eth_dev_init = eth_ixgbe_dev_init,
1094         .dev_private_size = sizeof(struct ixgbe_adapter),
1095 };
1096
1097 /*
1098  * virtual function driver struct
1099  */
1100 static struct eth_driver rte_ixgbevf_pmd = {
1101         {
1102                 .name = "rte_ixgbevf_pmd",
1103                 .id_table = pci_id_ixgbevf_map,
1104                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1105         },
1106         .eth_dev_init = eth_ixgbevf_dev_init,
1107         .dev_private_size = sizeof(struct ixgbe_adapter),
1108 };
1109
1110 /*
1111  * Driver initialization routine.
1112  * Invoked once at EAL init time.
1113  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1114  */
1115 static int
1116 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1117 {
1118         PMD_INIT_FUNC_TRACE();
1119
1120         rte_eth_driver_register(&rte_ixgbe_pmd);
1121         return 0;
1122 }
1123
1124 /*
1125  * VF Driver initialization routine.
1126  * Invoked one at EAL init time.
1127  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1128  */
1129 static int
1130 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1131 {
1132         PMD_INIT_FUNC_TRACE();
1133
1134         rte_eth_driver_register(&rte_ixgbevf_pmd);
1135         return (0);
1136 }
1137
1138 static int
1139 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1140 {
1141         struct ixgbe_hw *hw =
1142                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1143         struct ixgbe_vfta * shadow_vfta =
1144                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1145         uint32_t vfta;
1146         uint32_t vid_idx;
1147         uint32_t vid_bit;
1148
1149         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1150         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1151         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1152         if (on)
1153                 vfta |= vid_bit;
1154         else
1155                 vfta &= ~vid_bit;
1156         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1157
1158         /* update local VFTA copy */
1159         shadow_vfta->vfta[vid_idx] = vfta;
1160
1161         return 0;
1162 }
1163
1164 static void
1165 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1166 {
1167         if (on)
1168                 ixgbe_vlan_hw_strip_enable(dev, queue);
1169         else
1170                 ixgbe_vlan_hw_strip_disable(dev, queue);
1171 }
1172
1173 static void
1174 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1175 {
1176         struct ixgbe_hw *hw =
1177                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178
1179         /* Only the high 16-bits is valid */
1180         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1181 }
1182
1183 void
1184 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1185 {
1186         struct ixgbe_hw *hw =
1187                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1188         uint32_t vlnctrl;
1189
1190         PMD_INIT_FUNC_TRACE();
1191
1192         /* Filter Table Disable */
1193         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1194         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1195
1196         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1197 }
1198
1199 void
1200 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1201 {
1202         struct ixgbe_hw *hw =
1203                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204         struct ixgbe_vfta * shadow_vfta =
1205                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1206         uint32_t vlnctrl;
1207         uint16_t i;
1208
1209         PMD_INIT_FUNC_TRACE();
1210
1211         /* Filter Table Enable */
1212         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1213         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1214         vlnctrl |= IXGBE_VLNCTRL_VFE;
1215
1216         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1217
1218         /* write whatever is in local vfta copy */
1219         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1220                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1221 }
1222
1223 static void
1224 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1225 {
1226         struct ixgbe_hwstrip *hwstrip =
1227                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1228
1229         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1230                 return;
1231
1232         if (on)
1233                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1234         else
1235                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1236 }
1237
1238 static void
1239 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1240 {
1241         struct ixgbe_hw *hw =
1242                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1243         uint32_t ctrl;
1244
1245         PMD_INIT_FUNC_TRACE();
1246
1247         if (hw->mac.type == ixgbe_mac_82598EB) {
1248                 /* No queue level support */
1249                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1250                 return;
1251         }
1252         else {
1253                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1254                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1255                 ctrl &= ~IXGBE_RXDCTL_VME;
1256                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1257         }
1258         /* record those setting for HW strip per queue */
1259         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1260 }
1261
1262 static void
1263 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1264 {
1265         struct ixgbe_hw *hw =
1266                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1267         uint32_t ctrl;
1268
1269         PMD_INIT_FUNC_TRACE();
1270
1271         if (hw->mac.type == ixgbe_mac_82598EB) {
1272                 /* No queue level supported */
1273                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1274                 return;
1275         }
1276         else {
1277                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1278                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1279                 ctrl |= IXGBE_RXDCTL_VME;
1280                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1281         }
1282         /* record those setting for HW strip per queue */
1283         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1284 }
1285
1286 void
1287 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1288 {
1289         struct ixgbe_hw *hw =
1290                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291         uint32_t ctrl;
1292         uint16_t i;
1293
1294         PMD_INIT_FUNC_TRACE();
1295
1296         if (hw->mac.type == ixgbe_mac_82598EB) {
1297                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1298                 ctrl &= ~IXGBE_VLNCTRL_VME;
1299                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1300         }
1301         else {
1302                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1303                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1304                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1305                         ctrl &= ~IXGBE_RXDCTL_VME;
1306                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1307
1308                         /* record those setting for HW strip per queue */
1309                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1310                 }
1311         }
1312 }
1313
1314 void
1315 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1316 {
1317         struct ixgbe_hw *hw =
1318                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1319         uint32_t ctrl;
1320         uint16_t i;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         if (hw->mac.type == ixgbe_mac_82598EB) {
1325                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1326                 ctrl |= IXGBE_VLNCTRL_VME;
1327                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1328         }
1329         else {
1330                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1331                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1332                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1333                         ctrl |= IXGBE_RXDCTL_VME;
1334                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1335
1336                         /* record those setting for HW strip per queue */
1337                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1338                 }
1339         }
1340 }
1341
1342 static void
1343 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1344 {
1345         struct ixgbe_hw *hw =
1346                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347         uint32_t ctrl;
1348
1349         PMD_INIT_FUNC_TRACE();
1350
1351         /* DMATXCTRL: Geric Double VLAN Disable */
1352         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1353         ctrl &= ~IXGBE_DMATXCTL_GDV;
1354         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1355
1356         /* CTRL_EXT: Global Double VLAN Disable */
1357         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1358         ctrl &= ~IXGBE_EXTENDED_VLAN;
1359         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1360
1361 }
1362
1363 static void
1364 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1365 {
1366         struct ixgbe_hw *hw =
1367                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368         uint32_t ctrl;
1369
1370         PMD_INIT_FUNC_TRACE();
1371
1372         /* DMATXCTRL: Geric Double VLAN Enable */
1373         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1374         ctrl |= IXGBE_DMATXCTL_GDV;
1375         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1376
1377         /* CTRL_EXT: Global Double VLAN Enable */
1378         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1379         ctrl |= IXGBE_EXTENDED_VLAN;
1380         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1381
1382         /*
1383          * VET EXT field in the EXVET register = 0x8100 by default
1384          * So no need to change. Same to VT field of DMATXCTL register
1385          */
1386 }
1387
1388 static void
1389 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1390 {
1391         if(mask & ETH_VLAN_STRIP_MASK){
1392                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1393                         ixgbe_vlan_hw_strip_enable_all(dev);
1394                 else
1395                         ixgbe_vlan_hw_strip_disable_all(dev);
1396         }
1397
1398         if(mask & ETH_VLAN_FILTER_MASK){
1399                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1400                         ixgbe_vlan_hw_filter_enable(dev);
1401                 else
1402                         ixgbe_vlan_hw_filter_disable(dev);
1403         }
1404
1405         if(mask & ETH_VLAN_EXTEND_MASK){
1406                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1407                         ixgbe_vlan_hw_extend_enable(dev);
1408                 else
1409                         ixgbe_vlan_hw_extend_disable(dev);
1410         }
1411 }
1412
1413 static void
1414 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1415 {
1416         struct ixgbe_hw *hw =
1417                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1419         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1420         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1421         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1422 }
1423
1424 static int
1425 ixgbe_dev_configure(struct rte_eth_dev *dev)
1426 {
1427         struct ixgbe_interrupt *intr =
1428                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1429
1430         PMD_INIT_FUNC_TRACE();
1431
1432         /* set flag to update link status after init */
1433         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1434
1435         return 0;
1436 }
1437
1438 /*
1439  * Configure device link speed and setup link.
1440  * It returns 0 on success.
1441  */
1442 static int
1443 ixgbe_dev_start(struct rte_eth_dev *dev)
1444 {
1445         struct ixgbe_hw *hw =
1446                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1447         struct ixgbe_vf_info *vfinfo =
1448                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1449         int err, link_up = 0, negotiate = 0;
1450         uint32_t speed = 0;
1451         int mask = 0;
1452         int status;
1453         uint16_t vf, idx;
1454
1455         PMD_INIT_FUNC_TRACE();
1456
1457         /* IXGBE devices don't support half duplex */
1458         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1459                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1460                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1461                              dev->data->dev_conf.link_duplex,
1462                              dev->data->port_id);
1463                 return -EINVAL;
1464         }
1465
1466         /* stop adapter */
1467         hw->adapter_stopped = FALSE;
1468         ixgbe_stop_adapter(hw);
1469
1470         /* reinitialize adapter
1471          * this calls reset and start */
1472         status = ixgbe_pf_reset_hw(hw);
1473         if (status != 0)
1474                 return -1;
1475         hw->mac.ops.start_hw(hw);
1476         hw->mac.get_link_status = true;
1477
1478         /* configure PF module if SRIOV enabled */
1479         ixgbe_pf_host_configure(dev);
1480
1481         /* initialize transmission unit */
1482         ixgbe_dev_tx_init(dev);
1483
1484         /* This can fail when allocating mbufs for descriptor rings */
1485         err = ixgbe_dev_rx_init(dev);
1486         if (err) {
1487                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1488                 goto error;
1489         }
1490
1491         err = ixgbe_dev_rxtx_start(dev);
1492         if (err < 0) {
1493                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1494                 goto error;
1495         }
1496
1497         /* Skip link setup if loopback mode is enabled for 82599. */
1498         if (hw->mac.type == ixgbe_mac_82599EB &&
1499                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1500                 goto skip_link_setup;
1501
1502         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1503                 err = hw->mac.ops.setup_sfp(hw);
1504                 if (err)
1505                         goto error;
1506         }
1507
1508         /* Turn on the laser */
1509         ixgbe_enable_tx_laser(hw);
1510
1511         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1512         if (err)
1513                 goto error;
1514         dev->data->dev_link.link_status = link_up;
1515
1516         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1517         if (err)
1518                 goto error;
1519
1520         switch(dev->data->dev_conf.link_speed) {
1521         case ETH_LINK_SPEED_AUTONEG:
1522                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1523                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1524                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1525                 break;
1526         case ETH_LINK_SPEED_100:
1527                 /*
1528                  * Invalid for 82598 but error will be detected by
1529                  * ixgbe_setup_link()
1530                  */
1531                 speed = IXGBE_LINK_SPEED_100_FULL;
1532                 break;
1533         case ETH_LINK_SPEED_1000:
1534                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1535                 break;
1536         case ETH_LINK_SPEED_10000:
1537                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1538                 break;
1539         default:
1540                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1541                              dev->data->dev_conf.link_speed,
1542                              dev->data->port_id);
1543                 goto error;
1544         }
1545
1546         err = ixgbe_setup_link(hw, speed, link_up);
1547         if (err)
1548                 goto error;
1549
1550 skip_link_setup:
1551
1552         /* check if lsc interrupt is enabled */
1553         if (dev->data->dev_conf.intr_conf.lsc != 0)
1554                 ixgbe_dev_lsc_interrupt_setup(dev);
1555
1556         /* resume enabled intr since hw reset */
1557         ixgbe_enable_intr(dev);
1558
1559         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1560                 ETH_VLAN_EXTEND_MASK;
1561         ixgbe_vlan_offload_set(dev, mask);
1562
1563         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1564                 /* Enable vlan filtering for VMDq */
1565                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1566         }
1567
1568         /* Configure DCB hw */
1569         ixgbe_configure_dcb(dev);
1570
1571         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1572                 err = ixgbe_fdir_configure(dev);
1573                 if (err)
1574                         goto error;
1575         }
1576
1577         /* Restore vf rate limit */
1578         if (vfinfo != NULL) {
1579                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1580                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1581                                 if (vfinfo[vf].tx_rate[idx] != 0)
1582                                         ixgbe_set_vf_rate_limit(dev, vf,
1583                                                 vfinfo[vf].tx_rate[idx],
1584                                                 1 << idx);
1585         }
1586
1587         ixgbe_restore_statistics_mapping(dev);
1588
1589         return (0);
1590
1591 error:
1592         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1593         ixgbe_dev_clear_queues(dev);
1594         return -EIO;
1595 }
1596
1597 /*
1598  * Stop device: disable rx and tx functions to allow for reconfiguring.
1599  */
1600 static void
1601 ixgbe_dev_stop(struct rte_eth_dev *dev)
1602 {
1603         struct rte_eth_link link;
1604         struct ixgbe_hw *hw =
1605                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606         struct ixgbe_vf_info *vfinfo =
1607                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1608         int vf;
1609
1610         PMD_INIT_FUNC_TRACE();
1611
1612         /* disable interrupts */
1613         ixgbe_disable_intr(hw);
1614
1615         /* reset the NIC */
1616         ixgbe_pf_reset_hw(hw);
1617         hw->adapter_stopped = FALSE;
1618
1619         /* stop adapter */
1620         ixgbe_stop_adapter(hw);
1621
1622         for (vf = 0; vfinfo != NULL &&
1623                      vf < dev->pci_dev->max_vfs; vf++)
1624                 vfinfo[vf].clear_to_send = false;
1625
1626         /* Turn off the laser */
1627         ixgbe_disable_tx_laser(hw);
1628
1629         ixgbe_dev_clear_queues(dev);
1630
1631         /* Clear stored conf */
1632         dev->data->scattered_rx = 0;
1633
1634         /* Clear recorded link status */
1635         memset(&link, 0, sizeof(link));
1636         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1637 }
1638
1639 /*
1640  * Set device link up: enable tx laser.
1641  */
1642 static int
1643 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1644 {
1645         struct ixgbe_hw *hw =
1646                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647         if (hw->mac.type == ixgbe_mac_82599EB) {
1648 #ifdef RTE_NIC_BYPASS
1649                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1650                         /* Not suported in bypass mode */
1651                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1652                                      "by device id 0x%x", hw->device_id);
1653                         return -ENOTSUP;
1654                 }
1655 #endif
1656                 /* Turn on the laser */
1657                 ixgbe_enable_tx_laser(hw);
1658                 return 0;
1659         }
1660
1661         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1662                      hw->device_id);
1663         return -ENOTSUP;
1664 }
1665
1666 /*
1667  * Set device link down: disable tx laser.
1668  */
1669 static int
1670 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1671 {
1672         struct ixgbe_hw *hw =
1673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         if (hw->mac.type == ixgbe_mac_82599EB) {
1675 #ifdef RTE_NIC_BYPASS
1676                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1677                         /* Not suported in bypass mode */
1678                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1679                                      "by device id 0x%x", hw->device_id);
1680                         return -ENOTSUP;
1681                 }
1682 #endif
1683                 /* Turn off the laser */
1684                 ixgbe_disable_tx_laser(hw);
1685                 return 0;
1686         }
1687
1688         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1689                      hw->device_id);
1690         return -ENOTSUP;
1691 }
1692
1693 /*
1694  * Reest and stop device.
1695  */
1696 static void
1697 ixgbe_dev_close(struct rte_eth_dev *dev)
1698 {
1699         struct ixgbe_hw *hw =
1700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701
1702         PMD_INIT_FUNC_TRACE();
1703
1704         ixgbe_pf_reset_hw(hw);
1705
1706         ixgbe_dev_stop(dev);
1707         hw->adapter_stopped = 1;
1708
1709         ixgbe_disable_pcie_master(hw);
1710
1711         /* reprogram the RAR[0] in case user changed it. */
1712         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1713 }
1714
1715 /*
1716  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1717  */
1718 static void
1719 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1720 {
1721         struct ixgbe_hw *hw =
1722                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723         struct ixgbe_hw_stats *hw_stats =
1724                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1725         uint32_t bprc, lxon, lxoff, total;
1726         uint64_t total_missed_rx, total_qbrc, total_qprc;
1727         unsigned i;
1728
1729         total_missed_rx = 0;
1730         total_qbrc = 0;
1731         total_qprc = 0;
1732
1733         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1734         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1735         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1736         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1737
1738         for (i = 0; i < 8; i++) {
1739                 uint32_t mp;
1740                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1741                 /* global total per queue */
1742                 hw_stats->mpc[i] += mp;
1743                 /* Running comprehensive total for stats display */
1744                 total_missed_rx += hw_stats->mpc[i];
1745                 if (hw->mac.type == ixgbe_mac_82598EB)
1746                         hw_stats->rnbc[i] +=
1747                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1748                 hw_stats->pxontxc[i] +=
1749                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1750                 hw_stats->pxonrxc[i] +=
1751                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1752                 hw_stats->pxofftxc[i] +=
1753                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1754                 hw_stats->pxoffrxc[i] +=
1755                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1756                 hw_stats->pxon2offc[i] +=
1757                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1758         }
1759         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1760                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1761                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1762                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1763                 hw_stats->qbrc[i] +=
1764                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1765                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1766                 hw_stats->qbtc[i] +=
1767                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1768                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1769
1770                 total_qprc += hw_stats->qprc[i];
1771                 total_qbrc += hw_stats->qbrc[i];
1772         }
1773         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1774         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1775         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1776
1777         /* Note that gprc counts missed packets */
1778         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1779
1780         if (hw->mac.type != ixgbe_mac_82598EB) {
1781                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1782                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1783                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1784                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1785                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1786                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1787                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1788                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1789         } else {
1790                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1791                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1792                 /* 82598 only has a counter in the high register */
1793                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1794                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1795                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1796         }
1797
1798         /*
1799          * Workaround: mprc hardware is incorrectly counting
1800          * broadcasts, so for now we subtract those.
1801          */
1802         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1803         hw_stats->bprc += bprc;
1804         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1805         if (hw->mac.type == ixgbe_mac_82598EB)
1806                 hw_stats->mprc -= bprc;
1807
1808         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1809         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1810         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1811         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1812         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1813         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1814
1815         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1816         hw_stats->lxontxc += lxon;
1817         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1818         hw_stats->lxofftxc += lxoff;
1819         total = lxon + lxoff;
1820
1821         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1822         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1823         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1824         hw_stats->gptc -= total;
1825         hw_stats->mptc -= total;
1826         hw_stats->ptc64 -= total;
1827         hw_stats->gotc -= total * ETHER_MIN_LEN;
1828
1829         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1830         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1831         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1832         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1833         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1834         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1835         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1836         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1837         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1838         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1839         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1840         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1841         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1842         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1843         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1844         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1845         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1846         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1847         /* Only read FCOE on 82599 */
1848         if (hw->mac.type != ixgbe_mac_82598EB) {
1849                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1850                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1851                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1852                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1853                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1854         }
1855
1856         if (stats == NULL)
1857                 return;
1858
1859         /* Fill out the rte_eth_stats statistics structure */
1860         stats->ipackets = total_qprc;
1861         stats->ibytes = total_qbrc;
1862         stats->opackets = hw_stats->gptc;
1863         stats->obytes = hw_stats->gotc;
1864         stats->imcasts = hw_stats->mprc;
1865
1866         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1867                 stats->q_ipackets[i] = hw_stats->qprc[i];
1868                 stats->q_opackets[i] = hw_stats->qptc[i];
1869                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1870                 stats->q_obytes[i] = hw_stats->qbtc[i];
1871                 stats->q_errors[i] = hw_stats->qprdc[i];
1872         }
1873
1874         /* Rx Errors */
1875         stats->ibadcrc  = hw_stats->crcerrs;
1876         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1877         stats->imissed  = total_missed_rx;
1878         stats->ierrors  = stats->ibadcrc +
1879                           stats->ibadlen +
1880                           stats->imissed +
1881                           hw_stats->illerrc + hw_stats->errbc;
1882
1883         /* Tx Errors */
1884         stats->oerrors  = 0;
1885
1886         /* XON/XOFF pause frames */
1887         stats->tx_pause_xon  = hw_stats->lxontxc;
1888         stats->rx_pause_xon  = hw_stats->lxonrxc;
1889         stats->tx_pause_xoff = hw_stats->lxofftxc;
1890         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1891
1892         /* Flow Director Stats registers */
1893         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1894         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1895         stats->fdirmatch = hw_stats->fdirmatch;
1896         stats->fdirmiss = hw_stats->fdirmiss;
1897 }
1898
1899 static void
1900 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1901 {
1902         struct ixgbe_hw_stats *stats =
1903                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1904
1905         /* HW registers are cleared on read */
1906         ixgbe_dev_stats_get(dev, NULL);
1907
1908         /* Reset software totals */
1909         memset(stats, 0, sizeof(*stats));
1910 }
1911
1912 static void
1913 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1914 {
1915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1917                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1918
1919         /* Good Rx packet, include VF loopback */
1920         UPDATE_VF_STAT(IXGBE_VFGPRC,
1921             hw_stats->last_vfgprc, hw_stats->vfgprc);
1922
1923         /* Good Rx octets, include VF loopback */
1924         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1925             hw_stats->last_vfgorc, hw_stats->vfgorc);
1926
1927         /* Good Tx packet, include VF loopback */
1928         UPDATE_VF_STAT(IXGBE_VFGPTC,
1929             hw_stats->last_vfgptc, hw_stats->vfgptc);
1930
1931         /* Good Tx octets, include VF loopback */
1932         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1933             hw_stats->last_vfgotc, hw_stats->vfgotc);
1934
1935         /* Rx Multicst Packet */
1936         UPDATE_VF_STAT(IXGBE_VFMPRC,
1937             hw_stats->last_vfmprc, hw_stats->vfmprc);
1938
1939         if (stats == NULL)
1940                 return;
1941
1942         stats->ipackets = hw_stats->vfgprc;
1943         stats->ibytes = hw_stats->vfgorc;
1944         stats->opackets = hw_stats->vfgptc;
1945         stats->obytes = hw_stats->vfgotc;
1946         stats->imcasts = hw_stats->vfmprc;
1947 }
1948
1949 static void
1950 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1951 {
1952         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1953                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1954
1955         /* Sync HW register to the last stats */
1956         ixgbevf_dev_stats_get(dev, NULL);
1957
1958         /* reset HW current stats*/
1959         hw_stats->vfgprc = 0;
1960         hw_stats->vfgorc = 0;
1961         hw_stats->vfgptc = 0;
1962         hw_stats->vfgotc = 0;
1963         hw_stats->vfmprc = 0;
1964
1965 }
1966
1967 static void
1968 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1969 {
1970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1971
1972         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1973         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1974         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1975         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1976         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1977         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1978         dev_info->max_vfs = dev->pci_dev->max_vfs;
1979         if (hw->mac.type == ixgbe_mac_82598EB)
1980                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1981         else
1982                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1983         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1984         dev_info->rx_offload_capa =
1985                 DEV_RX_OFFLOAD_VLAN_STRIP |
1986                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1987                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1988                 DEV_RX_OFFLOAD_TCP_CKSUM;
1989         dev_info->tx_offload_capa =
1990                 DEV_TX_OFFLOAD_VLAN_INSERT |
1991                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1992                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1993                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1994                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1995                 DEV_TX_OFFLOAD_TCP_TSO;
1996
1997         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1998                 .rx_thresh = {
1999                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2000                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2001                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2002                 },
2003                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2004                 .rx_drop_en = 0,
2005         };
2006
2007         dev_info->default_txconf = (struct rte_eth_txconf) {
2008                 .tx_thresh = {
2009                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2010                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2011                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2012                 },
2013                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2014                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2015                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2016                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2017         };
2018         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2019 }
2020
2021 static void
2022 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2023                      struct rte_eth_dev_info *dev_info)
2024 {
2025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2026
2027         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2028         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2029         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2030         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2031         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2032         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2033         dev_info->max_vfs = dev->pci_dev->max_vfs;
2034         if (hw->mac.type == ixgbe_mac_82598EB)
2035                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2036         else
2037                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2038         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2039                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2040                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2041                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2042         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2043                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2044                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2045                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2046                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2047
2048         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2049                 .rx_thresh = {
2050                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2051                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2052                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2053                 },
2054                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2055                 .rx_drop_en = 0,
2056         };
2057
2058         dev_info->default_txconf = (struct rte_eth_txconf) {
2059                 .tx_thresh = {
2060                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2061                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2062                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2063                 },
2064                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2065                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2066                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2067                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2068         };
2069 }
2070
2071 /* return 0 means link status changed, -1 means not changed */
2072 static int
2073 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2074 {
2075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2076         struct rte_eth_link link, old;
2077         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2078         int link_up;
2079         int diag;
2080
2081         link.link_status = 0;
2082         link.link_speed = 0;
2083         link.link_duplex = 0;
2084         memset(&old, 0, sizeof(old));
2085         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2086
2087         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2088         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2089                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2090         else
2091                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2092         if (diag != 0) {
2093                 link.link_speed = ETH_LINK_SPEED_100;
2094                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2095                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2096                 if (link.link_status == old.link_status)
2097                         return -1;
2098                 return 0;
2099         }
2100
2101         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2102             !hw->mac.get_link_status) {
2103                 memcpy(&link, &old, sizeof(link));
2104                 return -1;
2105         }
2106
2107         if (link_up == 0) {
2108                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2109                 if (link.link_status == old.link_status)
2110                         return -1;
2111                 return 0;
2112         }
2113         link.link_status = 1;
2114         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2115
2116         switch (link_speed) {
2117         default:
2118         case IXGBE_LINK_SPEED_UNKNOWN:
2119                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2120                 link.link_speed = ETH_LINK_SPEED_100;
2121                 break;
2122
2123         case IXGBE_LINK_SPEED_100_FULL:
2124                 link.link_speed = ETH_LINK_SPEED_100;
2125                 break;
2126
2127         case IXGBE_LINK_SPEED_1GB_FULL:
2128                 link.link_speed = ETH_LINK_SPEED_1000;
2129                 break;
2130
2131         case IXGBE_LINK_SPEED_10GB_FULL:
2132                 link.link_speed = ETH_LINK_SPEED_10000;
2133                 break;
2134         }
2135         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2136
2137         if (link.link_status == old.link_status)
2138                 return -1;
2139
2140         return 0;
2141 }
2142
2143 static void
2144 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2145 {
2146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2147         uint32_t fctrl;
2148
2149         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2150         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2151         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2152 }
2153
2154 static void
2155 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2156 {
2157         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158         uint32_t fctrl;
2159
2160         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2161         fctrl &= (~IXGBE_FCTRL_UPE);
2162         if (dev->data->all_multicast == 1)
2163                 fctrl |= IXGBE_FCTRL_MPE;
2164         else
2165                 fctrl &= (~IXGBE_FCTRL_MPE);
2166         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2167 }
2168
2169 static void
2170 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2171 {
2172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         uint32_t fctrl;
2174
2175         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2176         fctrl |= IXGBE_FCTRL_MPE;
2177         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2178 }
2179
2180 static void
2181 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2182 {
2183         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2184         uint32_t fctrl;
2185
2186         if (dev->data->promiscuous == 1)
2187                 return; /* must remain in all_multicast mode */
2188
2189         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2190         fctrl &= (~IXGBE_FCTRL_MPE);
2191         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2192 }
2193
2194 /**
2195  * It clears the interrupt causes and enables the interrupt.
2196  * It will be called once only during nic initialized.
2197  *
2198  * @param dev
2199  *  Pointer to struct rte_eth_dev.
2200  *
2201  * @return
2202  *  - On success, zero.
2203  *  - On failure, a negative value.
2204  */
2205 static int
2206 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2207 {
2208         struct ixgbe_interrupt *intr =
2209                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2210
2211         ixgbe_dev_link_status_print(dev);
2212         intr->mask |= IXGBE_EICR_LSC;
2213
2214         return 0;
2215 }
2216
2217 /*
2218  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2219  *
2220  * @param dev
2221  *  Pointer to struct rte_eth_dev.
2222  *
2223  * @return
2224  *  - On success, zero.
2225  *  - On failure, a negative value.
2226  */
2227 static int
2228 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2229 {
2230         uint32_t eicr;
2231         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232         struct ixgbe_interrupt *intr =
2233                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2234
2235         /* clear all cause mask */
2236         ixgbe_disable_intr(hw);
2237
2238         /* read-on-clear nic registers here */
2239         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2240         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2241
2242         intr->flags = 0;
2243         if (eicr & IXGBE_EICR_LSC) {
2244                 /* set flag for async link update */
2245                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2246         }
2247
2248         if (eicr & IXGBE_EICR_MAILBOX)
2249                 intr->flags |= IXGBE_FLAG_MAILBOX;
2250
2251         return 0;
2252 }
2253
2254 /**
2255  * It gets and then prints the link status.
2256  *
2257  * @param dev
2258  *  Pointer to struct rte_eth_dev.
2259  *
2260  * @return
2261  *  - On success, zero.
2262  *  - On failure, a negative value.
2263  */
2264 static void
2265 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2266 {
2267         struct rte_eth_link link;
2268
2269         memset(&link, 0, sizeof(link));
2270         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2271         if (link.link_status) {
2272                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2273                                         (int)(dev->data->port_id),
2274                                         (unsigned)link.link_speed,
2275                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2276                                         "full-duplex" : "half-duplex");
2277         } else {
2278                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2279                                 (int)(dev->data->port_id));
2280         }
2281         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2282                                 dev->pci_dev->addr.domain,
2283                                 dev->pci_dev->addr.bus,
2284                                 dev->pci_dev->addr.devid,
2285                                 dev->pci_dev->addr.function);
2286 }
2287
2288 /*
2289  * It executes link_update after knowing an interrupt occurred.
2290  *
2291  * @param dev
2292  *  Pointer to struct rte_eth_dev.
2293  *
2294  * @return
2295  *  - On success, zero.
2296  *  - On failure, a negative value.
2297  */
2298 static int
2299 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2300 {
2301         struct ixgbe_interrupt *intr =
2302                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2303         int64_t timeout;
2304         struct rte_eth_link link;
2305         int intr_enable_delay = false;
2306
2307         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2308
2309         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2310                 ixgbe_pf_mbx_process(dev);
2311                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2312         }
2313
2314         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2315                 /* get the link status before link update, for predicting later */
2316                 memset(&link, 0, sizeof(link));
2317                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2318
2319                 ixgbe_dev_link_update(dev, 0);
2320
2321                 /* likely to up */
2322                 if (!link.link_status)
2323                         /* handle it 1 sec later, wait it being stable */
2324                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2325                 /* likely to down */
2326                 else
2327                         /* handle it 4 sec later, wait it being stable */
2328                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2329
2330                 ixgbe_dev_link_status_print(dev);
2331
2332                 intr_enable_delay = true;
2333         }
2334
2335         if (intr_enable_delay) {
2336                 if (rte_eal_alarm_set(timeout * 1000,
2337                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2338                         PMD_DRV_LOG(ERR, "Error setting alarm");
2339         } else {
2340                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2341                 ixgbe_enable_intr(dev);
2342                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2343         }
2344
2345
2346         return 0;
2347 }
2348
2349 /**
2350  * Interrupt handler which shall be registered for alarm callback for delayed
2351  * handling specific interrupt to wait for the stable nic state. As the
2352  * NIC interrupt state is not stable for ixgbe after link is just down,
2353  * it needs to wait 4 seconds to get the stable status.
2354  *
2355  * @param handle
2356  *  Pointer to interrupt handle.
2357  * @param param
2358  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2359  *
2360  * @return
2361  *  void
2362  */
2363 static void
2364 ixgbe_dev_interrupt_delayed_handler(void *param)
2365 {
2366         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2367         struct ixgbe_interrupt *intr =
2368                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2369         struct ixgbe_hw *hw =
2370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2371         uint32_t eicr;
2372
2373         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2374         if (eicr & IXGBE_EICR_MAILBOX)
2375                 ixgbe_pf_mbx_process(dev);
2376
2377         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2378                 ixgbe_dev_link_update(dev, 0);
2379                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2380                 ixgbe_dev_link_status_print(dev);
2381                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2382         }
2383
2384         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2385         ixgbe_enable_intr(dev);
2386         rte_intr_enable(&(dev->pci_dev->intr_handle));
2387 }
2388
2389 /**
2390  * Interrupt handler triggered by NIC  for handling
2391  * specific interrupt.
2392  *
2393  * @param handle
2394  *  Pointer to interrupt handle.
2395  * @param param
2396  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2397  *
2398  * @return
2399  *  void
2400  */
2401 static void
2402 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2403                                                         void *param)
2404 {
2405         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2406         ixgbe_dev_interrupt_get_status(dev);
2407         ixgbe_dev_interrupt_action(dev);
2408 }
2409
2410 static int
2411 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2412 {
2413         struct ixgbe_hw *hw;
2414
2415         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2416         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2417 }
2418
2419 static int
2420 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2421 {
2422         struct ixgbe_hw *hw;
2423
2424         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2426 }
2427
2428 static int
2429 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2430 {
2431         struct ixgbe_hw *hw;
2432         uint32_t mflcn_reg;
2433         uint32_t fccfg_reg;
2434         int rx_pause;
2435         int tx_pause;
2436
2437         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2438
2439         fc_conf->pause_time = hw->fc.pause_time;
2440         fc_conf->high_water = hw->fc.high_water[0];
2441         fc_conf->low_water = hw->fc.low_water[0];
2442         fc_conf->send_xon = hw->fc.send_xon;
2443         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2444
2445         /*
2446          * Return rx_pause status according to actual setting of
2447          * MFLCN register.
2448          */
2449         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2450         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2451                 rx_pause = 1;
2452         else
2453                 rx_pause = 0;
2454
2455         /*
2456          * Return tx_pause status according to actual setting of
2457          * FCCFG register.
2458          */
2459         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2460         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2461                 tx_pause = 1;
2462         else
2463                 tx_pause = 0;
2464
2465         if (rx_pause && tx_pause)
2466                 fc_conf->mode = RTE_FC_FULL;
2467         else if (rx_pause)
2468                 fc_conf->mode = RTE_FC_RX_PAUSE;
2469         else if (tx_pause)
2470                 fc_conf->mode = RTE_FC_TX_PAUSE;
2471         else
2472                 fc_conf->mode = RTE_FC_NONE;
2473
2474         return 0;
2475 }
2476
2477 static int
2478 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2479 {
2480         struct ixgbe_hw *hw;
2481         int err;
2482         uint32_t rx_buf_size;
2483         uint32_t max_high_water;
2484         uint32_t mflcn;
2485         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2486                 ixgbe_fc_none,
2487                 ixgbe_fc_rx_pause,
2488                 ixgbe_fc_tx_pause,
2489                 ixgbe_fc_full
2490         };
2491
2492         PMD_INIT_FUNC_TRACE();
2493
2494         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2496                 return -ENOTSUP;
2497         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2498         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2499
2500         /*
2501          * At least reserve one Ethernet frame for watermark
2502          * high_water/low_water in kilo bytes for ixgbe
2503          */
2504         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2505         if ((fc_conf->high_water > max_high_water) ||
2506                 (fc_conf->high_water < fc_conf->low_water)) {
2507                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2508                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2509                 return (-EINVAL);
2510         }
2511
2512         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2513         hw->fc.pause_time     = fc_conf->pause_time;
2514         hw->fc.high_water[0]  = fc_conf->high_water;
2515         hw->fc.low_water[0]   = fc_conf->low_water;
2516         hw->fc.send_xon       = fc_conf->send_xon;
2517
2518         err = ixgbe_fc_enable(hw);
2519
2520         /* Not negotiated is not an error case */
2521         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2522
2523                 /* check if we want to forward MAC frames - driver doesn't have native
2524                  * capability to do that, so we'll write the registers ourselves */
2525
2526                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2527
2528                 /* set or clear MFLCN.PMCF bit depending on configuration */
2529                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2530                         mflcn |= IXGBE_MFLCN_PMCF;
2531                 else
2532                         mflcn &= ~IXGBE_MFLCN_PMCF;
2533
2534                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2535                 IXGBE_WRITE_FLUSH(hw);
2536
2537                 return 0;
2538         }
2539
2540         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2541         return -EIO;
2542 }
2543
2544 /**
2545  *  ixgbe_pfc_enable_generic - Enable flow control
2546  *  @hw: pointer to hardware structure
2547  *  @tc_num: traffic class number
2548  *  Enable flow control according to the current settings.
2549  */
2550 static int
2551 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2552 {
2553         int ret_val = 0;
2554         uint32_t mflcn_reg, fccfg_reg;
2555         uint32_t reg;
2556         uint32_t fcrtl, fcrth;
2557         uint8_t i;
2558         uint8_t nb_rx_en;
2559
2560         /* Validate the water mark configuration */
2561         if (!hw->fc.pause_time) {
2562                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2563                 goto out;
2564         }
2565
2566         /* Low water mark of zero causes XOFF floods */
2567         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2568                  /* High/Low water can not be 0 */
2569                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2570                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2571                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2572                         goto out;
2573                 }
2574
2575                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2576                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2577                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2578                         goto out;
2579                 }
2580         }
2581         /* Negotiate the fc mode to use */
2582         ixgbe_fc_autoneg(hw);
2583
2584         /* Disable any previous flow control settings */
2585         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2586         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2587
2588         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2589         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2590
2591         switch (hw->fc.current_mode) {
2592         case ixgbe_fc_none:
2593                 /*
2594                  * If the count of enabled RX Priority Flow control >1,
2595                  * and the TX pause can not be disabled
2596                  */
2597                 nb_rx_en = 0;
2598                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2599                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2600                         if (reg & IXGBE_FCRTH_FCEN)
2601                                 nb_rx_en++;
2602                 }
2603                 if (nb_rx_en > 1)
2604                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2605                 break;
2606         case ixgbe_fc_rx_pause:
2607                 /*
2608                  * Rx Flow control is enabled and Tx Flow control is
2609                  * disabled by software override. Since there really
2610                  * isn't a way to advertise that we are capable of RX
2611                  * Pause ONLY, we will advertise that we support both
2612                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2613                  * disable the adapter's ability to send PAUSE frames.
2614                  */
2615                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2616                 /*
2617                  * If the count of enabled RX Priority Flow control >1,
2618                  * and the TX pause can not be disabled
2619                  */
2620                 nb_rx_en = 0;
2621                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2622                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2623                         if (reg & IXGBE_FCRTH_FCEN)
2624                                 nb_rx_en++;
2625                 }
2626                 if (nb_rx_en > 1)
2627                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2628                 break;
2629         case ixgbe_fc_tx_pause:
2630                 /*
2631                  * Tx Flow control is enabled, and Rx Flow control is
2632                  * disabled by software override.
2633                  */
2634                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2635                 break;
2636         case ixgbe_fc_full:
2637                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2638                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2639                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2640                 break;
2641         default:
2642                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2643                 ret_val = IXGBE_ERR_CONFIG;
2644                 goto out;
2645                 break;
2646         }
2647
2648         /* Set 802.3x based flow control settings. */
2649         mflcn_reg |= IXGBE_MFLCN_DPF;
2650         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2651         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2652
2653         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2654         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2655                 hw->fc.high_water[tc_num]) {
2656                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2657                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2658                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2659         } else {
2660                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2661                 /*
2662                  * In order to prevent Tx hangs when the internal Tx
2663                  * switch is enabled we must set the high water mark
2664                  * to the maximum FCRTH value.  This allows the Tx
2665                  * switch to function even under heavy Rx workloads.
2666                  */
2667                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2668         }
2669         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2670
2671         /* Configure pause time (2 TCs per register) */
2672         reg = hw->fc.pause_time * 0x00010001;
2673         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2674                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2675
2676         /* Configure flow control refresh threshold value */
2677         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2678
2679 out:
2680         return ret_val;
2681 }
2682
2683 static int
2684 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2685 {
2686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2687         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2688
2689         if(hw->mac.type != ixgbe_mac_82598EB) {
2690                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2691         }
2692         return ret_val;
2693 }
2694
2695 static int
2696 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2697 {
2698         int err;
2699         uint32_t rx_buf_size;
2700         uint32_t max_high_water;
2701         uint8_t tc_num;
2702         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2703         struct ixgbe_hw *hw =
2704                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2705         struct ixgbe_dcb_config *dcb_config =
2706                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2707
2708         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2709                 ixgbe_fc_none,
2710                 ixgbe_fc_rx_pause,
2711                 ixgbe_fc_tx_pause,
2712                 ixgbe_fc_full
2713         };
2714
2715         PMD_INIT_FUNC_TRACE();
2716
2717         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2718         tc_num = map[pfc_conf->priority];
2719         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2720         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2721         /*
2722          * At least reserve one Ethernet frame for watermark
2723          * high_water/low_water in kilo bytes for ixgbe
2724          */
2725         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2726         if ((pfc_conf->fc.high_water > max_high_water) ||
2727             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2728                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2729                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2730                 return (-EINVAL);
2731         }
2732
2733         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2734         hw->fc.pause_time = pfc_conf->fc.pause_time;
2735         hw->fc.send_xon = pfc_conf->fc.send_xon;
2736         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2737         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2738
2739         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2740
2741         /* Not negotiated is not an error case */
2742         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2743                 return 0;
2744
2745         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2746         return -EIO;
2747 }
2748
2749 static int
2750 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2751                           struct rte_eth_rss_reta_entry64 *reta_conf,
2752                           uint16_t reta_size)
2753 {
2754         uint8_t i, j, mask;
2755         uint32_t reta, r;
2756         uint16_t idx, shift;
2757         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2758
2759         PMD_INIT_FUNC_TRACE();
2760         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2761                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2762                         "(%d) doesn't match the number hardware can supported "
2763                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2764                 return -EINVAL;
2765         }
2766
2767         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2768                 idx = i / RTE_RETA_GROUP_SIZE;
2769                 shift = i % RTE_RETA_GROUP_SIZE;
2770                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2771                                                 IXGBE_4_BIT_MASK);
2772                 if (!mask)
2773                         continue;
2774                 if (mask == IXGBE_4_BIT_MASK)
2775                         r = 0;
2776                 else
2777                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2778                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2779                         if (mask & (0x1 << j))
2780                                 reta |= reta_conf[idx].reta[shift + j] <<
2781                                                         (CHAR_BIT * j);
2782                         else
2783                                 reta |= r & (IXGBE_8_BIT_MASK <<
2784                                                 (CHAR_BIT * j));
2785                 }
2786                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2787         }
2788
2789         return 0;
2790 }
2791
2792 static int
2793 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2794                          struct rte_eth_rss_reta_entry64 *reta_conf,
2795                          uint16_t reta_size)
2796 {
2797         uint8_t i, j, mask;
2798         uint32_t reta;
2799         uint16_t idx, shift;
2800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801
2802         PMD_INIT_FUNC_TRACE();
2803         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2804                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2805                         "(%d) doesn't match the number hardware can supported "
2806                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2807                 return -EINVAL;
2808         }
2809
2810         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2811                 idx = i / RTE_RETA_GROUP_SIZE;
2812                 shift = i % RTE_RETA_GROUP_SIZE;
2813                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2814                                                 IXGBE_4_BIT_MASK);
2815                 if (!mask)
2816                         continue;
2817
2818                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2819                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2820                         if (mask & (0x1 << j))
2821                                 reta_conf[idx].reta[shift + j] =
2822                                         ((reta >> (CHAR_BIT * j)) &
2823                                                 IXGBE_8_BIT_MASK);
2824                 }
2825         }
2826
2827         return 0;
2828 }
2829
2830 static void
2831 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2832                                 uint32_t index, uint32_t pool)
2833 {
2834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835         uint32_t enable_addr = 1;
2836
2837         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2838 }
2839
2840 static void
2841 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2842 {
2843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844
2845         ixgbe_clear_rar(hw, index);
2846 }
2847
2848 static int
2849 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2850 {
2851         uint32_t hlreg0;
2852         uint32_t maxfrs;
2853         struct ixgbe_hw *hw;
2854         struct rte_eth_dev_info dev_info;
2855         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2856
2857         ixgbe_dev_info_get(dev, &dev_info);
2858
2859         /* check that mtu is within the allowed range */
2860         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2861                 return -EINVAL;
2862
2863         /* refuse mtu that requires the support of scattered packets when this
2864          * feature has not been enabled before. */
2865         if (!dev->data->scattered_rx &&
2866             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2867              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2868                 return -EINVAL;
2869
2870         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2872
2873         /* switch to jumbo mode if needed */
2874         if (frame_size > ETHER_MAX_LEN) {
2875                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2876                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2877         } else {
2878                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2879                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2880         }
2881         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2882
2883         /* update max frame size */
2884         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2885
2886         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2887         maxfrs &= 0x0000FFFF;
2888         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2889         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2890
2891         return 0;
2892 }
2893
2894 /*
2895  * Virtual Function operations
2896  */
2897 static void
2898 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2899 {
2900         PMD_INIT_FUNC_TRACE();
2901
2902         /* Clear interrupt mask to stop from interrupts being generated */
2903         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2904
2905         IXGBE_WRITE_FLUSH(hw);
2906 }
2907
2908 static int
2909 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2910 {
2911         struct rte_eth_conf* conf = &dev->data->dev_conf;
2912
2913         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2914                      dev->data->port_id);
2915
2916         /*
2917          * VF has no ability to enable/disable HW CRC
2918          * Keep the persistent behavior the same as Host PF
2919          */
2920 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2921         if (!conf->rxmode.hw_strip_crc) {
2922                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2923                 conf->rxmode.hw_strip_crc = 1;
2924         }
2925 #else
2926         if (conf->rxmode.hw_strip_crc) {
2927                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2928                 conf->rxmode.hw_strip_crc = 0;
2929         }
2930 #endif
2931
2932         return 0;
2933 }
2934
2935 static int
2936 ixgbevf_dev_start(struct rte_eth_dev *dev)
2937 {
2938         struct ixgbe_hw *hw =
2939                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2940         int err, mask = 0;
2941
2942         PMD_INIT_FUNC_TRACE();
2943
2944         hw->mac.ops.reset_hw(hw);
2945         hw->mac.get_link_status = true;
2946
2947         /* negotiate mailbox API version to use with the PF. */
2948         ixgbevf_negotiate_api(hw);
2949
2950         ixgbevf_dev_tx_init(dev);
2951
2952         /* This can fail when allocating mbufs for descriptor rings */
2953         err = ixgbevf_dev_rx_init(dev);
2954         if (err) {
2955                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2956                 ixgbe_dev_clear_queues(dev);
2957                 return err;
2958         }
2959
2960         /* Set vfta */
2961         ixgbevf_set_vfta_all(dev,1);
2962
2963         /* Set HW strip */
2964         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2965                 ETH_VLAN_EXTEND_MASK;
2966         ixgbevf_vlan_offload_set(dev, mask);
2967
2968         ixgbevf_dev_rxtx_start(dev);
2969
2970         return 0;
2971 }
2972
2973 static void
2974 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2975 {
2976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2977
2978         PMD_INIT_FUNC_TRACE();
2979
2980         hw->adapter_stopped = TRUE;
2981         ixgbe_stop_adapter(hw);
2982
2983         /*
2984           * Clear what we set, but we still keep shadow_vfta to
2985           * restore after device starts
2986           */
2987         ixgbevf_set_vfta_all(dev,0);
2988
2989         /* Clear stored conf */
2990         dev->data->scattered_rx = 0;
2991
2992         ixgbe_dev_clear_queues(dev);
2993 }
2994
2995 static void
2996 ixgbevf_dev_close(struct rte_eth_dev *dev)
2997 {
2998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999
3000         PMD_INIT_FUNC_TRACE();
3001
3002         ixgbe_reset_hw(hw);
3003
3004         ixgbevf_dev_stop(dev);
3005
3006         /* reprogram the RAR[0] in case user changed it. */
3007         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3008 }
3009
3010 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3011 {
3012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3013         struct ixgbe_vfta * shadow_vfta =
3014                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3015         int i = 0, j = 0, vfta = 0, mask = 1;
3016
3017         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3018                 vfta = shadow_vfta->vfta[i];
3019                 if(vfta){
3020                         mask = 1;
3021                         for (j = 0; j < 32; j++){
3022                                 if(vfta & mask)
3023                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3024                                 mask<<=1;
3025                         }
3026                 }
3027         }
3028
3029 }
3030
3031 static int
3032 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3033 {
3034         struct ixgbe_hw *hw =
3035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3036         struct ixgbe_vfta * shadow_vfta =
3037                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3038         uint32_t vid_idx = 0;
3039         uint32_t vid_bit = 0;
3040         int ret = 0;
3041
3042         PMD_INIT_FUNC_TRACE();
3043
3044         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3045         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3046         if(ret){
3047                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3048                 return ret;
3049         }
3050         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3051         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3052
3053         /* Save what we set and retore it after device reset */
3054         if (on)
3055                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3056         else
3057                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3058
3059         return 0;
3060 }
3061
3062 static void
3063 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3064 {
3065         struct ixgbe_hw *hw =
3066                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067         uint32_t ctrl;
3068
3069         PMD_INIT_FUNC_TRACE();
3070
3071         if(queue >= hw->mac.max_rx_queues)
3072                 return;
3073
3074         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3075         if(on)
3076                 ctrl |= IXGBE_RXDCTL_VME;
3077         else
3078                 ctrl &= ~IXGBE_RXDCTL_VME;
3079         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3080
3081         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3082 }
3083
3084 static void
3085 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3086 {
3087         struct ixgbe_hw *hw =
3088                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3089         uint16_t i;
3090         int on = 0;
3091
3092         /* VF function only support hw strip feature, others are not support */
3093         if(mask & ETH_VLAN_STRIP_MASK){
3094                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3095
3096                 for(i=0; i < hw->mac.max_rx_queues; i++)
3097                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3098         }
3099 }
3100
3101 static int
3102 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3103 {
3104         uint32_t reg_val;
3105
3106         /* we only need to do this if VMDq is enabled */
3107         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3108         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3109                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3110                 return (-1);
3111         }
3112
3113         return 0;
3114 }
3115
3116 static uint32_t
3117 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3118 {
3119         uint32_t vector = 0;
3120         switch (hw->mac.mc_filter_type) {
3121         case 0:   /* use bits [47:36] of the address */
3122                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3123                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3124                 break;
3125         case 1:   /* use bits [46:35] of the address */
3126                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3127                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3128                 break;
3129         case 2:   /* use bits [45:34] of the address */
3130                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3131                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3132                 break;
3133         case 3:   /* use bits [43:32] of the address */
3134                 vector = ((uc_addr->addr_bytes[4]) |
3135                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3136                 break;
3137         default:  /* Invalid mc_filter_type */
3138                 break;
3139         }
3140
3141         /* vector can only be 12-bits or boundary will be exceeded */
3142         vector &= 0xFFF;
3143         return vector;
3144 }
3145
3146 static int
3147 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3148                                uint8_t on)
3149 {
3150         uint32_t vector;
3151         uint32_t uta_idx;
3152         uint32_t reg_val;
3153         uint32_t uta_shift;
3154         uint32_t rc;
3155         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3156         const uint32_t ixgbe_uta_bit_shift = 5;
3157         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3158         const uint32_t bit1 = 0x1;
3159
3160         struct ixgbe_hw *hw =
3161                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3162         struct ixgbe_uta_info *uta_info =
3163                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3164
3165         /* The UTA table only exists on 82599 hardware and newer */
3166         if (hw->mac.type < ixgbe_mac_82599EB)
3167                 return (-ENOTSUP);
3168
3169         vector = ixgbe_uta_vector(hw,mac_addr);
3170         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3171         uta_shift = vector & ixgbe_uta_bit_mask;
3172
3173         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3174         if(rc == on)
3175                 return 0;
3176
3177         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3178         if (on) {
3179                 uta_info->uta_in_use++;
3180                 reg_val |= (bit1 << uta_shift);
3181                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3182         } else {
3183                 uta_info->uta_in_use--;
3184                 reg_val &= ~(bit1 << uta_shift);
3185                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3186         }
3187
3188         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3189
3190         if (uta_info->uta_in_use > 0)
3191                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3192                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3193         else
3194                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3195
3196         return 0;
3197 }
3198
3199 static int
3200 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3201 {
3202         int i;
3203         struct ixgbe_hw *hw =
3204                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3205         struct ixgbe_uta_info *uta_info =
3206                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3207
3208         /* The UTA table only exists on 82599 hardware and newer */
3209         if (hw->mac.type < ixgbe_mac_82599EB)
3210                 return (-ENOTSUP);
3211
3212         if(on) {
3213                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3214                         uta_info->uta_shadow[i] = ~0;
3215                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3216                 }
3217         } else {
3218                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3219                         uta_info->uta_shadow[i] = 0;
3220                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3221                 }
3222         }
3223         return 0;
3224
3225 }
3226
3227 uint32_t
3228 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3229 {
3230         uint32_t new_val = orig_val;
3231
3232         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3233                 new_val |= IXGBE_VMOLR_AUPE;
3234         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3235                 new_val |= IXGBE_VMOLR_ROMPE;
3236         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3237                 new_val |= IXGBE_VMOLR_ROPE;
3238         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3239                 new_val |= IXGBE_VMOLR_BAM;
3240         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3241                 new_val |= IXGBE_VMOLR_MPE;
3242
3243         return new_val;
3244 }
3245
3246 static int
3247 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3248                                uint16_t rx_mask, uint8_t on)
3249 {
3250         int val = 0;
3251
3252         struct ixgbe_hw *hw =
3253                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3254         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3255
3256         if (hw->mac.type == ixgbe_mac_82598EB) {
3257                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3258                              " on 82599 hardware and newer");
3259                 return (-ENOTSUP);
3260         }
3261         if (ixgbe_vmdq_mode_check(hw) < 0)
3262                 return (-ENOTSUP);
3263
3264         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3265
3266         if (on)
3267                 vmolr |= val;
3268         else
3269                 vmolr &= ~val;
3270
3271         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3272
3273         return 0;
3274 }
3275
3276 static int
3277 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3278 {
3279         uint32_t reg,addr;
3280         uint32_t val;
3281         const uint8_t bit1 = 0x1;
3282
3283         struct ixgbe_hw *hw =
3284                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3285
3286         if (ixgbe_vmdq_mode_check(hw) < 0)
3287                 return (-ENOTSUP);
3288
3289         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3290         reg = IXGBE_READ_REG(hw, addr);
3291         val = bit1 << pool;
3292
3293         if (on)
3294                 reg |= val;
3295         else
3296                 reg &= ~val;
3297
3298         IXGBE_WRITE_REG(hw, addr,reg);
3299
3300         return 0;
3301 }
3302
3303 static int
3304 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3305 {
3306         uint32_t reg,addr;
3307         uint32_t val;
3308         const uint8_t bit1 = 0x1;
3309
3310         struct ixgbe_hw *hw =
3311                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312
3313         if (ixgbe_vmdq_mode_check(hw) < 0)
3314                 return (-ENOTSUP);
3315
3316         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3317         reg = IXGBE_READ_REG(hw, addr);
3318         val = bit1 << pool;
3319
3320         if (on)
3321                 reg |= val;
3322         else
3323                 reg &= ~val;
3324
3325         IXGBE_WRITE_REG(hw, addr,reg);
3326
3327         return 0;
3328 }
3329
3330 static int
3331 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3332                         uint64_t pool_mask, uint8_t vlan_on)
3333 {
3334         int ret = 0;
3335         uint16_t pool_idx;
3336         struct ixgbe_hw *hw =
3337                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3338
3339         if (ixgbe_vmdq_mode_check(hw) < 0)
3340                 return (-ENOTSUP);
3341         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3342                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3343                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3344                         if (ret < 0)
3345                                 return ret;
3346         }
3347
3348         return ret;
3349 }
3350
3351 static int
3352 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3353                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3354                         uint8_t rule_id, uint8_t on)
3355 {
3356         uint32_t mr_ctl,vlvf;
3357         uint32_t mp_lsb = 0;
3358         uint32_t mv_msb = 0;
3359         uint32_t mv_lsb = 0;
3360         uint32_t mp_msb = 0;
3361         uint8_t i = 0;
3362         int reg_index = 0;
3363         uint64_t vlan_mask = 0;
3364
3365         const uint8_t pool_mask_offset = 32;
3366         const uint8_t vlan_mask_offset = 32;
3367         const uint8_t dst_pool_offset = 8;
3368         const uint8_t rule_mr_offset  = 4;
3369         const uint8_t mirror_rule_mask= 0x0F;
3370
3371         struct ixgbe_mirror_info *mr_info =
3372                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3373         struct ixgbe_hw *hw =
3374                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3375
3376         if (ixgbe_vmdq_mode_check(hw) < 0)
3377                 return (-ENOTSUP);
3378
3379         /* Check if vlan mask is valid */
3380         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3381                 if (mirror_conf->vlan.vlan_mask == 0)
3382                         return (-EINVAL);
3383         }
3384
3385         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3386         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3387                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3388                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3389                                 /* search vlan id related pool vlan filter index */
3390                                 reg_index = ixgbe_find_vlvf_slot(hw,
3391                                                 mirror_conf->vlan.vlan_id[i]);
3392                                 if(reg_index < 0)
3393                                         return (-EINVAL);
3394                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3395                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3396                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3397                                                 == mirror_conf->vlan.vlan_id[i]))
3398                                         vlan_mask |= (1ULL << reg_index);
3399                                 else
3400                                         return (-EINVAL);
3401                         }
3402                 }
3403
3404                 if (on) {
3405                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3406                         mv_msb = vlan_mask >> vlan_mask_offset;
3407
3408                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3409                                                 mirror_conf->vlan.vlan_mask;
3410                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3411                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3412                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3413                                                 mirror_conf->vlan.vlan_id[i];
3414                         }
3415                 } else {
3416                         mv_lsb = 0;
3417                         mv_msb = 0;
3418                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3419                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3420                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3421                 }
3422         }
3423
3424         /*
3425          * if enable pool mirror, write related pool mask register,if disable
3426          * pool mirror, clear PFMRVM register
3427          */
3428         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3429                 if (on) {
3430                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3431                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3432                         mr_info->mr_conf[rule_id].pool_mask =
3433                                         mirror_conf->pool_mask;
3434
3435                 } else {
3436                         mp_lsb = 0;
3437                         mp_msb = 0;
3438                         mr_info->mr_conf[rule_id].pool_mask = 0;
3439                 }
3440         }
3441
3442         /* read  mirror control register and recalculate it */
3443         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3444
3445         if (on) {
3446                 mr_ctl |= mirror_conf->rule_type_mask;
3447                 mr_ctl &= mirror_rule_mask;
3448                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3449         } else
3450                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3451
3452         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3453         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3454
3455         /* write mirrror control  register */
3456         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3457
3458         /* write pool mirrror control  register */
3459         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3460                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3461                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3462                                 mp_msb);
3463         }
3464         /* write VLAN mirrror control  register */
3465         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3466                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3467                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3468                                 mv_msb);
3469         }
3470
3471         return 0;
3472 }
3473
3474 static int
3475 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3476 {
3477         int mr_ctl = 0;
3478         uint32_t lsb_val = 0;
3479         uint32_t msb_val = 0;
3480         const uint8_t rule_mr_offset = 4;
3481
3482         struct ixgbe_hw *hw =
3483                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484         struct ixgbe_mirror_info *mr_info =
3485                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3486
3487         if (ixgbe_vmdq_mode_check(hw) < 0)
3488                 return (-ENOTSUP);
3489
3490         memset(&mr_info->mr_conf[rule_id], 0,
3491                 sizeof(struct rte_eth_vmdq_mirror_conf));
3492
3493         /* clear PFVMCTL register */
3494         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3495
3496         /* clear pool mask register */
3497         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3498         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3499
3500         /* clear vlan mask register */
3501         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3502         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3503
3504         return 0;
3505 }
3506
3507 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3508         uint16_t queue_idx, uint16_t tx_rate)
3509 {
3510         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3511         uint32_t rf_dec, rf_int;
3512         uint32_t bcnrc_val;
3513         uint16_t link_speed = dev->data->dev_link.link_speed;
3514
3515         if (queue_idx >= hw->mac.max_tx_queues)
3516                 return -EINVAL;
3517
3518         if (tx_rate != 0) {
3519                 /* Calculate the rate factor values to set */
3520                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3521                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3522                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3523
3524                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3525                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3526                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3527                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3528         } else {
3529                 bcnrc_val = 0;
3530         }
3531
3532         /*
3533          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3534          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3535          * set as 0x4.
3536          */
3537         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3538                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3539                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3540                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3541                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3542         else
3543                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3544                         IXGBE_MMW_SIZE_DEFAULT);
3545
3546         /* Set RTTBCNRC of queue X */
3547         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3548         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3549         IXGBE_WRITE_FLUSH(hw);
3550
3551         return 0;
3552 }
3553
3554 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3555         uint16_t tx_rate, uint64_t q_msk)
3556 {
3557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3558         struct ixgbe_vf_info *vfinfo =
3559                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3560         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3561         uint32_t queue_stride =
3562                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3563         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3564         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3565         uint16_t total_rate = 0;
3566
3567         if (queue_end >= hw->mac.max_tx_queues)
3568                 return -EINVAL;
3569
3570         if (vfinfo != NULL) {
3571                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3572                         if (vf_idx == vf)
3573                                 continue;
3574                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3575                                 idx++)
3576                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3577                 }
3578         } else
3579                 return -EINVAL;
3580
3581         /* Store tx_rate for this vf. */
3582         for (idx = 0; idx < nb_q_per_pool; idx++) {
3583                 if (((uint64_t)0x1 << idx) & q_msk) {
3584                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3585                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3586                         total_rate += tx_rate;
3587                 }
3588         }
3589
3590         if (total_rate > dev->data->dev_link.link_speed) {
3591                 /*
3592                  * Reset stored TX rate of the VF if it causes exceed
3593                  * link speed.
3594                  */
3595                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3596                 return -EINVAL;
3597         }
3598
3599         /* Set RTTBCNRC of each queue/pool for vf X  */
3600         for (; queue_idx <= queue_end; queue_idx++) {
3601                 if (0x1 & q_msk)
3602                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3603                 q_msk = q_msk >> 1;
3604         }
3605
3606         return 0;
3607 }
3608
3609 static void
3610 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3611                      __attribute__((unused)) uint32_t index,
3612                      __attribute__((unused)) uint32_t pool)
3613 {
3614         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615         int diag;
3616
3617         /*
3618          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3619          * operation. Trap this case to avoid exhausting the [very limited]
3620          * set of PF resources used to store VF MAC addresses.
3621          */
3622         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3623                 return;
3624         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3625         if (diag == 0)
3626                 return;
3627         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3628 }
3629
3630 static void
3631 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3632 {
3633         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3634         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3635         struct ether_addr *mac_addr;
3636         uint32_t i;
3637         int diag;
3638
3639         /*
3640          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3641          * not support the deletion of a given MAC address.
3642          * Instead, it imposes to delete all MAC addresses, then to add again
3643          * all MAC addresses with the exception of the one to be deleted.
3644          */
3645         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3646
3647         /*
3648          * Add again all MAC addresses, with the exception of the deleted one
3649          * and of the permanent MAC address.
3650          */
3651         for (i = 0, mac_addr = dev->data->mac_addrs;
3652              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3653                 /* Skip the deleted MAC address */
3654                 if (i == index)
3655                         continue;
3656                 /* Skip NULL MAC addresses */
3657                 if (is_zero_ether_addr(mac_addr))
3658                         continue;
3659                 /* Skip the permanent MAC address */
3660                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3661                         continue;
3662                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3663                 if (diag != 0)
3664                         PMD_DRV_LOG(ERR,
3665                                     "Adding again MAC address "
3666                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3667                                     "diag=%d",
3668                                     mac_addr->addr_bytes[0],
3669                                     mac_addr->addr_bytes[1],
3670                                     mac_addr->addr_bytes[2],
3671                                     mac_addr->addr_bytes[3],
3672                                     mac_addr->addr_bytes[4],
3673                                     mac_addr->addr_bytes[5],
3674                                     diag);
3675         }
3676 }
3677
3678 /*
3679  * add syn filter
3680  *
3681  * @param
3682  * dev: Pointer to struct rte_eth_dev.
3683  * filter: ponter to the filter that will be added.
3684  * rx_queue: the queue id the filter assigned to.
3685  *
3686  * @return
3687  *    - On success, zero.
3688  *    - On failure, a negative value.
3689  */
3690 static int
3691 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3692                         struct rte_syn_filter *filter, uint16_t rx_queue)
3693 {
3694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3695         uint32_t synqf;
3696
3697         if (hw->mac.type != ixgbe_mac_82599EB)
3698                 return -ENOSYS;
3699
3700         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3701                 return -EINVAL;
3702
3703         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3704
3705         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3706                 return -EINVAL;
3707
3708         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3709                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3710
3711         if (filter->hig_pri)
3712                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3713         else
3714                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3715
3716         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3717         return 0;
3718 }
3719
3720 /*
3721  * remove syn filter
3722  *
3723  * @param
3724  * dev: Pointer to struct rte_eth_dev.
3725  *
3726  * @return
3727  *    - On success, zero.
3728  *    - On failure, a negative value.
3729  */
3730 static int
3731 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3732 {
3733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3734         uint32_t synqf;
3735
3736         if (hw->mac.type != ixgbe_mac_82599EB)
3737                 return -ENOSYS;
3738
3739         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3740
3741         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3742
3743         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3744         return 0;
3745 }
3746
3747 /*
3748  * get the syn filter's info
3749  *
3750  * @param
3751  * dev: Pointer to struct rte_eth_dev.
3752  * filter: ponter to the filter that returns.
3753  * *rx_queue: pointer to the queue id the filter assigned to.
3754  *
3755  * @return
3756  *    - On success, zero.
3757  *    - On failure, a negative value.
3758  */
3759 static int
3760 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3761                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3762
3763 {
3764         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3765         uint32_t synqf;
3766
3767         if (hw->mac.type != ixgbe_mac_82599EB)
3768                 return -ENOSYS;
3769
3770         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3771         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3772                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3773                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3774                 return 0;
3775         }
3776         return -ENOENT;
3777 }
3778
3779 static inline enum ixgbe_5tuple_protocol
3780 convert_protocol_type(uint8_t protocol_value)
3781 {
3782         if (protocol_value == IPPROTO_TCP)
3783                 return IXGBE_FILTER_PROTOCOL_TCP;
3784         else if (protocol_value == IPPROTO_UDP)
3785                 return IXGBE_FILTER_PROTOCOL_UDP;
3786         else if (protocol_value == IPPROTO_SCTP)
3787                 return IXGBE_FILTER_PROTOCOL_SCTP;
3788         else
3789                 return IXGBE_FILTER_PROTOCOL_NONE;
3790 }
3791
3792 static inline uint8_t
3793 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3794 {
3795         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3796                 return IPPROTO_TCP;
3797         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3798                 return IPPROTO_UDP;
3799         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3800                 return IPPROTO_SCTP;
3801         else
3802                 return 0;
3803 }
3804
3805 /*
3806  * add a 5tuple filter
3807  *
3808  * @param
3809  * dev: Pointer to struct rte_eth_dev.
3810  * index: the index the filter allocates.
3811  * filter: ponter to the filter that will be added.
3812  * rx_queue: the queue id the filter assigned to.
3813  *
3814  * @return
3815  *    - On success, zero.
3816  *    - On failure, a negative value.
3817  */
3818 static int
3819 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3820                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3821 {
3822         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3823         uint32_t ftqf, sdpqf = 0;
3824         uint32_t l34timir = 0;
3825         uint8_t mask = 0xff;
3826
3827         if (hw->mac.type != ixgbe_mac_82599EB)
3828                 return -ENOSYS;
3829
3830         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3831                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3832                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3833                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3834                 return -EINVAL;  /* filter index is out of range. */
3835
3836         if (filter->tcp_flags) {
3837                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3838                 return -EINVAL;
3839         }
3840
3841         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3842         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3843                 return -EINVAL;  /* filter index is in use. */
3844
3845         ftqf = 0;
3846         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3847         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3848
3849         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3850                 IXGBE_FTQF_PROTOCOL_MASK);
3851         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3852                 IXGBE_FTQF_PRIORITY_SHIFT);
3853         if (filter->src_ip_mask == 0) /* 0 means compare. */
3854                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3855         if (filter->dst_ip_mask == 0)
3856                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3857         if (filter->src_port_mask == 0)
3858                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3859         if (filter->dst_port_mask == 0)
3860                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3861         if (filter->protocol_mask == 0)
3862                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3863         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3864         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3865         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3866
3867         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3868         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3869         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3870         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3871
3872         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3873         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3874         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3875         return 0;
3876 }
3877
3878 /*
3879  * remove a 5tuple filter
3880  *
3881  * @param
3882  * dev: Pointer to struct rte_eth_dev.
3883  * index: the index the filter allocates.
3884  *
3885  * @return
3886  *    - On success, zero.
3887  *    - On failure, a negative value.
3888  */
3889 static int
3890 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3891                         uint16_t index)
3892 {
3893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3894
3895         if (hw->mac.type != ixgbe_mac_82599EB)
3896                 return -ENOSYS;
3897
3898         if (index >= IXGBE_MAX_FTQF_FILTERS)
3899                 return -EINVAL;  /* filter index is out of range. */
3900
3901         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3902         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3903         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3904         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3905         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3906         return 0;
3907 }
3908
3909 /*
3910  * get a 5tuple filter
3911  *
3912  * @param
3913  * dev: Pointer to struct rte_eth_dev.
3914  * index: the index the filter allocates
3915  * filter: ponter to the filter that returns.
3916  * *rx_queue: pointer of the queue id the filter assigned to.
3917  *
3918  * @return
3919  *    - On success, zero.
3920  *    - On failure, a negative value.
3921  */
3922 static int
3923 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3924                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3925 {
3926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3927         uint32_t sdpqf, ftqf, l34timir;
3928         uint8_t mask;
3929         enum ixgbe_5tuple_protocol proto;
3930
3931         if (hw->mac.type != ixgbe_mac_82599EB)
3932                 return -ENOSYS;
3933
3934         if (index >= IXGBE_MAX_FTQF_FILTERS)
3935                 return -EINVAL;  /* filter index is out of range. */
3936
3937         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3938         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3939                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3940                 filter->protocol = revert_protocol_type(proto);
3941                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3942                                         IXGBE_FTQF_PRIORITY_MASK;
3943                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3944                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3945                 filter->src_ip_mask =
3946                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3947                 filter->dst_ip_mask =
3948                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3949                 filter->src_port_mask =
3950                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3951                 filter->dst_port_mask =
3952                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3953                 filter->protocol_mask =
3954                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3955
3956                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3957                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3958                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3959                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3960                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3961                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3962
3963                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3964                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3965                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3966                 return 0;
3967         }
3968         return -ENOENT;
3969 }
3970
3971 static int
3972 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3973 {
3974         struct ixgbe_hw *hw;
3975         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3976
3977         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3978
3979         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3980                 return -EINVAL;
3981
3982         /* refuse mtu that requires the support of scattered packets when this
3983          * feature has not been enabled before. */
3984         if (!dev->data->scattered_rx &&
3985             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3986              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3987                 return -EINVAL;
3988
3989         /*
3990          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3991          * request of the version 2.0 of the mailbox API.
3992          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3993          * of the mailbox API.
3994          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3995          * prior to 3.11.33 which contains the following change:
3996          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3997          */
3998         ixgbevf_rlpml_set_vf(hw, max_frame);
3999
4000         /* update max frame size */
4001         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4002         return 0;
4003 }
4004
4005 #define MAC_TYPE_FILTER_SUP(type)    do {\
4006         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4007                 (type) != ixgbe_mac_X550)\
4008                 return -ENOTSUP;\
4009 } while (0)
4010
4011 static inline int
4012 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4013                         uint16_t ethertype)
4014 {
4015         int i;
4016
4017         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4018                 if (filter_info->ethertype_filters[i] == ethertype &&
4019                     (filter_info->ethertype_mask & (1 << i)))
4020                         return i;
4021         }
4022         return -1;
4023 }
4024
4025 static inline int
4026 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4027                         uint16_t ethertype)
4028 {
4029         int i;
4030
4031         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4032                 if (!(filter_info->ethertype_mask & (1 << i))) {
4033                         filter_info->ethertype_mask |= 1 << i;
4034                         filter_info->ethertype_filters[i] = ethertype;
4035                         return i;
4036                 }
4037         }
4038         return -1;
4039 }
4040
4041 static inline int
4042 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4043                         uint8_t idx)
4044 {
4045         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4046                 return -1;
4047         filter_info->ethertype_mask &= ~(1 << idx);
4048         filter_info->ethertype_filters[idx] = 0;
4049         return idx;
4050 }
4051
4052 static int
4053 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4054                         struct rte_eth_ethertype_filter *filter,
4055                         bool add)
4056 {
4057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4058         struct ixgbe_filter_info *filter_info =
4059                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4060         uint32_t etqf = 0;
4061         uint32_t etqs = 0;
4062         int ret;
4063
4064         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4065                 return -EINVAL;
4066
4067         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4068                 filter->ether_type == ETHER_TYPE_IPv6) {
4069                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4070                         " ethertype filter.", filter->ether_type);
4071                 return -EINVAL;
4072         }
4073
4074         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4075                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4076                 return -EINVAL;
4077         }
4078         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4079                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4080                 return -EINVAL;
4081         }
4082
4083         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4084         if (ret >= 0 && add) {
4085                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4086                             filter->ether_type);
4087                 return -EEXIST;
4088         }
4089         if (ret < 0 && !add) {
4090                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4091                             filter->ether_type);
4092                 return -ENOENT;
4093         }
4094
4095         if (add) {
4096                 ret = ixgbe_ethertype_filter_insert(filter_info,
4097                         filter->ether_type);
4098                 if (ret < 0) {
4099                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4100                         return -ENOSYS;
4101                 }
4102                 etqf = IXGBE_ETQF_FILTER_EN;
4103                 etqf |= (uint32_t)filter->ether_type;
4104                 etqs |= (uint32_t)((filter->queue <<
4105                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4106                                     IXGBE_ETQS_RX_QUEUE);
4107                 etqs |= IXGBE_ETQS_QUEUE_EN;
4108         } else {
4109                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4110                 if (ret < 0)
4111                         return -ENOSYS;
4112         }
4113         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4114         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4115         IXGBE_WRITE_FLUSH(hw);
4116
4117         return 0;
4118 }
4119
4120 static int
4121 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4122                         struct rte_eth_ethertype_filter *filter)
4123 {
4124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4125         struct ixgbe_filter_info *filter_info =
4126                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4127         uint32_t etqf, etqs;
4128         int ret;
4129
4130         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4131         if (ret < 0) {
4132                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4133                             filter->ether_type);
4134                 return -ENOENT;
4135         }
4136
4137         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4138         if (etqf & IXGBE_ETQF_FILTER_EN) {
4139                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4140                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4141                 filter->flags = 0;
4142                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4143                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4144                 return 0;
4145         }
4146         return -ENOENT;
4147 }
4148
4149 /*
4150  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4151  * @dev: pointer to rte_eth_dev structure
4152  * @filter_op:operation will be taken.
4153  * @arg: a pointer to specific structure corresponding to the filter_op
4154  */
4155 static int
4156 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4157                                 enum rte_filter_op filter_op,
4158                                 void *arg)
4159 {
4160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4161         int ret;
4162
4163         MAC_TYPE_FILTER_SUP(hw->mac.type);
4164
4165         if (filter_op == RTE_ETH_FILTER_NOP)
4166                 return 0;
4167
4168         if (arg == NULL) {
4169                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4170                             filter_op);
4171                 return -EINVAL;
4172         }
4173
4174         switch (filter_op) {
4175         case RTE_ETH_FILTER_ADD:
4176                 ret = ixgbe_add_del_ethertype_filter(dev,
4177                         (struct rte_eth_ethertype_filter *)arg,
4178                         TRUE);
4179                 break;
4180         case RTE_ETH_FILTER_DELETE:
4181                 ret = ixgbe_add_del_ethertype_filter(dev,
4182                         (struct rte_eth_ethertype_filter *)arg,
4183                         FALSE);
4184                 break;
4185         case RTE_ETH_FILTER_GET:
4186                 ret = ixgbe_get_ethertype_filter(dev,
4187                         (struct rte_eth_ethertype_filter *)arg);
4188                 break;
4189         default:
4190                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4191                 ret = -EINVAL;
4192                 break;
4193         }
4194         return ret;
4195 }
4196
4197 static int
4198 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4199                      enum rte_filter_type filter_type,
4200                      enum rte_filter_op filter_op,
4201                      void *arg)
4202 {
4203         int ret = -EINVAL;
4204
4205         switch (filter_type) {
4206         case RTE_ETH_FILTER_ETHERTYPE:
4207                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4208                 break;
4209         case RTE_ETH_FILTER_FDIR:
4210                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4211                 break;
4212         default:
4213                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4214                                                         filter_type);
4215                 break;
4216         }
4217
4218         return ret;
4219 }
4220
4221 static struct rte_driver rte_ixgbe_driver = {
4222         .type = PMD_PDEV,
4223         .init = rte_ixgbe_pmd_init,
4224 };
4225
4226 static struct rte_driver rte_ixgbevf_driver = {
4227         .type = PMD_PDEV,
4228         .init = rte_ixgbevf_pmd_init,
4229 };
4230
4231 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4232 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);