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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_tailq.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
62 #include "ixgbe_logs.h"
63 #include "ixgbe/ixgbe_api.h"
64 #include "ixgbe/ixgbe_vf.h"
65 #include "ixgbe/ixgbe_common.h"
66 #include "ixgbe_ethdev.h"
67 #include "ixgbe_bypass.h"
70 * High threshold controlling when to start sending XOFF frames. Must be at
71 * least 8 bytes less than receive packet buffer size. This value is in units
74 #define IXGBE_FC_HI 0x80
77 * Low threshold controlling when to start sending XON frames. This value is
78 * in units of 1024 bytes.
80 #define IXGBE_FC_LO 0x40
82 /* Timer value included in XOFF frames. */
83 #define IXGBE_FC_PAUSE 0x680
85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
86 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
87 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
90 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
92 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
94 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
95 struct rte_eth_dev *eth_dev);
96 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
97 static int ixgbe_dev_start(struct rte_eth_dev *dev);
98 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
99 static void ixgbe_dev_close(struct rte_eth_dev *dev);
100 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
101 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
102 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
103 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
104 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
105 int wait_to_complete);
106 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
107 struct rte_eth_stats *stats);
108 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
109 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
113 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
114 struct rte_eth_dev_info *dev_info);
115 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
116 uint16_t vlan_id, int on);
117 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
118 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
119 uint16_t queue, bool on);
120 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
122 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
123 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
124 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
125 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
126 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
128 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
129 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
130 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
131 struct rte_eth_fc_conf *fc_conf);
132 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
133 struct rte_eth_pfc_conf *pfc_conf);
134 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
135 struct rte_eth_rss_reta *reta_conf);
136 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
137 struct rte_eth_rss_reta *reta_conf);
138 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
139 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
140 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
141 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
142 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
144 static void ixgbe_dev_interrupt_delayed_handler(void *param);
145 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
146 uint32_t index, uint32_t pool);
147 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
148 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
150 /* For Virtual Function support */
151 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
152 struct rte_eth_dev *eth_dev);
153 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
154 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
155 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
156 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
157 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
158 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
161 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
162 uint16_t vlan_id, int on);
163 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
164 uint16_t queue, int on);
165 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
166 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
168 /* For Eth VMDQ APIs support */
169 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
170 ether_addr* mac_addr,uint8_t on);
171 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
172 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
173 uint16_t rx_mask, uint8_t on);
174 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
175 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
176 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
177 uint64_t pool_mask,uint8_t vlan_on);
178 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
179 struct rte_eth_vmdq_mirror_conf *mirror_conf,
180 uint8_t rule_id, uint8_t on);
181 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
185 * Define VF Stats MACRO for Non "cleared on read" register
187 #define UPDATE_VF_STAT(reg, last, cur) \
189 u32 latest = IXGBE_READ_REG(hw, reg); \
190 cur += latest - last; \
194 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
196 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
197 u64 new_msb = IXGBE_READ_REG(hw, msb); \
198 u64 latest = ((new_msb << 32) | new_lsb); \
199 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
203 #define IXGBE_SET_HWSTRIP(h, q) do{\
204 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
205 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
206 (h)->bitmap[idx] |= 1 << bit;\
209 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
210 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
211 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
212 (h)->bitmap[idx] &= ~(1 << bit);\
215 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
216 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
217 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
218 (r) = (h)->bitmap[idx] >> bit & 1;\
222 * The set of PCI devices this driver supports
224 static struct rte_pci_id pci_id_ixgbe_map[] = {
226 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
227 #include "rte_pci_dev_ids.h"
229 { .vendor_id = 0, /* sentinel */ },
234 * The set of PCI devices this driver supports (for 82599 VF)
236 static struct rte_pci_id pci_id_ixgbevf_map[] = {
238 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
239 #include "rte_pci_dev_ids.h"
240 { .vendor_id = 0, /* sentinel */ },
244 static struct eth_dev_ops ixgbe_eth_dev_ops = {
245 .dev_configure = ixgbe_dev_configure,
246 .dev_start = ixgbe_dev_start,
247 .dev_stop = ixgbe_dev_stop,
248 .dev_close = ixgbe_dev_close,
249 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
250 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
251 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
252 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
253 .link_update = ixgbe_dev_link_update,
254 .stats_get = ixgbe_dev_stats_get,
255 .stats_reset = ixgbe_dev_stats_reset,
256 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
257 .dev_infos_get = ixgbe_dev_info_get,
258 .vlan_filter_set = ixgbe_vlan_filter_set,
259 .vlan_tpid_set = ixgbe_vlan_tpid_set,
260 .vlan_offload_set = ixgbe_vlan_offload_set,
261 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
262 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
263 .rx_queue_release = ixgbe_dev_rx_queue_release,
264 .rx_queue_count = ixgbe_dev_rx_queue_count,
265 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
266 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
267 .tx_queue_release = ixgbe_dev_tx_queue_release,
268 .dev_led_on = ixgbe_dev_led_on,
269 .dev_led_off = ixgbe_dev_led_off,
270 .flow_ctrl_set = ixgbe_flow_ctrl_set,
271 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
272 .mac_addr_add = ixgbe_add_rar,
273 .mac_addr_remove = ixgbe_remove_rar,
274 .uc_hash_table_set = ixgbe_uc_hash_table_set,
275 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
276 .mirror_rule_set = ixgbe_mirror_rule_set,
277 .mirror_rule_reset = ixgbe_mirror_rule_reset,
278 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
279 .set_vf_rx = ixgbe_set_pool_rx,
280 .set_vf_tx = ixgbe_set_pool_tx,
281 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
282 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
283 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
284 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
285 .fdir_infos_get = ixgbe_fdir_info_get,
286 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
287 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
288 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
289 .fdir_set_masks = ixgbe_fdir_set_masks,
290 .reta_update = ixgbe_dev_rss_reta_update,
291 .reta_query = ixgbe_dev_rss_reta_query,
292 #ifdef RTE_NIC_BYPASS
293 .bypass_init = ixgbe_bypass_init,
294 .bypass_state_set = ixgbe_bypass_state_store,
295 .bypass_state_show = ixgbe_bypass_state_show,
296 .bypass_event_set = ixgbe_bypass_event_store,
297 .bypass_event_show = ixgbe_bypass_event_show,
298 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
299 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
300 .bypass_ver_show = ixgbe_bypass_ver_show,
301 .bypass_wd_reset = ixgbe_bypass_wd_reset,
302 #endif /* RTE_NIC_BYPASS */
306 * dev_ops for virtual function, bare necessities for basic vf
307 * operation have been implemented
309 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
311 .dev_configure = ixgbevf_dev_configure,
312 .dev_start = ixgbevf_dev_start,
313 .dev_stop = ixgbevf_dev_stop,
314 .link_update = ixgbe_dev_link_update,
315 .stats_get = ixgbevf_dev_stats_get,
316 .stats_reset = ixgbevf_dev_stats_reset,
317 .dev_close = ixgbevf_dev_close,
318 .dev_infos_get = ixgbe_dev_info_get,
319 .vlan_filter_set = ixgbevf_vlan_filter_set,
320 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
321 .vlan_offload_set = ixgbevf_vlan_offload_set,
322 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
323 .rx_queue_release = ixgbe_dev_rx_queue_release,
324 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
325 .tx_queue_release = ixgbe_dev_tx_queue_release,
329 * Atomically reads the link status information from global
330 * structure rte_eth_dev.
333 * - Pointer to the structure rte_eth_dev to read from.
334 * - Pointer to the buffer to be saved with the link status.
337 * - On success, zero.
338 * - On failure, negative value.
341 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
342 struct rte_eth_link *link)
344 struct rte_eth_link *dst = link;
345 struct rte_eth_link *src = &(dev->data->dev_link);
347 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
348 *(uint64_t *)src) == 0)
355 * Atomically writes the link status information into global
356 * structure rte_eth_dev.
359 * - Pointer to the structure rte_eth_dev to read from.
360 * - Pointer to the buffer to be saved with the link status.
363 * - On success, zero.
364 * - On failure, negative value.
367 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
368 struct rte_eth_link *link)
370 struct rte_eth_link *dst = &(dev->data->dev_link);
371 struct rte_eth_link *src = link;
373 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
374 *(uint64_t *)src) == 0)
381 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
384 ixgbe_is_sfp(struct ixgbe_hw *hw)
386 switch (hw->phy.type) {
387 case ixgbe_phy_sfp_avago:
388 case ixgbe_phy_sfp_ftl:
389 case ixgbe_phy_sfp_intel:
390 case ixgbe_phy_sfp_unknown:
391 case ixgbe_phy_sfp_passive_tyco:
392 case ixgbe_phy_sfp_passive_unknown:
399 static inline int32_t
400 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
405 status = ixgbe_reset_hw(hw);
407 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
408 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
409 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
410 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
411 IXGBE_WRITE_FLUSH(hw);
417 ixgbe_enable_intr(struct rte_eth_dev *dev)
419 struct ixgbe_interrupt *intr =
420 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
421 struct ixgbe_hw *hw =
422 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
424 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
425 IXGBE_WRITE_FLUSH(hw);
429 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
432 ixgbe_disable_intr(struct ixgbe_hw *hw)
434 PMD_INIT_FUNC_TRACE();
436 if (hw->mac.type == ixgbe_mac_82598EB) {
437 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
439 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
440 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
441 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
443 IXGBE_WRITE_FLUSH(hw);
447 * This function resets queue statistics mapping registers.
448 * From Niantic datasheet, Initialization of Statistics section:
449 * "...if software requires the queue counters, the RQSMR and TQSM registers
450 * must be re-programmed following a device reset.
453 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
457 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
458 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
459 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
465 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
470 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
471 #define NB_QMAP_FIELDS_PER_QSM_REG 4
472 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
474 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
475 struct ixgbe_stat_mapping_registers *stat_mappings =
476 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
477 uint32_t qsmr_mask = 0;
478 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
482 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
485 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
486 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
488 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
489 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
490 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
493 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
495 /* Now clear any previous stat_idx set */
496 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
498 stat_mappings->tqsm[n] &= ~clearing_mask;
500 stat_mappings->rqsmr[n] &= ~clearing_mask;
502 q_map = (uint32_t)stat_idx;
503 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
504 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
506 stat_mappings->tqsm[n] |= qsmr_mask;
508 stat_mappings->rqsmr[n] |= qsmr_mask;
510 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
512 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
513 is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
515 /* Now write the mapping in the appropriate register */
517 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
518 stat_mappings->rqsmr[n], n);
519 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
522 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
523 stat_mappings->tqsm[n], n);
524 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
530 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
532 struct ixgbe_stat_mapping_registers *stat_mappings =
533 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
537 /* write whatever was in stat mapping table to the NIC */
538 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
540 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
543 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
548 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
551 struct ixgbe_dcb_tc_config *tc;
552 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
554 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
555 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
556 for (i = 0; i < dcb_max_tc; i++) {
557 tc = &dcb_config->tc_config[i];
558 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
559 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
560 (uint8_t)(100/dcb_max_tc + (i & 1));
561 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
562 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
563 (uint8_t)(100/dcb_max_tc + (i & 1));
564 tc->pfc = ixgbe_dcb_pfc_disabled;
567 /* Initialize default user to priority mapping, UPx->TC0 */
568 tc = &dcb_config->tc_config[0];
569 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
570 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
571 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
572 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
573 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
575 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
576 dcb_config->pfc_mode_enable = false;
577 dcb_config->vt_mode = true;
578 dcb_config->round_robin_enable = false;
579 /* support all DCB capabilities in 82599 */
580 dcb_config->support.capabilities = 0xFF;
582 /*we only support 4 Tcs for X540*/
583 if (hw->mac.type == ixgbe_mac_X540) {
584 dcb_config->num_tcs.pg_tcs = 4;
585 dcb_config->num_tcs.pfc_tcs = 4;
590 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
591 * It returns 0 on success.
594 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
595 struct rte_eth_dev *eth_dev)
597 struct rte_pci_device *pci_dev;
598 struct ixgbe_hw *hw =
599 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
600 struct ixgbe_vfta * shadow_vfta =
601 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
602 struct ixgbe_hwstrip *hwstrip =
603 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
604 struct ixgbe_dcb_config *dcb_config =
605 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
610 PMD_INIT_FUNC_TRACE();
612 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
613 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
614 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
616 /* for secondary processes, we don't initialise any further as primary
617 * has already done this work. Only check we don't need a different
619 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
620 if (eth_dev->data->scattered_rx)
621 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
624 pci_dev = eth_dev->pci_dev;
626 /* Vendor and Device ID need to be set before init of shared code */
627 hw->device_id = pci_dev->id.device_id;
628 hw->vendor_id = pci_dev->id.vendor_id;
629 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
630 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
631 hw->allow_unsupported_sfp = 1;
634 /* Initialize the shared code */
635 #ifdef RTE_NIC_BYPASS
636 diag = ixgbe_bypass_init_shared_code(hw);
638 diag = ixgbe_init_shared_code(hw);
639 #endif /* RTE_NIC_BYPASS */
641 if (diag != IXGBE_SUCCESS) {
642 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
646 /* Initialize DCB configuration*/
647 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
648 ixgbe_dcb_init(hw,dcb_config);
649 /* Get Hardware Flow Control setting */
650 hw->fc.requested_mode = ixgbe_fc_full;
651 hw->fc.current_mode = ixgbe_fc_full;
652 hw->fc.pause_time = IXGBE_FC_PAUSE;
653 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
654 hw->fc.low_water[i] = IXGBE_FC_LO;
655 hw->fc.high_water[i] = IXGBE_FC_HI;
659 /* Make sure we have a good EEPROM before we read from it */
660 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
661 if (diag != IXGBE_SUCCESS) {
662 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
666 #ifdef RTE_NIC_BYPASS
667 diag = ixgbe_bypass_init_hw(hw);
669 diag = ixgbe_init_hw(hw);
670 #endif /* RTE_NIC_BYPASS */
673 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
674 * is called too soon after the kernel driver unbinding/binding occurs.
675 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
676 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
677 * also called. See ixgbe_identify_phy_82599(). The reason for the
678 * failure is not known, and only occuts when virtualisation features
679 * are disabled in the bios. A delay of 100ms was found to be enough by
680 * trial-and-error, and is doubled to be safe.
682 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
684 diag = ixgbe_init_hw(hw);
687 if (diag == IXGBE_ERR_EEPROM_VERSION) {
688 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
689 "LOM. Please be aware there may be issues associated "
690 "with your hardware.\n If you are experiencing problems "
691 "please contact your Intel or hardware representative "
692 "who provided you with this hardware.\n");
693 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
694 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
696 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
700 /* disable interrupt */
701 ixgbe_disable_intr(hw);
703 /* pick up the PCI bus settings for reporting later */
704 ixgbe_get_bus_info(hw);
706 /* reset mappings for queue statistics hw counters*/
707 ixgbe_reset_qstat_mappings(hw);
709 /* Allocate memory for storing MAC addresses */
710 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
711 hw->mac.num_rar_entries, 0);
712 if (eth_dev->data->mac_addrs == NULL) {
714 "Failed to allocate %u bytes needed to store "
716 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
719 /* Copy the permanent MAC address */
720 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
721 ð_dev->data->mac_addrs[0]);
723 /* Allocate memory for storing hash filter MAC addresses */
724 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
725 IXGBE_VMDQ_NUM_UC_MAC, 0);
726 if (eth_dev->data->hash_mac_addrs == NULL) {
728 "Failed to allocate %d bytes needed to store MAC addresses",
729 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
733 /* initialize the vfta */
734 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
736 /* initialize the hw strip bitmap*/
737 memset(hwstrip, 0, sizeof(*hwstrip));
739 /* initialize PF if max_vfs not zero */
740 ixgbe_pf_host_init(eth_dev);
742 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
743 /* let hardware know driver is loaded */
744 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
745 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
746 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
747 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
748 IXGBE_WRITE_FLUSH(hw);
750 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
752 "MAC: %d, PHY: %d, SFP+: %d<n",
753 (int) hw->mac.type, (int) hw->phy.type,
754 (int) hw->phy.sfp_type);
756 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
757 (int) hw->mac.type, (int) hw->phy.type);
759 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
760 eth_dev->data->port_id, pci_dev->id.vendor_id,
761 pci_dev->id.device_id);
763 rte_intr_callback_register(&(pci_dev->intr_handle),
764 ixgbe_dev_interrupt_handler, (void *)eth_dev);
766 /* enable uio intr after callback register */
767 rte_intr_enable(&(pci_dev->intr_handle));
769 /* enable support intr */
770 ixgbe_enable_intr(eth_dev);
775 static void ixgbevf_get_queue_num(struct ixgbe_hw *hw)
777 /* Traffic classes are not supported by now */
778 unsigned int tcs, tc;
781 * Must let PF know we are at mailbox API version 1.1.
782 * Otherwise PF won't answer properly.
783 * In case that PF fails to provide Rx/Tx queue number,
784 * max_tx_queues and max_rx_queues remain to be 1.
786 if (!ixgbevf_negotiate_api_version(hw, ixgbe_mbox_api_11))
787 ixgbevf_get_queues(hw, &tcs, &tc);
791 * Virtual Function device init
794 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
795 struct rte_eth_dev *eth_dev)
797 struct rte_pci_device *pci_dev;
798 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
800 struct ixgbe_vfta * shadow_vfta =
801 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
802 struct ixgbe_hwstrip *hwstrip =
803 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
805 PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
807 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
808 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
809 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
811 /* for secondary processes, we don't initialise any further as primary
812 * has already done this work. Only check we don't need a different
814 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
815 if (eth_dev->data->scattered_rx)
816 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
820 pci_dev = eth_dev->pci_dev;
822 hw->device_id = pci_dev->id.device_id;
823 hw->vendor_id = pci_dev->id.vendor_id;
824 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
826 /* initialize the vfta */
827 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
829 /* initialize the hw strip bitmap*/
830 memset(hwstrip, 0, sizeof(*hwstrip));
832 /* Initialize the shared code */
833 diag = ixgbe_init_shared_code(hw);
834 if (diag != IXGBE_SUCCESS) {
835 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
839 /* init_mailbox_params */
840 hw->mbx.ops.init_params(hw);
842 /* Disable the interrupts for VF */
843 ixgbevf_intr_disable(hw);
845 hw->mac.num_rar_entries = hw->mac.max_rx_queues;
846 diag = hw->mac.ops.reset_hw(hw);
848 if (diag != IXGBE_SUCCESS) {
849 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
850 RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
851 "\tThe most likely cause of this error is that the VM host\n"
852 "\thas not assigned a valid MAC address to this VF device.\n"
853 "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
854 "\ta possible solution to this problem.\n");
858 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
859 ixgbevf_get_queue_num(hw);
861 /* Allocate memory for storing MAC addresses */
862 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
863 hw->mac.num_rar_entries, 0);
864 if (eth_dev->data->mac_addrs == NULL) {
866 "Failed to allocate %u bytes needed to store "
868 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
872 /* Copy the permanent MAC address */
873 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
874 ð_dev->data->mac_addrs[0]);
876 /* reset the hardware with the new settings */
877 diag = hw->mac.ops.start_hw(hw);
883 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
887 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
888 eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
889 "ixgbe_mac_82599_vf");
894 static struct eth_driver rte_ixgbe_pmd = {
896 .name = "rte_ixgbe_pmd",
897 .id_table = pci_id_ixgbe_map,
898 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
900 .eth_dev_init = eth_ixgbe_dev_init,
901 .dev_private_size = sizeof(struct ixgbe_adapter),
905 * virtual function driver struct
907 static struct eth_driver rte_ixgbevf_pmd = {
909 .name = "rte_ixgbevf_pmd",
910 .id_table = pci_id_ixgbevf_map,
911 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
913 .eth_dev_init = eth_ixgbevf_dev_init,
914 .dev_private_size = sizeof(struct ixgbe_adapter),
918 * Driver initialization routine.
919 * Invoked once at EAL init time.
920 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
923 rte_ixgbe_pmd_init(void)
925 PMD_INIT_FUNC_TRACE();
927 rte_eth_driver_register(&rte_ixgbe_pmd);
932 * VF Driver initialization routine.
933 * Invoked one at EAL init time.
934 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
937 rte_ixgbevf_pmd_init(void)
939 DEBUGFUNC("rte_ixgbevf_pmd_init");
941 rte_eth_driver_register(&rte_ixgbevf_pmd);
946 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
948 struct ixgbe_hw *hw =
949 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
950 struct ixgbe_vfta * shadow_vfta =
951 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
956 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
957 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
958 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
963 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
965 /* update local VFTA copy */
966 shadow_vfta->vfta[vid_idx] = vfta;
972 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
975 ixgbe_vlan_hw_strip_enable(dev, queue);
977 ixgbe_vlan_hw_strip_disable(dev, queue);
981 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
983 struct ixgbe_hw *hw =
984 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
986 /* Only the high 16-bits is valid */
987 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
991 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
993 struct ixgbe_hw *hw =
994 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
997 PMD_INIT_FUNC_TRACE();
999 /* Filter Table Disable */
1000 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1001 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1003 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1007 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1009 struct ixgbe_hw *hw =
1010 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1011 struct ixgbe_vfta * shadow_vfta =
1012 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1016 PMD_INIT_FUNC_TRACE();
1018 /* Filter Table Enable */
1019 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1020 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1021 vlnctrl |= IXGBE_VLNCTRL_VFE;
1023 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1025 /* write whatever is in local vfta copy */
1026 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1027 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1031 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1033 struct ixgbe_hwstrip *hwstrip =
1034 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1036 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1040 IXGBE_SET_HWSTRIP(hwstrip, queue);
1042 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1046 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1048 struct ixgbe_hw *hw =
1049 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052 PMD_INIT_FUNC_TRACE();
1054 if (hw->mac.type == ixgbe_mac_82598EB) {
1055 /* No queue level support */
1056 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1060 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1061 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1062 ctrl &= ~IXGBE_RXDCTL_VME;
1063 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1065 /* record those setting for HW strip per queue */
1066 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1070 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1072 struct ixgbe_hw *hw =
1073 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1076 PMD_INIT_FUNC_TRACE();
1078 if (hw->mac.type == ixgbe_mac_82598EB) {
1079 /* No queue level supported */
1080 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1084 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1085 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1086 ctrl |= IXGBE_RXDCTL_VME;
1087 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1089 /* record those setting for HW strip per queue */
1090 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1094 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1096 struct ixgbe_hw *hw =
1097 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101 PMD_INIT_FUNC_TRACE();
1103 if (hw->mac.type == ixgbe_mac_82598EB) {
1104 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1105 ctrl &= ~IXGBE_VLNCTRL_VME;
1106 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1109 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1110 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1111 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1112 ctrl &= ~IXGBE_RXDCTL_VME;
1113 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1115 /* record those setting for HW strip per queue */
1116 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1122 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1124 struct ixgbe_hw *hw =
1125 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1129 PMD_INIT_FUNC_TRACE();
1131 if (hw->mac.type == ixgbe_mac_82598EB) {
1132 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1133 ctrl |= IXGBE_VLNCTRL_VME;
1134 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1137 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1138 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1139 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1140 ctrl |= IXGBE_RXDCTL_VME;
1141 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1143 /* record those setting for HW strip per queue */
1144 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1150 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1152 struct ixgbe_hw *hw =
1153 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1156 PMD_INIT_FUNC_TRACE();
1158 /* DMATXCTRL: Geric Double VLAN Disable */
1159 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1160 ctrl &= ~IXGBE_DMATXCTL_GDV;
1161 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1163 /* CTRL_EXT: Global Double VLAN Disable */
1164 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1165 ctrl &= ~IXGBE_EXTENDED_VLAN;
1166 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1171 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1173 struct ixgbe_hw *hw =
1174 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1177 PMD_INIT_FUNC_TRACE();
1179 /* DMATXCTRL: Geric Double VLAN Enable */
1180 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1181 ctrl |= IXGBE_DMATXCTL_GDV;
1182 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1184 /* CTRL_EXT: Global Double VLAN Enable */
1185 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1186 ctrl |= IXGBE_EXTENDED_VLAN;
1187 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1190 * VET EXT field in the EXVET register = 0x8100 by default
1191 * So no need to change. Same to VT field of DMATXCTL register
1196 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1198 if(mask & ETH_VLAN_STRIP_MASK){
1199 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1200 ixgbe_vlan_hw_strip_enable_all(dev);
1202 ixgbe_vlan_hw_strip_disable_all(dev);
1205 if(mask & ETH_VLAN_FILTER_MASK){
1206 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1207 ixgbe_vlan_hw_filter_enable(dev);
1209 ixgbe_vlan_hw_filter_disable(dev);
1212 if(mask & ETH_VLAN_EXTEND_MASK){
1213 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1214 ixgbe_vlan_hw_extend_enable(dev);
1216 ixgbe_vlan_hw_extend_disable(dev);
1221 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1223 struct ixgbe_hw *hw =
1224 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1225 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1226 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1227 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1228 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1232 ixgbe_dev_configure(struct rte_eth_dev *dev)
1234 struct ixgbe_interrupt *intr =
1235 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1237 PMD_INIT_FUNC_TRACE();
1239 /* set flag to update link status after init */
1240 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1246 * Configure device link speed and setup link.
1247 * It returns 0 on success.
1250 ixgbe_dev_start(struct rte_eth_dev *dev)
1252 struct ixgbe_hw *hw =
1253 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1254 int err, link_up = 0, negotiate = 0;
1259 PMD_INIT_FUNC_TRACE();
1261 /* IXGBE devices don't support half duplex */
1262 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1263 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1264 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1265 dev->data->dev_conf.link_duplex,
1266 dev->data->port_id);
1271 hw->adapter_stopped = FALSE;
1272 ixgbe_stop_adapter(hw);
1274 /* reinitialize adapter
1275 * this calls reset and start */
1276 status = ixgbe_pf_reset_hw(hw);
1279 hw->mac.ops.start_hw(hw);
1281 /* configure PF module if SRIOV enabled */
1282 ixgbe_pf_host_configure(dev);
1284 /* initialize transmission unit */
1285 ixgbe_dev_tx_init(dev);
1287 /* This can fail when allocating mbufs for descriptor rings */
1288 err = ixgbe_dev_rx_init(dev);
1290 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1294 ixgbe_dev_rxtx_start(dev);
1296 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1297 err = hw->mac.ops.setup_sfp(hw);
1302 /* Turn on the laser */
1303 ixgbe_enable_tx_laser(hw);
1305 /* Skip link setup if loopback mode is enabled for 82599. */
1306 if (hw->mac.type == ixgbe_mac_82599EB &&
1307 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1308 goto skip_link_setup;
1310 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1313 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1317 switch(dev->data->dev_conf.link_speed) {
1318 case ETH_LINK_SPEED_AUTONEG:
1319 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1320 IXGBE_LINK_SPEED_82599_AUTONEG :
1321 IXGBE_LINK_SPEED_82598_AUTONEG;
1323 case ETH_LINK_SPEED_100:
1325 * Invalid for 82598 but error will be detected by
1326 * ixgbe_setup_link()
1328 speed = IXGBE_LINK_SPEED_100_FULL;
1330 case ETH_LINK_SPEED_1000:
1331 speed = IXGBE_LINK_SPEED_1GB_FULL;
1333 case ETH_LINK_SPEED_10000:
1334 speed = IXGBE_LINK_SPEED_10GB_FULL;
1337 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1338 dev->data->dev_conf.link_speed,
1339 dev->data->port_id);
1343 err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1349 /* check if lsc interrupt is enabled */
1350 if (dev->data->dev_conf.intr_conf.lsc != 0)
1351 ixgbe_dev_lsc_interrupt_setup(dev);
1353 /* resume enabled intr since hw reset */
1354 ixgbe_enable_intr(dev);
1356 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1357 ETH_VLAN_EXTEND_MASK;
1358 ixgbe_vlan_offload_set(dev, mask);
1360 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1361 /* Enable vlan filtering for VMDq */
1362 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1365 /* Configure DCB hw */
1366 ixgbe_configure_dcb(dev);
1368 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1369 err = ixgbe_fdir_configure(dev);
1374 ixgbe_restore_statistics_mapping(dev);
1379 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1380 ixgbe_dev_clear_queues(dev);
1385 * Stop device: disable rx and tx functions to allow for reconfiguring.
1388 ixgbe_dev_stop(struct rte_eth_dev *dev)
1390 struct rte_eth_link link;
1391 struct ixgbe_hw *hw =
1392 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1393 struct ixgbe_vf_info *vfinfo =
1394 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1397 PMD_INIT_FUNC_TRACE();
1399 /* disable interrupts */
1400 ixgbe_disable_intr(hw);
1403 ixgbe_pf_reset_hw(hw);
1404 hw->adapter_stopped = FALSE;
1407 ixgbe_stop_adapter(hw);
1409 for (vf = 0; vfinfo != NULL &&
1410 vf < dev->pci_dev->max_vfs; vf++)
1411 vfinfo[vf].clear_to_send = false;
1413 /* Turn off the laser */
1414 ixgbe_disable_tx_laser(hw);
1416 ixgbe_dev_clear_queues(dev);
1418 /* Clear recorded link status */
1419 memset(&link, 0, sizeof(link));
1420 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1424 * Reest and stop device.
1427 ixgbe_dev_close(struct rte_eth_dev *dev)
1429 struct ixgbe_hw *hw =
1430 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1432 PMD_INIT_FUNC_TRACE();
1434 ixgbe_pf_reset_hw(hw);
1436 ixgbe_dev_stop(dev);
1437 hw->adapter_stopped = 1;
1439 ixgbe_disable_pcie_master(hw);
1441 /* reprogram the RAR[0] in case user changed it. */
1442 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1446 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1449 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1451 struct ixgbe_hw *hw =
1452 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453 struct ixgbe_hw_stats *hw_stats =
1454 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1455 uint32_t bprc, lxon, lxoff, total;
1456 uint64_t total_missed_rx, total_qbrc, total_qprc;
1459 total_missed_rx = 0;
1463 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1464 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1465 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1466 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1468 for (i = 0; i < 8; i++) {
1470 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1471 /* global total per queue */
1472 hw_stats->mpc[i] += mp;
1473 /* Running comprehensive total for stats display */
1474 total_missed_rx += hw_stats->mpc[i];
1475 if (hw->mac.type == ixgbe_mac_82598EB)
1476 hw_stats->rnbc[i] +=
1477 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1478 hw_stats->pxontxc[i] +=
1479 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1480 hw_stats->pxonrxc[i] +=
1481 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1482 hw_stats->pxofftxc[i] +=
1483 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1484 hw_stats->pxoffrxc[i] +=
1485 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1486 hw_stats->pxon2offc[i] +=
1487 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1489 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1490 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1491 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1492 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1493 hw_stats->qbrc[i] +=
1494 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1495 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1496 hw_stats->qbtc[i] +=
1497 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1498 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1500 total_qprc += hw_stats->qprc[i];
1501 total_qbrc += hw_stats->qbrc[i];
1503 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1504 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1505 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1507 /* Note that gprc counts missed packets */
1508 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1510 if (hw->mac.type != ixgbe_mac_82598EB) {
1511 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1512 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1513 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1514 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1515 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1516 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1517 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1518 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1520 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1521 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1522 /* 82598 only has a counter in the high register */
1523 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1524 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1525 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1529 * Workaround: mprc hardware is incorrectly counting
1530 * broadcasts, so for now we subtract those.
1532 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1533 hw_stats->bprc += bprc;
1534 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1535 if (hw->mac.type == ixgbe_mac_82598EB)
1536 hw_stats->mprc -= bprc;
1538 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1539 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1540 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1541 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1542 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1543 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1545 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1546 hw_stats->lxontxc += lxon;
1547 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1548 hw_stats->lxofftxc += lxoff;
1549 total = lxon + lxoff;
1551 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1552 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1553 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1554 hw_stats->gptc -= total;
1555 hw_stats->mptc -= total;
1556 hw_stats->ptc64 -= total;
1557 hw_stats->gotc -= total * ETHER_MIN_LEN;
1559 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1560 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1561 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1562 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1563 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1564 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1565 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1566 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1567 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1568 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1569 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1570 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1571 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1572 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1573 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1574 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1575 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1576 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1577 /* Only read FCOE on 82599 */
1578 if (hw->mac.type != ixgbe_mac_82598EB) {
1579 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1580 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1581 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1582 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1583 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1589 /* Fill out the rte_eth_stats statistics structure */
1590 stats->ipackets = total_qprc;
1591 stats->ibytes = total_qbrc;
1592 stats->opackets = hw_stats->gptc;
1593 stats->obytes = hw_stats->gotc;
1594 stats->imcasts = hw_stats->mprc;
1596 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1597 stats->q_ipackets[i] = hw_stats->qprc[i];
1598 stats->q_opackets[i] = hw_stats->qptc[i];
1599 stats->q_ibytes[i] = hw_stats->qbrc[i];
1600 stats->q_obytes[i] = hw_stats->qbtc[i];
1601 stats->q_errors[i] = hw_stats->qprdc[i];
1605 stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1610 /* Flow Director Stats registers */
1611 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1612 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1613 stats->fdirmatch = hw_stats->fdirmatch;
1614 stats->fdirmiss = hw_stats->fdirmiss;
1618 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1620 struct ixgbe_hw_stats *stats =
1621 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1623 /* HW registers are cleared on read */
1624 ixgbe_dev_stats_get(dev, NULL);
1626 /* Reset software totals */
1627 memset(stats, 0, sizeof(*stats));
1631 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1633 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1635 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1637 /* Good Rx packet, include VF loopback */
1638 UPDATE_VF_STAT(IXGBE_VFGPRC,
1639 hw_stats->last_vfgprc, hw_stats->vfgprc);
1641 /* Good Rx octets, include VF loopback */
1642 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1643 hw_stats->last_vfgorc, hw_stats->vfgorc);
1645 /* Good Tx packet, include VF loopback */
1646 UPDATE_VF_STAT(IXGBE_VFGPTC,
1647 hw_stats->last_vfgptc, hw_stats->vfgptc);
1649 /* Good Tx octets, include VF loopback */
1650 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1651 hw_stats->last_vfgotc, hw_stats->vfgotc);
1653 /* Rx Multicst Packet */
1654 UPDATE_VF_STAT(IXGBE_VFMPRC,
1655 hw_stats->last_vfmprc, hw_stats->vfmprc);
1660 memset(stats, 0, sizeof(*stats));
1661 stats->ipackets = hw_stats->vfgprc;
1662 stats->ibytes = hw_stats->vfgorc;
1663 stats->opackets = hw_stats->vfgptc;
1664 stats->obytes = hw_stats->vfgotc;
1665 stats->imcasts = hw_stats->vfmprc;
1669 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1671 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1672 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1674 /* Sync HW register to the last stats */
1675 ixgbevf_dev_stats_get(dev, NULL);
1677 /* reset HW current stats*/
1678 hw_stats->vfgprc = 0;
1679 hw_stats->vfgorc = 0;
1680 hw_stats->vfgptc = 0;
1681 hw_stats->vfgotc = 0;
1682 hw_stats->vfmprc = 0;
1687 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1689 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1692 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1693 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1694 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1695 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1696 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1697 dev_info->max_vfs = dev->pci_dev->max_vfs;
1698 if (hw->mac.type == ixgbe_mac_82598EB)
1699 dev_info->max_vmdq_pools = ETH_16_POOLS;
1701 dev_info->max_vmdq_pools = ETH_64_POOLS;
1702 dev_info->rx_offload_capa =
1703 DEV_RX_OFFLOAD_VLAN_STRIP |
1704 DEV_RX_OFFLOAD_IPV4_CKSUM |
1705 DEV_RX_OFFLOAD_UDP_CKSUM |
1706 DEV_RX_OFFLOAD_TCP_CKSUM;
1707 dev_info->tx_offload_capa =
1708 DEV_TX_OFFLOAD_VLAN_INSERT |
1709 DEV_TX_OFFLOAD_IPV4_CKSUM |
1710 DEV_TX_OFFLOAD_UDP_CKSUM |
1711 DEV_TX_OFFLOAD_TCP_CKSUM |
1712 DEV_TX_OFFLOAD_SCTP_CKSUM;
1715 /* return 0 means link status changed, -1 means not changed */
1717 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1719 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1720 struct rte_eth_link link, old;
1721 ixgbe_link_speed link_speed;
1725 link.link_status = 0;
1726 link.link_speed = 0;
1727 link.link_duplex = 0;
1728 memset(&old, 0, sizeof(old));
1729 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1731 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1732 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1733 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1735 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1737 link.link_speed = ETH_LINK_SPEED_100;
1738 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1739 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1740 if (link.link_status == old.link_status)
1746 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1747 if (link.link_status == old.link_status)
1751 link.link_status = 1;
1752 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1754 switch (link_speed) {
1756 case IXGBE_LINK_SPEED_UNKNOWN:
1757 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1758 link.link_speed = ETH_LINK_SPEED_100;
1761 case IXGBE_LINK_SPEED_100_FULL:
1762 link.link_speed = ETH_LINK_SPEED_100;
1765 case IXGBE_LINK_SPEED_1GB_FULL:
1766 link.link_speed = ETH_LINK_SPEED_1000;
1769 case IXGBE_LINK_SPEED_10GB_FULL:
1770 link.link_speed = ETH_LINK_SPEED_10000;
1773 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1775 if (link.link_status == old.link_status)
1782 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1784 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1787 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1788 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1789 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1793 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1795 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1799 fctrl &= (~IXGBE_FCTRL_UPE);
1800 if (dev->data->all_multicast == 1)
1801 fctrl |= IXGBE_FCTRL_MPE;
1803 fctrl &= (~IXGBE_FCTRL_MPE);
1804 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1808 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1810 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1813 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1814 fctrl |= IXGBE_FCTRL_MPE;
1815 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1819 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1821 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1824 if (dev->data->promiscuous == 1)
1825 return; /* must remain in all_multicast mode */
1827 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1828 fctrl &= (~IXGBE_FCTRL_MPE);
1829 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1833 * It clears the interrupt causes and enables the interrupt.
1834 * It will be called once only during nic initialized.
1837 * Pointer to struct rte_eth_dev.
1840 * - On success, zero.
1841 * - On failure, a negative value.
1844 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1846 struct ixgbe_interrupt *intr =
1847 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1849 ixgbe_dev_link_status_print(dev);
1850 intr->mask |= IXGBE_EICR_LSC;
1856 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1859 * Pointer to struct rte_eth_dev.
1862 * - On success, zero.
1863 * - On failure, a negative value.
1866 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1869 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870 struct ixgbe_interrupt *intr =
1871 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1873 /* clear all cause mask */
1874 ixgbe_disable_intr(hw);
1876 /* read-on-clear nic registers here */
1877 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1878 PMD_DRV_LOG(INFO, "eicr %x", eicr);
1881 if (eicr & IXGBE_EICR_LSC) {
1882 /* set flag for async link update */
1883 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1886 if (eicr & IXGBE_EICR_MAILBOX)
1887 intr->flags |= IXGBE_FLAG_MAILBOX;
1893 * It gets and then prints the link status.
1896 * Pointer to struct rte_eth_dev.
1899 * - On success, zero.
1900 * - On failure, a negative value.
1903 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1905 struct rte_eth_link link;
1907 memset(&link, 0, sizeof(link));
1908 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1909 if (link.link_status) {
1910 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1911 (int)(dev->data->port_id),
1912 (unsigned)link.link_speed,
1913 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1914 "full-duplex" : "half-duplex");
1916 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1917 (int)(dev->data->port_id));
1919 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1920 dev->pci_dev->addr.domain,
1921 dev->pci_dev->addr.bus,
1922 dev->pci_dev->addr.devid,
1923 dev->pci_dev->addr.function);
1927 * It executes link_update after knowing an interrupt occured.
1930 * Pointer to struct rte_eth_dev.
1933 * - On success, zero.
1934 * - On failure, a negative value.
1937 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1939 struct ixgbe_interrupt *intr =
1940 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1942 struct rte_eth_link link;
1943 int intr_enable_delay = false;
1945 PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1947 if (intr->flags & IXGBE_FLAG_MAILBOX) {
1948 ixgbe_pf_mbx_process(dev);
1949 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1952 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1953 /* get the link status before link update, for predicting later */
1954 memset(&link, 0, sizeof(link));
1955 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1957 ixgbe_dev_link_update(dev, 0);
1960 if (!link.link_status)
1961 /* handle it 1 sec later, wait it being stable */
1962 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1963 /* likely to down */
1965 /* handle it 4 sec later, wait it being stable */
1966 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1968 ixgbe_dev_link_status_print(dev);
1970 intr_enable_delay = true;
1973 if (intr_enable_delay) {
1974 if (rte_eal_alarm_set(timeout * 1000,
1975 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
1976 PMD_DRV_LOG(ERR, "Error setting alarm");
1978 PMD_DRV_LOG(DEBUG, "enable intr immediately");
1979 ixgbe_enable_intr(dev);
1980 rte_intr_enable(&(dev->pci_dev->intr_handle));
1988 * Interrupt handler which shall be registered for alarm callback for delayed
1989 * handling specific interrupt to wait for the stable nic state. As the
1990 * NIC interrupt state is not stable for ixgbe after link is just down,
1991 * it needs to wait 4 seconds to get the stable status.
1994 * Pointer to interrupt handle.
1996 * The address of parameter (struct rte_eth_dev *) regsitered before.
2002 ixgbe_dev_interrupt_delayed_handler(void *param)
2004 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2005 struct ixgbe_interrupt *intr =
2006 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2007 struct ixgbe_hw *hw =
2008 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2012 if (eicr & IXGBE_EICR_MAILBOX)
2013 ixgbe_pf_mbx_process(dev);
2015 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2016 ixgbe_dev_link_update(dev, 0);
2017 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2018 ixgbe_dev_link_status_print(dev);
2019 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2022 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2023 ixgbe_enable_intr(dev);
2024 rte_intr_enable(&(dev->pci_dev->intr_handle));
2028 * Interrupt handler triggered by NIC for handling
2029 * specific interrupt.
2032 * Pointer to interrupt handle.
2034 * The address of parameter (struct rte_eth_dev *) regsitered before.
2040 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2043 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2044 ixgbe_dev_interrupt_get_status(dev);
2045 ixgbe_dev_interrupt_action(dev);
2049 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2051 struct ixgbe_hw *hw;
2053 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2058 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2060 struct ixgbe_hw *hw;
2062 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2067 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2069 struct ixgbe_hw *hw;
2071 uint32_t rx_buf_size;
2072 uint32_t max_high_water;
2074 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2081 PMD_INIT_FUNC_TRACE();
2083 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2085 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2088 * At least reserve one Ethernet frame for watermark
2089 * high_water/low_water in kilo bytes for ixgbe
2091 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2092 if ((fc_conf->high_water > max_high_water) ||
2093 (fc_conf->high_water < fc_conf->low_water)) {
2094 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2095 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2099 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2100 hw->fc.pause_time = fc_conf->pause_time;
2101 hw->fc.high_water[0] = fc_conf->high_water;
2102 hw->fc.low_water[0] = fc_conf->low_water;
2103 hw->fc.send_xon = fc_conf->send_xon;
2105 err = ixgbe_fc_enable(hw);
2107 /* Not negotiated is not an error case */
2108 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2110 /* check if we want to forward MAC frames - driver doesn't have native
2111 * capability to do that, so we'll write the registers ourselves */
2113 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2115 /* set or clear MFLCN.PMCF bit depending on configuration */
2116 if (fc_conf->mac_ctrl_frame_fwd != 0)
2117 mflcn |= IXGBE_MFLCN_PMCF;
2119 mflcn &= ~IXGBE_MFLCN_PMCF;
2121 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2122 IXGBE_WRITE_FLUSH(hw);
2127 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2132 * ixgbe_pfc_enable_generic - Enable flow control
2133 * @hw: pointer to hardware structure
2134 * @tc_num: traffic class number
2135 * Enable flow control according to the current settings.
2138 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2141 uint32_t mflcn_reg, fccfg_reg;
2143 uint32_t fcrtl, fcrth;
2147 /* Validate the water mark configuration */
2148 if (!hw->fc.pause_time) {
2149 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2153 /* Low water mark of zero causes XOFF floods */
2154 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2155 /* High/Low water can not be 0 */
2156 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2157 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2158 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2162 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2163 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2164 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2168 /* Negotiate the fc mode to use */
2169 ixgbe_fc_autoneg(hw);
2171 /* Disable any previous flow control settings */
2172 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2173 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2175 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2176 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2178 switch (hw->fc.current_mode) {
2181 * If the count of enabled RX Priority Flow control >1,
2182 * and the TX pause can not be disabled
2185 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2186 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2187 if (reg & IXGBE_FCRTH_FCEN)
2191 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2193 case ixgbe_fc_rx_pause:
2195 * Rx Flow control is enabled and Tx Flow control is
2196 * disabled by software override. Since there really
2197 * isn't a way to advertise that we are capable of RX
2198 * Pause ONLY, we will advertise that we support both
2199 * symmetric and asymmetric Rx PAUSE. Later, we will
2200 * disable the adapter's ability to send PAUSE frames.
2202 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2204 * If the count of enabled RX Priority Flow control >1,
2205 * and the TX pause can not be disabled
2208 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2209 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2210 if (reg & IXGBE_FCRTH_FCEN)
2214 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2216 case ixgbe_fc_tx_pause:
2218 * Tx Flow control is enabled, and Rx Flow control is
2219 * disabled by software override.
2221 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2224 /* Flow control (both Rx and Tx) is enabled by SW override. */
2225 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2226 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2229 DEBUGOUT("Flow control param set incorrectly\n");
2230 ret_val = IXGBE_ERR_CONFIG;
2235 /* Set 802.3x based flow control settings. */
2236 mflcn_reg |= IXGBE_MFLCN_DPF;
2237 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2238 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2240 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2241 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2242 hw->fc.high_water[tc_num]) {
2243 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2244 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2245 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2247 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2249 * In order to prevent Tx hangs when the internal Tx
2250 * switch is enabled we must set the high water mark
2251 * to the maximum FCRTH value. This allows the Tx
2252 * switch to function even under heavy Rx workloads.
2254 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2256 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2258 /* Configure pause time (2 TCs per register) */
2259 reg = hw->fc.pause_time * 0x00010001;
2260 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2261 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2263 /* Configure flow control refresh threshold value */
2264 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2271 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2273 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2276 if(hw->mac.type != ixgbe_mac_82598EB) {
2277 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2283 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2286 uint32_t rx_buf_size;
2287 uint32_t max_high_water;
2289 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2290 struct ixgbe_hw *hw =
2291 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2292 struct ixgbe_dcb_config *dcb_config =
2293 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2295 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2302 PMD_INIT_FUNC_TRACE();
2304 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2305 tc_num = map[pfc_conf->priority];
2306 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2307 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2309 * At least reserve one Ethernet frame for watermark
2310 * high_water/low_water in kilo bytes for ixgbe
2312 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2313 if ((pfc_conf->fc.high_water > max_high_water) ||
2314 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2315 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2316 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2320 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2321 hw->fc.pause_time = pfc_conf->fc.pause_time;
2322 hw->fc.send_xon = pfc_conf->fc.send_xon;
2323 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2324 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2326 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2328 /* Not negotiated is not an error case */
2329 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2332 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2337 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2338 struct rte_eth_rss_reta *reta_conf)
2342 struct ixgbe_hw *hw =
2343 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345 PMD_INIT_FUNC_TRACE();
2347 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2348 * 128-entries in 32 registers
2350 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2351 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2352 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2354 mask = (uint8_t)((reta_conf->mask_hi >>
2355 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2359 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2361 for (j = 0; j < 4; j++) {
2362 if (mask & (0x1 << j)) {
2364 reta &= ~(0xFF << 8 * j);
2365 reta |= reta_conf->reta[i + j] << 8*j;
2368 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2376 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2377 struct rte_eth_rss_reta *reta_conf)
2381 struct ixgbe_hw *hw =
2382 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384 PMD_INIT_FUNC_TRACE();
2386 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2387 * 128-entries in 32 registers
2389 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2390 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2391 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2393 mask = (uint8_t)((reta_conf->mask_hi >>
2394 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2397 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2398 for (j = 0; j < 4; j++) {
2399 if (mask & (0x1 << j))
2400 reta_conf->reta[i + j] =
2401 (uint8_t)((reta >> 8 * j) & 0xFF);
2410 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2411 uint32_t index, uint32_t pool)
2413 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414 uint32_t enable_addr = 1;
2416 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2420 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2422 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424 ixgbe_clear_rar(hw, index);
2428 * Virtual Function operations
2431 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2433 PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2435 /* Clear interrupt mask to stop from interrupts being generated */
2436 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2438 IXGBE_WRITE_FLUSH(hw);
2442 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2444 struct rte_eth_conf* conf = &dev->data->dev_conf;
2446 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2447 dev->data->port_id);
2450 * VF has no ability to enable/disable HW CRC
2451 * Keep the persistent behavior the same as Host PF
2453 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2454 if (!conf->rxmode.hw_strip_crc) {
2455 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2456 conf->rxmode.hw_strip_crc = 1;
2459 if (conf->rxmode.hw_strip_crc) {
2460 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2461 conf->rxmode.hw_strip_crc = 0;
2469 ixgbevf_dev_start(struct rte_eth_dev *dev)
2471 struct ixgbe_hw *hw =
2472 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2477 hw->mac.ops.reset_hw(hw);
2479 ixgbevf_dev_tx_init(dev);
2481 /* This can fail when allocating mbufs for descriptor rings */
2482 err = ixgbevf_dev_rx_init(dev);
2484 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2485 ixgbe_dev_clear_queues(dev);
2490 ixgbevf_set_vfta_all(dev,1);
2493 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2494 ETH_VLAN_EXTEND_MASK;
2495 ixgbevf_vlan_offload_set(dev, mask);
2497 ixgbevf_dev_rxtx_start(dev);
2503 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2505 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2509 hw->adapter_stopped = TRUE;
2510 ixgbe_stop_adapter(hw);
2513 * Clear what we set, but we still keep shadow_vfta to
2514 * restore after device starts
2516 ixgbevf_set_vfta_all(dev,0);
2518 ixgbe_dev_clear_queues(dev);
2522 ixgbevf_dev_close(struct rte_eth_dev *dev)
2524 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2530 ixgbevf_dev_stop(dev);
2532 /* reprogram the RAR[0] in case user changed it. */
2533 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2536 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2538 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539 struct ixgbe_vfta * shadow_vfta =
2540 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2541 int i = 0, j = 0, vfta = 0, mask = 1;
2543 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2544 vfta = shadow_vfta->vfta[i];
2547 for (j = 0; j < 32; j++){
2549 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2558 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2560 struct ixgbe_hw *hw =
2561 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562 struct ixgbe_vfta * shadow_vfta =
2563 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2564 uint32_t vid_idx = 0;
2565 uint32_t vid_bit = 0;
2568 PMD_INIT_FUNC_TRACE();
2570 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2571 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2573 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2576 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2577 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2579 /* Save what we set and retore it after device reset */
2581 shadow_vfta->vfta[vid_idx] |= vid_bit;
2583 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2589 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2591 struct ixgbe_hw *hw =
2592 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2595 PMD_INIT_FUNC_TRACE();
2597 if(queue >= hw->mac.max_rx_queues)
2600 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2602 ctrl |= IXGBE_RXDCTL_VME;
2604 ctrl &= ~IXGBE_RXDCTL_VME;
2605 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2607 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2611 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2613 struct ixgbe_hw *hw =
2614 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618 /* VF function only support hw strip feature, others are not support */
2619 if(mask & ETH_VLAN_STRIP_MASK){
2620 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2622 for(i=0; i < hw->mac.max_rx_queues; i++)
2623 ixgbevf_vlan_strip_queue_set(dev,i,on);
2628 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2632 /* we only need to do this if VMDq is enabled */
2633 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2634 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2635 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2643 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2645 uint32_t vector = 0;
2646 switch (hw->mac.mc_filter_type) {
2647 case 0: /* use bits [47:36] of the address */
2648 vector = ((uc_addr->addr_bytes[4] >> 4) |
2649 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2651 case 1: /* use bits [46:35] of the address */
2652 vector = ((uc_addr->addr_bytes[4] >> 3) |
2653 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2655 case 2: /* use bits [45:34] of the address */
2656 vector = ((uc_addr->addr_bytes[4] >> 2) |
2657 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2659 case 3: /* use bits [43:32] of the address */
2660 vector = ((uc_addr->addr_bytes[4]) |
2661 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2663 default: /* Invalid mc_filter_type */
2667 /* vector can only be 12-bits or boundary will be exceeded */
2673 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2681 const uint32_t ixgbe_uta_idx_mask = 0x7F;
2682 const uint32_t ixgbe_uta_bit_shift = 5;
2683 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2684 const uint32_t bit1 = 0x1;
2686 struct ixgbe_hw *hw =
2687 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688 struct ixgbe_uta_info *uta_info =
2689 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2691 /* The UTA table only exists on 82599 hardware and newer */
2692 if (hw->mac.type < ixgbe_mac_82599EB)
2695 vector = ixgbe_uta_vector(hw,mac_addr);
2696 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2697 uta_shift = vector & ixgbe_uta_bit_mask;
2699 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2703 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2705 uta_info->uta_in_use++;
2706 reg_val |= (bit1 << uta_shift);
2707 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2709 uta_info->uta_in_use--;
2710 reg_val &= ~(bit1 << uta_shift);
2711 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2714 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2716 if (uta_info->uta_in_use > 0)
2717 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2718 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2720 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2726 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2729 struct ixgbe_hw *hw =
2730 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2731 struct ixgbe_uta_info *uta_info =
2732 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2734 /* The UTA table only exists on 82599 hardware and newer */
2735 if (hw->mac.type < ixgbe_mac_82599EB)
2739 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2740 uta_info->uta_shadow[i] = ~0;
2741 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2744 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2745 uta_info->uta_shadow[i] = 0;
2746 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2753 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2754 uint16_t rx_mask, uint8_t on)
2758 struct ixgbe_hw *hw =
2759 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2760 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2762 if (hw->mac.type == ixgbe_mac_82598EB) {
2763 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2764 " on 82599 hardware and newer\n");
2767 if (ixgbe_vmdq_mode_check(hw) < 0)
2770 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2771 val |= IXGBE_VMOLR_AUPE;
2772 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2773 val |= IXGBE_VMOLR_ROMPE;
2774 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2775 val |= IXGBE_VMOLR_ROPE;
2776 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2777 val |= IXGBE_VMOLR_BAM;
2778 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2779 val |= IXGBE_VMOLR_MPE;
2786 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2792 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2796 const uint8_t bit1 = 0x1;
2798 struct ixgbe_hw *hw =
2799 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801 if (ixgbe_vmdq_mode_check(hw) < 0)
2804 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2805 reg = IXGBE_READ_REG(hw, addr);
2813 IXGBE_WRITE_REG(hw, addr,reg);
2819 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2823 const uint8_t bit1 = 0x1;
2825 struct ixgbe_hw *hw =
2826 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2828 if (ixgbe_vmdq_mode_check(hw) < 0)
2831 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2832 reg = IXGBE_READ_REG(hw, addr);
2840 IXGBE_WRITE_REG(hw, addr,reg);
2846 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2847 uint64_t pool_mask, uint8_t vlan_on)
2851 struct ixgbe_hw *hw =
2852 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854 if (ixgbe_vmdq_mode_check(hw) < 0)
2856 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2857 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2858 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2867 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2868 struct rte_eth_vmdq_mirror_conf *mirror_conf,
2869 uint8_t rule_id, uint8_t on)
2871 uint32_t mr_ctl,vlvf;
2872 uint32_t mp_lsb = 0;
2873 uint32_t mv_msb = 0;
2874 uint32_t mv_lsb = 0;
2875 uint32_t mp_msb = 0;
2878 uint64_t vlan_mask = 0;
2880 const uint8_t pool_mask_offset = 32;
2881 const uint8_t vlan_mask_offset = 32;
2882 const uint8_t dst_pool_offset = 8;
2883 const uint8_t rule_mr_offset = 4;
2884 const uint8_t mirror_rule_mask= 0x0F;
2886 struct ixgbe_mirror_info *mr_info =
2887 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2888 struct ixgbe_hw *hw =
2889 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891 if (ixgbe_vmdq_mode_check(hw) < 0)
2894 /* Check if vlan mask is valid */
2895 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2896 if (mirror_conf->vlan.vlan_mask == 0)
2900 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2901 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2902 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2903 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2904 /* search vlan id related pool vlan filter index */
2905 reg_index = ixgbe_find_vlvf_slot(hw,
2906 mirror_conf->vlan.vlan_id[i]);
2909 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2910 if ((vlvf & IXGBE_VLVF_VIEN) &&
2911 ((vlvf & IXGBE_VLVF_VLANID_MASK)
2912 == mirror_conf->vlan.vlan_id[i]))
2913 vlan_mask |= (1ULL << reg_index);
2920 mv_lsb = vlan_mask & 0xFFFFFFFF;
2921 mv_msb = vlan_mask >> vlan_mask_offset;
2923 mr_info->mr_conf[rule_id].vlan.vlan_mask =
2924 mirror_conf->vlan.vlan_mask;
2925 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2926 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2927 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2928 mirror_conf->vlan.vlan_id[i];
2933 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
2934 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
2935 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
2940 * if enable pool mirror, write related pool mask register,if disable
2941 * pool mirror, clear PFMRVM register
2943 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2945 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
2946 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
2947 mr_info->mr_conf[rule_id].pool_mask =
2948 mirror_conf->pool_mask;
2953 mr_info->mr_conf[rule_id].pool_mask = 0;
2957 /* read mirror control register and recalculate it */
2958 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
2961 mr_ctl |= mirror_conf->rule_type_mask;
2962 mr_ctl &= mirror_rule_mask;
2963 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
2965 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
2967 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
2968 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
2970 /* write mirrror control register */
2971 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
2973 /* write pool mirrror control register */
2974 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2975 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
2976 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
2979 /* write VLAN mirrror control register */
2980 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2981 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
2982 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
2990 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
2993 uint32_t lsb_val = 0;
2994 uint32_t msb_val = 0;
2995 const uint8_t rule_mr_offset = 4;
2997 struct ixgbe_hw *hw =
2998 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999 struct ixgbe_mirror_info *mr_info =
3000 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3002 if (ixgbe_vmdq_mode_check(hw) < 0)
3005 memset(&mr_info->mr_conf[rule_id], 0,
3006 sizeof(struct rte_eth_vmdq_mirror_conf));
3008 /* clear PFVMCTL register */
3009 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3011 /* clear pool mask register */
3012 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3013 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3015 /* clear vlan mask register */
3016 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3017 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);