lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  96
  97 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  98
  99 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 100                 struct rte_eth_dev *eth_dev);
 101 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 102 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 104 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 105 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 106 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 107 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 108 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 109 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 110 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 111 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 112                                 int wait_to_complete);
 113 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_stats *stats);
 115 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 116 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 117                                              uint16_t queue_id,
 118                                              uint8_t stat_idx,
 119                                              uint8_t is_rx);
 120 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 121                                 struct rte_eth_dev_info *dev_info);
 122
 123 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 128 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 129                 uint16_t queue, bool on);
 130 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 131                 int on);
 132 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 133 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 134 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 135 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 136 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 137
 138 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 139 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 140 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 141                                struct rte_eth_fc_conf *fc_conf);
 142 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 143                                struct rte_eth_fc_conf *fc_conf);
 144 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 145                 struct rte_eth_pfc_conf *pfc_conf);
 146 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 147                 struct rte_eth_rss_reta *reta_conf);
 148 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 149                 struct rte_eth_rss_reta *reta_conf);
 150 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 154 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 155                 void *param);
 156 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 157 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 158                 uint32_t index, uint32_t pool);
 159 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 160 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 161
 162 /* For Virtual Function support */
 163 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 164                 struct rte_eth_dev *eth_dev);
 165 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 166 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 167 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 168 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 169 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 170 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 171                 struct rte_eth_stats *stats);
 172 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 173 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 174                 uint16_t vlan_id, int on);
 175 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 176                 uint16_t queue, int on);
 177 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 178 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 179
 180 /* For Eth VMDQ APIs support */
 181 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 182                 ether_addr* mac_addr,uint8_t on);
 183 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 184 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 185                 uint16_t rx_mask, uint8_t on);
 186 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 187 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 188 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 189                 uint64_t pool_mask,uint8_t vlan_on);
 190 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 191                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 192                 uint8_t rule_id, uint8_t on);
 193 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 194                 uint8_t rule_id);
 195
 196 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 197                 uint16_t queue_idx, uint16_t tx_rate);
 198 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 199                 uint16_t tx_rate, uint64_t q_msk);
 200
 201 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 202                                  struct ether_addr *mac_addr,
 203                                  uint32_t index, uint32_t pool);
 204 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 205 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 206                         struct rte_syn_filter *filter, uint16_t rx_queue);
 207 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 208 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 209                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 210 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 211                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 212 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 213                         uint16_t index);
 214 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 215                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 216 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 217                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 218 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 219                         uint16_t index);
 220 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 221                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 222
 223 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 224
 225 /*
 226  * Define VF Stats MACRO for Non "cleared on read" register
 227  */
 228 #define UPDATE_VF_STAT(reg, last, cur)                          \
 229 {                                                               \
 230         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 231         cur += latest - last;                                   \
 232         last = latest;                                          \
 233 }
 234
 235 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 236 {                                                                \
 237         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 238         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 239         u64 latest = ((new_msb << 32) | new_lsb);                \
 240         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 241         last = latest;                                           \
 242 }
 243
 244 #define IXGBE_SET_HWSTRIP(h, q) do{\
 245                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 246                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 247                 (h)->bitmap[idx] |= 1 << bit;\
 248         }while(0)
 249
 250 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 251                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 252                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 253                 (h)->bitmap[idx] &= ~(1 << bit);\
 254         }while(0)
 255
 256 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 257                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 258                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 259                 (r) = (h)->bitmap[idx] >> bit & 1;\
 260         }while(0)
 261
 262 /*
 263  * The set of PCI devices this driver supports
 264  */
 265 static struct rte_pci_id pci_id_ixgbe_map[] = {
 266
 267 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 268 #include "rte_pci_dev_ids.h"
 269
 270 { .vendor_id = 0, /* sentinel */ },
 271 };
 272
 273
 274 /*
 275  * The set of PCI devices this driver supports (for 82599 VF)
 276  */
 277 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 278
 279 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 280 #include "rte_pci_dev_ids.h"
 281 { .vendor_id = 0, /* sentinel */ },
 282
 283 };
 284
 285 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 286         .dev_configure        = ixgbe_dev_configure,
 287         .dev_start            = ixgbe_dev_start,
 288         .dev_stop             = ixgbe_dev_stop,
 289         .dev_set_link_up    = ixgbe_dev_set_link_up,
 290         .dev_set_link_down  = ixgbe_dev_set_link_down,
 291         .dev_close            = ixgbe_dev_close,
 292         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 293         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 294         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 295         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 296         .link_update          = ixgbe_dev_link_update,
 297         .stats_get            = ixgbe_dev_stats_get,
 298         .stats_reset          = ixgbe_dev_stats_reset,
 299         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 300         .dev_infos_get        = ixgbe_dev_info_get,
 301         .mtu_set              = ixgbe_dev_mtu_set,
 302         .vlan_filter_set      = ixgbe_vlan_filter_set,
 303         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 304         .vlan_offload_set     = ixgbe_vlan_offload_set,
 305         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 306         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 307         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 308         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 309         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 310         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 311         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 312         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 313         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 314         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 315         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 316         .dev_led_on           = ixgbe_dev_led_on,
 317         .dev_led_off          = ixgbe_dev_led_off,
 318         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 319         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 320         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 321         .mac_addr_add         = ixgbe_add_rar,
 322         .mac_addr_remove      = ixgbe_remove_rar,
 323         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 324         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 325         .mirror_rule_set      = ixgbe_mirror_rule_set,
 326         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 327         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 328         .set_vf_rx            = ixgbe_set_pool_rx,
 329         .set_vf_tx            = ixgbe_set_pool_tx,
 330         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 331         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 332         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 333         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 334         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 335         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 336         .fdir_infos_get               = ixgbe_fdir_info_get,
 337         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 338         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 339         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 340         .fdir_set_masks               = ixgbe_fdir_set_masks,
 341         .reta_update          = ixgbe_dev_rss_reta_update,
 342         .reta_query           = ixgbe_dev_rss_reta_query,
 343 #ifdef RTE_NIC_BYPASS
 344         .bypass_init          = ixgbe_bypass_init,
 345         .bypass_state_set     = ixgbe_bypass_state_store,
 346         .bypass_state_show    = ixgbe_bypass_state_show,
 347         .bypass_event_set     = ixgbe_bypass_event_store,
 348         .bypass_event_show    = ixgbe_bypass_event_show,
 349         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 350         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 351         .bypass_ver_show      = ixgbe_bypass_ver_show,
 352         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 353 #endif /* RTE_NIC_BYPASS */
 354         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 355         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 356         .add_syn_filter          = ixgbe_add_syn_filter,
 357         .remove_syn_filter       = ixgbe_remove_syn_filter,
 358         .get_syn_filter          = ixgbe_get_syn_filter,
 359         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 360         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 361         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 362         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 363         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 364         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 365 };
 366
 367 /*
 368  * dev_ops for virtual function, bare necessities for basic vf
 369  * operation have been implemented
 370  */
 371 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 372
 373         .dev_configure        = ixgbevf_dev_configure,
 374         .dev_start            = ixgbevf_dev_start,
 375         .dev_stop             = ixgbevf_dev_stop,
 376         .link_update          = ixgbe_dev_link_update,
 377         .stats_get            = ixgbevf_dev_stats_get,
 378         .stats_reset          = ixgbevf_dev_stats_reset,
 379         .dev_close            = ixgbevf_dev_close,
 380         .dev_infos_get        = ixgbe_dev_info_get,
 381         .mtu_set              = ixgbevf_dev_set_mtu,
 382         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 383         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 384         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 385         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 386         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 387         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 388         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 389         .mac_addr_add         = ixgbevf_add_mac_addr,
 390         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 391 };
 392
 393 /**
 394  * Atomically reads the link status information from global
 395  * structure rte_eth_dev.
 396  *
 397  * @param dev
 398  *   - Pointer to the structure rte_eth_dev to read from.
 399  *   - Pointer to the buffer to be saved with the link status.
 400  *
 401  * @return
 402  *   - On success, zero.
 403  *   - On failure, negative value.
 404  */
 405 static inline int
 406 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 407                                 struct rte_eth_link *link)
 408 {
 409         struct rte_eth_link *dst = link;
 410         struct rte_eth_link *src = &(dev->data->dev_link);
 411
 412         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 413                                         *(uint64_t *)src) == 0)
 414                 return -1;
 415
 416         return 0;
 417 }
 418
 419 /**
 420  * Atomically writes the link status information into global
 421  * structure rte_eth_dev.
 422  *
 423  * @param dev
 424  *   - Pointer to the structure rte_eth_dev to read from.
 425  *   - Pointer to the buffer to be saved with the link status.
 426  *
 427  * @return
 428  *   - On success, zero.
 429  *   - On failure, negative value.
 430  */
 431 static inline int
 432 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 433                                 struct rte_eth_link *link)
 434 {
 435         struct rte_eth_link *dst = &(dev->data->dev_link);
 436         struct rte_eth_link *src = link;
 437
 438         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 439                                         *(uint64_t *)src) == 0)
 440                 return -1;
 441
 442         return 0;
 443 }
 444
 445 /*
 446  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 447  */
 448 static inline int
 449 ixgbe_is_sfp(struct ixgbe_hw *hw)
 450 {
 451         switch (hw->phy.type) {
 452         case ixgbe_phy_sfp_avago:
 453         case ixgbe_phy_sfp_ftl:
 454         case ixgbe_phy_sfp_intel:
 455         case ixgbe_phy_sfp_unknown:
 456         case ixgbe_phy_sfp_passive_tyco:
 457         case ixgbe_phy_sfp_passive_unknown:
 458                 return 1;
 459         default:
 460                 return 0;
 461         }
 462 }
 463
 464 static inline int32_t
 465 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 466 {
 467         uint32_t ctrl_ext;
 468         int32_t status;
 469
 470         status = ixgbe_reset_hw(hw);
 471
 472         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 473         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 474         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 475         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 476         IXGBE_WRITE_FLUSH(hw);
 477
 478         return status;
 479 }
 480
 481 static inline void
 482 ixgbe_enable_intr(struct rte_eth_dev *dev)
 483 {
 484         struct ixgbe_interrupt *intr =
 485                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 486         struct ixgbe_hw *hw =
 487                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 488
 489         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 490         IXGBE_WRITE_FLUSH(hw);
 491 }
 492
 493 /*
 494  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 495  */
 496 static void
 497 ixgbe_disable_intr(struct ixgbe_hw *hw)
 498 {
 499         PMD_INIT_FUNC_TRACE();
 500
 501         if (hw->mac.type == ixgbe_mac_82598EB) {
 502                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 503         } else {
 504                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 505                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 506                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 507         }
 508         IXGBE_WRITE_FLUSH(hw);
 509 }
 510
 511 /*
 512  * This function resets queue statistics mapping registers.
 513  * From Niantic datasheet, Initialization of Statistics section:
 514  * "...if software requires the queue counters, the RQSMR and TQSM registers
 515  * must be re-programmed following a device reset.
 516  */
 517 static void
 518 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 519 {
 520         uint32_t i;
 521
 522         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 523                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 524                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 525         }
 526 }
 527
 528
 529 static int
 530 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 531                                   uint16_t queue_id,
 532                                   uint8_t stat_idx,
 533                                   uint8_t is_rx)
 534 {
 535 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 536 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 537 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 538
 539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 540         struct ixgbe_stat_mapping_registers *stat_mappings =
 541                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 542         uint32_t qsmr_mask = 0;
 543         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 544         uint32_t q_map;
 545         uint8_t n, offset;
 546
 547         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 548                 return -ENOSYS;
 549
 550         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 551                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 552                      queue_id, stat_idx);
 553
 554         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 555         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 556                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 557                 return -EIO;
 558         }
 559         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 560
 561         /* Now clear any previous stat_idx set */
 562         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 563         if (!is_rx)
 564                 stat_mappings->tqsm[n] &= ~clearing_mask;
 565         else
 566                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 567
 568         q_map = (uint32_t)stat_idx;
 569         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 570         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 571         if (!is_rx)
 572                 stat_mappings->tqsm[n] |= qsmr_mask;
 573         else
 574                 stat_mappings->rqsmr[n] |= qsmr_mask;
 575
 576         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 577                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 578                      queue_id, stat_idx);
 579         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 580                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 581
 582         /* Now write the mapping in the appropriate register */
 583         if (is_rx) {
 584                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 585                              stat_mappings->rqsmr[n], n);
 586                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 587         }
 588         else {
 589                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 590                              stat_mappings->tqsm[n], n);
 591                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 592         }
 593         return 0;
 594 }
 595
 596 static void
 597 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 598 {
 599         struct ixgbe_stat_mapping_registers *stat_mappings =
 600                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 601         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 602         int i;
 603
 604         /* write whatever was in stat mapping table to the NIC */
 605         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 606                 /* rx */
 607                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 608
 609                 /* tx */
 610                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 611         }
 612 }
 613
 614 static void
 615 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 616 {
 617         uint8_t i;
 618         struct ixgbe_dcb_tc_config *tc;
 619         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 620
 621         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 622         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 623         for (i = 0; i < dcb_max_tc; i++) {
 624                 tc = &dcb_config->tc_config[i];
 625                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 626                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 627                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 628                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 629                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 630                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 631                 tc->pfc = ixgbe_dcb_pfc_disabled;
 632         }
 633
 634         /* Initialize default user to priority mapping, UPx->TC0 */
 635         tc = &dcb_config->tc_config[0];
 636         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 637         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 638         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 639                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 640                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 641         }
 642         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 643         dcb_config->pfc_mode_enable = false;
 644         dcb_config->vt_mode = true;
 645         dcb_config->round_robin_enable = false;
 646         /* support all DCB capabilities in 82599 */
 647         dcb_config->support.capabilities = 0xFF;
 648
 649         /*we only support 4 Tcs for X540*/
 650         if (hw->mac.type == ixgbe_mac_X540) {
 651                 dcb_config->num_tcs.pg_tcs = 4;
 652                 dcb_config->num_tcs.pfc_tcs = 4;
 653         }
 654 }
 655
 656 /*
 657  * Ensure that all locks are released before first NVM or PHY access
 658  */
 659 static void
 660 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 661 {
 662         uint16_t mask;
 663
 664         /*
 665          * Phy lock should not fail in this early stage. If this is the case,
 666          * it is due to an improper exit of the application.
 667          * So force the release of the faulty lock. Release of common lock
 668          * is done automatically by swfw_sync function.
 669          */
 670         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 671         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 672                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 673         }
 674         ixgbe_release_swfw_semaphore(hw, mask);
 675
 676         /*
 677          * These ones are more tricky since they are common to all ports; but
 678          * swfw_sync retries last long enough (1s) to be almost sure that if
 679          * lock can not be taken it is due to an improper lock of the
 680          * semaphore.
 681          */
 682         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 683         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 684                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 685         }
 686         ixgbe_release_swfw_semaphore(hw, mask);
 687 }
 688
 689 /*
 690  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 691  * It returns 0 on success.
 692  */
 693 static int
 694 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 695                      struct rte_eth_dev *eth_dev)
 696 {
 697         struct rte_pci_device *pci_dev;
 698         struct ixgbe_hw *hw =
 699                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 700         struct ixgbe_vfta * shadow_vfta =
 701                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 702         struct ixgbe_hwstrip *hwstrip =
 703                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 704         struct ixgbe_dcb_config *dcb_config =
 705                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 706         uint32_t ctrl_ext;
 707         uint16_t csum;
 708         int diag, i;
 709
 710         PMD_INIT_FUNC_TRACE();
 711
 712         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 713         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 714         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 715
 716         /* for secondary processes, we don't initialise any further as primary
 717          * has already done this work. Only check we don't need a different
 718          * RX function */
 719         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 720                 if (eth_dev->data->scattered_rx)
 721                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 722                 return 0;
 723         }
 724         pci_dev = eth_dev->pci_dev;
 725
 726         /* Vendor and Device ID need to be set before init of shared code */
 727         hw->device_id = pci_dev->id.device_id;
 728         hw->vendor_id = pci_dev->id.vendor_id;
 729         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 730         hw->allow_unsupported_sfp = 1;
 731
 732         /* Initialize the shared code (base driver) */
 733 #ifdef RTE_NIC_BYPASS
 734         diag = ixgbe_bypass_init_shared_code(hw);
 735 #else
 736         diag = ixgbe_init_shared_code(hw);
 737 #endif /* RTE_NIC_BYPASS */
 738
 739         if (diag != IXGBE_SUCCESS) {
 740                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 741                 return -EIO;
 742         }
 743
 744         /* pick up the PCI bus settings for reporting later */
 745         ixgbe_get_bus_info(hw);
 746
 747         /* Unlock any pending hardware semaphore */
 748         ixgbe_swfw_lock_reset(hw);
 749
 750         /* Initialize DCB configuration*/
 751         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 752         ixgbe_dcb_init(hw,dcb_config);
 753         /* Get Hardware Flow Control setting */
 754         hw->fc.requested_mode = ixgbe_fc_full;
 755         hw->fc.current_mode = ixgbe_fc_full;
 756         hw->fc.pause_time = IXGBE_FC_PAUSE;
 757         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 758                 hw->fc.low_water[i] = IXGBE_FC_LO;
 759                 hw->fc.high_water[i] = IXGBE_FC_HI;
 760         }
 761         hw->fc.send_xon = 1;
 762
 763         /* Make sure we have a good EEPROM before we read from it */
 764         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 765         if (diag != IXGBE_SUCCESS) {
 766                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 767                 return -EIO;
 768         }
 769
 770 #ifdef RTE_NIC_BYPASS
 771         diag = ixgbe_bypass_init_hw(hw);
 772 #else
 773         diag = ixgbe_init_hw(hw);
 774 #endif /* RTE_NIC_BYPASS */
 775
 776         /*
 777          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 778          * is called too soon after the kernel driver unbinding/binding occurs.
 779          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 780          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 781          * also called. See ixgbe_identify_phy_82599(). The reason for the
 782          * failure is not known, and only occuts when virtualisation features
 783          * are disabled in the bios. A delay of 100ms  was found to be enough by
 784          * trial-and-error, and is doubled to be safe.
 785          */
 786         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 787                 rte_delay_ms(200);
 788                 diag = ixgbe_init_hw(hw);
 789         }
 790
 791         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 792                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 793                     "LOM.  Please be aware there may be issues associated "
 794                     "with your hardware.");
 795                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 796                     "please contact your Intel or hardware representative "
 797                     "who provided you with this hardware.");
 798         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 799                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 800         if (diag) {
 801                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 802                 return -EIO;
 803         }
 804
 805         /* disable interrupt */
 806         ixgbe_disable_intr(hw);
 807
 808         /* reset mappings for queue statistics hw counters*/
 809         ixgbe_reset_qstat_mappings(hw);
 810
 811         /* Allocate memory for storing MAC addresses */
 812         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 813                         hw->mac.num_rar_entries, 0);
 814         if (eth_dev->data->mac_addrs == NULL) {
 815                 PMD_INIT_LOG(ERR,
 816                         "Failed to allocate %u bytes needed to store "
 817                         "MAC addresses",
 818                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 819                 return -ENOMEM;
 820         }
 821         /* Copy the permanent MAC address */
 822         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 823                         &eth_dev->data->mac_addrs[0]);
 824
 825         /* Allocate memory for storing hash filter MAC addresses */
 826         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 827                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 828         if (eth_dev->data->hash_mac_addrs == NULL) {
 829                 PMD_INIT_LOG(ERR,
 830                         "Failed to allocate %d bytes needed to store MAC addresses",
 831                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 832                 return -ENOMEM;
 833         }
 834
 835         /* initialize the vfta */
 836         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 837
 838         /* initialize the hw strip bitmap*/
 839         memset(hwstrip, 0, sizeof(*hwstrip));
 840
 841         /* initialize PF if max_vfs not zero */
 842         ixgbe_pf_host_init(eth_dev);
 843
 844         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 845         /* let hardware know driver is loaded */
 846         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 847         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 848         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 849         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 850         IXGBE_WRITE_FLUSH(hw);
 851
 852         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 853                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 854                              (int) hw->mac.type, (int) hw->phy.type,
 855                              (int) hw->phy.sfp_type);
 856         else
 857                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 858                              (int) hw->mac.type, (int) hw->phy.type);
 859
 860         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 861                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 862                         pci_dev->id.device_id);
 863
 864         rte_intr_callback_register(&(pci_dev->intr_handle),
 865                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 866
 867         /* enable uio intr after callback register */
 868         rte_intr_enable(&(pci_dev->intr_handle));
 869
 870         /* enable support intr */
 871         ixgbe_enable_intr(eth_dev);
 872
 873         return 0;
 874 }
 875
 876
 877 /*
 878  * Negotiate mailbox API version with the PF.
 879  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 880  * Then we try to negotiate starting with the most recent one.
 881  * If all negotiation attempts fail, then we will proceed with
 882  * the default one (ixgbe_mbox_api_10).
 883  */
 884 static void
 885 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 886 {
 887         int32_t i;
 888
 889         /* start with highest supported, proceed down */
 890         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 891                 ixgbe_mbox_api_11,
 892                 ixgbe_mbox_api_10,
 893         };
 894
 895         for (i = 0;
 896                         i != RTE_DIM(sup_ver) &&
 897                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 898                         i++)
 899                 ;
 900 }
 901
 902 static void
 903 generate_random_mac_addr(struct ether_addr *mac_addr)
 904 {
 905         uint64_t random;
 906
 907         /* Set Organizationally Unique Identifier (OUI) prefix. */
 908         mac_addr->addr_bytes[0] = 0x00;
 909         mac_addr->addr_bytes[1] = 0x09;
 910         mac_addr->addr_bytes[2] = 0xC0;
 911         /* Force indication of locally assigned MAC address. */
 912         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 913         /* Generate the last 3 bytes of the MAC address with a random number. */
 914         random = rte_rand();
 915         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 916 }
 917
 918 /*
 919  * Virtual Function device init
 920  */
 921 static int
 922 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 923                      struct rte_eth_dev *eth_dev)
 924 {
 925         int diag;
 926         uint32_t tc, tcs;
 927         struct rte_pci_device *pci_dev;
 928         struct ixgbe_hw *hw =
 929                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 930         struct ixgbe_vfta * shadow_vfta =
 931                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 932         struct ixgbe_hwstrip *hwstrip =
 933                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 934         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 935
 936         PMD_INIT_FUNC_TRACE();
 937
 938         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 939         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 940         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 941
 942         /* for secondary processes, we don't initialise any further as primary
 943          * has already done this work. Only check we don't need a different
 944          * RX function */
 945         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 946                 if (eth_dev->data->scattered_rx)
 947                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 948                 return 0;
 949         }
 950
 951         pci_dev = eth_dev->pci_dev;
 952
 953         hw->device_id = pci_dev->id.device_id;
 954         hw->vendor_id = pci_dev->id.vendor_id;
 955         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 956
 957         /* initialize the vfta */
 958         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 959
 960         /* initialize the hw strip bitmap*/
 961         memset(hwstrip, 0, sizeof(*hwstrip));
 962
 963         /* Initialize the shared code (base driver) */
 964         diag = ixgbe_init_shared_code(hw);
 965         if (diag != IXGBE_SUCCESS) {
 966                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 967                 return -EIO;
 968         }
 969
 970         /* init_mailbox_params */
 971         hw->mbx.ops.init_params(hw);
 972
 973         /* Disable the interrupts for VF */
 974         ixgbevf_intr_disable(hw);
 975
 976         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
 977         diag = hw->mac.ops.reset_hw(hw);
 978
 979         /*
 980          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
 981          * the underlying PF driver has not assigned a MAC address to the VF.
 982          * In this case, assign a random MAC address.
 983          */
 984         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
 985                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 986                 return (diag);
 987         }
 988
 989         /* negotiate mailbox API version to use with the PF. */
 990         ixgbevf_negotiate_api(hw);
 991
 992         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
 993         ixgbevf_get_queues(hw, &tcs, &tc);
 994
 995         /* Allocate memory for storing MAC addresses */
 996         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 997                         hw->mac.num_rar_entries, 0);
 998         if (eth_dev->data->mac_addrs == NULL) {
 999                 PMD_INIT_LOG(ERR,
1000                         "Failed to allocate %u bytes needed to store "
1001                         "MAC addresses",
1002                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1003                 return -ENOMEM;
1004         }
1005
1006         /* Generate a random MAC address, if none was assigned by PF. */
1007         if (is_zero_ether_addr(perm_addr)) {
1008                 generate_random_mac_addr(perm_addr);
1009                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1010                 if (diag) {
1011                         rte_free(eth_dev->data->mac_addrs);
1012                         eth_dev->data->mac_addrs = NULL;
1013                         return diag;
1014                 }
1015                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1016                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1017                              "%02x:%02x:%02x:%02x:%02x:%02x",
1018                              perm_addr->addr_bytes[0],
1019                              perm_addr->addr_bytes[1],
1020                              perm_addr->addr_bytes[2],
1021                              perm_addr->addr_bytes[3],
1022                              perm_addr->addr_bytes[4],
1023                              perm_addr->addr_bytes[5]);
1024         }
1025
1026         /* Copy the permanent MAC address */
1027         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1028
1029         /* reset the hardware with the new settings */
1030         diag = hw->mac.ops.start_hw(hw);
1031         switch (diag) {
1032                 case  0:
1033                         break;
1034
1035                 default:
1036                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1037                         return (-EIO);
1038         }
1039
1040         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1041                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1042                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1043
1044         return 0;
1045 }
1046
1047 static struct eth_driver rte_ixgbe_pmd = {
1048         {
1049                 .name = "rte_ixgbe_pmd",
1050                 .id_table = pci_id_ixgbe_map,
1051                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1052         },
1053         .eth_dev_init = eth_ixgbe_dev_init,
1054         .dev_private_size = sizeof(struct ixgbe_adapter),
1055 };
1056
1057 /*
1058  * virtual function driver struct
1059  */
1060 static struct eth_driver rte_ixgbevf_pmd = {
1061         {
1062                 .name = "rte_ixgbevf_pmd",
1063                 .id_table = pci_id_ixgbevf_map,
1064                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1065         },
1066         .eth_dev_init = eth_ixgbevf_dev_init,
1067         .dev_private_size = sizeof(struct ixgbe_adapter),
1068 };
1069
1070 /*
1071  * Driver initialization routine.
1072  * Invoked once at EAL init time.
1073  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1074  */
1075 static int
1076 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1077 {
1078         PMD_INIT_FUNC_TRACE();
1079
1080         rte_eth_driver_register(&rte_ixgbe_pmd);
1081         return 0;
1082 }
1083
1084 /*
1085  * VF Driver initialization routine.
1086  * Invoked one at EAL init time.
1087  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1088  */
1089 static int
1090 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1091 {
1092         PMD_INIT_FUNC_TRACE();
1093
1094         rte_eth_driver_register(&rte_ixgbevf_pmd);
1095         return (0);
1096 }
1097
1098 static int
1099 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1100 {
1101         struct ixgbe_hw *hw =
1102                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103         struct ixgbe_vfta * shadow_vfta =
1104                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1105         uint32_t vfta;
1106         uint32_t vid_idx;
1107         uint32_t vid_bit;
1108
1109         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1110         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1111         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1112         if (on)
1113                 vfta |= vid_bit;
1114         else
1115                 vfta &= ~vid_bit;
1116         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1117
1118         /* update local VFTA copy */
1119         shadow_vfta->vfta[vid_idx] = vfta;
1120
1121         return 0;
1122 }
1123
1124 static void
1125 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1126 {
1127         if (on)
1128                 ixgbe_vlan_hw_strip_enable(dev, queue);
1129         else
1130                 ixgbe_vlan_hw_strip_disable(dev, queue);
1131 }
1132
1133 static void
1134 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1135 {
1136         struct ixgbe_hw *hw =
1137                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1138
1139         /* Only the high 16-bits is valid */
1140         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1141 }
1142
1143 void
1144 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1145 {
1146         struct ixgbe_hw *hw =
1147                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1148         uint32_t vlnctrl;
1149
1150         PMD_INIT_FUNC_TRACE();
1151
1152         /* Filter Table Disable */
1153         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1154         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1155
1156         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1157 }
1158
1159 void
1160 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1161 {
1162         struct ixgbe_hw *hw =
1163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1164         struct ixgbe_vfta * shadow_vfta =
1165                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1166         uint32_t vlnctrl;
1167         uint16_t i;
1168
1169         PMD_INIT_FUNC_TRACE();
1170
1171         /* Filter Table Enable */
1172         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1173         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1174         vlnctrl |= IXGBE_VLNCTRL_VFE;
1175
1176         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1177
1178         /* write whatever is in local vfta copy */
1179         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1180                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1181 }
1182
1183 static void
1184 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1185 {
1186         struct ixgbe_hwstrip *hwstrip =
1187                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1188
1189         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1190                 return;
1191
1192         if (on)
1193                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1194         else
1195                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1196 }
1197
1198 static void
1199 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1200 {
1201         struct ixgbe_hw *hw =
1202                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203         uint32_t ctrl;
1204
1205         PMD_INIT_FUNC_TRACE();
1206
1207         if (hw->mac.type == ixgbe_mac_82598EB) {
1208                 /* No queue level support */
1209                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1210                 return;
1211         }
1212         else {
1213                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1214                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1215                 ctrl &= ~IXGBE_RXDCTL_VME;
1216                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1217         }
1218         /* record those setting for HW strip per queue */
1219         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1220 }
1221
1222 static void
1223 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1224 {
1225         struct ixgbe_hw *hw =
1226                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1227         uint32_t ctrl;
1228
1229         PMD_INIT_FUNC_TRACE();
1230
1231         if (hw->mac.type == ixgbe_mac_82598EB) {
1232                 /* No queue level supported */
1233                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1234                 return;
1235         }
1236         else {
1237                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1238                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1239                 ctrl |= IXGBE_RXDCTL_VME;
1240                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1241         }
1242         /* record those setting for HW strip per queue */
1243         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1244 }
1245
1246 void
1247 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1248 {
1249         struct ixgbe_hw *hw =
1250                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1251         uint32_t ctrl;
1252         uint16_t i;
1253
1254         PMD_INIT_FUNC_TRACE();
1255
1256         if (hw->mac.type == ixgbe_mac_82598EB) {
1257                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1258                 ctrl &= ~IXGBE_VLNCTRL_VME;
1259                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1260         }
1261         else {
1262                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1263                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1264                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1265                         ctrl &= ~IXGBE_RXDCTL_VME;
1266                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1267
1268                         /* record those setting for HW strip per queue */
1269                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1270                 }
1271         }
1272 }
1273
1274 void
1275 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1276 {
1277         struct ixgbe_hw *hw =
1278                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1279         uint32_t ctrl;
1280         uint16_t i;
1281
1282         PMD_INIT_FUNC_TRACE();
1283
1284         if (hw->mac.type == ixgbe_mac_82598EB) {
1285                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1286                 ctrl |= IXGBE_VLNCTRL_VME;
1287                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1288         }
1289         else {
1290                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1291                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1292                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1293                         ctrl |= IXGBE_RXDCTL_VME;
1294                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1295
1296                         /* record those setting for HW strip per queue */
1297                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1298                 }
1299         }
1300 }
1301
1302 static void
1303 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1304 {
1305         struct ixgbe_hw *hw =
1306                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307         uint32_t ctrl;
1308
1309         PMD_INIT_FUNC_TRACE();
1310
1311         /* DMATXCTRL: Geric Double VLAN Disable */
1312         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1313         ctrl &= ~IXGBE_DMATXCTL_GDV;
1314         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1315
1316         /* CTRL_EXT: Global Double VLAN Disable */
1317         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1318         ctrl &= ~IXGBE_EXTENDED_VLAN;
1319         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1320
1321 }
1322
1323 static void
1324 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1325 {
1326         struct ixgbe_hw *hw =
1327                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1328         uint32_t ctrl;
1329
1330         PMD_INIT_FUNC_TRACE();
1331
1332         /* DMATXCTRL: Geric Double VLAN Enable */
1333         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1334         ctrl |= IXGBE_DMATXCTL_GDV;
1335         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1336
1337         /* CTRL_EXT: Global Double VLAN Enable */
1338         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1339         ctrl |= IXGBE_EXTENDED_VLAN;
1340         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1341
1342         /*
1343          * VET EXT field in the EXVET register = 0x8100 by default
1344          * So no need to change. Same to VT field of DMATXCTL register
1345          */
1346 }
1347
1348 static void
1349 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1350 {
1351         if(mask & ETH_VLAN_STRIP_MASK){
1352                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1353                         ixgbe_vlan_hw_strip_enable_all(dev);
1354                 else
1355                         ixgbe_vlan_hw_strip_disable_all(dev);
1356         }
1357
1358         if(mask & ETH_VLAN_FILTER_MASK){
1359                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1360                         ixgbe_vlan_hw_filter_enable(dev);
1361                 else
1362                         ixgbe_vlan_hw_filter_disable(dev);
1363         }
1364
1365         if(mask & ETH_VLAN_EXTEND_MASK){
1366                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1367                         ixgbe_vlan_hw_extend_enable(dev);
1368                 else
1369                         ixgbe_vlan_hw_extend_disable(dev);
1370         }
1371 }
1372
1373 static void
1374 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1375 {
1376         struct ixgbe_hw *hw =
1377                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1379         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1380         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1381         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1382 }
1383
1384 static int
1385 ixgbe_dev_configure(struct rte_eth_dev *dev)
1386 {
1387         struct ixgbe_interrupt *intr =
1388                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1389
1390         PMD_INIT_FUNC_TRACE();
1391
1392         /* set flag to update link status after init */
1393         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1394
1395         return 0;
1396 }
1397
1398 /*
1399  * Configure device link speed and setup link.
1400  * It returns 0 on success.
1401  */
1402 static int
1403 ixgbe_dev_start(struct rte_eth_dev *dev)
1404 {
1405         struct ixgbe_hw *hw =
1406                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1407         struct ixgbe_vf_info *vfinfo =
1408                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1409         int err, link_up = 0, negotiate = 0;
1410         uint32_t speed = 0;
1411         int mask = 0;
1412         int status;
1413         uint16_t vf, idx;
1414
1415         PMD_INIT_FUNC_TRACE();
1416
1417         /* IXGBE devices don't support half duplex */
1418         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1419                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1420                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1421                              dev->data->dev_conf.link_duplex,
1422                              dev->data->port_id);
1423                 return -EINVAL;
1424         }
1425
1426         /* stop adapter */
1427         hw->adapter_stopped = FALSE;
1428         ixgbe_stop_adapter(hw);
1429
1430         /* reinitialize adapter
1431          * this calls reset and start */
1432         status = ixgbe_pf_reset_hw(hw);
1433         if (status != 0)
1434                 return -1;
1435         hw->mac.ops.start_hw(hw);
1436
1437         /* configure PF module if SRIOV enabled */
1438         ixgbe_pf_host_configure(dev);
1439
1440         /* initialize transmission unit */
1441         ixgbe_dev_tx_init(dev);
1442
1443         /* This can fail when allocating mbufs for descriptor rings */
1444         err = ixgbe_dev_rx_init(dev);
1445         if (err) {
1446                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1447                 goto error;
1448         }
1449
1450         ixgbe_dev_rxtx_start(dev);
1451
1452         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1453                 err = hw->mac.ops.setup_sfp(hw);
1454                 if (err)
1455                         goto error;
1456         }
1457
1458         /* Turn on the laser */
1459         ixgbe_enable_tx_laser(hw);
1460
1461         /* Skip link setup if loopback mode is enabled for 82599. */
1462         if (hw->mac.type == ixgbe_mac_82599EB &&
1463                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1464                 goto skip_link_setup;
1465
1466         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1467         if (err)
1468                 goto error;
1469         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1470         if (err)
1471                 goto error;
1472
1473         switch(dev->data->dev_conf.link_speed) {
1474         case ETH_LINK_SPEED_AUTONEG:
1475                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1476                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1477                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1478                 break;
1479         case ETH_LINK_SPEED_100:
1480                 /*
1481                  * Invalid for 82598 but error will be detected by
1482                  * ixgbe_setup_link()
1483                  */
1484                 speed = IXGBE_LINK_SPEED_100_FULL;
1485                 break;
1486         case ETH_LINK_SPEED_1000:
1487                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1488                 break;
1489         case ETH_LINK_SPEED_10000:
1490                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1491                 break;
1492         default:
1493                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1494                              dev->data->dev_conf.link_speed,
1495                              dev->data->port_id);
1496                 goto error;
1497         }
1498
1499         err = ixgbe_setup_link(hw, speed, link_up);
1500         if (err)
1501                 goto error;
1502
1503 skip_link_setup:
1504
1505         /* check if lsc interrupt is enabled */
1506         if (dev->data->dev_conf.intr_conf.lsc != 0)
1507                 ixgbe_dev_lsc_interrupt_setup(dev);
1508
1509         /* resume enabled intr since hw reset */
1510         ixgbe_enable_intr(dev);
1511
1512         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1513                 ETH_VLAN_EXTEND_MASK;
1514         ixgbe_vlan_offload_set(dev, mask);
1515
1516         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1517                 /* Enable vlan filtering for VMDq */
1518                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1519         }
1520
1521         /* Configure DCB hw */
1522         ixgbe_configure_dcb(dev);
1523
1524         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1525                 err = ixgbe_fdir_configure(dev);
1526                 if (err)
1527                         goto error;
1528         }
1529
1530         /* Restore vf rate limit */
1531         if (vfinfo != NULL) {
1532                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1533                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1534                                 if (vfinfo[vf].tx_rate[idx] != 0)
1535                                         ixgbe_set_vf_rate_limit(dev, vf,
1536                                                 vfinfo[vf].tx_rate[idx],
1537                                                 1 << idx);
1538         }
1539
1540         ixgbe_restore_statistics_mapping(dev);
1541
1542         return (0);
1543
1544 error:
1545         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1546         ixgbe_dev_clear_queues(dev);
1547         return -EIO;
1548 }
1549
1550 /*
1551  * Stop device: disable rx and tx functions to allow for reconfiguring.
1552  */
1553 static void
1554 ixgbe_dev_stop(struct rte_eth_dev *dev)
1555 {
1556         struct rte_eth_link link;
1557         struct ixgbe_hw *hw =
1558                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1559         struct ixgbe_vf_info *vfinfo =
1560                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1561         int vf;
1562
1563         PMD_INIT_FUNC_TRACE();
1564
1565         /* disable interrupts */
1566         ixgbe_disable_intr(hw);
1567
1568         /* reset the NIC */
1569         ixgbe_pf_reset_hw(hw);
1570         hw->adapter_stopped = FALSE;
1571
1572         /* stop adapter */
1573         ixgbe_stop_adapter(hw);
1574
1575         for (vf = 0; vfinfo != NULL &&
1576                      vf < dev->pci_dev->max_vfs; vf++)
1577                 vfinfo[vf].clear_to_send = false;
1578
1579         /* Turn off the laser */
1580         ixgbe_disable_tx_laser(hw);
1581
1582         ixgbe_dev_clear_queues(dev);
1583
1584         /* Clear recorded link status */
1585         memset(&link, 0, sizeof(link));
1586         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1587 }
1588
1589 /*
1590  * Set device link up: enable tx laser.
1591  */
1592 static int
1593 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1594 {
1595         struct ixgbe_hw *hw =
1596                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597         if (hw->mac.type == ixgbe_mac_82599EB) {
1598 #ifdef RTE_NIC_BYPASS
1599                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1600                         /* Not suported in bypass mode */
1601                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1602                                      "by device id 0x%x", hw->device_id);
1603                         return -ENOTSUP;
1604                 }
1605 #endif
1606                 /* Turn on the laser */
1607                 ixgbe_enable_tx_laser(hw);
1608                 return 0;
1609         }
1610
1611         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1612                      hw->device_id);
1613         return -ENOTSUP;
1614 }
1615
1616 /*
1617  * Set device link down: disable tx laser.
1618  */
1619 static int
1620 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1621 {
1622         struct ixgbe_hw *hw =
1623                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1624         if (hw->mac.type == ixgbe_mac_82599EB) {
1625 #ifdef RTE_NIC_BYPASS
1626                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1627                         /* Not suported in bypass mode */
1628                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1629                                      "by device id 0x%x", hw->device_id);
1630                         return -ENOTSUP;
1631                 }
1632 #endif
1633                 /* Turn off the laser */
1634                 ixgbe_disable_tx_laser(hw);
1635                 return 0;
1636         }
1637
1638         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1639                      hw->device_id);
1640         return -ENOTSUP;
1641 }
1642
1643 /*
1644  * Reest and stop device.
1645  */
1646 static void
1647 ixgbe_dev_close(struct rte_eth_dev *dev)
1648 {
1649         struct ixgbe_hw *hw =
1650                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651
1652         PMD_INIT_FUNC_TRACE();
1653
1654         ixgbe_pf_reset_hw(hw);
1655
1656         ixgbe_dev_stop(dev);
1657         hw->adapter_stopped = 1;
1658
1659         ixgbe_disable_pcie_master(hw);
1660
1661         /* reprogram the RAR[0] in case user changed it. */
1662         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1663 }
1664
1665 /*
1666  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1667  */
1668 static void
1669 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1670 {
1671         struct ixgbe_hw *hw =
1672                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673         struct ixgbe_hw_stats *hw_stats =
1674                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1675         uint32_t bprc, lxon, lxoff, total;
1676         uint64_t total_missed_rx, total_qbrc, total_qprc;
1677         unsigned i;
1678
1679         total_missed_rx = 0;
1680         total_qbrc = 0;
1681         total_qprc = 0;
1682
1683         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1684         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1685         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1686         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1687
1688         for (i = 0; i < 8; i++) {
1689                 uint32_t mp;
1690                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1691                 /* global total per queue */
1692                 hw_stats->mpc[i] += mp;
1693                 /* Running comprehensive total for stats display */
1694                 total_missed_rx += hw_stats->mpc[i];
1695                 if (hw->mac.type == ixgbe_mac_82598EB)
1696                         hw_stats->rnbc[i] +=
1697                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1698                 hw_stats->pxontxc[i] +=
1699                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1700                 hw_stats->pxonrxc[i] +=
1701                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1702                 hw_stats->pxofftxc[i] +=
1703                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1704                 hw_stats->pxoffrxc[i] +=
1705                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1706                 hw_stats->pxon2offc[i] +=
1707                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1708         }
1709         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1710                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1711                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1712                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1713                 hw_stats->qbrc[i] +=
1714                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1715                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1716                 hw_stats->qbtc[i] +=
1717                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1718                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1719
1720                 total_qprc += hw_stats->qprc[i];
1721                 total_qbrc += hw_stats->qbrc[i];
1722         }
1723         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1724         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1725         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1726
1727         /* Note that gprc counts missed packets */
1728         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1729
1730         if (hw->mac.type != ixgbe_mac_82598EB) {
1731                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1732                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1733                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1734                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1735                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1736                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1737                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1738                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1739         } else {
1740                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1741                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1742                 /* 82598 only has a counter in the high register */
1743                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1744                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1745                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1746         }
1747
1748         /*
1749          * Workaround: mprc hardware is incorrectly counting
1750          * broadcasts, so for now we subtract those.
1751          */
1752         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1753         hw_stats->bprc += bprc;
1754         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1755         if (hw->mac.type == ixgbe_mac_82598EB)
1756                 hw_stats->mprc -= bprc;
1757
1758         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1759         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1760         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1761         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1762         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1763         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1764
1765         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1766         hw_stats->lxontxc += lxon;
1767         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1768         hw_stats->lxofftxc += lxoff;
1769         total = lxon + lxoff;
1770
1771         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1772         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1773         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1774         hw_stats->gptc -= total;
1775         hw_stats->mptc -= total;
1776         hw_stats->ptc64 -= total;
1777         hw_stats->gotc -= total * ETHER_MIN_LEN;
1778
1779         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1780         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1781         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1782         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1783         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1784         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1785         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1786         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1787         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1788         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1789         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1790         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1791         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1792         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1793         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1794         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1795         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1796         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1797         /* Only read FCOE on 82599 */
1798         if (hw->mac.type != ixgbe_mac_82598EB) {
1799                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1800                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1801                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1802                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1803                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1804         }
1805
1806         if (stats == NULL)
1807                 return;
1808
1809         /* Fill out the rte_eth_stats statistics structure */
1810         stats->ipackets = total_qprc;
1811         stats->ibytes = total_qbrc;
1812         stats->opackets = hw_stats->gptc;
1813         stats->obytes = hw_stats->gotc;
1814         stats->imcasts = hw_stats->mprc;
1815
1816         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1817                 stats->q_ipackets[i] = hw_stats->qprc[i];
1818                 stats->q_opackets[i] = hw_stats->qptc[i];
1819                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1820                 stats->q_obytes[i] = hw_stats->qbtc[i];
1821                 stats->q_errors[i] = hw_stats->qprdc[i];
1822         }
1823
1824         /* Rx Errors */
1825         stats->ibadcrc  = hw_stats->crcerrs;
1826         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1827         stats->imissed  = total_missed_rx;
1828         stats->ierrors  = stats->ibadcrc +
1829                           stats->ibadlen +
1830                           stats->imissed +
1831                           hw_stats->illerrc + hw_stats->errbc;
1832
1833         /* Tx Errors */
1834         stats->oerrors  = 0;
1835
1836         /* XON/XOFF pause frames */
1837         stats->tx_pause_xon  = hw_stats->lxontxc;
1838         stats->rx_pause_xon  = hw_stats->lxonrxc;
1839         stats->tx_pause_xoff = hw_stats->lxofftxc;
1840         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1841
1842         /* Flow Director Stats registers */
1843         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1844         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1845         stats->fdirmatch = hw_stats->fdirmatch;
1846         stats->fdirmiss = hw_stats->fdirmiss;
1847 }
1848
1849 static void
1850 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1851 {
1852         struct ixgbe_hw_stats *stats =
1853                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1854
1855         /* HW registers are cleared on read */
1856         ixgbe_dev_stats_get(dev, NULL);
1857
1858         /* Reset software totals */
1859         memset(stats, 0, sizeof(*stats));
1860 }
1861
1862 static void
1863 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1864 {
1865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1866         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1867                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1868
1869         /* Good Rx packet, include VF loopback */
1870         UPDATE_VF_STAT(IXGBE_VFGPRC,
1871             hw_stats->last_vfgprc, hw_stats->vfgprc);
1872
1873         /* Good Rx octets, include VF loopback */
1874         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1875             hw_stats->last_vfgorc, hw_stats->vfgorc);
1876
1877         /* Good Tx packet, include VF loopback */
1878         UPDATE_VF_STAT(IXGBE_VFGPTC,
1879             hw_stats->last_vfgptc, hw_stats->vfgptc);
1880
1881         /* Good Tx octets, include VF loopback */
1882         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1883             hw_stats->last_vfgotc, hw_stats->vfgotc);
1884
1885         /* Rx Multicst Packet */
1886         UPDATE_VF_STAT(IXGBE_VFMPRC,
1887             hw_stats->last_vfmprc, hw_stats->vfmprc);
1888
1889         if (stats == NULL)
1890                 return;
1891
1892         memset(stats, 0, sizeof(*stats));
1893         stats->ipackets = hw_stats->vfgprc;
1894         stats->ibytes = hw_stats->vfgorc;
1895         stats->opackets = hw_stats->vfgptc;
1896         stats->obytes = hw_stats->vfgotc;
1897         stats->imcasts = hw_stats->vfmprc;
1898 }
1899
1900 static void
1901 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1902 {
1903         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1904                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1905
1906         /* Sync HW register to the last stats */
1907         ixgbevf_dev_stats_get(dev, NULL);
1908
1909         /* reset HW current stats*/
1910         hw_stats->vfgprc = 0;
1911         hw_stats->vfgorc = 0;
1912         hw_stats->vfgptc = 0;
1913         hw_stats->vfgotc = 0;
1914         hw_stats->vfmprc = 0;
1915
1916 }
1917
1918 static void
1919 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1920 {
1921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922
1923         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1924         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1925         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1926         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1927         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1928         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1929         dev_info->max_vfs = dev->pci_dev->max_vfs;
1930         if (hw->mac.type == ixgbe_mac_82598EB)
1931                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1932         else
1933                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1934         dev_info->rx_offload_capa =
1935                 DEV_RX_OFFLOAD_VLAN_STRIP |
1936                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1937                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1938                 DEV_RX_OFFLOAD_TCP_CKSUM;
1939         dev_info->tx_offload_capa =
1940                 DEV_TX_OFFLOAD_VLAN_INSERT |
1941                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1942                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1943                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1944                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1945 }
1946
1947 /* return 0 means link status changed, -1 means not changed */
1948 static int
1949 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1950 {
1951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952         struct rte_eth_link link, old;
1953         ixgbe_link_speed link_speed;
1954         int link_up;
1955         int diag;
1956
1957         link.link_status = 0;
1958         link.link_speed = 0;
1959         link.link_duplex = 0;
1960         memset(&old, 0, sizeof(old));
1961         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1962
1963         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1964         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1965                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1966         else
1967                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1968         if (diag != 0) {
1969                 link.link_speed = ETH_LINK_SPEED_100;
1970                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1971                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1972                 if (link.link_status == old.link_status)
1973                         return -1;
1974                 return 0;
1975         }
1976
1977         if (link_up == 0) {
1978                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1979                 if (link.link_status == old.link_status)
1980                         return -1;
1981                 return 0;
1982         }
1983         link.link_status = 1;
1984         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1985
1986         switch (link_speed) {
1987         default:
1988         case IXGBE_LINK_SPEED_UNKNOWN:
1989                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1990                 link.link_speed = ETH_LINK_SPEED_100;
1991                 break;
1992
1993         case IXGBE_LINK_SPEED_100_FULL:
1994                 link.link_speed = ETH_LINK_SPEED_100;
1995                 break;
1996
1997         case IXGBE_LINK_SPEED_1GB_FULL:
1998                 link.link_speed = ETH_LINK_SPEED_1000;
1999                 break;
2000
2001         case IXGBE_LINK_SPEED_10GB_FULL:
2002                 link.link_speed = ETH_LINK_SPEED_10000;
2003                 break;
2004         }
2005         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2006
2007         if (link.link_status == old.link_status)
2008                 return -1;
2009
2010         return 0;
2011 }
2012
2013 static void
2014 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2015 {
2016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         uint32_t fctrl;
2018
2019         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2020         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2021         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2022 }
2023
2024 static void
2025 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2026 {
2027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         uint32_t fctrl;
2029
2030         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2031         fctrl &= (~IXGBE_FCTRL_UPE);
2032         if (dev->data->all_multicast == 1)
2033                 fctrl |= IXGBE_FCTRL_MPE;
2034         else
2035                 fctrl &= (~IXGBE_FCTRL_MPE);
2036         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2037 }
2038
2039 static void
2040 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2041 {
2042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2043         uint32_t fctrl;
2044
2045         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2046         fctrl |= IXGBE_FCTRL_MPE;
2047         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2048 }
2049
2050 static void
2051 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2052 {
2053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054         uint32_t fctrl;
2055
2056         if (dev->data->promiscuous == 1)
2057                 return; /* must remain in all_multicast mode */
2058
2059         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2060         fctrl &= (~IXGBE_FCTRL_MPE);
2061         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2062 }
2063
2064 /**
2065  * It clears the interrupt causes and enables the interrupt.
2066  * It will be called once only during nic initialized.
2067  *
2068  * @param dev
2069  *  Pointer to struct rte_eth_dev.
2070  *
2071  * @return
2072  *  - On success, zero.
2073  *  - On failure, a negative value.
2074  */
2075 static int
2076 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2077 {
2078         struct ixgbe_interrupt *intr =
2079                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2080
2081         ixgbe_dev_link_status_print(dev);
2082         intr->mask |= IXGBE_EICR_LSC;
2083
2084         return 0;
2085 }
2086
2087 /*
2088  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2089  *
2090  * @param dev
2091  *  Pointer to struct rte_eth_dev.
2092  *
2093  * @return
2094  *  - On success, zero.
2095  *  - On failure, a negative value.
2096  */
2097 static int
2098 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2099 {
2100         uint32_t eicr;
2101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102         struct ixgbe_interrupt *intr =
2103                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2104
2105         /* clear all cause mask */
2106         ixgbe_disable_intr(hw);
2107
2108         /* read-on-clear nic registers here */
2109         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2110         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2111
2112         intr->flags = 0;
2113         if (eicr & IXGBE_EICR_LSC) {
2114                 /* set flag for async link update */
2115                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2116         }
2117
2118         if (eicr & IXGBE_EICR_MAILBOX)
2119                 intr->flags |= IXGBE_FLAG_MAILBOX;
2120
2121         return 0;
2122 }
2123
2124 /**
2125  * It gets and then prints the link status.
2126  *
2127  * @param dev
2128  *  Pointer to struct rte_eth_dev.
2129  *
2130  * @return
2131  *  - On success, zero.
2132  *  - On failure, a negative value.
2133  */
2134 static void
2135 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2136 {
2137         struct rte_eth_link link;
2138
2139         memset(&link, 0, sizeof(link));
2140         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2141         if (link.link_status) {
2142                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2143                                         (int)(dev->data->port_id),
2144                                         (unsigned)link.link_speed,
2145                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2146                                         "full-duplex" : "half-duplex");
2147         } else {
2148                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2149                                 (int)(dev->data->port_id));
2150         }
2151         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2152                                 dev->pci_dev->addr.domain,
2153                                 dev->pci_dev->addr.bus,
2154                                 dev->pci_dev->addr.devid,
2155                                 dev->pci_dev->addr.function);
2156 }
2157
2158 /*
2159  * It executes link_update after knowing an interrupt occurred.
2160  *
2161  * @param dev
2162  *  Pointer to struct rte_eth_dev.
2163  *
2164  * @return
2165  *  - On success, zero.
2166  *  - On failure, a negative value.
2167  */
2168 static int
2169 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2170 {
2171         struct ixgbe_interrupt *intr =
2172                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2173         int64_t timeout;
2174         struct rte_eth_link link;
2175         int intr_enable_delay = false;
2176
2177         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2178
2179         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2180                 ixgbe_pf_mbx_process(dev);
2181                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2182         }
2183
2184         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2185                 /* get the link status before link update, for predicting later */
2186                 memset(&link, 0, sizeof(link));
2187                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2188
2189                 ixgbe_dev_link_update(dev, 0);
2190
2191                 /* likely to up */
2192                 if (!link.link_status)
2193                         /* handle it 1 sec later, wait it being stable */
2194                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2195                 /* likely to down */
2196                 else
2197                         /* handle it 4 sec later, wait it being stable */
2198                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2199
2200                 ixgbe_dev_link_status_print(dev);
2201
2202                 intr_enable_delay = true;
2203         }
2204
2205         if (intr_enable_delay) {
2206                 if (rte_eal_alarm_set(timeout * 1000,
2207                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2208                         PMD_DRV_LOG(ERR, "Error setting alarm");
2209         } else {
2210                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2211                 ixgbe_enable_intr(dev);
2212                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2213         }
2214
2215
2216         return 0;
2217 }
2218
2219 /**
2220  * Interrupt handler which shall be registered for alarm callback for delayed
2221  * handling specific interrupt to wait for the stable nic state. As the
2222  * NIC interrupt state is not stable for ixgbe after link is just down,
2223  * it needs to wait 4 seconds to get the stable status.
2224  *
2225  * @param handle
2226  *  Pointer to interrupt handle.
2227  * @param param
2228  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2229  *
2230  * @return
2231  *  void
2232  */
2233 static void
2234 ixgbe_dev_interrupt_delayed_handler(void *param)
2235 {
2236         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2237         struct ixgbe_interrupt *intr =
2238                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2239         struct ixgbe_hw *hw =
2240                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2241         uint32_t eicr;
2242
2243         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2244         if (eicr & IXGBE_EICR_MAILBOX)
2245                 ixgbe_pf_mbx_process(dev);
2246
2247         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2248                 ixgbe_dev_link_update(dev, 0);
2249                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2250                 ixgbe_dev_link_status_print(dev);
2251                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2252         }
2253
2254         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2255         ixgbe_enable_intr(dev);
2256         rte_intr_enable(&(dev->pci_dev->intr_handle));
2257 }
2258
2259 /**
2260  * Interrupt handler triggered by NIC  for handling
2261  * specific interrupt.
2262  *
2263  * @param handle
2264  *  Pointer to interrupt handle.
2265  * @param param
2266  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2267  *
2268  * @return
2269  *  void
2270  */
2271 static void
2272 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2273                                                         void *param)
2274 {
2275         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2276         ixgbe_dev_interrupt_get_status(dev);
2277         ixgbe_dev_interrupt_action(dev);
2278 }
2279
2280 static int
2281 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2282 {
2283         struct ixgbe_hw *hw;
2284
2285         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2286         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2287 }
2288
2289 static int
2290 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2291 {
2292         struct ixgbe_hw *hw;
2293
2294         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2295         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2296 }
2297
2298 static int
2299 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2300 {
2301         struct ixgbe_hw *hw;
2302         uint32_t mflcn_reg;
2303         uint32_t fccfg_reg;
2304         int rx_pause;
2305         int tx_pause;
2306
2307         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2308
2309         fc_conf->pause_time = hw->fc.pause_time;
2310         fc_conf->high_water = hw->fc.high_water[0];
2311         fc_conf->low_water = hw->fc.low_water[0];
2312         fc_conf->send_xon = hw->fc.send_xon;
2313         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2314
2315         /*
2316          * Return rx_pause status according to actual setting of
2317          * MFLCN register.
2318          */
2319         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2320         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2321                 rx_pause = 1;
2322         else
2323                 rx_pause = 0;
2324
2325         /*
2326          * Return tx_pause status according to actual setting of
2327          * FCCFG register.
2328          */
2329         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2330         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2331                 tx_pause = 1;
2332         else
2333                 tx_pause = 0;
2334
2335         if (rx_pause && tx_pause)
2336                 fc_conf->mode = RTE_FC_FULL;
2337         else if (rx_pause)
2338                 fc_conf->mode = RTE_FC_RX_PAUSE;
2339         else if (tx_pause)
2340                 fc_conf->mode = RTE_FC_TX_PAUSE;
2341         else
2342                 fc_conf->mode = RTE_FC_NONE;
2343
2344         return 0;
2345 }
2346
2347 static int
2348 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2349 {
2350         struct ixgbe_hw *hw;
2351         int err;
2352         uint32_t rx_buf_size;
2353         uint32_t max_high_water;
2354         uint32_t mflcn;
2355         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2356                 ixgbe_fc_none,
2357                 ixgbe_fc_rx_pause,
2358                 ixgbe_fc_tx_pause,
2359                 ixgbe_fc_full
2360         };
2361
2362         PMD_INIT_FUNC_TRACE();
2363
2364         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2365         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2366                 return -ENOTSUP;
2367         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2368         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2369
2370         /*
2371          * At least reserve one Ethernet frame for watermark
2372          * high_water/low_water in kilo bytes for ixgbe
2373          */
2374         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2375         if ((fc_conf->high_water > max_high_water) ||
2376                 (fc_conf->high_water < fc_conf->low_water)) {
2377                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2378                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2379                 return (-EINVAL);
2380         }
2381
2382         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2383         hw->fc.pause_time     = fc_conf->pause_time;
2384         hw->fc.high_water[0]  = fc_conf->high_water;
2385         hw->fc.low_water[0]   = fc_conf->low_water;
2386         hw->fc.send_xon       = fc_conf->send_xon;
2387
2388         err = ixgbe_fc_enable(hw);
2389
2390         /* Not negotiated is not an error case */
2391         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2392
2393                 /* check if we want to forward MAC frames - driver doesn't have native
2394                  * capability to do that, so we'll write the registers ourselves */
2395
2396                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2397
2398                 /* set or clear MFLCN.PMCF bit depending on configuration */
2399                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2400                         mflcn |= IXGBE_MFLCN_PMCF;
2401                 else
2402                         mflcn &= ~IXGBE_MFLCN_PMCF;
2403
2404                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2405                 IXGBE_WRITE_FLUSH(hw);
2406
2407                 return 0;
2408         }
2409
2410         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2411         return -EIO;
2412 }
2413
2414 /**
2415  *  ixgbe_pfc_enable_generic - Enable flow control
2416  *  @hw: pointer to hardware structure
2417  *  @tc_num: traffic class number
2418  *  Enable flow control according to the current settings.
2419  */
2420 static int
2421 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2422 {
2423         int ret_val = 0;
2424         uint32_t mflcn_reg, fccfg_reg;
2425         uint32_t reg;
2426         uint32_t fcrtl, fcrth;
2427         uint8_t i;
2428         uint8_t nb_rx_en;
2429
2430         /* Validate the water mark configuration */
2431         if (!hw->fc.pause_time) {
2432                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2433                 goto out;
2434         }
2435
2436         /* Low water mark of zero causes XOFF floods */
2437         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2438                  /* High/Low water can not be 0 */
2439                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2440                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2441                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2442                         goto out;
2443                 }
2444
2445                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2446                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2447                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2448                         goto out;
2449                 }
2450         }
2451         /* Negotiate the fc mode to use */
2452         ixgbe_fc_autoneg(hw);
2453
2454         /* Disable any previous flow control settings */
2455         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2456         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2457
2458         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2459         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2460
2461         switch (hw->fc.current_mode) {
2462         case ixgbe_fc_none:
2463                 /*
2464                  * If the count of enabled RX Priority Flow control >1,
2465                  * and the TX pause can not be disabled
2466                  */
2467                 nb_rx_en = 0;
2468                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2469                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2470                         if (reg & IXGBE_FCRTH_FCEN)
2471                                 nb_rx_en++;
2472                 }
2473                 if (nb_rx_en > 1)
2474                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2475                 break;
2476         case ixgbe_fc_rx_pause:
2477                 /*
2478                  * Rx Flow control is enabled and Tx Flow control is
2479                  * disabled by software override. Since there really
2480                  * isn't a way to advertise that we are capable of RX
2481                  * Pause ONLY, we will advertise that we support both
2482                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2483                  * disable the adapter's ability to send PAUSE frames.
2484                  */
2485                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2486                 /*
2487                  * If the count of enabled RX Priority Flow control >1,
2488                  * and the TX pause can not be disabled
2489                  */
2490                 nb_rx_en = 0;
2491                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2492                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2493                         if (reg & IXGBE_FCRTH_FCEN)
2494                                 nb_rx_en++;
2495                 }
2496                 if (nb_rx_en > 1)
2497                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2498                 break;
2499         case ixgbe_fc_tx_pause:
2500                 /*
2501                  * Tx Flow control is enabled, and Rx Flow control is
2502                  * disabled by software override.
2503                  */
2504                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2505                 break;
2506         case ixgbe_fc_full:
2507                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2508                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2509                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2510                 break;
2511         default:
2512                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2513                 ret_val = IXGBE_ERR_CONFIG;
2514                 goto out;
2515                 break;
2516         }
2517
2518         /* Set 802.3x based flow control settings. */
2519         mflcn_reg |= IXGBE_MFLCN_DPF;
2520         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2521         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2522
2523         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2524         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2525                 hw->fc.high_water[tc_num]) {
2526                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2527                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2528                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2529         } else {
2530                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2531                 /*
2532                  * In order to prevent Tx hangs when the internal Tx
2533                  * switch is enabled we must set the high water mark
2534                  * to the maximum FCRTH value.  This allows the Tx
2535                  * switch to function even under heavy Rx workloads.
2536                  */
2537                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2538         }
2539         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2540
2541         /* Configure pause time (2 TCs per register) */
2542         reg = hw->fc.pause_time * 0x00010001;
2543         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2544                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2545
2546         /* Configure flow control refresh threshold value */
2547         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2548
2549 out:
2550         return ret_val;
2551 }
2552
2553 static int
2554 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2555 {
2556         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2557         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2558
2559         if(hw->mac.type != ixgbe_mac_82598EB) {
2560                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2561         }
2562         return ret_val;
2563 }
2564
2565 static int
2566 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2567 {
2568         int err;
2569         uint32_t rx_buf_size;
2570         uint32_t max_high_water;
2571         uint8_t tc_num;
2572         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2573         struct ixgbe_hw *hw =
2574                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575         struct ixgbe_dcb_config *dcb_config =
2576                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2577
2578         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2579                 ixgbe_fc_none,
2580                 ixgbe_fc_rx_pause,
2581                 ixgbe_fc_tx_pause,
2582                 ixgbe_fc_full
2583         };
2584
2585         PMD_INIT_FUNC_TRACE();
2586
2587         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2588         tc_num = map[pfc_conf->priority];
2589         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2590         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2591         /*
2592          * At least reserve one Ethernet frame for watermark
2593          * high_water/low_water in kilo bytes for ixgbe
2594          */
2595         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2596         if ((pfc_conf->fc.high_water > max_high_water) ||
2597             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2598                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2599                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2600                 return (-EINVAL);
2601         }
2602
2603         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2604         hw->fc.pause_time = pfc_conf->fc.pause_time;
2605         hw->fc.send_xon = pfc_conf->fc.send_xon;
2606         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2607         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2608
2609         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2610
2611         /* Not negotiated is not an error case */
2612         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2613                 return 0;
2614
2615         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2616         return -EIO;
2617 }
2618
2619 static int
2620 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2621                                 struct rte_eth_rss_reta *reta_conf)
2622 {
2623         uint8_t i,j,mask;
2624         uint32_t reta;
2625         struct ixgbe_hw *hw =
2626                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627
2628         PMD_INIT_FUNC_TRACE();
2629         /*
2630         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2631         * 128-entries in 32 registers
2632          */
2633         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2634                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2635                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2636                 else
2637                         mask = (uint8_t)((reta_conf->mask_hi >>
2638                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2639                 if (mask != 0) {
2640                         reta = 0;
2641                         if (mask != 0xF)
2642                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2643
2644                         for (j = 0; j < 4; j++) {
2645                                 if (mask & (0x1 << j)) {
2646                                         if (mask != 0xF)
2647                                                 reta &= ~(0xFF << 8 * j);
2648                                         reta |= reta_conf->reta[i + j] << 8*j;
2649                                 }
2650                         }
2651                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2652                 }
2653         }
2654
2655         return 0;
2656 }
2657
2658 static int
2659 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2660                                 struct rte_eth_rss_reta *reta_conf)
2661 {
2662         uint8_t i,j,mask;
2663         uint32_t reta;
2664         struct ixgbe_hw *hw =
2665                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2666
2667         PMD_INIT_FUNC_TRACE();
2668         /*
2669          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2670          * 128-entries in 32 registers
2671          */
2672         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2673                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2674                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2675                 else
2676                         mask = (uint8_t)((reta_conf->mask_hi >>
2677                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2678
2679                 if (mask != 0) {
2680                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2681                         for (j = 0; j < 4; j++) {
2682                                 if (mask & (0x1 << j))
2683                                         reta_conf->reta[i + j] =
2684                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2685                         }
2686                 }
2687         }
2688
2689         return 0;
2690 }
2691
2692 static void
2693 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2694                                 uint32_t index, uint32_t pool)
2695 {
2696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697         uint32_t enable_addr = 1;
2698
2699         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2700 }
2701
2702 static void
2703 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2704 {
2705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2706
2707         ixgbe_clear_rar(hw, index);
2708 }
2709
2710 static int
2711 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2712 {
2713         uint32_t hlreg0;
2714         uint32_t maxfrs;
2715         struct ixgbe_hw *hw;
2716         struct rte_eth_dev_info dev_info;
2717         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2718
2719         ixgbe_dev_info_get(dev, &dev_info);
2720
2721         /* check that mtu is within the allowed range */
2722         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2723                 return -EINVAL;
2724
2725         /* refuse mtu that requires the support of scattered packets when this
2726          * feature has not been enabled before. */
2727         if (!dev->data->scattered_rx &&
2728             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2729              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2730                 return -EINVAL;
2731
2732         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2733         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2734
2735         /* switch to jumbo mode if needed */
2736         if (frame_size > ETHER_MAX_LEN) {
2737                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2738                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2739         } else {
2740                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2741                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2742         }
2743         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2744
2745         /* update max frame size */
2746         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2747
2748         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2749         maxfrs &= 0x0000FFFF;
2750         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2751         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2752
2753         return 0;
2754 }
2755
2756 /*
2757  * Virtual Function operations
2758  */
2759 static void
2760 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2761 {
2762         PMD_INIT_FUNC_TRACE();
2763
2764         /* Clear interrupt mask to stop from interrupts being generated */
2765         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2766
2767         IXGBE_WRITE_FLUSH(hw);
2768 }
2769
2770 static int
2771 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2772 {
2773         struct rte_eth_conf* conf = &dev->data->dev_conf;
2774
2775         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2776                      dev->data->port_id);
2777
2778         /*
2779          * VF has no ability to enable/disable HW CRC
2780          * Keep the persistent behavior the same as Host PF
2781          */
2782 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2783         if (!conf->rxmode.hw_strip_crc) {
2784                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2785                 conf->rxmode.hw_strip_crc = 1;
2786         }
2787 #else
2788         if (conf->rxmode.hw_strip_crc) {
2789                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2790                 conf->rxmode.hw_strip_crc = 0;
2791         }
2792 #endif
2793
2794         return 0;
2795 }
2796
2797 static int
2798 ixgbevf_dev_start(struct rte_eth_dev *dev)
2799 {
2800         struct ixgbe_hw *hw =
2801                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2802         int err, mask = 0;
2803
2804         PMD_INIT_FUNC_TRACE();
2805
2806         hw->mac.ops.reset_hw(hw);
2807
2808         /* negotiate mailbox API version to use with the PF. */
2809         ixgbevf_negotiate_api(hw);
2810
2811         ixgbevf_dev_tx_init(dev);
2812
2813         /* This can fail when allocating mbufs for descriptor rings */
2814         err = ixgbevf_dev_rx_init(dev);
2815         if (err) {
2816                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2817                 ixgbe_dev_clear_queues(dev);
2818                 return err;
2819         }
2820
2821         /* Set vfta */
2822         ixgbevf_set_vfta_all(dev,1);
2823
2824         /* Set HW strip */
2825         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2826                 ETH_VLAN_EXTEND_MASK;
2827         ixgbevf_vlan_offload_set(dev, mask);
2828
2829         ixgbevf_dev_rxtx_start(dev);
2830
2831         return 0;
2832 }
2833
2834 static void
2835 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2836 {
2837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838
2839         PMD_INIT_FUNC_TRACE();
2840
2841         hw->adapter_stopped = TRUE;
2842         ixgbe_stop_adapter(hw);
2843
2844         /*
2845           * Clear what we set, but we still keep shadow_vfta to
2846           * restore after device starts
2847           */
2848         ixgbevf_set_vfta_all(dev,0);
2849
2850         ixgbe_dev_clear_queues(dev);
2851 }
2852
2853 static void
2854 ixgbevf_dev_close(struct rte_eth_dev *dev)
2855 {
2856         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2857
2858         PMD_INIT_FUNC_TRACE();
2859
2860         ixgbe_reset_hw(hw);
2861
2862         ixgbevf_dev_stop(dev);
2863
2864         /* reprogram the RAR[0] in case user changed it. */
2865         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2866 }
2867
2868 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2869 {
2870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871         struct ixgbe_vfta * shadow_vfta =
2872                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2873         int i = 0, j = 0, vfta = 0, mask = 1;
2874
2875         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2876                 vfta = shadow_vfta->vfta[i];
2877                 if(vfta){
2878                         mask = 1;
2879                         for (j = 0; j < 32; j++){
2880                                 if(vfta & mask)
2881                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2882                                 mask<<=1;
2883                         }
2884                 }
2885         }
2886
2887 }
2888
2889 static int
2890 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2891 {
2892         struct ixgbe_hw *hw =
2893                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2894         struct ixgbe_vfta * shadow_vfta =
2895                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2896         uint32_t vid_idx = 0;
2897         uint32_t vid_bit = 0;
2898         int ret = 0;
2899
2900         PMD_INIT_FUNC_TRACE();
2901
2902         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2903         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2904         if(ret){
2905                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2906                 return ret;
2907         }
2908         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2909         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2910
2911         /* Save what we set and retore it after device reset */
2912         if (on)
2913                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2914         else
2915                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2916
2917         return 0;
2918 }
2919
2920 static void
2921 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2922 {
2923         struct ixgbe_hw *hw =
2924                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2925         uint32_t ctrl;
2926
2927         PMD_INIT_FUNC_TRACE();
2928
2929         if(queue >= hw->mac.max_rx_queues)
2930                 return;
2931
2932         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2933         if(on)
2934                 ctrl |= IXGBE_RXDCTL_VME;
2935         else
2936                 ctrl &= ~IXGBE_RXDCTL_VME;
2937         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2938
2939         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2940 }
2941
2942 static void
2943 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2944 {
2945         struct ixgbe_hw *hw =
2946                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947         uint16_t i;
2948         int on = 0;
2949
2950         /* VF function only support hw strip feature, others are not support */
2951         if(mask & ETH_VLAN_STRIP_MASK){
2952                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2953
2954                 for(i=0; i < hw->mac.max_rx_queues; i++)
2955                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2956         }
2957 }
2958
2959 static int
2960 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2961 {
2962         uint32_t reg_val;
2963
2964         /* we only need to do this if VMDq is enabled */
2965         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2966         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2967                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
2968                 return (-1);
2969         }
2970
2971         return 0;
2972 }
2973
2974 static uint32_t
2975 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2976 {
2977         uint32_t vector = 0;
2978         switch (hw->mac.mc_filter_type) {
2979         case 0:   /* use bits [47:36] of the address */
2980                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2981                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2982                 break;
2983         case 1:   /* use bits [46:35] of the address */
2984                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2985                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2986                 break;
2987         case 2:   /* use bits [45:34] of the address */
2988                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2989                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2990                 break;
2991         case 3:   /* use bits [43:32] of the address */
2992                 vector = ((uc_addr->addr_bytes[4]) |
2993                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2994                 break;
2995         default:  /* Invalid mc_filter_type */
2996                 break;
2997         }
2998
2999         /* vector can only be 12-bits or boundary will be exceeded */
3000         vector &= 0xFFF;
3001         return vector;
3002 }
3003
3004 static int
3005 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3006                                uint8_t on)
3007 {
3008         uint32_t vector;
3009         uint32_t uta_idx;
3010         uint32_t reg_val;
3011         uint32_t uta_shift;
3012         uint32_t rc;
3013         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3014         const uint32_t ixgbe_uta_bit_shift = 5;
3015         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3016         const uint32_t bit1 = 0x1;
3017
3018         struct ixgbe_hw *hw =
3019                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3020         struct ixgbe_uta_info *uta_info =
3021                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3022
3023         /* The UTA table only exists on 82599 hardware and newer */
3024         if (hw->mac.type < ixgbe_mac_82599EB)
3025                 return (-ENOTSUP);
3026
3027         vector = ixgbe_uta_vector(hw,mac_addr);
3028         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3029         uta_shift = vector & ixgbe_uta_bit_mask;
3030
3031         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3032         if(rc == on)
3033                 return 0;
3034
3035         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3036         if (on) {
3037                 uta_info->uta_in_use++;
3038                 reg_val |= (bit1 << uta_shift);
3039                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3040         } else {
3041                 uta_info->uta_in_use--;
3042                 reg_val &= ~(bit1 << uta_shift);
3043                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3044         }
3045
3046         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3047
3048         if (uta_info->uta_in_use > 0)
3049                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3050                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3051         else
3052                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3053
3054         return 0;
3055 }
3056
3057 static int
3058 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3059 {
3060         int i;
3061         struct ixgbe_hw *hw =
3062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3063         struct ixgbe_uta_info *uta_info =
3064                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3065
3066         /* The UTA table only exists on 82599 hardware and newer */
3067         if (hw->mac.type < ixgbe_mac_82599EB)
3068                 return (-ENOTSUP);
3069
3070         if(on) {
3071                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3072                         uta_info->uta_shadow[i] = ~0;
3073                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3074                 }
3075         } else {
3076                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3077                         uta_info->uta_shadow[i] = 0;
3078                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3079                 }
3080         }
3081         return 0;
3082
3083 }
3084 static int
3085 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3086                                uint16_t rx_mask, uint8_t on)
3087 {
3088         int val = 0;
3089
3090         struct ixgbe_hw *hw =
3091                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3092         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3093
3094         if (hw->mac.type == ixgbe_mac_82598EB) {
3095                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3096                              " on 82599 hardware and newer");
3097                 return (-ENOTSUP);
3098         }
3099         if (ixgbe_vmdq_mode_check(hw) < 0)
3100                 return (-ENOTSUP);
3101
3102         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
3103                 val |= IXGBE_VMOLR_AUPE;
3104         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
3105                 val |= IXGBE_VMOLR_ROMPE;
3106         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3107                 val |= IXGBE_VMOLR_ROPE;
3108         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3109                 val |= IXGBE_VMOLR_BAM;
3110         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3111                 val |= IXGBE_VMOLR_MPE;
3112
3113         if (on)
3114                 vmolr |= val;
3115         else
3116                 vmolr &= ~val;
3117
3118         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3119
3120         return 0;
3121 }
3122
3123 static int
3124 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3125 {
3126         uint32_t reg,addr;
3127         uint32_t val;
3128         const uint8_t bit1 = 0x1;
3129
3130         struct ixgbe_hw *hw =
3131                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132
3133         if (ixgbe_vmdq_mode_check(hw) < 0)
3134                 return (-ENOTSUP);
3135
3136         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3137         reg = IXGBE_READ_REG(hw, addr);
3138         val = bit1 << pool;
3139
3140         if (on)
3141                 reg |= val;
3142         else
3143                 reg &= ~val;
3144
3145         IXGBE_WRITE_REG(hw, addr,reg);
3146
3147         return 0;
3148 }
3149
3150 static int
3151 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3152 {
3153         uint32_t reg,addr;
3154         uint32_t val;
3155         const uint8_t bit1 = 0x1;
3156
3157         struct ixgbe_hw *hw =
3158                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159
3160         if (ixgbe_vmdq_mode_check(hw) < 0)
3161                 return (-ENOTSUP);
3162
3163         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3164         reg = IXGBE_READ_REG(hw, addr);
3165         val = bit1 << pool;
3166
3167         if (on)
3168                 reg |= val;
3169         else
3170                 reg &= ~val;
3171
3172         IXGBE_WRITE_REG(hw, addr,reg);
3173
3174         return 0;
3175 }
3176
3177 static int
3178 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3179                         uint64_t pool_mask, uint8_t vlan_on)
3180 {
3181         int ret = 0;
3182         uint16_t pool_idx;
3183         struct ixgbe_hw *hw =
3184                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3185
3186         if (ixgbe_vmdq_mode_check(hw) < 0)
3187                 return (-ENOTSUP);
3188         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3189                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3190                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3191                         if (ret < 0)
3192                                 return ret;
3193         }
3194
3195         return ret;
3196 }
3197
3198 static int
3199 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3200                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3201                         uint8_t rule_id, uint8_t on)
3202 {
3203         uint32_t mr_ctl,vlvf;
3204         uint32_t mp_lsb = 0;
3205         uint32_t mv_msb = 0;
3206         uint32_t mv_lsb = 0;
3207         uint32_t mp_msb = 0;
3208         uint8_t i = 0;
3209         int reg_index = 0;
3210         uint64_t vlan_mask = 0;
3211
3212         const uint8_t pool_mask_offset = 32;
3213         const uint8_t vlan_mask_offset = 32;
3214         const uint8_t dst_pool_offset = 8;
3215         const uint8_t rule_mr_offset  = 4;
3216         const uint8_t mirror_rule_mask= 0x0F;
3217
3218         struct ixgbe_mirror_info *mr_info =
3219                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3220         struct ixgbe_hw *hw =
3221                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3222
3223         if (ixgbe_vmdq_mode_check(hw) < 0)
3224                 return (-ENOTSUP);
3225
3226         /* Check if vlan mask is valid */
3227         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3228                 if (mirror_conf->vlan.vlan_mask == 0)
3229                         return (-EINVAL);
3230         }
3231
3232         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3233         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3234                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3235                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3236                                 /* search vlan id related pool vlan filter index */
3237                                 reg_index = ixgbe_find_vlvf_slot(hw,
3238                                                 mirror_conf->vlan.vlan_id[i]);
3239                                 if(reg_index < 0)
3240                                         return (-EINVAL);
3241                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3242                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3243                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3244                                                 == mirror_conf->vlan.vlan_id[i]))
3245                                         vlan_mask |= (1ULL << reg_index);
3246                                 else
3247                                         return (-EINVAL);
3248                         }
3249                 }
3250
3251                 if (on) {
3252                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3253                         mv_msb = vlan_mask >> vlan_mask_offset;
3254
3255                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3256                                                 mirror_conf->vlan.vlan_mask;
3257                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3258                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3259                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3260                                                 mirror_conf->vlan.vlan_id[i];
3261                         }
3262                 } else {
3263                         mv_lsb = 0;
3264                         mv_msb = 0;
3265                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3266                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3267                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3268                 }
3269         }
3270
3271         /*
3272          * if enable pool mirror, write related pool mask register,if disable
3273          * pool mirror, clear PFMRVM register
3274          */
3275         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3276                 if (on) {
3277                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3278                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3279                         mr_info->mr_conf[rule_id].pool_mask =
3280                                         mirror_conf->pool_mask;
3281
3282                 } else {
3283                         mp_lsb = 0;
3284                         mp_msb = 0;
3285                         mr_info->mr_conf[rule_id].pool_mask = 0;
3286                 }
3287         }
3288
3289         /* read  mirror control register and recalculate it */
3290         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3291
3292         if (on) {
3293                 mr_ctl |= mirror_conf->rule_type_mask;
3294                 mr_ctl &= mirror_rule_mask;
3295                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3296         } else
3297                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3298
3299         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3300         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3301
3302         /* write mirrror control  register */
3303         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3304
3305         /* write pool mirrror control  register */
3306         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3307                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3308                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3309                                 mp_msb);
3310         }
3311         /* write VLAN mirrror control  register */
3312         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3313                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3314                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3315                                 mv_msb);
3316         }
3317
3318         return 0;
3319 }
3320
3321 static int
3322 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3323 {
3324         int mr_ctl = 0;
3325         uint32_t lsb_val = 0;
3326         uint32_t msb_val = 0;
3327         const uint8_t rule_mr_offset = 4;
3328
3329         struct ixgbe_hw *hw =
3330                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3331         struct ixgbe_mirror_info *mr_info =
3332                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3333
3334         if (ixgbe_vmdq_mode_check(hw) < 0)
3335                 return (-ENOTSUP);
3336
3337         memset(&mr_info->mr_conf[rule_id], 0,
3338                 sizeof(struct rte_eth_vmdq_mirror_conf));
3339
3340         /* clear PFVMCTL register */
3341         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3342
3343         /* clear pool mask register */
3344         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3345         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3346
3347         /* clear vlan mask register */
3348         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3349         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3350
3351         return 0;
3352 }
3353
3354 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3355         uint16_t queue_idx, uint16_t tx_rate)
3356 {
3357         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358         uint32_t rf_dec, rf_int;
3359         uint32_t bcnrc_val;
3360         uint16_t link_speed = dev->data->dev_link.link_speed;
3361
3362         if (queue_idx >= hw->mac.max_tx_queues)
3363                 return -EINVAL;
3364
3365         if (tx_rate != 0) {
3366                 /* Calculate the rate factor values to set */
3367                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3368                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3369                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3370
3371                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3372                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3373                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3374                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3375         } else {
3376                 bcnrc_val = 0;
3377         }
3378
3379         /*
3380          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3381          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3382          * set as 0x4.
3383          */
3384         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3385                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3386                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3387                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3388                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3389         else
3390                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3391                         IXGBE_MMW_SIZE_DEFAULT);
3392
3393         /* Set RTTBCNRC of queue X */
3394         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3395         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3396         IXGBE_WRITE_FLUSH(hw);
3397
3398         return 0;
3399 }
3400
3401 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3402         uint16_t tx_rate, uint64_t q_msk)
3403 {
3404         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405         struct ixgbe_vf_info *vfinfo =
3406                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3407         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3408         uint32_t queue_stride =
3409                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3410         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3411         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3412         uint16_t total_rate = 0;
3413
3414         if (queue_end >= hw->mac.max_tx_queues)
3415                 return -EINVAL;
3416
3417         if (vfinfo != NULL) {
3418                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3419                         if (vf_idx == vf)
3420                                 continue;
3421                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3422                                 idx++)
3423                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3424                 }
3425         } else
3426                 return -EINVAL;
3427
3428         /* Store tx_rate for this vf. */
3429         for (idx = 0; idx < nb_q_per_pool; idx++) {
3430                 if (((uint64_t)0x1 << idx) & q_msk) {
3431                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3432                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3433                         total_rate += tx_rate;
3434                 }
3435         }
3436
3437         if (total_rate > dev->data->dev_link.link_speed) {
3438                 /*
3439                  * Reset stored TX rate of the VF if it causes exceed
3440                  * link speed.
3441                  */
3442                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3443                 return -EINVAL;
3444         }
3445
3446         /* Set RTTBCNRC of each queue/pool for vf X  */
3447         for (; queue_idx <= queue_end; queue_idx++) {
3448                 if (0x1 & q_msk)
3449                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3450                 q_msk = q_msk >> 1;
3451         }
3452
3453         return 0;
3454 }
3455
3456 static void
3457 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3458                      __attribute__((unused)) uint32_t index,
3459                      __attribute__((unused)) uint32_t pool)
3460 {
3461         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462         int diag;
3463
3464         /*
3465          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3466          * operation. Trap this case to avoid exhausting the [very limited]
3467          * set of PF resources used to store VF MAC addresses.
3468          */
3469         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3470                 return;
3471         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3472         if (diag == 0)
3473                 return;
3474         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3475 }
3476
3477 static void
3478 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3479 {
3480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3482         struct ether_addr *mac_addr;
3483         uint32_t i;
3484         int diag;
3485
3486         /*
3487          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3488          * not support the deletion of a given MAC address.
3489          * Instead, it imposes to delete all MAC addresses, then to add again
3490          * all MAC addresses with the exception of the one to be deleted.
3491          */
3492         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3493
3494         /*
3495          * Add again all MAC addresses, with the exception of the deleted one
3496          * and of the permanent MAC address.
3497          */
3498         for (i = 0, mac_addr = dev->data->mac_addrs;
3499              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3500                 /* Skip the deleted MAC address */
3501                 if (i == index)
3502                         continue;
3503                 /* Skip NULL MAC addresses */
3504                 if (is_zero_ether_addr(mac_addr))
3505                         continue;
3506                 /* Skip the permanent MAC address */
3507                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3508                         continue;
3509                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3510                 if (diag != 0)
3511                         PMD_DRV_LOG(ERR,
3512                                     "Adding again MAC address "
3513                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3514                                     "diag=%d",
3515                                     mac_addr->addr_bytes[0],
3516                                     mac_addr->addr_bytes[1],
3517                                     mac_addr->addr_bytes[2],
3518                                     mac_addr->addr_bytes[3],
3519                                     mac_addr->addr_bytes[4],
3520                                     mac_addr->addr_bytes[5],
3521                                     diag);
3522         }
3523 }
3524
3525 /*
3526  * add syn filter
3527  *
3528  * @param
3529  * dev: Pointer to struct rte_eth_dev.
3530  * filter: ponter to the filter that will be added.
3531  * rx_queue: the queue id the filter assigned to.
3532  *
3533  * @return
3534  *    - On success, zero.
3535  *    - On failure, a negative value.
3536  */
3537 static int
3538 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3539                         struct rte_syn_filter *filter, uint16_t rx_queue)
3540 {
3541         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542         uint32_t synqf;
3543
3544         if (hw->mac.type != ixgbe_mac_82599EB)
3545                 return -ENOSYS;
3546
3547         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3548                 return -EINVAL;
3549
3550         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3551
3552         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3553                 return -EINVAL;
3554
3555         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3556                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3557
3558         if (filter->hig_pri)
3559                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3560         else
3561                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3562
3563         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3564         return 0;
3565 }
3566
3567 /*
3568  * remove syn filter
3569  *
3570  * @param
3571  * dev: Pointer to struct rte_eth_dev.
3572  *
3573  * @return
3574  *    - On success, zero.
3575  *    - On failure, a negative value.
3576  */
3577 static int
3578 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3579 {
3580         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3581         uint32_t synqf;
3582
3583         if (hw->mac.type != ixgbe_mac_82599EB)
3584                 return -ENOSYS;
3585
3586         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3587
3588         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3589
3590         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3591         return 0;
3592 }
3593
3594 /*
3595  * get the syn filter's info
3596  *
3597  * @param
3598  * dev: Pointer to struct rte_eth_dev.
3599  * filter: ponter to the filter that returns.
3600  * *rx_queue: pointer to the queue id the filter assigned to.
3601  *
3602  * @return
3603  *    - On success, zero.
3604  *    - On failure, a negative value.
3605  */
3606 static int
3607 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3608                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3609
3610 {
3611         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612         uint32_t synqf;
3613
3614         if (hw->mac.type != ixgbe_mac_82599EB)
3615                 return -ENOSYS;
3616
3617         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3618         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3619                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3620                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3621                 return 0;
3622         }
3623         return -ENOENT;
3624 }
3625
3626 /*
3627  * add an ethertype filter
3628  *
3629  * @param
3630  * dev: Pointer to struct rte_eth_dev.
3631  * index: the index the filter allocates.
3632  * filter: ponter to the filter that will be added.
3633  * rx_queue: the queue id the filter assigned to.
3634  *
3635  * @return
3636  *    - On success, zero.
3637  *    - On failure, a negative value.
3638  */
3639 static int
3640 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3641                         uint16_t index, struct rte_ethertype_filter *filter,
3642                         uint16_t rx_queue)
3643 {
3644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645         uint32_t etqf, etqs = 0;
3646
3647         if (hw->mac.type != ixgbe_mac_82599EB)
3648                 return -ENOSYS;
3649
3650         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3651                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3652                 return -EINVAL;
3653
3654         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3655         if (etqf & IXGBE_ETQF_FILTER_EN)
3656                 return -EINVAL;  /* filter index is in use. */
3657
3658         etqf = 0;
3659         etqf |= IXGBE_ETQF_FILTER_EN;
3660         etqf |= (uint32_t)filter->ethertype;
3661
3662         if (filter->priority_en) {
3663                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3664                         return -EINVAL;
3665                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3666                 etqf |= IXGBE_ETQF_UP_EN;
3667         }
3668         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3669         etqs |= IXGBE_ETQS_QUEUE_EN;
3670
3671         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3672         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3673         return 0;
3674 }
3675
3676 /*
3677  * remove an ethertype filter
3678  *
3679  * @param
3680  * dev: Pointer to struct rte_eth_dev.
3681  * index: the index the filter allocates.
3682  *
3683  * @return
3684  *    - On success, zero.
3685  *    - On failure, a negative value.
3686  */
3687 static int
3688 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3689                         uint16_t index)
3690 {
3691         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3692
3693         if (hw->mac.type != ixgbe_mac_82599EB)
3694                 return -ENOSYS;
3695
3696         if (index >= IXGBE_MAX_ETQF_FILTERS)
3697                 return -EINVAL;
3698
3699         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3700         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3701
3702         return 0;
3703 }
3704
3705 /*
3706  * get an ethertype filter
3707  *
3708  * @param
3709  * dev: Pointer to struct rte_eth_dev.
3710  * index: the index the filter allocates.
3711  * filter: ponter to the filter that will be gotten.
3712  * *rx_queue: the ponited of the queue id the filter assigned to.
3713  *
3714  * @return
3715  *    - On success, zero.
3716  *    - On failure, a negative value.
3717  */
3718 static int
3719 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3720                         uint16_t index, struct rte_ethertype_filter *filter,
3721                         uint16_t *rx_queue)
3722 {
3723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3724         uint32_t etqf, etqs;
3725
3726         if (hw->mac.type != ixgbe_mac_82599EB)
3727                 return -ENOSYS;
3728
3729         if (index >= IXGBE_MAX_ETQF_FILTERS)
3730                 return -EINVAL;
3731
3732         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3733         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3734         if (etqf & IXGBE_ETQF_FILTER_EN) {
3735                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3736                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3737                 if (filter->priority_en)
3738                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3739                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3740                 return 0;
3741         }
3742         return -ENOENT;
3743 }
3744
3745 static inline enum ixgbe_5tuple_protocol
3746 convert_protocol_type(uint8_t protocol_value)
3747 {
3748         if (protocol_value == IPPROTO_TCP)
3749                 return IXGBE_FILTER_PROTOCOL_TCP;
3750         else if (protocol_value == IPPROTO_UDP)
3751                 return IXGBE_FILTER_PROTOCOL_UDP;
3752         else if (protocol_value == IPPROTO_SCTP)
3753                 return IXGBE_FILTER_PROTOCOL_SCTP;
3754         else
3755                 return IXGBE_FILTER_PROTOCOL_NONE;
3756 }
3757
3758 static inline uint8_t
3759 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3760 {
3761         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3762                 return IPPROTO_TCP;
3763         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3764                 return IPPROTO_UDP;
3765         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3766                 return IPPROTO_SCTP;
3767         else
3768                 return 0;
3769 }
3770
3771 /*
3772  * add a 5tuple filter
3773  *
3774  * @param
3775  * dev: Pointer to struct rte_eth_dev.
3776  * index: the index the filter allocates.
3777  * filter: ponter to the filter that will be added.
3778  * rx_queue: the queue id the filter assigned to.
3779  *
3780  * @return
3781  *    - On success, zero.
3782  *    - On failure, a negative value.
3783  */
3784 static int
3785 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3786                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3787 {
3788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3789         uint32_t ftqf, sdpqf = 0;
3790         uint32_t l34timir = 0;
3791         uint8_t mask = 0xff;
3792
3793         if (hw->mac.type != ixgbe_mac_82599EB)
3794                 return -ENOSYS;
3795
3796         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3797                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3798                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3799                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3800                 return -EINVAL;  /* filter index is out of range. */
3801
3802         if (filter->tcp_flags) {
3803                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3804                 return -EINVAL;
3805         }
3806
3807         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3808         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3809                 return -EINVAL;  /* filter index is in use. */
3810
3811         ftqf = 0;
3812         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3813         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3814
3815         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3816                 IXGBE_FTQF_PROTOCOL_MASK);
3817         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3818                 IXGBE_FTQF_PRIORITY_SHIFT);
3819         if (filter->src_ip_mask == 0) /* 0 means compare. */
3820                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3821         if (filter->dst_ip_mask == 0)
3822                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3823         if (filter->src_port_mask == 0)
3824                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3825         if (filter->dst_port_mask == 0)
3826                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3827         if (filter->protocol_mask == 0)
3828                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3829         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3830         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3831         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3832
3833         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3834         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3835         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3836         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3837
3838         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3839         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3840         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3841         return 0;
3842 }
3843
3844 /*
3845  * remove a 5tuple filter
3846  *
3847  * @param
3848  * dev: Pointer to struct rte_eth_dev.
3849  * index: the index the filter allocates.
3850  *
3851  * @return
3852  *    - On success, zero.
3853  *    - On failure, a negative value.
3854  */
3855 static int
3856 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3857                         uint16_t index)
3858 {
3859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3860
3861         if (hw->mac.type != ixgbe_mac_82599EB)
3862                 return -ENOSYS;
3863
3864         if (index >= IXGBE_MAX_FTQF_FILTERS)
3865                 return -EINVAL;  /* filter index is out of range. */
3866
3867         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3868         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3869         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3870         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3871         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3872         return 0;
3873 }
3874
3875 /*
3876  * get a 5tuple filter
3877  *
3878  * @param
3879  * dev: Pointer to struct rte_eth_dev.
3880  * index: the index the filter allocates
3881  * filter: ponter to the filter that returns.
3882  * *rx_queue: pointer of the queue id the filter assigned to.
3883  *
3884  * @return
3885  *    - On success, zero.
3886  *    - On failure, a negative value.
3887  */
3888 static int
3889 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3890                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3891 {
3892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3893         uint32_t sdpqf, ftqf, l34timir;
3894         uint8_t mask;
3895         enum ixgbe_5tuple_protocol proto;
3896
3897         if (hw->mac.type != ixgbe_mac_82599EB)
3898                 return -ENOSYS;
3899
3900         if (index >= IXGBE_MAX_FTQF_FILTERS)
3901                 return -EINVAL;  /* filter index is out of range. */
3902
3903         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3904         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3905                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3906                 filter->protocol = revert_protocol_type(proto);
3907                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3908                                         IXGBE_FTQF_PRIORITY_MASK;
3909                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3910                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3911                 filter->src_ip_mask =
3912                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3913                 filter->dst_ip_mask =
3914                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3915                 filter->src_port_mask =
3916                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3917                 filter->dst_port_mask =
3918                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3919                 filter->protocol_mask =
3920                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3921
3922                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3923                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3924                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3925                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3926                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3927                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3928
3929                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3930                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3931                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3932                 return 0;
3933         }
3934         return -ENOENT;
3935 }
3936
3937 static int
3938 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3939 {
3940         struct ixgbe_hw *hw;
3941         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3942
3943         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944
3945         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3946                 return -EINVAL;
3947
3948         /* refuse mtu that requires the support of scattered packets when this
3949          * feature has not been enabled before. */
3950         if (!dev->data->scattered_rx &&
3951             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3952              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3953                 return -EINVAL;
3954
3955         /*
3956          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3957          * request of the version 2.0 of the mailbox API.
3958          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3959          * of the mailbox API.
3960          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3961          * prior to 3.11.33 which contains the following change:
3962          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3963          */
3964         ixgbevf_rlpml_set_vf(hw, max_frame);
3965
3966         /* update max frame size */
3967         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3968         return 0;
3969 }
3970
3971 static struct rte_driver rte_ixgbe_driver = {
3972         .type = PMD_PDEV,
3973         .init = rte_ixgbe_pmd_init,
3974 };
3975
3976 static struct rte_driver rte_ixgbevf_driver = {
3977         .type = PMD_PDEV,
3978         .init = rte_ixgbevf_pmd_init,
3979 };
3980
3981 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3982 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);