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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_tailq.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
63 #include "ixgbe_logs.h"
64 #include "ixgbe/ixgbe_api.h"
65 #include "ixgbe/ixgbe_vf.h"
66 #include "ixgbe/ixgbe_common.h"
67 #include "ixgbe_ethdev.h"
68 #include "ixgbe_bypass.h"
71 * High threshold controlling when to start sending XOFF frames. Must be at
72 * least 8 bytes less than receive packet buffer size. This value is in units
75 #define IXGBE_FC_HI 0x80
78 * Low threshold controlling when to start sending XON frames. This value is
79 * in units of 1024 bytes.
81 #define IXGBE_FC_LO 0x40
83 /* Timer value included in XOFF frames. */
84 #define IXGBE_FC_PAUSE 0x680
86 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
87 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
88 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
91 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
93 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
95 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
96 struct rte_eth_dev *eth_dev);
97 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
98 static int ixgbe_dev_start(struct rte_eth_dev *dev);
99 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
100 static void ixgbe_dev_close(struct rte_eth_dev *dev);
101 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
102 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
103 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
104 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
105 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
106 int wait_to_complete);
107 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
108 struct rte_eth_stats *stats);
109 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
110 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
114 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
115 struct rte_eth_dev_info *dev_info);
116 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
117 uint16_t vlan_id, int on);
118 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
119 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
120 uint16_t queue, bool on);
121 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
123 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
124 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
125 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
126 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
127 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
129 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
130 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
131 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
132 struct rte_eth_fc_conf *fc_conf);
133 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
134 struct rte_eth_pfc_conf *pfc_conf);
135 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
136 struct rte_eth_rss_reta *reta_conf);
137 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
138 struct rte_eth_rss_reta *reta_conf);
139 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
140 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
141 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
142 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
143 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
145 static void ixgbe_dev_interrupt_delayed_handler(void *param);
146 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
147 uint32_t index, uint32_t pool);
148 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
149 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
151 /* For Virtual Function support */
152 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
153 struct rte_eth_dev *eth_dev);
154 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
155 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
156 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
157 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
158 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
159 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
160 struct rte_eth_stats *stats);
161 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
162 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
163 uint16_t vlan_id, int on);
164 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
165 uint16_t queue, int on);
166 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
167 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
169 /* For Eth VMDQ APIs support */
170 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
171 ether_addr* mac_addr,uint8_t on);
172 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
173 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
174 uint16_t rx_mask, uint8_t on);
175 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
176 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
177 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
178 uint64_t pool_mask,uint8_t vlan_on);
179 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
180 struct rte_eth_vmdq_mirror_conf *mirror_conf,
181 uint8_t rule_id, uint8_t on);
182 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
186 * Define VF Stats MACRO for Non "cleared on read" register
188 #define UPDATE_VF_STAT(reg, last, cur) \
190 u32 latest = IXGBE_READ_REG(hw, reg); \
191 cur += latest - last; \
195 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
197 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
198 u64 new_msb = IXGBE_READ_REG(hw, msb); \
199 u64 latest = ((new_msb << 32) | new_lsb); \
200 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
204 #define IXGBE_SET_HWSTRIP(h, q) do{\
205 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
206 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
207 (h)->bitmap[idx] |= 1 << bit;\
210 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
211 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
212 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
213 (h)->bitmap[idx] &= ~(1 << bit);\
216 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
217 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
218 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
219 (r) = (h)->bitmap[idx] >> bit & 1;\
223 * The set of PCI devices this driver supports
225 static struct rte_pci_id pci_id_ixgbe_map[] = {
227 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
228 #include "rte_pci_dev_ids.h"
230 { .vendor_id = 0, /* sentinel */ },
235 * The set of PCI devices this driver supports (for 82599 VF)
237 static struct rte_pci_id pci_id_ixgbevf_map[] = {
239 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
240 #include "rte_pci_dev_ids.h"
241 { .vendor_id = 0, /* sentinel */ },
245 static struct eth_dev_ops ixgbe_eth_dev_ops = {
246 .dev_configure = ixgbe_dev_configure,
247 .dev_start = ixgbe_dev_start,
248 .dev_stop = ixgbe_dev_stop,
249 .dev_close = ixgbe_dev_close,
250 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
251 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
252 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
253 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
254 .link_update = ixgbe_dev_link_update,
255 .stats_get = ixgbe_dev_stats_get,
256 .stats_reset = ixgbe_dev_stats_reset,
257 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
258 .dev_infos_get = ixgbe_dev_info_get,
259 .vlan_filter_set = ixgbe_vlan_filter_set,
260 .vlan_tpid_set = ixgbe_vlan_tpid_set,
261 .vlan_offload_set = ixgbe_vlan_offload_set,
262 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
263 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
264 .rx_queue_release = ixgbe_dev_rx_queue_release,
265 .rx_queue_count = ixgbe_dev_rx_queue_count,
266 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
267 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
268 .tx_queue_release = ixgbe_dev_tx_queue_release,
269 .dev_led_on = ixgbe_dev_led_on,
270 .dev_led_off = ixgbe_dev_led_off,
271 .flow_ctrl_set = ixgbe_flow_ctrl_set,
272 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
273 .mac_addr_add = ixgbe_add_rar,
274 .mac_addr_remove = ixgbe_remove_rar,
275 .uc_hash_table_set = ixgbe_uc_hash_table_set,
276 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
277 .mirror_rule_set = ixgbe_mirror_rule_set,
278 .mirror_rule_reset = ixgbe_mirror_rule_reset,
279 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
280 .set_vf_rx = ixgbe_set_pool_rx,
281 .set_vf_tx = ixgbe_set_pool_tx,
282 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
283 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
284 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
285 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
286 .fdir_infos_get = ixgbe_fdir_info_get,
287 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
288 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
289 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
290 .fdir_set_masks = ixgbe_fdir_set_masks,
291 .reta_update = ixgbe_dev_rss_reta_update,
292 .reta_query = ixgbe_dev_rss_reta_query,
293 #ifdef RTE_NIC_BYPASS
294 .bypass_init = ixgbe_bypass_init,
295 .bypass_state_set = ixgbe_bypass_state_store,
296 .bypass_state_show = ixgbe_bypass_state_show,
297 .bypass_event_set = ixgbe_bypass_event_store,
298 .bypass_event_show = ixgbe_bypass_event_show,
299 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
300 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
301 .bypass_ver_show = ixgbe_bypass_ver_show,
302 .bypass_wd_reset = ixgbe_bypass_wd_reset,
303 #endif /* RTE_NIC_BYPASS */
307 * dev_ops for virtual function, bare necessities for basic vf
308 * operation have been implemented
310 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
312 .dev_configure = ixgbevf_dev_configure,
313 .dev_start = ixgbevf_dev_start,
314 .dev_stop = ixgbevf_dev_stop,
315 .link_update = ixgbe_dev_link_update,
316 .stats_get = ixgbevf_dev_stats_get,
317 .stats_reset = ixgbevf_dev_stats_reset,
318 .dev_close = ixgbevf_dev_close,
319 .dev_infos_get = ixgbe_dev_info_get,
320 .vlan_filter_set = ixgbevf_vlan_filter_set,
321 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
322 .vlan_offload_set = ixgbevf_vlan_offload_set,
323 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
324 .rx_queue_release = ixgbe_dev_rx_queue_release,
325 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
326 .tx_queue_release = ixgbe_dev_tx_queue_release,
330 * Atomically reads the link status information from global
331 * structure rte_eth_dev.
334 * - Pointer to the structure rte_eth_dev to read from.
335 * - Pointer to the buffer to be saved with the link status.
338 * - On success, zero.
339 * - On failure, negative value.
342 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
343 struct rte_eth_link *link)
345 struct rte_eth_link *dst = link;
346 struct rte_eth_link *src = &(dev->data->dev_link);
348 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
349 *(uint64_t *)src) == 0)
356 * Atomically writes the link status information into global
357 * structure rte_eth_dev.
360 * - Pointer to the structure rte_eth_dev to read from.
361 * - Pointer to the buffer to be saved with the link status.
364 * - On success, zero.
365 * - On failure, negative value.
368 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
369 struct rte_eth_link *link)
371 struct rte_eth_link *dst = &(dev->data->dev_link);
372 struct rte_eth_link *src = link;
374 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
375 *(uint64_t *)src) == 0)
382 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
385 ixgbe_is_sfp(struct ixgbe_hw *hw)
387 switch (hw->phy.type) {
388 case ixgbe_phy_sfp_avago:
389 case ixgbe_phy_sfp_ftl:
390 case ixgbe_phy_sfp_intel:
391 case ixgbe_phy_sfp_unknown:
392 case ixgbe_phy_sfp_passive_tyco:
393 case ixgbe_phy_sfp_passive_unknown:
400 static inline int32_t
401 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
406 status = ixgbe_reset_hw(hw);
408 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
409 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
410 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
411 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
412 IXGBE_WRITE_FLUSH(hw);
418 ixgbe_enable_intr(struct rte_eth_dev *dev)
420 struct ixgbe_interrupt *intr =
421 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
422 struct ixgbe_hw *hw =
423 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
425 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
426 IXGBE_WRITE_FLUSH(hw);
430 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
433 ixgbe_disable_intr(struct ixgbe_hw *hw)
435 PMD_INIT_FUNC_TRACE();
437 if (hw->mac.type == ixgbe_mac_82598EB) {
438 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
440 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
441 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
442 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
444 IXGBE_WRITE_FLUSH(hw);
448 * This function resets queue statistics mapping registers.
449 * From Niantic datasheet, Initialization of Statistics section:
450 * "...if software requires the queue counters, the RQSMR and TQSM registers
451 * must be re-programmed following a device reset.
454 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
458 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
459 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
460 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
466 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
471 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
472 #define NB_QMAP_FIELDS_PER_QSM_REG 4
473 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
475 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
476 struct ixgbe_stat_mapping_registers *stat_mappings =
477 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
478 uint32_t qsmr_mask = 0;
479 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
483 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
486 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
487 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
489 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
490 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
491 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
494 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
496 /* Now clear any previous stat_idx set */
497 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
499 stat_mappings->tqsm[n] &= ~clearing_mask;
501 stat_mappings->rqsmr[n] &= ~clearing_mask;
503 q_map = (uint32_t)stat_idx;
504 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
505 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
507 stat_mappings->tqsm[n] |= qsmr_mask;
509 stat_mappings->rqsmr[n] |= qsmr_mask;
511 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
513 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
514 is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
516 /* Now write the mapping in the appropriate register */
518 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
519 stat_mappings->rqsmr[n], n);
520 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
523 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
524 stat_mappings->tqsm[n], n);
525 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
531 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
533 struct ixgbe_stat_mapping_registers *stat_mappings =
534 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
535 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
538 /* write whatever was in stat mapping table to the NIC */
539 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
541 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
544 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
549 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
552 struct ixgbe_dcb_tc_config *tc;
553 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
555 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
556 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
557 for (i = 0; i < dcb_max_tc; i++) {
558 tc = &dcb_config->tc_config[i];
559 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
560 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
561 (uint8_t)(100/dcb_max_tc + (i & 1));
562 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
563 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
564 (uint8_t)(100/dcb_max_tc + (i & 1));
565 tc->pfc = ixgbe_dcb_pfc_disabled;
568 /* Initialize default user to priority mapping, UPx->TC0 */
569 tc = &dcb_config->tc_config[0];
570 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
571 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
572 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
573 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
574 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
576 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
577 dcb_config->pfc_mode_enable = false;
578 dcb_config->vt_mode = true;
579 dcb_config->round_robin_enable = false;
580 /* support all DCB capabilities in 82599 */
581 dcb_config->support.capabilities = 0xFF;
583 /*we only support 4 Tcs for X540*/
584 if (hw->mac.type == ixgbe_mac_X540) {
585 dcb_config->num_tcs.pg_tcs = 4;
586 dcb_config->num_tcs.pfc_tcs = 4;
591 * Ensure that all locks are released before first NVM or PHY access
594 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
599 * Phy lock should not fail in this early stage. If this is the case,
600 * it is due to an improper exit of the application.
601 * So force the release of the faulty lock. Release of common lock
602 * is done automatically by swfw_sync function.
604 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
605 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
606 DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
608 ixgbe_release_swfw_semaphore(hw, mask);
611 * These ones are more tricky since they are common to all ports; but
612 * swfw_sync retries last long enough (1s) to be almost sure that if
613 * lock can not be taken it is due to an improper lock of the
616 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
617 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
618 DEBUGOUT("SWFW common locks released");
620 ixgbe_release_swfw_semaphore(hw, mask);
624 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
625 * It returns 0 on success.
628 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
629 struct rte_eth_dev *eth_dev)
631 struct rte_pci_device *pci_dev;
632 struct ixgbe_hw *hw =
633 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
634 struct ixgbe_vfta * shadow_vfta =
635 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
636 struct ixgbe_hwstrip *hwstrip =
637 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
638 struct ixgbe_dcb_config *dcb_config =
639 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
644 PMD_INIT_FUNC_TRACE();
646 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
647 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
648 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
650 /* for secondary processes, we don't initialise any further as primary
651 * has already done this work. Only check we don't need a different
653 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
654 if (eth_dev->data->scattered_rx)
655 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
658 pci_dev = eth_dev->pci_dev;
660 /* Vendor and Device ID need to be set before init of shared code */
661 hw->device_id = pci_dev->id.device_id;
662 hw->vendor_id = pci_dev->id.vendor_id;
663 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
664 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
665 hw->allow_unsupported_sfp = 1;
668 /* Initialize the shared code */
669 #ifdef RTE_NIC_BYPASS
670 diag = ixgbe_bypass_init_shared_code(hw);
672 diag = ixgbe_init_shared_code(hw);
673 #endif /* RTE_NIC_BYPASS */
675 if (diag != IXGBE_SUCCESS) {
676 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
680 /* pick up the PCI bus settings for reporting later */
681 ixgbe_get_bus_info(hw);
683 /* Unlock any pending hardware semaphore */
684 ixgbe_swfw_lock_reset(hw);
686 /* Initialize DCB configuration*/
687 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
688 ixgbe_dcb_init(hw,dcb_config);
689 /* Get Hardware Flow Control setting */
690 hw->fc.requested_mode = ixgbe_fc_full;
691 hw->fc.current_mode = ixgbe_fc_full;
692 hw->fc.pause_time = IXGBE_FC_PAUSE;
693 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
694 hw->fc.low_water[i] = IXGBE_FC_LO;
695 hw->fc.high_water[i] = IXGBE_FC_HI;
699 /* Make sure we have a good EEPROM before we read from it */
700 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
701 if (diag != IXGBE_SUCCESS) {
702 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
706 #ifdef RTE_NIC_BYPASS
707 diag = ixgbe_bypass_init_hw(hw);
709 diag = ixgbe_init_hw(hw);
710 #endif /* RTE_NIC_BYPASS */
713 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
714 * is called too soon after the kernel driver unbinding/binding occurs.
715 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
716 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
717 * also called. See ixgbe_identify_phy_82599(). The reason for the
718 * failure is not known, and only occuts when virtualisation features
719 * are disabled in the bios. A delay of 100ms was found to be enough by
720 * trial-and-error, and is doubled to be safe.
722 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
724 diag = ixgbe_init_hw(hw);
727 if (diag == IXGBE_ERR_EEPROM_VERSION) {
728 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
729 "LOM. Please be aware there may be issues associated "
730 "with your hardware.\n If you are experiencing problems "
731 "please contact your Intel or hardware representative "
732 "who provided you with this hardware.\n");
733 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
734 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
736 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
740 /* disable interrupt */
741 ixgbe_disable_intr(hw);
743 /* reset mappings for queue statistics hw counters*/
744 ixgbe_reset_qstat_mappings(hw);
746 /* Allocate memory for storing MAC addresses */
747 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
748 hw->mac.num_rar_entries, 0);
749 if (eth_dev->data->mac_addrs == NULL) {
751 "Failed to allocate %u bytes needed to store "
753 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
756 /* Copy the permanent MAC address */
757 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
758 ð_dev->data->mac_addrs[0]);
760 /* Allocate memory for storing hash filter MAC addresses */
761 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
762 IXGBE_VMDQ_NUM_UC_MAC, 0);
763 if (eth_dev->data->hash_mac_addrs == NULL) {
765 "Failed to allocate %d bytes needed to store MAC addresses",
766 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
770 /* initialize the vfta */
771 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
773 /* initialize the hw strip bitmap*/
774 memset(hwstrip, 0, sizeof(*hwstrip));
776 /* initialize PF if max_vfs not zero */
777 ixgbe_pf_host_init(eth_dev);
779 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
780 /* let hardware know driver is loaded */
781 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
782 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
783 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
784 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
785 IXGBE_WRITE_FLUSH(hw);
787 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
789 "MAC: %d, PHY: %d, SFP+: %d<n",
790 (int) hw->mac.type, (int) hw->phy.type,
791 (int) hw->phy.sfp_type);
793 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
794 (int) hw->mac.type, (int) hw->phy.type);
796 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
797 eth_dev->data->port_id, pci_dev->id.vendor_id,
798 pci_dev->id.device_id);
800 rte_intr_callback_register(&(pci_dev->intr_handle),
801 ixgbe_dev_interrupt_handler, (void *)eth_dev);
803 /* enable uio intr after callback register */
804 rte_intr_enable(&(pci_dev->intr_handle));
806 /* enable support intr */
807 ixgbe_enable_intr(eth_dev);
814 * Negotiate mailbox API version with the PF.
815 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
816 * Then we try to negotiate starting with the most recent one.
817 * If all negotiation attempts fail, then we will proceed with
818 * the default one (ixgbe_mbox_api_10).
821 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
825 /* start with highest supported, proceed down */
826 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
832 i != RTE_DIM(sup_ver) &&
833 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
839 * Virtual Function device init
842 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
843 struct rte_eth_dev *eth_dev)
847 struct rte_pci_device *pci_dev;
848 struct ixgbe_hw *hw =
849 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
850 struct ixgbe_vfta * shadow_vfta =
851 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
852 struct ixgbe_hwstrip *hwstrip =
853 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
855 PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
857 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
858 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
859 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
861 /* for secondary processes, we don't initialise any further as primary
862 * has already done this work. Only check we don't need a different
864 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
865 if (eth_dev->data->scattered_rx)
866 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
870 pci_dev = eth_dev->pci_dev;
872 hw->device_id = pci_dev->id.device_id;
873 hw->vendor_id = pci_dev->id.vendor_id;
874 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
876 /* initialize the vfta */
877 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
879 /* initialize the hw strip bitmap*/
880 memset(hwstrip, 0, sizeof(*hwstrip));
882 /* Initialize the shared code */
883 diag = ixgbe_init_shared_code(hw);
884 if (diag != IXGBE_SUCCESS) {
885 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
889 /* init_mailbox_params */
890 hw->mbx.ops.init_params(hw);
892 /* Disable the interrupts for VF */
893 ixgbevf_intr_disable(hw);
895 hw->mac.num_rar_entries = hw->mac.max_rx_queues;
896 diag = hw->mac.ops.reset_hw(hw);
898 if (diag != IXGBE_SUCCESS) {
899 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
900 RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
901 "\tThe most likely cause of this error is that the VM host\n"
902 "\thas not assigned a valid MAC address to this VF device.\n"
903 "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
904 "\ta possible solution to this problem.\n");
908 /* negotiate mailbox API version to use with the PF. */
909 ixgbevf_negotiate_api(hw);
911 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
912 ixgbevf_get_queues(hw, &tcs, &tc);
914 /* Allocate memory for storing MAC addresses */
915 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
916 hw->mac.num_rar_entries, 0);
917 if (eth_dev->data->mac_addrs == NULL) {
919 "Failed to allocate %u bytes needed to store "
921 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
925 /* Copy the permanent MAC address */
926 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
927 ð_dev->data->mac_addrs[0]);
929 /* reset the hardware with the new settings */
930 diag = hw->mac.ops.start_hw(hw);
936 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
940 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
941 eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
942 "ixgbe_mac_82599_vf");
947 static struct eth_driver rte_ixgbe_pmd = {
949 .name = "rte_ixgbe_pmd",
950 .id_table = pci_id_ixgbe_map,
951 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
953 .eth_dev_init = eth_ixgbe_dev_init,
954 .dev_private_size = sizeof(struct ixgbe_adapter),
958 * virtual function driver struct
960 static struct eth_driver rte_ixgbevf_pmd = {
962 .name = "rte_ixgbevf_pmd",
963 .id_table = pci_id_ixgbevf_map,
964 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
966 .eth_dev_init = eth_ixgbevf_dev_init,
967 .dev_private_size = sizeof(struct ixgbe_adapter),
971 * Driver initialization routine.
972 * Invoked once at EAL init time.
973 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
976 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
978 PMD_INIT_FUNC_TRACE();
980 rte_eth_driver_register(&rte_ixgbe_pmd);
985 * VF Driver initialization routine.
986 * Invoked one at EAL init time.
987 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
990 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
992 DEBUGFUNC("rte_ixgbevf_pmd_init");
994 rte_eth_driver_register(&rte_ixgbevf_pmd);
999 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1001 struct ixgbe_hw *hw =
1002 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1003 struct ixgbe_vfta * shadow_vfta =
1004 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1009 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1010 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1011 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1016 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1018 /* update local VFTA copy */
1019 shadow_vfta->vfta[vid_idx] = vfta;
1025 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1028 ixgbe_vlan_hw_strip_enable(dev, queue);
1030 ixgbe_vlan_hw_strip_disable(dev, queue);
1034 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1036 struct ixgbe_hw *hw =
1037 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039 /* Only the high 16-bits is valid */
1040 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1044 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1046 struct ixgbe_hw *hw =
1047 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050 PMD_INIT_FUNC_TRACE();
1052 /* Filter Table Disable */
1053 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1054 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1056 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1060 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1062 struct ixgbe_hw *hw =
1063 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1064 struct ixgbe_vfta * shadow_vfta =
1065 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1069 PMD_INIT_FUNC_TRACE();
1071 /* Filter Table Enable */
1072 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1073 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1074 vlnctrl |= IXGBE_VLNCTRL_VFE;
1076 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1078 /* write whatever is in local vfta copy */
1079 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1080 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1084 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1086 struct ixgbe_hwstrip *hwstrip =
1087 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1089 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1093 IXGBE_SET_HWSTRIP(hwstrip, queue);
1095 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1099 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1101 struct ixgbe_hw *hw =
1102 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105 PMD_INIT_FUNC_TRACE();
1107 if (hw->mac.type == ixgbe_mac_82598EB) {
1108 /* No queue level support */
1109 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1113 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1114 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1115 ctrl &= ~IXGBE_RXDCTL_VME;
1116 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1118 /* record those setting for HW strip per queue */
1119 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1123 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1125 struct ixgbe_hw *hw =
1126 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1129 PMD_INIT_FUNC_TRACE();
1131 if (hw->mac.type == ixgbe_mac_82598EB) {
1132 /* No queue level supported */
1133 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1137 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1138 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1139 ctrl |= IXGBE_RXDCTL_VME;
1140 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1142 /* record those setting for HW strip per queue */
1143 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1147 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1149 struct ixgbe_hw *hw =
1150 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1154 PMD_INIT_FUNC_TRACE();
1156 if (hw->mac.type == ixgbe_mac_82598EB) {
1157 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1158 ctrl &= ~IXGBE_VLNCTRL_VME;
1159 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1162 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1163 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1164 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1165 ctrl &= ~IXGBE_RXDCTL_VME;
1166 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1168 /* record those setting for HW strip per queue */
1169 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1175 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1177 struct ixgbe_hw *hw =
1178 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1182 PMD_INIT_FUNC_TRACE();
1184 if (hw->mac.type == ixgbe_mac_82598EB) {
1185 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1186 ctrl |= IXGBE_VLNCTRL_VME;
1187 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1190 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1191 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1192 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1193 ctrl |= IXGBE_RXDCTL_VME;
1194 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1196 /* record those setting for HW strip per queue */
1197 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1203 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1205 struct ixgbe_hw *hw =
1206 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1209 PMD_INIT_FUNC_TRACE();
1211 /* DMATXCTRL: Geric Double VLAN Disable */
1212 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1213 ctrl &= ~IXGBE_DMATXCTL_GDV;
1214 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1216 /* CTRL_EXT: Global Double VLAN Disable */
1217 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1218 ctrl &= ~IXGBE_EXTENDED_VLAN;
1219 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1224 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1226 struct ixgbe_hw *hw =
1227 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1230 PMD_INIT_FUNC_TRACE();
1232 /* DMATXCTRL: Geric Double VLAN Enable */
1233 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1234 ctrl |= IXGBE_DMATXCTL_GDV;
1235 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1237 /* CTRL_EXT: Global Double VLAN Enable */
1238 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1239 ctrl |= IXGBE_EXTENDED_VLAN;
1240 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1243 * VET EXT field in the EXVET register = 0x8100 by default
1244 * So no need to change. Same to VT field of DMATXCTL register
1249 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1251 if(mask & ETH_VLAN_STRIP_MASK){
1252 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1253 ixgbe_vlan_hw_strip_enable_all(dev);
1255 ixgbe_vlan_hw_strip_disable_all(dev);
1258 if(mask & ETH_VLAN_FILTER_MASK){
1259 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1260 ixgbe_vlan_hw_filter_enable(dev);
1262 ixgbe_vlan_hw_filter_disable(dev);
1265 if(mask & ETH_VLAN_EXTEND_MASK){
1266 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1267 ixgbe_vlan_hw_extend_enable(dev);
1269 ixgbe_vlan_hw_extend_disable(dev);
1274 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1276 struct ixgbe_hw *hw =
1277 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1278 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1279 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1280 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1281 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1285 ixgbe_dev_configure(struct rte_eth_dev *dev)
1287 struct ixgbe_interrupt *intr =
1288 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1290 PMD_INIT_FUNC_TRACE();
1292 /* set flag to update link status after init */
1293 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1299 * Configure device link speed and setup link.
1300 * It returns 0 on success.
1303 ixgbe_dev_start(struct rte_eth_dev *dev)
1305 struct ixgbe_hw *hw =
1306 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307 int err, link_up = 0, negotiate = 0;
1312 PMD_INIT_FUNC_TRACE();
1314 /* IXGBE devices don't support half duplex */
1315 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1316 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1317 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1318 dev->data->dev_conf.link_duplex,
1319 dev->data->port_id);
1324 hw->adapter_stopped = FALSE;
1325 ixgbe_stop_adapter(hw);
1327 /* reinitialize adapter
1328 * this calls reset and start */
1329 status = ixgbe_pf_reset_hw(hw);
1332 hw->mac.ops.start_hw(hw);
1334 /* configure PF module if SRIOV enabled */
1335 ixgbe_pf_host_configure(dev);
1337 /* initialize transmission unit */
1338 ixgbe_dev_tx_init(dev);
1340 /* This can fail when allocating mbufs for descriptor rings */
1341 err = ixgbe_dev_rx_init(dev);
1343 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1347 ixgbe_dev_rxtx_start(dev);
1349 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1350 err = hw->mac.ops.setup_sfp(hw);
1355 /* Turn on the laser */
1356 ixgbe_enable_tx_laser(hw);
1358 /* Skip link setup if loopback mode is enabled for 82599. */
1359 if (hw->mac.type == ixgbe_mac_82599EB &&
1360 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1361 goto skip_link_setup;
1363 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1366 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1370 switch(dev->data->dev_conf.link_speed) {
1371 case ETH_LINK_SPEED_AUTONEG:
1372 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1373 IXGBE_LINK_SPEED_82599_AUTONEG :
1374 IXGBE_LINK_SPEED_82598_AUTONEG;
1376 case ETH_LINK_SPEED_100:
1378 * Invalid for 82598 but error will be detected by
1379 * ixgbe_setup_link()
1381 speed = IXGBE_LINK_SPEED_100_FULL;
1383 case ETH_LINK_SPEED_1000:
1384 speed = IXGBE_LINK_SPEED_1GB_FULL;
1386 case ETH_LINK_SPEED_10000:
1387 speed = IXGBE_LINK_SPEED_10GB_FULL;
1390 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1391 dev->data->dev_conf.link_speed,
1392 dev->data->port_id);
1396 err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1402 /* check if lsc interrupt is enabled */
1403 if (dev->data->dev_conf.intr_conf.lsc != 0)
1404 ixgbe_dev_lsc_interrupt_setup(dev);
1406 /* resume enabled intr since hw reset */
1407 ixgbe_enable_intr(dev);
1409 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1410 ETH_VLAN_EXTEND_MASK;
1411 ixgbe_vlan_offload_set(dev, mask);
1413 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1414 /* Enable vlan filtering for VMDq */
1415 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1418 /* Configure DCB hw */
1419 ixgbe_configure_dcb(dev);
1421 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1422 err = ixgbe_fdir_configure(dev);
1427 ixgbe_restore_statistics_mapping(dev);
1432 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1433 ixgbe_dev_clear_queues(dev);
1438 * Stop device: disable rx and tx functions to allow for reconfiguring.
1441 ixgbe_dev_stop(struct rte_eth_dev *dev)
1443 struct rte_eth_link link;
1444 struct ixgbe_hw *hw =
1445 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1446 struct ixgbe_vf_info *vfinfo =
1447 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1450 PMD_INIT_FUNC_TRACE();
1452 /* disable interrupts */
1453 ixgbe_disable_intr(hw);
1456 ixgbe_pf_reset_hw(hw);
1457 hw->adapter_stopped = FALSE;
1460 ixgbe_stop_adapter(hw);
1462 for (vf = 0; vfinfo != NULL &&
1463 vf < dev->pci_dev->max_vfs; vf++)
1464 vfinfo[vf].clear_to_send = false;
1466 /* Turn off the laser */
1467 ixgbe_disable_tx_laser(hw);
1469 ixgbe_dev_clear_queues(dev);
1471 /* Clear recorded link status */
1472 memset(&link, 0, sizeof(link));
1473 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1477 * Reest and stop device.
1480 ixgbe_dev_close(struct rte_eth_dev *dev)
1482 struct ixgbe_hw *hw =
1483 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485 PMD_INIT_FUNC_TRACE();
1487 ixgbe_pf_reset_hw(hw);
1489 ixgbe_dev_stop(dev);
1490 hw->adapter_stopped = 1;
1492 ixgbe_disable_pcie_master(hw);
1494 /* reprogram the RAR[0] in case user changed it. */
1495 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1499 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1502 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1504 struct ixgbe_hw *hw =
1505 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506 struct ixgbe_hw_stats *hw_stats =
1507 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1508 uint32_t bprc, lxon, lxoff, total;
1509 uint64_t total_missed_rx, total_qbrc, total_qprc;
1512 total_missed_rx = 0;
1516 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1517 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1518 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1519 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1521 for (i = 0; i < 8; i++) {
1523 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1524 /* global total per queue */
1525 hw_stats->mpc[i] += mp;
1526 /* Running comprehensive total for stats display */
1527 total_missed_rx += hw_stats->mpc[i];
1528 if (hw->mac.type == ixgbe_mac_82598EB)
1529 hw_stats->rnbc[i] +=
1530 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1531 hw_stats->pxontxc[i] +=
1532 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1533 hw_stats->pxonrxc[i] +=
1534 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1535 hw_stats->pxofftxc[i] +=
1536 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1537 hw_stats->pxoffrxc[i] +=
1538 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1539 hw_stats->pxon2offc[i] +=
1540 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1542 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1543 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1544 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1545 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1546 hw_stats->qbrc[i] +=
1547 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1548 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1549 hw_stats->qbtc[i] +=
1550 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1551 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1553 total_qprc += hw_stats->qprc[i];
1554 total_qbrc += hw_stats->qbrc[i];
1556 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1557 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1558 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1560 /* Note that gprc counts missed packets */
1561 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1563 if (hw->mac.type != ixgbe_mac_82598EB) {
1564 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1565 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1566 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1567 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1568 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1569 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1570 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1571 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1573 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1574 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1575 /* 82598 only has a counter in the high register */
1576 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1577 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1578 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1582 * Workaround: mprc hardware is incorrectly counting
1583 * broadcasts, so for now we subtract those.
1585 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1586 hw_stats->bprc += bprc;
1587 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1588 if (hw->mac.type == ixgbe_mac_82598EB)
1589 hw_stats->mprc -= bprc;
1591 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1592 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1593 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1594 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1595 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1596 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1598 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1599 hw_stats->lxontxc += lxon;
1600 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1601 hw_stats->lxofftxc += lxoff;
1602 total = lxon + lxoff;
1604 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1605 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1606 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1607 hw_stats->gptc -= total;
1608 hw_stats->mptc -= total;
1609 hw_stats->ptc64 -= total;
1610 hw_stats->gotc -= total * ETHER_MIN_LEN;
1612 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1613 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1614 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1615 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1616 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1617 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1618 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1619 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1620 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1621 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1622 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1623 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1624 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1625 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1626 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1627 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1628 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1629 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1630 /* Only read FCOE on 82599 */
1631 if (hw->mac.type != ixgbe_mac_82598EB) {
1632 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1633 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1634 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1635 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1636 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1642 /* Fill out the rte_eth_stats statistics structure */
1643 stats->ipackets = total_qprc;
1644 stats->ibytes = total_qbrc;
1645 stats->opackets = hw_stats->gptc;
1646 stats->obytes = hw_stats->gotc;
1647 stats->imcasts = hw_stats->mprc;
1649 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1650 stats->q_ipackets[i] = hw_stats->qprc[i];
1651 stats->q_opackets[i] = hw_stats->qptc[i];
1652 stats->q_ibytes[i] = hw_stats->qbrc[i];
1653 stats->q_obytes[i] = hw_stats->qbtc[i];
1654 stats->q_errors[i] = hw_stats->qprdc[i];
1658 stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1663 /* XON/XOFF pause frames */
1664 stats->tx_pause_xon = hw_stats->lxontxc;
1665 stats->rx_pause_xon = hw_stats->lxonrxc;
1666 stats->tx_pause_xoff = hw_stats->lxofftxc;
1667 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1669 /* Flow Director Stats registers */
1670 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1671 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1672 stats->fdirmatch = hw_stats->fdirmatch;
1673 stats->fdirmiss = hw_stats->fdirmiss;
1677 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1679 struct ixgbe_hw_stats *stats =
1680 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1682 /* HW registers are cleared on read */
1683 ixgbe_dev_stats_get(dev, NULL);
1685 /* Reset software totals */
1686 memset(stats, 0, sizeof(*stats));
1690 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1692 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1694 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1696 /* Good Rx packet, include VF loopback */
1697 UPDATE_VF_STAT(IXGBE_VFGPRC,
1698 hw_stats->last_vfgprc, hw_stats->vfgprc);
1700 /* Good Rx octets, include VF loopback */
1701 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1702 hw_stats->last_vfgorc, hw_stats->vfgorc);
1704 /* Good Tx packet, include VF loopback */
1705 UPDATE_VF_STAT(IXGBE_VFGPTC,
1706 hw_stats->last_vfgptc, hw_stats->vfgptc);
1708 /* Good Tx octets, include VF loopback */
1709 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1710 hw_stats->last_vfgotc, hw_stats->vfgotc);
1712 /* Rx Multicst Packet */
1713 UPDATE_VF_STAT(IXGBE_VFMPRC,
1714 hw_stats->last_vfmprc, hw_stats->vfmprc);
1719 memset(stats, 0, sizeof(*stats));
1720 stats->ipackets = hw_stats->vfgprc;
1721 stats->ibytes = hw_stats->vfgorc;
1722 stats->opackets = hw_stats->vfgptc;
1723 stats->obytes = hw_stats->vfgotc;
1724 stats->imcasts = hw_stats->vfmprc;
1728 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1730 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1731 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1733 /* Sync HW register to the last stats */
1734 ixgbevf_dev_stats_get(dev, NULL);
1736 /* reset HW current stats*/
1737 hw_stats->vfgprc = 0;
1738 hw_stats->vfgorc = 0;
1739 hw_stats->vfgptc = 0;
1740 hw_stats->vfgotc = 0;
1741 hw_stats->vfmprc = 0;
1746 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1748 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1751 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1752 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1753 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1754 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1755 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1756 dev_info->max_vfs = dev->pci_dev->max_vfs;
1757 if (hw->mac.type == ixgbe_mac_82598EB)
1758 dev_info->max_vmdq_pools = ETH_16_POOLS;
1760 dev_info->max_vmdq_pools = ETH_64_POOLS;
1761 dev_info->rx_offload_capa =
1762 DEV_RX_OFFLOAD_VLAN_STRIP |
1763 DEV_RX_OFFLOAD_IPV4_CKSUM |
1764 DEV_RX_OFFLOAD_UDP_CKSUM |
1765 DEV_RX_OFFLOAD_TCP_CKSUM;
1766 dev_info->tx_offload_capa =
1767 DEV_TX_OFFLOAD_VLAN_INSERT |
1768 DEV_TX_OFFLOAD_IPV4_CKSUM |
1769 DEV_TX_OFFLOAD_UDP_CKSUM |
1770 DEV_TX_OFFLOAD_TCP_CKSUM |
1771 DEV_TX_OFFLOAD_SCTP_CKSUM;
1774 /* return 0 means link status changed, -1 means not changed */
1776 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1778 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1779 struct rte_eth_link link, old;
1780 ixgbe_link_speed link_speed;
1784 link.link_status = 0;
1785 link.link_speed = 0;
1786 link.link_duplex = 0;
1787 memset(&old, 0, sizeof(old));
1788 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1790 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1791 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1792 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1794 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1796 link.link_speed = ETH_LINK_SPEED_100;
1797 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1798 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1799 if (link.link_status == old.link_status)
1805 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1806 if (link.link_status == old.link_status)
1810 link.link_status = 1;
1811 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1813 switch (link_speed) {
1815 case IXGBE_LINK_SPEED_UNKNOWN:
1816 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1817 link.link_speed = ETH_LINK_SPEED_100;
1820 case IXGBE_LINK_SPEED_100_FULL:
1821 link.link_speed = ETH_LINK_SPEED_100;
1824 case IXGBE_LINK_SPEED_1GB_FULL:
1825 link.link_speed = ETH_LINK_SPEED_1000;
1828 case IXGBE_LINK_SPEED_10GB_FULL:
1829 link.link_speed = ETH_LINK_SPEED_10000;
1832 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1834 if (link.link_status == old.link_status)
1841 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1843 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1847 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1848 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1852 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1854 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1858 fctrl &= (~IXGBE_FCTRL_UPE);
1859 if (dev->data->all_multicast == 1)
1860 fctrl |= IXGBE_FCTRL_MPE;
1862 fctrl &= (~IXGBE_FCTRL_MPE);
1863 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1867 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1869 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1873 fctrl |= IXGBE_FCTRL_MPE;
1874 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1878 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1880 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883 if (dev->data->promiscuous == 1)
1884 return; /* must remain in all_multicast mode */
1886 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1887 fctrl &= (~IXGBE_FCTRL_MPE);
1888 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1892 * It clears the interrupt causes and enables the interrupt.
1893 * It will be called once only during nic initialized.
1896 * Pointer to struct rte_eth_dev.
1899 * - On success, zero.
1900 * - On failure, a negative value.
1903 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1905 struct ixgbe_interrupt *intr =
1906 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1908 ixgbe_dev_link_status_print(dev);
1909 intr->mask |= IXGBE_EICR_LSC;
1915 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1918 * Pointer to struct rte_eth_dev.
1921 * - On success, zero.
1922 * - On failure, a negative value.
1925 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1928 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929 struct ixgbe_interrupt *intr =
1930 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1932 /* clear all cause mask */
1933 ixgbe_disable_intr(hw);
1935 /* read-on-clear nic registers here */
1936 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1937 PMD_DRV_LOG(INFO, "eicr %x", eicr);
1940 if (eicr & IXGBE_EICR_LSC) {
1941 /* set flag for async link update */
1942 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1945 if (eicr & IXGBE_EICR_MAILBOX)
1946 intr->flags |= IXGBE_FLAG_MAILBOX;
1952 * It gets and then prints the link status.
1955 * Pointer to struct rte_eth_dev.
1958 * - On success, zero.
1959 * - On failure, a negative value.
1962 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1964 struct rte_eth_link link;
1966 memset(&link, 0, sizeof(link));
1967 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1968 if (link.link_status) {
1969 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1970 (int)(dev->data->port_id),
1971 (unsigned)link.link_speed,
1972 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1973 "full-duplex" : "half-duplex");
1975 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1976 (int)(dev->data->port_id));
1978 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1979 dev->pci_dev->addr.domain,
1980 dev->pci_dev->addr.bus,
1981 dev->pci_dev->addr.devid,
1982 dev->pci_dev->addr.function);
1986 * It executes link_update after knowing an interrupt occurred.
1989 * Pointer to struct rte_eth_dev.
1992 * - On success, zero.
1993 * - On failure, a negative value.
1996 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1998 struct ixgbe_interrupt *intr =
1999 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2001 struct rte_eth_link link;
2002 int intr_enable_delay = false;
2004 PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
2006 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2007 ixgbe_pf_mbx_process(dev);
2008 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2011 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2012 /* get the link status before link update, for predicting later */
2013 memset(&link, 0, sizeof(link));
2014 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2016 ixgbe_dev_link_update(dev, 0);
2019 if (!link.link_status)
2020 /* handle it 1 sec later, wait it being stable */
2021 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2022 /* likely to down */
2024 /* handle it 4 sec later, wait it being stable */
2025 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2027 ixgbe_dev_link_status_print(dev);
2029 intr_enable_delay = true;
2032 if (intr_enable_delay) {
2033 if (rte_eal_alarm_set(timeout * 1000,
2034 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2035 PMD_DRV_LOG(ERR, "Error setting alarm");
2037 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2038 ixgbe_enable_intr(dev);
2039 rte_intr_enable(&(dev->pci_dev->intr_handle));
2047 * Interrupt handler which shall be registered for alarm callback for delayed
2048 * handling specific interrupt to wait for the stable nic state. As the
2049 * NIC interrupt state is not stable for ixgbe after link is just down,
2050 * it needs to wait 4 seconds to get the stable status.
2053 * Pointer to interrupt handle.
2055 * The address of parameter (struct rte_eth_dev *) regsitered before.
2061 ixgbe_dev_interrupt_delayed_handler(void *param)
2063 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2064 struct ixgbe_interrupt *intr =
2065 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2066 struct ixgbe_hw *hw =
2067 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2071 if (eicr & IXGBE_EICR_MAILBOX)
2072 ixgbe_pf_mbx_process(dev);
2074 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2075 ixgbe_dev_link_update(dev, 0);
2076 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2077 ixgbe_dev_link_status_print(dev);
2078 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2081 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2082 ixgbe_enable_intr(dev);
2083 rte_intr_enable(&(dev->pci_dev->intr_handle));
2087 * Interrupt handler triggered by NIC for handling
2088 * specific interrupt.
2091 * Pointer to interrupt handle.
2093 * The address of parameter (struct rte_eth_dev *) regsitered before.
2099 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2102 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2103 ixgbe_dev_interrupt_get_status(dev);
2104 ixgbe_dev_interrupt_action(dev);
2108 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2110 struct ixgbe_hw *hw;
2112 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2117 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2119 struct ixgbe_hw *hw;
2121 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2122 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2126 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2128 struct ixgbe_hw *hw;
2130 uint32_t rx_buf_size;
2131 uint32_t max_high_water;
2133 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2140 PMD_INIT_FUNC_TRACE();
2142 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2144 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2147 * At least reserve one Ethernet frame for watermark
2148 * high_water/low_water in kilo bytes for ixgbe
2150 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2151 if ((fc_conf->high_water > max_high_water) ||
2152 (fc_conf->high_water < fc_conf->low_water)) {
2153 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2154 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2158 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2159 hw->fc.pause_time = fc_conf->pause_time;
2160 hw->fc.high_water[0] = fc_conf->high_water;
2161 hw->fc.low_water[0] = fc_conf->low_water;
2162 hw->fc.send_xon = fc_conf->send_xon;
2164 err = ixgbe_fc_enable(hw);
2166 /* Not negotiated is not an error case */
2167 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2169 /* check if we want to forward MAC frames - driver doesn't have native
2170 * capability to do that, so we'll write the registers ourselves */
2172 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2174 /* set or clear MFLCN.PMCF bit depending on configuration */
2175 if (fc_conf->mac_ctrl_frame_fwd != 0)
2176 mflcn |= IXGBE_MFLCN_PMCF;
2178 mflcn &= ~IXGBE_MFLCN_PMCF;
2180 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2181 IXGBE_WRITE_FLUSH(hw);
2186 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2191 * ixgbe_pfc_enable_generic - Enable flow control
2192 * @hw: pointer to hardware structure
2193 * @tc_num: traffic class number
2194 * Enable flow control according to the current settings.
2197 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2200 uint32_t mflcn_reg, fccfg_reg;
2202 uint32_t fcrtl, fcrth;
2206 /* Validate the water mark configuration */
2207 if (!hw->fc.pause_time) {
2208 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2212 /* Low water mark of zero causes XOFF floods */
2213 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2214 /* High/Low water can not be 0 */
2215 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2216 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2217 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2221 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2222 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2223 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2227 /* Negotiate the fc mode to use */
2228 ixgbe_fc_autoneg(hw);
2230 /* Disable any previous flow control settings */
2231 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2232 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2234 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2235 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2237 switch (hw->fc.current_mode) {
2240 * If the count of enabled RX Priority Flow control >1,
2241 * and the TX pause can not be disabled
2244 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2245 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2246 if (reg & IXGBE_FCRTH_FCEN)
2250 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2252 case ixgbe_fc_rx_pause:
2254 * Rx Flow control is enabled and Tx Flow control is
2255 * disabled by software override. Since there really
2256 * isn't a way to advertise that we are capable of RX
2257 * Pause ONLY, we will advertise that we support both
2258 * symmetric and asymmetric Rx PAUSE. Later, we will
2259 * disable the adapter's ability to send PAUSE frames.
2261 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2263 * If the count of enabled RX Priority Flow control >1,
2264 * and the TX pause can not be disabled
2267 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2268 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2269 if (reg & IXGBE_FCRTH_FCEN)
2273 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2275 case ixgbe_fc_tx_pause:
2277 * Tx Flow control is enabled, and Rx Flow control is
2278 * disabled by software override.
2280 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2283 /* Flow control (both Rx and Tx) is enabled by SW override. */
2284 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2285 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2288 DEBUGOUT("Flow control param set incorrectly\n");
2289 ret_val = IXGBE_ERR_CONFIG;
2294 /* Set 802.3x based flow control settings. */
2295 mflcn_reg |= IXGBE_MFLCN_DPF;
2296 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2297 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2299 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2300 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2301 hw->fc.high_water[tc_num]) {
2302 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2303 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2304 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2306 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2308 * In order to prevent Tx hangs when the internal Tx
2309 * switch is enabled we must set the high water mark
2310 * to the maximum FCRTH value. This allows the Tx
2311 * switch to function even under heavy Rx workloads.
2313 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2315 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2317 /* Configure pause time (2 TCs per register) */
2318 reg = hw->fc.pause_time * 0x00010001;
2319 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2320 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2322 /* Configure flow control refresh threshold value */
2323 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2330 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2332 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2335 if(hw->mac.type != ixgbe_mac_82598EB) {
2336 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2342 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2345 uint32_t rx_buf_size;
2346 uint32_t max_high_water;
2348 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2349 struct ixgbe_hw *hw =
2350 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351 struct ixgbe_dcb_config *dcb_config =
2352 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2354 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2361 PMD_INIT_FUNC_TRACE();
2363 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2364 tc_num = map[pfc_conf->priority];
2365 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2366 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2368 * At least reserve one Ethernet frame for watermark
2369 * high_water/low_water in kilo bytes for ixgbe
2371 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2372 if ((pfc_conf->fc.high_water > max_high_water) ||
2373 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2374 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2375 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2379 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2380 hw->fc.pause_time = pfc_conf->fc.pause_time;
2381 hw->fc.send_xon = pfc_conf->fc.send_xon;
2382 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2383 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2385 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2387 /* Not negotiated is not an error case */
2388 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2391 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2396 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2397 struct rte_eth_rss_reta *reta_conf)
2401 struct ixgbe_hw *hw =
2402 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404 PMD_INIT_FUNC_TRACE();
2406 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2407 * 128-entries in 32 registers
2409 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2410 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2411 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2413 mask = (uint8_t)((reta_conf->mask_hi >>
2414 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2418 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2420 for (j = 0; j < 4; j++) {
2421 if (mask & (0x1 << j)) {
2423 reta &= ~(0xFF << 8 * j);
2424 reta |= reta_conf->reta[i + j] << 8*j;
2427 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2435 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2436 struct rte_eth_rss_reta *reta_conf)
2440 struct ixgbe_hw *hw =
2441 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2443 PMD_INIT_FUNC_TRACE();
2445 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2446 * 128-entries in 32 registers
2448 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2449 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2450 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2452 mask = (uint8_t)((reta_conf->mask_hi >>
2453 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2456 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2457 for (j = 0; j < 4; j++) {
2458 if (mask & (0x1 << j))
2459 reta_conf->reta[i + j] =
2460 (uint8_t)((reta >> 8 * j) & 0xFF);
2469 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2470 uint32_t index, uint32_t pool)
2472 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2473 uint32_t enable_addr = 1;
2475 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2479 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2481 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2483 ixgbe_clear_rar(hw, index);
2487 * Virtual Function operations
2490 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2492 PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2494 /* Clear interrupt mask to stop from interrupts being generated */
2495 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2497 IXGBE_WRITE_FLUSH(hw);
2501 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2503 struct rte_eth_conf* conf = &dev->data->dev_conf;
2505 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2506 dev->data->port_id);
2509 * VF has no ability to enable/disable HW CRC
2510 * Keep the persistent behavior the same as Host PF
2512 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2513 if (!conf->rxmode.hw_strip_crc) {
2514 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2515 conf->rxmode.hw_strip_crc = 1;
2518 if (conf->rxmode.hw_strip_crc) {
2519 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2520 conf->rxmode.hw_strip_crc = 0;
2528 ixgbevf_dev_start(struct rte_eth_dev *dev)
2530 struct ixgbe_hw *hw =
2531 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2536 hw->mac.ops.reset_hw(hw);
2538 /* negotiate mailbox API version to use with the PF. */
2539 ixgbevf_negotiate_api(hw);
2541 ixgbevf_dev_tx_init(dev);
2543 /* This can fail when allocating mbufs for descriptor rings */
2544 err = ixgbevf_dev_rx_init(dev);
2546 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2547 ixgbe_dev_clear_queues(dev);
2552 ixgbevf_set_vfta_all(dev,1);
2555 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2556 ETH_VLAN_EXTEND_MASK;
2557 ixgbevf_vlan_offload_set(dev, mask);
2559 ixgbevf_dev_rxtx_start(dev);
2565 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2567 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2571 hw->adapter_stopped = TRUE;
2572 ixgbe_stop_adapter(hw);
2575 * Clear what we set, but we still keep shadow_vfta to
2576 * restore after device starts
2578 ixgbevf_set_vfta_all(dev,0);
2580 ixgbe_dev_clear_queues(dev);
2584 ixgbevf_dev_close(struct rte_eth_dev *dev)
2586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2588 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2592 ixgbevf_dev_stop(dev);
2594 /* reprogram the RAR[0] in case user changed it. */
2595 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2598 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2600 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601 struct ixgbe_vfta * shadow_vfta =
2602 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2603 int i = 0, j = 0, vfta = 0, mask = 1;
2605 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2606 vfta = shadow_vfta->vfta[i];
2609 for (j = 0; j < 32; j++){
2611 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2620 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2622 struct ixgbe_hw *hw =
2623 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2624 struct ixgbe_vfta * shadow_vfta =
2625 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2626 uint32_t vid_idx = 0;
2627 uint32_t vid_bit = 0;
2630 PMD_INIT_FUNC_TRACE();
2632 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2633 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2635 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2638 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2639 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2641 /* Save what we set and retore it after device reset */
2643 shadow_vfta->vfta[vid_idx] |= vid_bit;
2645 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2651 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2653 struct ixgbe_hw *hw =
2654 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657 PMD_INIT_FUNC_TRACE();
2659 if(queue >= hw->mac.max_rx_queues)
2662 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2664 ctrl |= IXGBE_RXDCTL_VME;
2666 ctrl &= ~IXGBE_RXDCTL_VME;
2667 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2669 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2673 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2675 struct ixgbe_hw *hw =
2676 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2680 /* VF function only support hw strip feature, others are not support */
2681 if(mask & ETH_VLAN_STRIP_MASK){
2682 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2684 for(i=0; i < hw->mac.max_rx_queues; i++)
2685 ixgbevf_vlan_strip_queue_set(dev,i,on);
2690 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2694 /* we only need to do this if VMDq is enabled */
2695 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2696 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2697 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2705 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2707 uint32_t vector = 0;
2708 switch (hw->mac.mc_filter_type) {
2709 case 0: /* use bits [47:36] of the address */
2710 vector = ((uc_addr->addr_bytes[4] >> 4) |
2711 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2713 case 1: /* use bits [46:35] of the address */
2714 vector = ((uc_addr->addr_bytes[4] >> 3) |
2715 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2717 case 2: /* use bits [45:34] of the address */
2718 vector = ((uc_addr->addr_bytes[4] >> 2) |
2719 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2721 case 3: /* use bits [43:32] of the address */
2722 vector = ((uc_addr->addr_bytes[4]) |
2723 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2725 default: /* Invalid mc_filter_type */
2729 /* vector can only be 12-bits or boundary will be exceeded */
2735 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2743 const uint32_t ixgbe_uta_idx_mask = 0x7F;
2744 const uint32_t ixgbe_uta_bit_shift = 5;
2745 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2746 const uint32_t bit1 = 0x1;
2748 struct ixgbe_hw *hw =
2749 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2750 struct ixgbe_uta_info *uta_info =
2751 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2753 /* The UTA table only exists on 82599 hardware and newer */
2754 if (hw->mac.type < ixgbe_mac_82599EB)
2757 vector = ixgbe_uta_vector(hw,mac_addr);
2758 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2759 uta_shift = vector & ixgbe_uta_bit_mask;
2761 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2765 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2767 uta_info->uta_in_use++;
2768 reg_val |= (bit1 << uta_shift);
2769 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2771 uta_info->uta_in_use--;
2772 reg_val &= ~(bit1 << uta_shift);
2773 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2776 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2778 if (uta_info->uta_in_use > 0)
2779 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2780 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2782 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2788 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2791 struct ixgbe_hw *hw =
2792 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793 struct ixgbe_uta_info *uta_info =
2794 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2796 /* The UTA table only exists on 82599 hardware and newer */
2797 if (hw->mac.type < ixgbe_mac_82599EB)
2801 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2802 uta_info->uta_shadow[i] = ~0;
2803 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2806 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2807 uta_info->uta_shadow[i] = 0;
2808 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2815 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2816 uint16_t rx_mask, uint8_t on)
2820 struct ixgbe_hw *hw =
2821 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2824 if (hw->mac.type == ixgbe_mac_82598EB) {
2825 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2826 " on 82599 hardware and newer\n");
2829 if (ixgbe_vmdq_mode_check(hw) < 0)
2832 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2833 val |= IXGBE_VMOLR_AUPE;
2834 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2835 val |= IXGBE_VMOLR_ROMPE;
2836 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2837 val |= IXGBE_VMOLR_ROPE;
2838 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2839 val |= IXGBE_VMOLR_BAM;
2840 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2841 val |= IXGBE_VMOLR_MPE;
2848 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2854 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2858 const uint8_t bit1 = 0x1;
2860 struct ixgbe_hw *hw =
2861 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2863 if (ixgbe_vmdq_mode_check(hw) < 0)
2866 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2867 reg = IXGBE_READ_REG(hw, addr);
2875 IXGBE_WRITE_REG(hw, addr,reg);
2881 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2885 const uint8_t bit1 = 0x1;
2887 struct ixgbe_hw *hw =
2888 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890 if (ixgbe_vmdq_mode_check(hw) < 0)
2893 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2894 reg = IXGBE_READ_REG(hw, addr);
2902 IXGBE_WRITE_REG(hw, addr,reg);
2908 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2909 uint64_t pool_mask, uint8_t vlan_on)
2913 struct ixgbe_hw *hw =
2914 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916 if (ixgbe_vmdq_mode_check(hw) < 0)
2918 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2919 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2920 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2929 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2930 struct rte_eth_vmdq_mirror_conf *mirror_conf,
2931 uint8_t rule_id, uint8_t on)
2933 uint32_t mr_ctl,vlvf;
2934 uint32_t mp_lsb = 0;
2935 uint32_t mv_msb = 0;
2936 uint32_t mv_lsb = 0;
2937 uint32_t mp_msb = 0;
2940 uint64_t vlan_mask = 0;
2942 const uint8_t pool_mask_offset = 32;
2943 const uint8_t vlan_mask_offset = 32;
2944 const uint8_t dst_pool_offset = 8;
2945 const uint8_t rule_mr_offset = 4;
2946 const uint8_t mirror_rule_mask= 0x0F;
2948 struct ixgbe_mirror_info *mr_info =
2949 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2950 struct ixgbe_hw *hw =
2951 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953 if (ixgbe_vmdq_mode_check(hw) < 0)
2956 /* Check if vlan mask is valid */
2957 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2958 if (mirror_conf->vlan.vlan_mask == 0)
2962 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2963 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2964 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2965 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2966 /* search vlan id related pool vlan filter index */
2967 reg_index = ixgbe_find_vlvf_slot(hw,
2968 mirror_conf->vlan.vlan_id[i]);
2971 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2972 if ((vlvf & IXGBE_VLVF_VIEN) &&
2973 ((vlvf & IXGBE_VLVF_VLANID_MASK)
2974 == mirror_conf->vlan.vlan_id[i]))
2975 vlan_mask |= (1ULL << reg_index);
2982 mv_lsb = vlan_mask & 0xFFFFFFFF;
2983 mv_msb = vlan_mask >> vlan_mask_offset;
2985 mr_info->mr_conf[rule_id].vlan.vlan_mask =
2986 mirror_conf->vlan.vlan_mask;
2987 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2988 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2989 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2990 mirror_conf->vlan.vlan_id[i];
2995 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
2996 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
2997 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3002 * if enable pool mirror, write related pool mask register,if disable
3003 * pool mirror, clear PFMRVM register
3005 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3007 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3008 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3009 mr_info->mr_conf[rule_id].pool_mask =
3010 mirror_conf->pool_mask;
3015 mr_info->mr_conf[rule_id].pool_mask = 0;
3019 /* read mirror control register and recalculate it */
3020 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3023 mr_ctl |= mirror_conf->rule_type_mask;
3024 mr_ctl &= mirror_rule_mask;
3025 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3027 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3029 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3030 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3032 /* write mirrror control register */
3033 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3035 /* write pool mirrror control register */
3036 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3037 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3038 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3041 /* write VLAN mirrror control register */
3042 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3043 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3044 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3052 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3055 uint32_t lsb_val = 0;
3056 uint32_t msb_val = 0;
3057 const uint8_t rule_mr_offset = 4;
3059 struct ixgbe_hw *hw =
3060 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3061 struct ixgbe_mirror_info *mr_info =
3062 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3064 if (ixgbe_vmdq_mode_check(hw) < 0)
3067 memset(&mr_info->mr_conf[rule_id], 0,
3068 sizeof(struct rte_eth_vmdq_mirror_conf));
3070 /* clear PFVMCTL register */
3071 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3073 /* clear pool mask register */
3074 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3075 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3077 /* clear vlan mask register */
3078 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3079 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3084 static struct rte_driver rte_ixgbe_driver = {
3086 .init = rte_ixgbe_pmd_init,
3089 static struct rte_driver rte_ixgbevf_driver = {
3091 .init = rte_ixgbevf_pmd_init,
3094 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3095 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);