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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_tailq.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
62 #include "ixgbe_logs.h"
63 #include "ixgbe/ixgbe_api.h"
64 #include "ixgbe/ixgbe_vf.h"
65 #include "ixgbe/ixgbe_common.h"
66 #include "ixgbe_ethdev.h"
67 #include "ixgbe_bypass.h"
70 * High threshold controlling when to start sending XOFF frames. Must be at
71 * least 8 bytes less than receive packet buffer size. This value is in units
74 #define IXGBE_FC_HI 0x80
77 * Low threshold controlling when to start sending XON frames. This value is
78 * in units of 1024 bytes.
80 #define IXGBE_FC_LO 0x40
82 /* Timer value included in XOFF frames. */
83 #define IXGBE_FC_PAUSE 0x680
85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
86 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
87 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
90 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
92 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
94 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
95 struct rte_eth_dev *eth_dev);
96 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
97 static int ixgbe_dev_start(struct rte_eth_dev *dev);
98 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
99 static void ixgbe_dev_close(struct rte_eth_dev *dev);
100 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
101 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
102 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
103 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
104 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
105 int wait_to_complete);
106 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
107 struct rte_eth_stats *stats);
108 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
109 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
113 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
114 struct rte_eth_dev_info *dev_info);
115 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
116 uint16_t vlan_id, int on);
117 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
118 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
119 uint16_t queue, bool on);
120 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
122 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
123 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
124 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
125 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
126 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
128 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
129 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
130 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
131 struct rte_eth_fc_conf *fc_conf);
132 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
133 struct rte_eth_pfc_conf *pfc_conf);
134 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
135 struct rte_eth_rss_reta *reta_conf);
136 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
137 struct rte_eth_rss_reta *reta_conf);
138 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
139 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
140 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
141 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
142 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
144 static void ixgbe_dev_interrupt_delayed_handler(void *param);
145 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
146 uint32_t index, uint32_t pool);
147 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
148 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
150 /* For Virtual Function support */
151 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
152 struct rte_eth_dev *eth_dev);
153 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
154 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
155 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
156 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
157 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
158 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
161 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
162 uint16_t vlan_id, int on);
163 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
164 uint16_t queue, int on);
165 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
166 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
168 /* For Eth VMDQ APIs support */
169 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
170 ether_addr* mac_addr,uint8_t on);
171 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
172 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
173 uint16_t rx_mask, uint8_t on);
174 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
175 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
176 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
177 uint64_t pool_mask,uint8_t vlan_on);
178 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
179 struct rte_eth_vmdq_mirror_conf *mirror_conf,
180 uint8_t rule_id, uint8_t on);
181 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
185 * Define VF Stats MACRO for Non "cleared on read" register
187 #define UPDATE_VF_STAT(reg, last, cur) \
189 u32 latest = IXGBE_READ_REG(hw, reg); \
190 cur += latest - last; \
194 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
196 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
197 u64 new_msb = IXGBE_READ_REG(hw, msb); \
198 u64 latest = ((new_msb << 32) | new_lsb); \
199 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
203 #define IXGBE_SET_HWSTRIP(h, q) do{\
204 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
205 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
206 (h)->bitmap[idx] |= 1 << bit;\
209 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
210 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
211 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
212 (h)->bitmap[idx] &= ~(1 << bit);\
215 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
216 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
217 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
218 (r) = (h)->bitmap[idx] >> bit & 1;\
222 * The set of PCI devices this driver supports
224 static struct rte_pci_id pci_id_ixgbe_map[] = {
226 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
227 #include "rte_pci_dev_ids.h"
229 { .vendor_id = 0, /* sentinel */ },
234 * The set of PCI devices this driver supports (for 82599 VF)
236 static struct rte_pci_id pci_id_ixgbevf_map[] = {
238 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
239 #include "rte_pci_dev_ids.h"
240 { .vendor_id = 0, /* sentinel */ },
244 static struct eth_dev_ops ixgbe_eth_dev_ops = {
245 .dev_configure = ixgbe_dev_configure,
246 .dev_start = ixgbe_dev_start,
247 .dev_stop = ixgbe_dev_stop,
248 .dev_close = ixgbe_dev_close,
249 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
250 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
251 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
252 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
253 .link_update = ixgbe_dev_link_update,
254 .stats_get = ixgbe_dev_stats_get,
255 .stats_reset = ixgbe_dev_stats_reset,
256 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
257 .dev_infos_get = ixgbe_dev_info_get,
258 .vlan_filter_set = ixgbe_vlan_filter_set,
259 .vlan_tpid_set = ixgbe_vlan_tpid_set,
260 .vlan_offload_set = ixgbe_vlan_offload_set,
261 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
262 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
263 .rx_queue_release = ixgbe_dev_rx_queue_release,
264 .rx_queue_count = ixgbe_dev_rx_queue_count,
265 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
266 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
267 .tx_queue_release = ixgbe_dev_tx_queue_release,
268 .dev_led_on = ixgbe_dev_led_on,
269 .dev_led_off = ixgbe_dev_led_off,
270 .flow_ctrl_set = ixgbe_flow_ctrl_set,
271 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
272 .mac_addr_add = ixgbe_add_rar,
273 .mac_addr_remove = ixgbe_remove_rar,
274 .uc_hash_table_set = ixgbe_uc_hash_table_set,
275 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
276 .mirror_rule_set = ixgbe_mirror_rule_set,
277 .mirror_rule_reset = ixgbe_mirror_rule_reset,
278 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
279 .set_vf_rx = ixgbe_set_pool_rx,
280 .set_vf_tx = ixgbe_set_pool_tx,
281 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
282 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
283 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
284 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
285 .fdir_infos_get = ixgbe_fdir_info_get,
286 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
287 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
288 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
289 .fdir_set_masks = ixgbe_fdir_set_masks,
290 .reta_update = ixgbe_dev_rss_reta_update,
291 .reta_query = ixgbe_dev_rss_reta_query,
292 #ifdef RTE_NIC_BYPASS
293 .bypass_init = ixgbe_bypass_init,
294 .bypass_state_set = ixgbe_bypass_state_store,
295 .bypass_state_show = ixgbe_bypass_state_show,
296 .bypass_event_set = ixgbe_bypass_event_store,
297 .bypass_event_show = ixgbe_bypass_event_show,
298 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
299 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
300 .bypass_ver_show = ixgbe_bypass_ver_show,
301 .bypass_wd_reset = ixgbe_bypass_wd_reset,
302 #endif /* RTE_NIC_BYPASS */
306 * dev_ops for virtual function, bare necessities for basic vf
307 * operation have been implemented
309 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
311 .dev_configure = ixgbevf_dev_configure,
312 .dev_start = ixgbevf_dev_start,
313 .dev_stop = ixgbevf_dev_stop,
314 .link_update = ixgbe_dev_link_update,
315 .stats_get = ixgbevf_dev_stats_get,
316 .stats_reset = ixgbevf_dev_stats_reset,
317 .dev_close = ixgbevf_dev_close,
318 .dev_infos_get = ixgbe_dev_info_get,
319 .vlan_filter_set = ixgbevf_vlan_filter_set,
320 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
321 .vlan_offload_set = ixgbevf_vlan_offload_set,
322 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
323 .rx_queue_release = ixgbe_dev_rx_queue_release,
324 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
325 .tx_queue_release = ixgbe_dev_tx_queue_release,
329 * Atomically reads the link status information from global
330 * structure rte_eth_dev.
333 * - Pointer to the structure rte_eth_dev to read from.
334 * - Pointer to the buffer to be saved with the link status.
337 * - On success, zero.
338 * - On failure, negative value.
341 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
342 struct rte_eth_link *link)
344 struct rte_eth_link *dst = link;
345 struct rte_eth_link *src = &(dev->data->dev_link);
347 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
348 *(uint64_t *)src) == 0)
355 * Atomically writes the link status information into global
356 * structure rte_eth_dev.
359 * - Pointer to the structure rte_eth_dev to read from.
360 * - Pointer to the buffer to be saved with the link status.
363 * - On success, zero.
364 * - On failure, negative value.
367 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
368 struct rte_eth_link *link)
370 struct rte_eth_link *dst = &(dev->data->dev_link);
371 struct rte_eth_link *src = link;
373 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
374 *(uint64_t *)src) == 0)
381 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
384 ixgbe_is_sfp(struct ixgbe_hw *hw)
386 switch (hw->phy.type) {
387 case ixgbe_phy_sfp_avago:
388 case ixgbe_phy_sfp_ftl:
389 case ixgbe_phy_sfp_intel:
390 case ixgbe_phy_sfp_unknown:
391 case ixgbe_phy_sfp_passive_tyco:
392 case ixgbe_phy_sfp_passive_unknown:
399 static inline int32_t
400 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
405 status = ixgbe_reset_hw(hw);
407 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
408 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
409 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
410 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
411 IXGBE_WRITE_FLUSH(hw);
417 ixgbe_enable_intr(struct rte_eth_dev *dev)
419 struct ixgbe_interrupt *intr =
420 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
421 struct ixgbe_hw *hw =
422 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
424 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
425 IXGBE_WRITE_FLUSH(hw);
429 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
432 ixgbe_disable_intr(struct ixgbe_hw *hw)
434 PMD_INIT_FUNC_TRACE();
436 if (hw->mac.type == ixgbe_mac_82598EB) {
437 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
439 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
440 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
441 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
443 IXGBE_WRITE_FLUSH(hw);
447 * This function resets queue statistics mapping registers.
448 * From Niantic datasheet, Initialization of Statistics section:
449 * "...if software requires the queue counters, the RQSMR and TQSM registers
450 * must be re-programmed following a device reset.
453 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
457 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
458 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
459 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
465 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
470 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
471 #define NB_QMAP_FIELDS_PER_QSM_REG 4
472 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
474 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
475 struct ixgbe_stat_mapping_registers *stat_mappings =
476 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
477 uint32_t qsmr_mask = 0;
478 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
482 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
485 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
486 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
488 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
489 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
490 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
493 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
495 /* Now clear any previous stat_idx set */
496 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
498 stat_mappings->tqsm[n] &= ~clearing_mask;
500 stat_mappings->rqsmr[n] &= ~clearing_mask;
502 q_map = (uint32_t)stat_idx;
503 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
504 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
506 stat_mappings->tqsm[n] |= qsmr_mask;
508 stat_mappings->rqsmr[n] |= qsmr_mask;
510 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
512 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
513 is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
515 /* Now write the mapping in the appropriate register */
517 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
518 stat_mappings->rqsmr[n], n);
519 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
522 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
523 stat_mappings->tqsm[n], n);
524 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
530 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
532 struct ixgbe_stat_mapping_registers *stat_mappings =
533 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
537 /* write whatever was in stat mapping table to the NIC */
538 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
540 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
543 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
548 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
551 struct ixgbe_dcb_tc_config *tc;
552 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
554 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
555 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
556 for (i = 0; i < dcb_max_tc; i++) {
557 tc = &dcb_config->tc_config[i];
558 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
559 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
560 (uint8_t)(100/dcb_max_tc + (i & 1));
561 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
562 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
563 (uint8_t)(100/dcb_max_tc + (i & 1));
564 tc->pfc = ixgbe_dcb_pfc_disabled;
567 /* Initialize default user to priority mapping, UPx->TC0 */
568 tc = &dcb_config->tc_config[0];
569 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
570 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
571 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
572 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
573 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
575 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
576 dcb_config->pfc_mode_enable = false;
577 dcb_config->vt_mode = true;
578 dcb_config->round_robin_enable = false;
579 /* support all DCB capabilities in 82599 */
580 dcb_config->support.capabilities = 0xFF;
582 /*we only support 4 Tcs for X540*/
583 if (hw->mac.type == ixgbe_mac_X540) {
584 dcb_config->num_tcs.pg_tcs = 4;
585 dcb_config->num_tcs.pfc_tcs = 4;
590 * Ensure that all locks are released before first NVM or PHY access
593 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
598 * Phy lock should not fail in this early stage. If this is the case,
599 * it is due to an improper exit of the application.
600 * So force the release of the faulty lock. Release of common lock
601 * is done automatically by swfw_sync function.
603 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
604 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
605 DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
607 ixgbe_release_swfw_semaphore(hw, mask);
610 * These ones are more tricky since they are common to all ports; but
611 * swfw_sync retries last long enough (1s) to be almost sure that if
612 * lock can not be taken it is due to an improper lock of the
615 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
616 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
617 DEBUGOUT("SWFW common locks released");
619 ixgbe_release_swfw_semaphore(hw, mask);
623 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
624 * It returns 0 on success.
627 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
628 struct rte_eth_dev *eth_dev)
630 struct rte_pci_device *pci_dev;
631 struct ixgbe_hw *hw =
632 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
633 struct ixgbe_vfta * shadow_vfta =
634 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
635 struct ixgbe_hwstrip *hwstrip =
636 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
637 struct ixgbe_dcb_config *dcb_config =
638 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
643 PMD_INIT_FUNC_TRACE();
645 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
646 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
647 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
649 /* for secondary processes, we don't initialise any further as primary
650 * has already done this work. Only check we don't need a different
652 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
653 if (eth_dev->data->scattered_rx)
654 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
657 pci_dev = eth_dev->pci_dev;
659 /* Vendor and Device ID need to be set before init of shared code */
660 hw->device_id = pci_dev->id.device_id;
661 hw->vendor_id = pci_dev->id.vendor_id;
662 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
663 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
664 hw->allow_unsupported_sfp = 1;
667 /* Initialize the shared code */
668 #ifdef RTE_NIC_BYPASS
669 diag = ixgbe_bypass_init_shared_code(hw);
671 diag = ixgbe_init_shared_code(hw);
672 #endif /* RTE_NIC_BYPASS */
674 if (diag != IXGBE_SUCCESS) {
675 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
679 /* pick up the PCI bus settings for reporting later */
680 ixgbe_get_bus_info(hw);
682 /* Unlock any pending hardware semaphore */
683 ixgbe_swfw_lock_reset(hw);
685 /* Initialize DCB configuration*/
686 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
687 ixgbe_dcb_init(hw,dcb_config);
688 /* Get Hardware Flow Control setting */
689 hw->fc.requested_mode = ixgbe_fc_full;
690 hw->fc.current_mode = ixgbe_fc_full;
691 hw->fc.pause_time = IXGBE_FC_PAUSE;
692 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
693 hw->fc.low_water[i] = IXGBE_FC_LO;
694 hw->fc.high_water[i] = IXGBE_FC_HI;
698 /* Make sure we have a good EEPROM before we read from it */
699 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
700 if (diag != IXGBE_SUCCESS) {
701 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
705 #ifdef RTE_NIC_BYPASS
706 diag = ixgbe_bypass_init_hw(hw);
708 diag = ixgbe_init_hw(hw);
709 #endif /* RTE_NIC_BYPASS */
712 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
713 * is called too soon after the kernel driver unbinding/binding occurs.
714 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
715 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
716 * also called. See ixgbe_identify_phy_82599(). The reason for the
717 * failure is not known, and only occuts when virtualisation features
718 * are disabled in the bios. A delay of 100ms was found to be enough by
719 * trial-and-error, and is doubled to be safe.
721 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
723 diag = ixgbe_init_hw(hw);
726 if (diag == IXGBE_ERR_EEPROM_VERSION) {
727 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
728 "LOM. Please be aware there may be issues associated "
729 "with your hardware.\n If you are experiencing problems "
730 "please contact your Intel or hardware representative "
731 "who provided you with this hardware.\n");
732 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
733 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
735 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
739 /* disable interrupt */
740 ixgbe_disable_intr(hw);
742 /* reset mappings for queue statistics hw counters*/
743 ixgbe_reset_qstat_mappings(hw);
745 /* Allocate memory for storing MAC addresses */
746 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
747 hw->mac.num_rar_entries, 0);
748 if (eth_dev->data->mac_addrs == NULL) {
750 "Failed to allocate %u bytes needed to store "
752 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
755 /* Copy the permanent MAC address */
756 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
757 ð_dev->data->mac_addrs[0]);
759 /* Allocate memory for storing hash filter MAC addresses */
760 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
761 IXGBE_VMDQ_NUM_UC_MAC, 0);
762 if (eth_dev->data->hash_mac_addrs == NULL) {
764 "Failed to allocate %d bytes needed to store MAC addresses",
765 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
769 /* initialize the vfta */
770 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
772 /* initialize the hw strip bitmap*/
773 memset(hwstrip, 0, sizeof(*hwstrip));
775 /* initialize PF if max_vfs not zero */
776 ixgbe_pf_host_init(eth_dev);
778 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
779 /* let hardware know driver is loaded */
780 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
781 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
782 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
783 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
784 IXGBE_WRITE_FLUSH(hw);
786 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
788 "MAC: %d, PHY: %d, SFP+: %d<n",
789 (int) hw->mac.type, (int) hw->phy.type,
790 (int) hw->phy.sfp_type);
792 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
793 (int) hw->mac.type, (int) hw->phy.type);
795 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
796 eth_dev->data->port_id, pci_dev->id.vendor_id,
797 pci_dev->id.device_id);
799 rte_intr_callback_register(&(pci_dev->intr_handle),
800 ixgbe_dev_interrupt_handler, (void *)eth_dev);
802 /* enable uio intr after callback register */
803 rte_intr_enable(&(pci_dev->intr_handle));
805 /* enable support intr */
806 ixgbe_enable_intr(eth_dev);
811 static void ixgbevf_get_queue_num(struct ixgbe_hw *hw)
813 /* Traffic classes are not supported by now */
814 unsigned int tcs, tc;
817 * Must let PF know we are at mailbox API version 1.1.
818 * Otherwise PF won't answer properly.
819 * In case that PF fails to provide Rx/Tx queue number,
820 * max_tx_queues and max_rx_queues remain to be 1.
822 if (!ixgbevf_negotiate_api_version(hw, ixgbe_mbox_api_11))
823 ixgbevf_get_queues(hw, &tcs, &tc);
827 * Virtual Function device init
830 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
831 struct rte_eth_dev *eth_dev)
833 struct rte_pci_device *pci_dev;
834 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
836 struct ixgbe_vfta * shadow_vfta =
837 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
838 struct ixgbe_hwstrip *hwstrip =
839 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
841 PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
843 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
844 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
845 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
847 /* for secondary processes, we don't initialise any further as primary
848 * has already done this work. Only check we don't need a different
850 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
851 if (eth_dev->data->scattered_rx)
852 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
856 pci_dev = eth_dev->pci_dev;
858 hw->device_id = pci_dev->id.device_id;
859 hw->vendor_id = pci_dev->id.vendor_id;
860 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
862 /* initialize the vfta */
863 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
865 /* initialize the hw strip bitmap*/
866 memset(hwstrip, 0, sizeof(*hwstrip));
868 /* Initialize the shared code */
869 diag = ixgbe_init_shared_code(hw);
870 if (diag != IXGBE_SUCCESS) {
871 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
875 /* init_mailbox_params */
876 hw->mbx.ops.init_params(hw);
878 /* Disable the interrupts for VF */
879 ixgbevf_intr_disable(hw);
881 hw->mac.num_rar_entries = hw->mac.max_rx_queues;
882 diag = hw->mac.ops.reset_hw(hw);
884 if (diag != IXGBE_SUCCESS) {
885 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
886 RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
887 "\tThe most likely cause of this error is that the VM host\n"
888 "\thas not assigned a valid MAC address to this VF device.\n"
889 "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
890 "\ta possible solution to this problem.\n");
894 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
895 ixgbevf_get_queue_num(hw);
897 /* Allocate memory for storing MAC addresses */
898 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
899 hw->mac.num_rar_entries, 0);
900 if (eth_dev->data->mac_addrs == NULL) {
902 "Failed to allocate %u bytes needed to store "
904 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
908 /* Copy the permanent MAC address */
909 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
910 ð_dev->data->mac_addrs[0]);
912 /* reset the hardware with the new settings */
913 diag = hw->mac.ops.start_hw(hw);
919 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
923 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
924 eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
925 "ixgbe_mac_82599_vf");
930 static struct eth_driver rte_ixgbe_pmd = {
932 .name = "rte_ixgbe_pmd",
933 .id_table = pci_id_ixgbe_map,
934 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
936 .eth_dev_init = eth_ixgbe_dev_init,
937 .dev_private_size = sizeof(struct ixgbe_adapter),
941 * virtual function driver struct
943 static struct eth_driver rte_ixgbevf_pmd = {
945 .name = "rte_ixgbevf_pmd",
946 .id_table = pci_id_ixgbevf_map,
947 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
949 .eth_dev_init = eth_ixgbevf_dev_init,
950 .dev_private_size = sizeof(struct ixgbe_adapter),
954 * Driver initialization routine.
955 * Invoked once at EAL init time.
956 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
959 rte_ixgbe_pmd_init(void)
961 PMD_INIT_FUNC_TRACE();
963 rte_eth_driver_register(&rte_ixgbe_pmd);
968 * VF Driver initialization routine.
969 * Invoked one at EAL init time.
970 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
973 rte_ixgbevf_pmd_init(void)
975 DEBUGFUNC("rte_ixgbevf_pmd_init");
977 rte_eth_driver_register(&rte_ixgbevf_pmd);
982 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
984 struct ixgbe_hw *hw =
985 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
986 struct ixgbe_vfta * shadow_vfta =
987 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
992 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
993 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
994 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
999 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1001 /* update local VFTA copy */
1002 shadow_vfta->vfta[vid_idx] = vfta;
1008 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1011 ixgbe_vlan_hw_strip_enable(dev, queue);
1013 ixgbe_vlan_hw_strip_disable(dev, queue);
1017 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1019 struct ixgbe_hw *hw =
1020 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022 /* Only the high 16-bits is valid */
1023 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1027 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1029 struct ixgbe_hw *hw =
1030 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1033 PMD_INIT_FUNC_TRACE();
1035 /* Filter Table Disable */
1036 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1037 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1039 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1043 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1045 struct ixgbe_hw *hw =
1046 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1047 struct ixgbe_vfta * shadow_vfta =
1048 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1052 PMD_INIT_FUNC_TRACE();
1054 /* Filter Table Enable */
1055 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1056 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1057 vlnctrl |= IXGBE_VLNCTRL_VFE;
1059 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1061 /* write whatever is in local vfta copy */
1062 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1063 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1067 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1069 struct ixgbe_hwstrip *hwstrip =
1070 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1072 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1076 IXGBE_SET_HWSTRIP(hwstrip, queue);
1078 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1082 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1084 struct ixgbe_hw *hw =
1085 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1088 PMD_INIT_FUNC_TRACE();
1090 if (hw->mac.type == ixgbe_mac_82598EB) {
1091 /* No queue level support */
1092 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1096 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1097 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1098 ctrl &= ~IXGBE_RXDCTL_VME;
1099 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1101 /* record those setting for HW strip per queue */
1102 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1106 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1108 struct ixgbe_hw *hw =
1109 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112 PMD_INIT_FUNC_TRACE();
1114 if (hw->mac.type == ixgbe_mac_82598EB) {
1115 /* No queue level supported */
1116 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1120 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1121 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1122 ctrl |= IXGBE_RXDCTL_VME;
1123 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1125 /* record those setting for HW strip per queue */
1126 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1130 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1132 struct ixgbe_hw *hw =
1133 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1137 PMD_INIT_FUNC_TRACE();
1139 if (hw->mac.type == ixgbe_mac_82598EB) {
1140 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1141 ctrl &= ~IXGBE_VLNCTRL_VME;
1142 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1145 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1146 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1147 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1148 ctrl &= ~IXGBE_RXDCTL_VME;
1149 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1151 /* record those setting for HW strip per queue */
1152 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1158 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1160 struct ixgbe_hw *hw =
1161 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1165 PMD_INIT_FUNC_TRACE();
1167 if (hw->mac.type == ixgbe_mac_82598EB) {
1168 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1169 ctrl |= IXGBE_VLNCTRL_VME;
1170 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1173 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1174 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1175 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1176 ctrl |= IXGBE_RXDCTL_VME;
1177 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1179 /* record those setting for HW strip per queue */
1180 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1186 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1188 struct ixgbe_hw *hw =
1189 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1192 PMD_INIT_FUNC_TRACE();
1194 /* DMATXCTRL: Geric Double VLAN Disable */
1195 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1196 ctrl &= ~IXGBE_DMATXCTL_GDV;
1197 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1199 /* CTRL_EXT: Global Double VLAN Disable */
1200 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1201 ctrl &= ~IXGBE_EXTENDED_VLAN;
1202 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1207 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1209 struct ixgbe_hw *hw =
1210 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1213 PMD_INIT_FUNC_TRACE();
1215 /* DMATXCTRL: Geric Double VLAN Enable */
1216 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1217 ctrl |= IXGBE_DMATXCTL_GDV;
1218 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1220 /* CTRL_EXT: Global Double VLAN Enable */
1221 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1222 ctrl |= IXGBE_EXTENDED_VLAN;
1223 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1226 * VET EXT field in the EXVET register = 0x8100 by default
1227 * So no need to change. Same to VT field of DMATXCTL register
1232 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1234 if(mask & ETH_VLAN_STRIP_MASK){
1235 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1236 ixgbe_vlan_hw_strip_enable_all(dev);
1238 ixgbe_vlan_hw_strip_disable_all(dev);
1241 if(mask & ETH_VLAN_FILTER_MASK){
1242 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1243 ixgbe_vlan_hw_filter_enable(dev);
1245 ixgbe_vlan_hw_filter_disable(dev);
1248 if(mask & ETH_VLAN_EXTEND_MASK){
1249 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1250 ixgbe_vlan_hw_extend_enable(dev);
1252 ixgbe_vlan_hw_extend_disable(dev);
1257 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1259 struct ixgbe_hw *hw =
1260 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1261 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1262 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1263 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1264 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1268 ixgbe_dev_configure(struct rte_eth_dev *dev)
1270 struct ixgbe_interrupt *intr =
1271 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1273 PMD_INIT_FUNC_TRACE();
1275 /* set flag to update link status after init */
1276 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1282 * Configure device link speed and setup link.
1283 * It returns 0 on success.
1286 ixgbe_dev_start(struct rte_eth_dev *dev)
1288 struct ixgbe_hw *hw =
1289 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1290 int err, link_up = 0, negotiate = 0;
1295 PMD_INIT_FUNC_TRACE();
1297 /* IXGBE devices don't support half duplex */
1298 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1299 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1300 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1301 dev->data->dev_conf.link_duplex,
1302 dev->data->port_id);
1307 hw->adapter_stopped = FALSE;
1308 ixgbe_stop_adapter(hw);
1310 /* reinitialize adapter
1311 * this calls reset and start */
1312 status = ixgbe_pf_reset_hw(hw);
1315 hw->mac.ops.start_hw(hw);
1317 /* configure PF module if SRIOV enabled */
1318 ixgbe_pf_host_configure(dev);
1320 /* initialize transmission unit */
1321 ixgbe_dev_tx_init(dev);
1323 /* This can fail when allocating mbufs for descriptor rings */
1324 err = ixgbe_dev_rx_init(dev);
1326 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1330 ixgbe_dev_rxtx_start(dev);
1332 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1333 err = hw->mac.ops.setup_sfp(hw);
1338 /* Turn on the laser */
1339 ixgbe_enable_tx_laser(hw);
1341 /* Skip link setup if loopback mode is enabled for 82599. */
1342 if (hw->mac.type == ixgbe_mac_82599EB &&
1343 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1344 goto skip_link_setup;
1346 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1349 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1353 switch(dev->data->dev_conf.link_speed) {
1354 case ETH_LINK_SPEED_AUTONEG:
1355 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1356 IXGBE_LINK_SPEED_82599_AUTONEG :
1357 IXGBE_LINK_SPEED_82598_AUTONEG;
1359 case ETH_LINK_SPEED_100:
1361 * Invalid for 82598 but error will be detected by
1362 * ixgbe_setup_link()
1364 speed = IXGBE_LINK_SPEED_100_FULL;
1366 case ETH_LINK_SPEED_1000:
1367 speed = IXGBE_LINK_SPEED_1GB_FULL;
1369 case ETH_LINK_SPEED_10000:
1370 speed = IXGBE_LINK_SPEED_10GB_FULL;
1373 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1374 dev->data->dev_conf.link_speed,
1375 dev->data->port_id);
1379 err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1385 /* check if lsc interrupt is enabled */
1386 if (dev->data->dev_conf.intr_conf.lsc != 0)
1387 ixgbe_dev_lsc_interrupt_setup(dev);
1389 /* resume enabled intr since hw reset */
1390 ixgbe_enable_intr(dev);
1392 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1393 ETH_VLAN_EXTEND_MASK;
1394 ixgbe_vlan_offload_set(dev, mask);
1396 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1397 /* Enable vlan filtering for VMDq */
1398 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1401 /* Configure DCB hw */
1402 ixgbe_configure_dcb(dev);
1404 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1405 err = ixgbe_fdir_configure(dev);
1410 ixgbe_restore_statistics_mapping(dev);
1415 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1416 ixgbe_dev_clear_queues(dev);
1421 * Stop device: disable rx and tx functions to allow for reconfiguring.
1424 ixgbe_dev_stop(struct rte_eth_dev *dev)
1426 struct rte_eth_link link;
1427 struct ixgbe_hw *hw =
1428 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429 struct ixgbe_vf_info *vfinfo =
1430 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1433 PMD_INIT_FUNC_TRACE();
1435 /* disable interrupts */
1436 ixgbe_disable_intr(hw);
1439 ixgbe_pf_reset_hw(hw);
1440 hw->adapter_stopped = FALSE;
1443 ixgbe_stop_adapter(hw);
1445 for (vf = 0; vfinfo != NULL &&
1446 vf < dev->pci_dev->max_vfs; vf++)
1447 vfinfo[vf].clear_to_send = false;
1449 /* Turn off the laser */
1450 ixgbe_disable_tx_laser(hw);
1452 ixgbe_dev_clear_queues(dev);
1454 /* Clear recorded link status */
1455 memset(&link, 0, sizeof(link));
1456 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1460 * Reest and stop device.
1463 ixgbe_dev_close(struct rte_eth_dev *dev)
1465 struct ixgbe_hw *hw =
1466 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1468 PMD_INIT_FUNC_TRACE();
1470 ixgbe_pf_reset_hw(hw);
1472 ixgbe_dev_stop(dev);
1473 hw->adapter_stopped = 1;
1475 ixgbe_disable_pcie_master(hw);
1477 /* reprogram the RAR[0] in case user changed it. */
1478 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1482 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1485 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1487 struct ixgbe_hw *hw =
1488 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489 struct ixgbe_hw_stats *hw_stats =
1490 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1491 uint32_t bprc, lxon, lxoff, total;
1492 uint64_t total_missed_rx, total_qbrc, total_qprc;
1495 total_missed_rx = 0;
1499 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1500 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1501 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1502 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1504 for (i = 0; i < 8; i++) {
1506 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1507 /* global total per queue */
1508 hw_stats->mpc[i] += mp;
1509 /* Running comprehensive total for stats display */
1510 total_missed_rx += hw_stats->mpc[i];
1511 if (hw->mac.type == ixgbe_mac_82598EB)
1512 hw_stats->rnbc[i] +=
1513 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1514 hw_stats->pxontxc[i] +=
1515 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1516 hw_stats->pxonrxc[i] +=
1517 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1518 hw_stats->pxofftxc[i] +=
1519 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1520 hw_stats->pxoffrxc[i] +=
1521 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1522 hw_stats->pxon2offc[i] +=
1523 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1525 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1526 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1527 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1528 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1529 hw_stats->qbrc[i] +=
1530 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1531 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1532 hw_stats->qbtc[i] +=
1533 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1534 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1536 total_qprc += hw_stats->qprc[i];
1537 total_qbrc += hw_stats->qbrc[i];
1539 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1540 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1541 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1543 /* Note that gprc counts missed packets */
1544 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1546 if (hw->mac.type != ixgbe_mac_82598EB) {
1547 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1548 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1549 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1550 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1551 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1552 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1553 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1554 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1556 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1557 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1558 /* 82598 only has a counter in the high register */
1559 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1560 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1561 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1565 * Workaround: mprc hardware is incorrectly counting
1566 * broadcasts, so for now we subtract those.
1568 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1569 hw_stats->bprc += bprc;
1570 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1571 if (hw->mac.type == ixgbe_mac_82598EB)
1572 hw_stats->mprc -= bprc;
1574 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1575 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1576 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1577 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1578 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1579 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1581 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1582 hw_stats->lxontxc += lxon;
1583 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1584 hw_stats->lxofftxc += lxoff;
1585 total = lxon + lxoff;
1587 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1588 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1589 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1590 hw_stats->gptc -= total;
1591 hw_stats->mptc -= total;
1592 hw_stats->ptc64 -= total;
1593 hw_stats->gotc -= total * ETHER_MIN_LEN;
1595 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1596 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1597 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1598 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1599 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1600 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1601 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1602 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1603 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1604 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1605 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1606 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1607 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1608 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1609 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1610 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1611 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1612 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1613 /* Only read FCOE on 82599 */
1614 if (hw->mac.type != ixgbe_mac_82598EB) {
1615 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1616 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1617 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1618 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1619 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1625 /* Fill out the rte_eth_stats statistics structure */
1626 stats->ipackets = total_qprc;
1627 stats->ibytes = total_qbrc;
1628 stats->opackets = hw_stats->gptc;
1629 stats->obytes = hw_stats->gotc;
1630 stats->imcasts = hw_stats->mprc;
1632 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1633 stats->q_ipackets[i] = hw_stats->qprc[i];
1634 stats->q_opackets[i] = hw_stats->qptc[i];
1635 stats->q_ibytes[i] = hw_stats->qbrc[i];
1636 stats->q_obytes[i] = hw_stats->qbtc[i];
1637 stats->q_errors[i] = hw_stats->qprdc[i];
1641 stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1646 /* XON/XOFF pause frames */
1647 stats->tx_pause_xon = hw_stats->lxontxc;
1648 stats->rx_pause_xon = hw_stats->lxonrxc;
1649 stats->tx_pause_xoff = hw_stats->lxofftxc;
1650 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1652 /* Flow Director Stats registers */
1653 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1654 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1655 stats->fdirmatch = hw_stats->fdirmatch;
1656 stats->fdirmiss = hw_stats->fdirmiss;
1660 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1662 struct ixgbe_hw_stats *stats =
1663 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1665 /* HW registers are cleared on read */
1666 ixgbe_dev_stats_get(dev, NULL);
1668 /* Reset software totals */
1669 memset(stats, 0, sizeof(*stats));
1673 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1675 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1677 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1679 /* Good Rx packet, include VF loopback */
1680 UPDATE_VF_STAT(IXGBE_VFGPRC,
1681 hw_stats->last_vfgprc, hw_stats->vfgprc);
1683 /* Good Rx octets, include VF loopback */
1684 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1685 hw_stats->last_vfgorc, hw_stats->vfgorc);
1687 /* Good Tx packet, include VF loopback */
1688 UPDATE_VF_STAT(IXGBE_VFGPTC,
1689 hw_stats->last_vfgptc, hw_stats->vfgptc);
1691 /* Good Tx octets, include VF loopback */
1692 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1693 hw_stats->last_vfgotc, hw_stats->vfgotc);
1695 /* Rx Multicst Packet */
1696 UPDATE_VF_STAT(IXGBE_VFMPRC,
1697 hw_stats->last_vfmprc, hw_stats->vfmprc);
1702 memset(stats, 0, sizeof(*stats));
1703 stats->ipackets = hw_stats->vfgprc;
1704 stats->ibytes = hw_stats->vfgorc;
1705 stats->opackets = hw_stats->vfgptc;
1706 stats->obytes = hw_stats->vfgotc;
1707 stats->imcasts = hw_stats->vfmprc;
1711 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1713 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1714 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1716 /* Sync HW register to the last stats */
1717 ixgbevf_dev_stats_get(dev, NULL);
1719 /* reset HW current stats*/
1720 hw_stats->vfgprc = 0;
1721 hw_stats->vfgorc = 0;
1722 hw_stats->vfgptc = 0;
1723 hw_stats->vfgotc = 0;
1724 hw_stats->vfmprc = 0;
1729 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1731 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1733 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1734 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1735 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1736 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1737 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1738 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1739 dev_info->max_vfs = dev->pci_dev->max_vfs;
1740 if (hw->mac.type == ixgbe_mac_82598EB)
1741 dev_info->max_vmdq_pools = ETH_16_POOLS;
1743 dev_info->max_vmdq_pools = ETH_64_POOLS;
1744 dev_info->rx_offload_capa =
1745 DEV_RX_OFFLOAD_VLAN_STRIP |
1746 DEV_RX_OFFLOAD_IPV4_CKSUM |
1747 DEV_RX_OFFLOAD_UDP_CKSUM |
1748 DEV_RX_OFFLOAD_TCP_CKSUM;
1749 dev_info->tx_offload_capa =
1750 DEV_TX_OFFLOAD_VLAN_INSERT |
1751 DEV_TX_OFFLOAD_IPV4_CKSUM |
1752 DEV_TX_OFFLOAD_UDP_CKSUM |
1753 DEV_TX_OFFLOAD_TCP_CKSUM |
1754 DEV_TX_OFFLOAD_SCTP_CKSUM;
1757 /* return 0 means link status changed, -1 means not changed */
1759 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1761 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1762 struct rte_eth_link link, old;
1763 ixgbe_link_speed link_speed;
1767 link.link_status = 0;
1768 link.link_speed = 0;
1769 link.link_duplex = 0;
1770 memset(&old, 0, sizeof(old));
1771 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1773 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1774 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1775 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1777 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1779 link.link_speed = ETH_LINK_SPEED_100;
1780 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1781 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1782 if (link.link_status == old.link_status)
1788 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1789 if (link.link_status == old.link_status)
1793 link.link_status = 1;
1794 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1796 switch (link_speed) {
1798 case IXGBE_LINK_SPEED_UNKNOWN:
1799 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1800 link.link_speed = ETH_LINK_SPEED_100;
1803 case IXGBE_LINK_SPEED_100_FULL:
1804 link.link_speed = ETH_LINK_SPEED_100;
1807 case IXGBE_LINK_SPEED_1GB_FULL:
1808 link.link_speed = ETH_LINK_SPEED_1000;
1811 case IXGBE_LINK_SPEED_10GB_FULL:
1812 link.link_speed = ETH_LINK_SPEED_10000;
1815 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1817 if (link.link_status == old.link_status)
1824 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1826 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1830 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1831 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1835 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1837 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1841 fctrl &= (~IXGBE_FCTRL_UPE);
1842 if (dev->data->all_multicast == 1)
1843 fctrl |= IXGBE_FCTRL_MPE;
1845 fctrl &= (~IXGBE_FCTRL_MPE);
1846 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1850 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1852 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1856 fctrl |= IXGBE_FCTRL_MPE;
1857 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1861 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1863 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1866 if (dev->data->promiscuous == 1)
1867 return; /* must remain in all_multicast mode */
1869 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1870 fctrl &= (~IXGBE_FCTRL_MPE);
1871 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1875 * It clears the interrupt causes and enables the interrupt.
1876 * It will be called once only during nic initialized.
1879 * Pointer to struct rte_eth_dev.
1882 * - On success, zero.
1883 * - On failure, a negative value.
1886 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1888 struct ixgbe_interrupt *intr =
1889 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1891 ixgbe_dev_link_status_print(dev);
1892 intr->mask |= IXGBE_EICR_LSC;
1898 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1901 * Pointer to struct rte_eth_dev.
1904 * - On success, zero.
1905 * - On failure, a negative value.
1908 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1911 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912 struct ixgbe_interrupt *intr =
1913 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1915 /* clear all cause mask */
1916 ixgbe_disable_intr(hw);
1918 /* read-on-clear nic registers here */
1919 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1920 PMD_DRV_LOG(INFO, "eicr %x", eicr);
1923 if (eicr & IXGBE_EICR_LSC) {
1924 /* set flag for async link update */
1925 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1928 if (eicr & IXGBE_EICR_MAILBOX)
1929 intr->flags |= IXGBE_FLAG_MAILBOX;
1935 * It gets and then prints the link status.
1938 * Pointer to struct rte_eth_dev.
1941 * - On success, zero.
1942 * - On failure, a negative value.
1945 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1947 struct rte_eth_link link;
1949 memset(&link, 0, sizeof(link));
1950 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1951 if (link.link_status) {
1952 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1953 (int)(dev->data->port_id),
1954 (unsigned)link.link_speed,
1955 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1956 "full-duplex" : "half-duplex");
1958 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1959 (int)(dev->data->port_id));
1961 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1962 dev->pci_dev->addr.domain,
1963 dev->pci_dev->addr.bus,
1964 dev->pci_dev->addr.devid,
1965 dev->pci_dev->addr.function);
1969 * It executes link_update after knowing an interrupt occured.
1972 * Pointer to struct rte_eth_dev.
1975 * - On success, zero.
1976 * - On failure, a negative value.
1979 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1981 struct ixgbe_interrupt *intr =
1982 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1984 struct rte_eth_link link;
1985 int intr_enable_delay = false;
1987 PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1989 if (intr->flags & IXGBE_FLAG_MAILBOX) {
1990 ixgbe_pf_mbx_process(dev);
1991 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1994 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1995 /* get the link status before link update, for predicting later */
1996 memset(&link, 0, sizeof(link));
1997 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1999 ixgbe_dev_link_update(dev, 0);
2002 if (!link.link_status)
2003 /* handle it 1 sec later, wait it being stable */
2004 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2005 /* likely to down */
2007 /* handle it 4 sec later, wait it being stable */
2008 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2010 ixgbe_dev_link_status_print(dev);
2012 intr_enable_delay = true;
2015 if (intr_enable_delay) {
2016 if (rte_eal_alarm_set(timeout * 1000,
2017 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2018 PMD_DRV_LOG(ERR, "Error setting alarm");
2020 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2021 ixgbe_enable_intr(dev);
2022 rte_intr_enable(&(dev->pci_dev->intr_handle));
2030 * Interrupt handler which shall be registered for alarm callback for delayed
2031 * handling specific interrupt to wait for the stable nic state. As the
2032 * NIC interrupt state is not stable for ixgbe after link is just down,
2033 * it needs to wait 4 seconds to get the stable status.
2036 * Pointer to interrupt handle.
2038 * The address of parameter (struct rte_eth_dev *) regsitered before.
2044 ixgbe_dev_interrupt_delayed_handler(void *param)
2046 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2047 struct ixgbe_interrupt *intr =
2048 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2049 struct ixgbe_hw *hw =
2050 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2054 if (eicr & IXGBE_EICR_MAILBOX)
2055 ixgbe_pf_mbx_process(dev);
2057 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2058 ixgbe_dev_link_update(dev, 0);
2059 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2060 ixgbe_dev_link_status_print(dev);
2061 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2064 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2065 ixgbe_enable_intr(dev);
2066 rte_intr_enable(&(dev->pci_dev->intr_handle));
2070 * Interrupt handler triggered by NIC for handling
2071 * specific interrupt.
2074 * Pointer to interrupt handle.
2076 * The address of parameter (struct rte_eth_dev *) regsitered before.
2082 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2085 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2086 ixgbe_dev_interrupt_get_status(dev);
2087 ixgbe_dev_interrupt_action(dev);
2091 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2093 struct ixgbe_hw *hw;
2095 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2100 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2102 struct ixgbe_hw *hw;
2104 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2109 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2111 struct ixgbe_hw *hw;
2113 uint32_t rx_buf_size;
2114 uint32_t max_high_water;
2116 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2123 PMD_INIT_FUNC_TRACE();
2125 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2127 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2130 * At least reserve one Ethernet frame for watermark
2131 * high_water/low_water in kilo bytes for ixgbe
2133 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2134 if ((fc_conf->high_water > max_high_water) ||
2135 (fc_conf->high_water < fc_conf->low_water)) {
2136 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2137 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2141 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2142 hw->fc.pause_time = fc_conf->pause_time;
2143 hw->fc.high_water[0] = fc_conf->high_water;
2144 hw->fc.low_water[0] = fc_conf->low_water;
2145 hw->fc.send_xon = fc_conf->send_xon;
2147 err = ixgbe_fc_enable(hw);
2149 /* Not negotiated is not an error case */
2150 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2152 /* check if we want to forward MAC frames - driver doesn't have native
2153 * capability to do that, so we'll write the registers ourselves */
2155 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2157 /* set or clear MFLCN.PMCF bit depending on configuration */
2158 if (fc_conf->mac_ctrl_frame_fwd != 0)
2159 mflcn |= IXGBE_MFLCN_PMCF;
2161 mflcn &= ~IXGBE_MFLCN_PMCF;
2163 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2164 IXGBE_WRITE_FLUSH(hw);
2169 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2174 * ixgbe_pfc_enable_generic - Enable flow control
2175 * @hw: pointer to hardware structure
2176 * @tc_num: traffic class number
2177 * Enable flow control according to the current settings.
2180 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2183 uint32_t mflcn_reg, fccfg_reg;
2185 uint32_t fcrtl, fcrth;
2189 /* Validate the water mark configuration */
2190 if (!hw->fc.pause_time) {
2191 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2195 /* Low water mark of zero causes XOFF floods */
2196 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2197 /* High/Low water can not be 0 */
2198 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2199 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2200 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2204 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2205 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2206 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2210 /* Negotiate the fc mode to use */
2211 ixgbe_fc_autoneg(hw);
2213 /* Disable any previous flow control settings */
2214 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2215 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2217 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2218 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2220 switch (hw->fc.current_mode) {
2223 * If the count of enabled RX Priority Flow control >1,
2224 * and the TX pause can not be disabled
2227 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2228 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2229 if (reg & IXGBE_FCRTH_FCEN)
2233 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2235 case ixgbe_fc_rx_pause:
2237 * Rx Flow control is enabled and Tx Flow control is
2238 * disabled by software override. Since there really
2239 * isn't a way to advertise that we are capable of RX
2240 * Pause ONLY, we will advertise that we support both
2241 * symmetric and asymmetric Rx PAUSE. Later, we will
2242 * disable the adapter's ability to send PAUSE frames.
2244 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2246 * If the count of enabled RX Priority Flow control >1,
2247 * and the TX pause can not be disabled
2250 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2251 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2252 if (reg & IXGBE_FCRTH_FCEN)
2256 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2258 case ixgbe_fc_tx_pause:
2260 * Tx Flow control is enabled, and Rx Flow control is
2261 * disabled by software override.
2263 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2266 /* Flow control (both Rx and Tx) is enabled by SW override. */
2267 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2268 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2271 DEBUGOUT("Flow control param set incorrectly\n");
2272 ret_val = IXGBE_ERR_CONFIG;
2277 /* Set 802.3x based flow control settings. */
2278 mflcn_reg |= IXGBE_MFLCN_DPF;
2279 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2280 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2282 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2283 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2284 hw->fc.high_water[tc_num]) {
2285 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2286 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2287 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2289 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2291 * In order to prevent Tx hangs when the internal Tx
2292 * switch is enabled we must set the high water mark
2293 * to the maximum FCRTH value. This allows the Tx
2294 * switch to function even under heavy Rx workloads.
2296 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2298 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2300 /* Configure pause time (2 TCs per register) */
2301 reg = hw->fc.pause_time * 0x00010001;
2302 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2303 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2305 /* Configure flow control refresh threshold value */
2306 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2313 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2315 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2318 if(hw->mac.type != ixgbe_mac_82598EB) {
2319 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2325 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2328 uint32_t rx_buf_size;
2329 uint32_t max_high_water;
2331 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2332 struct ixgbe_hw *hw =
2333 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2334 struct ixgbe_dcb_config *dcb_config =
2335 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2337 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2344 PMD_INIT_FUNC_TRACE();
2346 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2347 tc_num = map[pfc_conf->priority];
2348 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2349 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2351 * At least reserve one Ethernet frame for watermark
2352 * high_water/low_water in kilo bytes for ixgbe
2354 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2355 if ((pfc_conf->fc.high_water > max_high_water) ||
2356 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2357 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2358 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2362 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2363 hw->fc.pause_time = pfc_conf->fc.pause_time;
2364 hw->fc.send_xon = pfc_conf->fc.send_xon;
2365 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2366 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2368 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2370 /* Not negotiated is not an error case */
2371 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2374 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2379 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2380 struct rte_eth_rss_reta *reta_conf)
2384 struct ixgbe_hw *hw =
2385 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387 PMD_INIT_FUNC_TRACE();
2389 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2390 * 128-entries in 32 registers
2392 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2393 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2394 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2396 mask = (uint8_t)((reta_conf->mask_hi >>
2397 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2401 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2403 for (j = 0; j < 4; j++) {
2404 if (mask & (0x1 << j)) {
2406 reta &= ~(0xFF << 8 * j);
2407 reta |= reta_conf->reta[i + j] << 8*j;
2410 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2418 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2419 struct rte_eth_rss_reta *reta_conf)
2423 struct ixgbe_hw *hw =
2424 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426 PMD_INIT_FUNC_TRACE();
2428 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2429 * 128-entries in 32 registers
2431 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2432 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2433 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2435 mask = (uint8_t)((reta_conf->mask_hi >>
2436 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2439 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2440 for (j = 0; j < 4; j++) {
2441 if (mask & (0x1 << j))
2442 reta_conf->reta[i + j] =
2443 (uint8_t)((reta >> 8 * j) & 0xFF);
2452 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2453 uint32_t index, uint32_t pool)
2455 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456 uint32_t enable_addr = 1;
2458 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2462 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2464 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466 ixgbe_clear_rar(hw, index);
2470 * Virtual Function operations
2473 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2475 PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2477 /* Clear interrupt mask to stop from interrupts being generated */
2478 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2480 IXGBE_WRITE_FLUSH(hw);
2484 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2486 struct rte_eth_conf* conf = &dev->data->dev_conf;
2488 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2489 dev->data->port_id);
2492 * VF has no ability to enable/disable HW CRC
2493 * Keep the persistent behavior the same as Host PF
2495 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2496 if (!conf->rxmode.hw_strip_crc) {
2497 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2498 conf->rxmode.hw_strip_crc = 1;
2501 if (conf->rxmode.hw_strip_crc) {
2502 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2503 conf->rxmode.hw_strip_crc = 0;
2511 ixgbevf_dev_start(struct rte_eth_dev *dev)
2513 struct ixgbe_hw *hw =
2514 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2517 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2519 hw->mac.ops.reset_hw(hw);
2521 ixgbevf_dev_tx_init(dev);
2523 /* This can fail when allocating mbufs for descriptor rings */
2524 err = ixgbevf_dev_rx_init(dev);
2526 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2527 ixgbe_dev_clear_queues(dev);
2532 ixgbevf_set_vfta_all(dev,1);
2535 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2536 ETH_VLAN_EXTEND_MASK;
2537 ixgbevf_vlan_offload_set(dev, mask);
2539 ixgbevf_dev_rxtx_start(dev);
2545 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2547 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2551 hw->adapter_stopped = TRUE;
2552 ixgbe_stop_adapter(hw);
2555 * Clear what we set, but we still keep shadow_vfta to
2556 * restore after device starts
2558 ixgbevf_set_vfta_all(dev,0);
2560 ixgbe_dev_clear_queues(dev);
2564 ixgbevf_dev_close(struct rte_eth_dev *dev)
2566 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2568 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2572 ixgbevf_dev_stop(dev);
2574 /* reprogram the RAR[0] in case user changed it. */
2575 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2578 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2580 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581 struct ixgbe_vfta * shadow_vfta =
2582 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2583 int i = 0, j = 0, vfta = 0, mask = 1;
2585 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2586 vfta = shadow_vfta->vfta[i];
2589 for (j = 0; j < 32; j++){
2591 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2600 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2602 struct ixgbe_hw *hw =
2603 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2604 struct ixgbe_vfta * shadow_vfta =
2605 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2606 uint32_t vid_idx = 0;
2607 uint32_t vid_bit = 0;
2610 PMD_INIT_FUNC_TRACE();
2612 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2613 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2615 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2618 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2619 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2621 /* Save what we set and retore it after device reset */
2623 shadow_vfta->vfta[vid_idx] |= vid_bit;
2625 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2631 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2633 struct ixgbe_hw *hw =
2634 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2637 PMD_INIT_FUNC_TRACE();
2639 if(queue >= hw->mac.max_rx_queues)
2642 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2644 ctrl |= IXGBE_RXDCTL_VME;
2646 ctrl &= ~IXGBE_RXDCTL_VME;
2647 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2649 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2653 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2655 struct ixgbe_hw *hw =
2656 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660 /* VF function only support hw strip feature, others are not support */
2661 if(mask & ETH_VLAN_STRIP_MASK){
2662 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2664 for(i=0; i < hw->mac.max_rx_queues; i++)
2665 ixgbevf_vlan_strip_queue_set(dev,i,on);
2670 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2674 /* we only need to do this if VMDq is enabled */
2675 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2676 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2677 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2685 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2687 uint32_t vector = 0;
2688 switch (hw->mac.mc_filter_type) {
2689 case 0: /* use bits [47:36] of the address */
2690 vector = ((uc_addr->addr_bytes[4] >> 4) |
2691 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2693 case 1: /* use bits [46:35] of the address */
2694 vector = ((uc_addr->addr_bytes[4] >> 3) |
2695 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2697 case 2: /* use bits [45:34] of the address */
2698 vector = ((uc_addr->addr_bytes[4] >> 2) |
2699 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2701 case 3: /* use bits [43:32] of the address */
2702 vector = ((uc_addr->addr_bytes[4]) |
2703 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2705 default: /* Invalid mc_filter_type */
2709 /* vector can only be 12-bits or boundary will be exceeded */
2715 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2723 const uint32_t ixgbe_uta_idx_mask = 0x7F;
2724 const uint32_t ixgbe_uta_bit_shift = 5;
2725 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2726 const uint32_t bit1 = 0x1;
2728 struct ixgbe_hw *hw =
2729 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730 struct ixgbe_uta_info *uta_info =
2731 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2733 /* The UTA table only exists on 82599 hardware and newer */
2734 if (hw->mac.type < ixgbe_mac_82599EB)
2737 vector = ixgbe_uta_vector(hw,mac_addr);
2738 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2739 uta_shift = vector & ixgbe_uta_bit_mask;
2741 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2745 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2747 uta_info->uta_in_use++;
2748 reg_val |= (bit1 << uta_shift);
2749 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2751 uta_info->uta_in_use--;
2752 reg_val &= ~(bit1 << uta_shift);
2753 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2756 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2758 if (uta_info->uta_in_use > 0)
2759 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2760 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2762 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2768 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2771 struct ixgbe_hw *hw =
2772 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2773 struct ixgbe_uta_info *uta_info =
2774 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2776 /* The UTA table only exists on 82599 hardware and newer */
2777 if (hw->mac.type < ixgbe_mac_82599EB)
2781 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2782 uta_info->uta_shadow[i] = ~0;
2783 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2786 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2787 uta_info->uta_shadow[i] = 0;
2788 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2795 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2796 uint16_t rx_mask, uint8_t on)
2800 struct ixgbe_hw *hw =
2801 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2802 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2804 if (hw->mac.type == ixgbe_mac_82598EB) {
2805 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2806 " on 82599 hardware and newer\n");
2809 if (ixgbe_vmdq_mode_check(hw) < 0)
2812 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2813 val |= IXGBE_VMOLR_AUPE;
2814 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2815 val |= IXGBE_VMOLR_ROMPE;
2816 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2817 val |= IXGBE_VMOLR_ROPE;
2818 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2819 val |= IXGBE_VMOLR_BAM;
2820 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2821 val |= IXGBE_VMOLR_MPE;
2828 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2834 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2838 const uint8_t bit1 = 0x1;
2840 struct ixgbe_hw *hw =
2841 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843 if (ixgbe_vmdq_mode_check(hw) < 0)
2846 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2847 reg = IXGBE_READ_REG(hw, addr);
2855 IXGBE_WRITE_REG(hw, addr,reg);
2861 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2865 const uint8_t bit1 = 0x1;
2867 struct ixgbe_hw *hw =
2868 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870 if (ixgbe_vmdq_mode_check(hw) < 0)
2873 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2874 reg = IXGBE_READ_REG(hw, addr);
2882 IXGBE_WRITE_REG(hw, addr,reg);
2888 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2889 uint64_t pool_mask, uint8_t vlan_on)
2893 struct ixgbe_hw *hw =
2894 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896 if (ixgbe_vmdq_mode_check(hw) < 0)
2898 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2899 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2900 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2909 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2910 struct rte_eth_vmdq_mirror_conf *mirror_conf,
2911 uint8_t rule_id, uint8_t on)
2913 uint32_t mr_ctl,vlvf;
2914 uint32_t mp_lsb = 0;
2915 uint32_t mv_msb = 0;
2916 uint32_t mv_lsb = 0;
2917 uint32_t mp_msb = 0;
2920 uint64_t vlan_mask = 0;
2922 const uint8_t pool_mask_offset = 32;
2923 const uint8_t vlan_mask_offset = 32;
2924 const uint8_t dst_pool_offset = 8;
2925 const uint8_t rule_mr_offset = 4;
2926 const uint8_t mirror_rule_mask= 0x0F;
2928 struct ixgbe_mirror_info *mr_info =
2929 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2930 struct ixgbe_hw *hw =
2931 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2933 if (ixgbe_vmdq_mode_check(hw) < 0)
2936 /* Check if vlan mask is valid */
2937 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2938 if (mirror_conf->vlan.vlan_mask == 0)
2942 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2943 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2944 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2945 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2946 /* search vlan id related pool vlan filter index */
2947 reg_index = ixgbe_find_vlvf_slot(hw,
2948 mirror_conf->vlan.vlan_id[i]);
2951 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2952 if ((vlvf & IXGBE_VLVF_VIEN) &&
2953 ((vlvf & IXGBE_VLVF_VLANID_MASK)
2954 == mirror_conf->vlan.vlan_id[i]))
2955 vlan_mask |= (1ULL << reg_index);
2962 mv_lsb = vlan_mask & 0xFFFFFFFF;
2963 mv_msb = vlan_mask >> vlan_mask_offset;
2965 mr_info->mr_conf[rule_id].vlan.vlan_mask =
2966 mirror_conf->vlan.vlan_mask;
2967 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2968 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2969 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2970 mirror_conf->vlan.vlan_id[i];
2975 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
2976 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
2977 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
2982 * if enable pool mirror, write related pool mask register,if disable
2983 * pool mirror, clear PFMRVM register
2985 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2987 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
2988 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
2989 mr_info->mr_conf[rule_id].pool_mask =
2990 mirror_conf->pool_mask;
2995 mr_info->mr_conf[rule_id].pool_mask = 0;
2999 /* read mirror control register and recalculate it */
3000 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3003 mr_ctl |= mirror_conf->rule_type_mask;
3004 mr_ctl &= mirror_rule_mask;
3005 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3007 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3009 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3010 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3012 /* write mirrror control register */
3013 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3015 /* write pool mirrror control register */
3016 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3017 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3018 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3021 /* write VLAN mirrror control register */
3022 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3023 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3024 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3032 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3035 uint32_t lsb_val = 0;
3036 uint32_t msb_val = 0;
3037 const uint8_t rule_mr_offset = 4;
3039 struct ixgbe_hw *hw =
3040 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3041 struct ixgbe_mirror_info *mr_info =
3042 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3044 if (ixgbe_vmdq_mode_check(hw) < 0)
3047 memset(&mr_info->mr_conf[rule_id], 0,
3048 sizeof(struct rte_eth_vmdq_mirror_conf));
3050 /* clear PFVMCTL register */
3051 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3053 /* clear pool mask register */
3054 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3055 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3057 /* clear vlan mask register */
3058 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3059 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);