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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
65 #include "ixgbe_logs.h"
66 #include "ixgbe/ixgbe_api.h"
67 #include "ixgbe/ixgbe_vf.h"
68 #include "ixgbe/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
74 * High threshold controlling when to start sending XOFF frames. Must be at
75 * least 8 bytes less than receive packet buffer size. This value is in units
78 #define IXGBE_FC_HI 0x80
81 * Low threshold controlling when to start sending XON frames. This value is
82 * in units of 1024 bytes.
84 #define IXGBE_FC_LO 0x40
86 /* Timer value included in XOFF frames. */
87 #define IXGBE_FC_PAUSE 0x680
89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
90 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
91 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
93 #define IXGBE_MMW_SIZE_DEFAULT 0x4
94 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
97 * Default values for RX/TX configuration
99 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
100 #define IXGBE_DEFAULT_RX_PTHRESH 8
101 #define IXGBE_DEFAULT_RX_HTHRESH 8
102 #define IXGBE_DEFAULT_RX_WTHRESH 0
104 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
105 #define IXGBE_DEFAULT_TX_PTHRESH 32
106 #define IXGBE_DEFAULT_TX_HTHRESH 0
107 #define IXGBE_DEFAULT_TX_WTHRESH 0
108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
110 /* Bit shift and mask */
111 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
112 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
113 #define IXGBE_8_BIT_WIDTH CHAR_BIT
114 #define IXGBE_8_BIT_MASK UINT8_MAX
116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
121 struct rte_eth_dev *eth_dev);
122 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
123 static int ixgbe_dev_start(struct rte_eth_dev *dev);
124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
125 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
126 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
133 int wait_to_complete);
134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
135 struct rte_eth_stats *stats);
136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
142 struct rte_eth_dev_info *dev_info);
143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
144 struct rte_eth_dev_info *dev_info);
145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
148 uint16_t vlan_id, int on);
149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
151 uint16_t queue, bool on);
152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
163 struct rte_eth_fc_conf *fc_conf);
164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
165 struct rte_eth_fc_conf *fc_conf);
166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
167 struct rte_eth_pfc_conf *pfc_conf);
168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
169 struct rte_eth_rss_reta_entry64 *reta_conf,
171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
172 struct rte_eth_rss_reta_entry64 *reta_conf,
174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
182 uint32_t index, uint32_t pool);
183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
186 /* For Virtual Function support */
187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
188 struct rte_eth_dev *eth_dev);
189 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
190 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
195 struct rte_eth_stats *stats);
196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
198 uint16_t vlan_id, int on);
199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
200 uint16_t queue, int on);
201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
204 /* For Eth VMDQ APIs support */
205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
206 ether_addr* mac_addr,uint8_t on);
207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
208 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
209 uint16_t rx_mask, uint8_t on);
210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
213 uint64_t pool_mask,uint8_t vlan_on);
214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
215 struct rte_eth_vmdq_mirror_conf *mirror_conf,
216 uint8_t rule_id, uint8_t on);
217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
221 uint16_t queue_idx, uint16_t tx_rate);
222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
223 uint16_t tx_rate, uint64_t q_msk);
225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
226 struct ether_addr *mac_addr,
227 uint32_t index, uint32_t pool);
228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
229 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
230 struct rte_eth_syn_filter *filter,
232 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
233 struct rte_eth_syn_filter *filter);
234 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
235 enum rte_filter_op filter_op,
237 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
238 struct ixgbe_5tuple_filter *filter);
239 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
240 struct ixgbe_5tuple_filter *filter);
241 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
242 struct rte_eth_ntuple_filter *filter,
244 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
245 enum rte_filter_op filter_op,
247 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
248 struct rte_eth_ntuple_filter *filter);
249 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
250 struct rte_eth_ethertype_filter *filter,
252 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
253 enum rte_filter_op filter_op,
255 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
256 struct rte_eth_ethertype_filter *filter);
257 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
258 enum rte_filter_type filter_type,
259 enum rte_filter_op filter_op,
261 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
264 * Define VF Stats MACRO for Non "cleared on read" register
266 #define UPDATE_VF_STAT(reg, last, cur) \
268 u32 latest = IXGBE_READ_REG(hw, reg); \
269 cur += latest - last; \
273 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
275 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
276 u64 new_msb = IXGBE_READ_REG(hw, msb); \
277 u64 latest = ((new_msb << 32) | new_lsb); \
278 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
282 #define IXGBE_SET_HWSTRIP(h, q) do{\
283 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
284 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
285 (h)->bitmap[idx] |= 1 << bit;\
288 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
289 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
290 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
291 (h)->bitmap[idx] &= ~(1 << bit);\
294 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
295 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
296 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
297 (r) = (h)->bitmap[idx] >> bit & 1;\
301 * The set of PCI devices this driver supports
303 static struct rte_pci_id pci_id_ixgbe_map[] = {
305 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
306 #include "rte_pci_dev_ids.h"
308 { .vendor_id = 0, /* sentinel */ },
313 * The set of PCI devices this driver supports (for 82599 VF)
315 static struct rte_pci_id pci_id_ixgbevf_map[] = {
317 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
318 #include "rte_pci_dev_ids.h"
319 { .vendor_id = 0, /* sentinel */ },
323 static struct eth_dev_ops ixgbe_eth_dev_ops = {
324 .dev_configure = ixgbe_dev_configure,
325 .dev_start = ixgbe_dev_start,
326 .dev_stop = ixgbe_dev_stop,
327 .dev_set_link_up = ixgbe_dev_set_link_up,
328 .dev_set_link_down = ixgbe_dev_set_link_down,
329 .dev_close = ixgbe_dev_close,
330 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
331 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
332 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
333 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
334 .link_update = ixgbe_dev_link_update,
335 .stats_get = ixgbe_dev_stats_get,
336 .stats_reset = ixgbe_dev_stats_reset,
337 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
338 .dev_infos_get = ixgbe_dev_info_get,
339 .mtu_set = ixgbe_dev_mtu_set,
340 .vlan_filter_set = ixgbe_vlan_filter_set,
341 .vlan_tpid_set = ixgbe_vlan_tpid_set,
342 .vlan_offload_set = ixgbe_vlan_offload_set,
343 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
344 .rx_queue_start = ixgbe_dev_rx_queue_start,
345 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
346 .tx_queue_start = ixgbe_dev_tx_queue_start,
347 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
348 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
349 .rx_queue_release = ixgbe_dev_rx_queue_release,
350 .rx_queue_count = ixgbe_dev_rx_queue_count,
351 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
352 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
353 .tx_queue_release = ixgbe_dev_tx_queue_release,
354 .dev_led_on = ixgbe_dev_led_on,
355 .dev_led_off = ixgbe_dev_led_off,
356 .flow_ctrl_get = ixgbe_flow_ctrl_get,
357 .flow_ctrl_set = ixgbe_flow_ctrl_set,
358 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
359 .mac_addr_add = ixgbe_add_rar,
360 .mac_addr_remove = ixgbe_remove_rar,
361 .uc_hash_table_set = ixgbe_uc_hash_table_set,
362 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
363 .mirror_rule_set = ixgbe_mirror_rule_set,
364 .mirror_rule_reset = ixgbe_mirror_rule_reset,
365 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
366 .set_vf_rx = ixgbe_set_pool_rx,
367 .set_vf_tx = ixgbe_set_pool_tx,
368 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
369 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
370 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
371 .reta_update = ixgbe_dev_rss_reta_update,
372 .reta_query = ixgbe_dev_rss_reta_query,
373 #ifdef RTE_NIC_BYPASS
374 .bypass_init = ixgbe_bypass_init,
375 .bypass_state_set = ixgbe_bypass_state_store,
376 .bypass_state_show = ixgbe_bypass_state_show,
377 .bypass_event_set = ixgbe_bypass_event_store,
378 .bypass_event_show = ixgbe_bypass_event_show,
379 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
380 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
381 .bypass_ver_show = ixgbe_bypass_ver_show,
382 .bypass_wd_reset = ixgbe_bypass_wd_reset,
383 #endif /* RTE_NIC_BYPASS */
384 .rss_hash_update = ixgbe_dev_rss_hash_update,
385 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
386 .filter_ctrl = ixgbe_dev_filter_ctrl,
390 * dev_ops for virtual function, bare necessities for basic vf
391 * operation have been implemented
393 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
395 .dev_configure = ixgbevf_dev_configure,
396 .dev_start = ixgbevf_dev_start,
397 .dev_stop = ixgbevf_dev_stop,
398 .link_update = ixgbe_dev_link_update,
399 .stats_get = ixgbevf_dev_stats_get,
400 .stats_reset = ixgbevf_dev_stats_reset,
401 .dev_close = ixgbevf_dev_close,
402 .dev_infos_get = ixgbevf_dev_info_get,
403 .mtu_set = ixgbevf_dev_set_mtu,
404 .vlan_filter_set = ixgbevf_vlan_filter_set,
405 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
406 .vlan_offload_set = ixgbevf_vlan_offload_set,
407 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
408 .rx_queue_release = ixgbe_dev_rx_queue_release,
409 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
410 .tx_queue_release = ixgbe_dev_tx_queue_release,
411 .mac_addr_add = ixgbevf_add_mac_addr,
412 .mac_addr_remove = ixgbevf_remove_mac_addr,
416 * Atomically reads the link status information from global
417 * structure rte_eth_dev.
420 * - Pointer to the structure rte_eth_dev to read from.
421 * - Pointer to the buffer to be saved with the link status.
424 * - On success, zero.
425 * - On failure, negative value.
428 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
429 struct rte_eth_link *link)
431 struct rte_eth_link *dst = link;
432 struct rte_eth_link *src = &(dev->data->dev_link);
434 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
435 *(uint64_t *)src) == 0)
442 * Atomically writes the link status information into global
443 * structure rte_eth_dev.
446 * - Pointer to the structure rte_eth_dev to read from.
447 * - Pointer to the buffer to be saved with the link status.
450 * - On success, zero.
451 * - On failure, negative value.
454 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
455 struct rte_eth_link *link)
457 struct rte_eth_link *dst = &(dev->data->dev_link);
458 struct rte_eth_link *src = link;
460 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
461 *(uint64_t *)src) == 0)
468 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
471 ixgbe_is_sfp(struct ixgbe_hw *hw)
473 switch (hw->phy.type) {
474 case ixgbe_phy_sfp_avago:
475 case ixgbe_phy_sfp_ftl:
476 case ixgbe_phy_sfp_intel:
477 case ixgbe_phy_sfp_unknown:
478 case ixgbe_phy_sfp_passive_tyco:
479 case ixgbe_phy_sfp_passive_unknown:
486 static inline int32_t
487 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
492 status = ixgbe_reset_hw(hw);
494 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
495 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
496 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
497 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
498 IXGBE_WRITE_FLUSH(hw);
504 ixgbe_enable_intr(struct rte_eth_dev *dev)
506 struct ixgbe_interrupt *intr =
507 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
508 struct ixgbe_hw *hw =
509 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
511 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
512 IXGBE_WRITE_FLUSH(hw);
516 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
519 ixgbe_disable_intr(struct ixgbe_hw *hw)
521 PMD_INIT_FUNC_TRACE();
523 if (hw->mac.type == ixgbe_mac_82598EB) {
524 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
526 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
527 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
528 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
530 IXGBE_WRITE_FLUSH(hw);
534 * This function resets queue statistics mapping registers.
535 * From Niantic datasheet, Initialization of Statistics section:
536 * "...if software requires the queue counters, the RQSMR and TQSM registers
537 * must be re-programmed following a device reset.
540 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
544 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
545 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
546 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
552 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
557 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
558 #define NB_QMAP_FIELDS_PER_QSM_REG 4
559 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
561 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
562 struct ixgbe_stat_mapping_registers *stat_mappings =
563 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
564 uint32_t qsmr_mask = 0;
565 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
569 if ((hw->mac.type != ixgbe_mac_82599EB) &&
570 (hw->mac.type != ixgbe_mac_X540) &&
571 (hw->mac.type != ixgbe_mac_X550) &&
572 (hw->mac.type != ixgbe_mac_X550EM_x))
575 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
576 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
579 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
580 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
581 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
584 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
586 /* Now clear any previous stat_idx set */
587 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
589 stat_mappings->tqsm[n] &= ~clearing_mask;
591 stat_mappings->rqsmr[n] &= ~clearing_mask;
593 q_map = (uint32_t)stat_idx;
594 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
595 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
597 stat_mappings->tqsm[n] |= qsmr_mask;
599 stat_mappings->rqsmr[n] |= qsmr_mask;
601 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
602 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
604 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
605 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
607 /* Now write the mapping in the appropriate register */
609 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
610 stat_mappings->rqsmr[n], n);
611 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
614 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
615 stat_mappings->tqsm[n], n);
616 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
622 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
624 struct ixgbe_stat_mapping_registers *stat_mappings =
625 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
626 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
629 /* write whatever was in stat mapping table to the NIC */
630 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
632 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
635 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
640 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
643 struct ixgbe_dcb_tc_config *tc;
644 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
646 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
647 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
648 for (i = 0; i < dcb_max_tc; i++) {
649 tc = &dcb_config->tc_config[i];
650 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
651 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
652 (uint8_t)(100/dcb_max_tc + (i & 1));
653 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
654 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
655 (uint8_t)(100/dcb_max_tc + (i & 1));
656 tc->pfc = ixgbe_dcb_pfc_disabled;
659 /* Initialize default user to priority mapping, UPx->TC0 */
660 tc = &dcb_config->tc_config[0];
661 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
662 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
663 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
664 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
665 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
667 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
668 dcb_config->pfc_mode_enable = false;
669 dcb_config->vt_mode = true;
670 dcb_config->round_robin_enable = false;
671 /* support all DCB capabilities in 82599 */
672 dcb_config->support.capabilities = 0xFF;
674 /*we only support 4 Tcs for X540, X550 */
675 if (hw->mac.type == ixgbe_mac_X540 ||
676 hw->mac.type == ixgbe_mac_X550 ||
677 hw->mac.type == ixgbe_mac_X550EM_x) {
678 dcb_config->num_tcs.pg_tcs = 4;
679 dcb_config->num_tcs.pfc_tcs = 4;
684 * Ensure that all locks are released before first NVM or PHY access
687 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
692 * Phy lock should not fail in this early stage. If this is the case,
693 * it is due to an improper exit of the application.
694 * So force the release of the faulty lock. Release of common lock
695 * is done automatically by swfw_sync function.
697 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
698 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
699 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
701 ixgbe_release_swfw_semaphore(hw, mask);
704 * These ones are more tricky since they are common to all ports; but
705 * swfw_sync retries last long enough (1s) to be almost sure that if
706 * lock can not be taken it is due to an improper lock of the
709 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
710 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
711 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
713 ixgbe_release_swfw_semaphore(hw, mask);
717 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
718 * It returns 0 on success.
721 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
722 struct rte_eth_dev *eth_dev)
724 struct rte_pci_device *pci_dev;
725 struct ixgbe_hw *hw =
726 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
727 struct ixgbe_vfta * shadow_vfta =
728 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
729 struct ixgbe_hwstrip *hwstrip =
730 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
731 struct ixgbe_dcb_config *dcb_config =
732 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
733 struct ixgbe_filter_info *filter_info =
734 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
739 PMD_INIT_FUNC_TRACE();
741 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
742 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
743 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
746 * For secondary processes, we don't initialise any further as primary
747 * has already done this work. Only check we don't need a different
748 * RX and TX function.
750 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
751 struct igb_tx_queue *txq;
752 /* TX queue function in primary, set by last queue initialized
753 * Tx queue may not initialized by primary process */
754 if (eth_dev->data->tx_queues) {
755 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
756 set_tx_function(eth_dev, txq);
758 /* Use default TX function if we get here */
759 PMD_INIT_LOG(INFO, "No TX queues configured yet. "
760 "Using default TX function.");
763 if (eth_dev->data->scattered_rx)
764 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
767 pci_dev = eth_dev->pci_dev;
769 /* Vendor and Device ID need to be set before init of shared code */
770 hw->device_id = pci_dev->id.device_id;
771 hw->vendor_id = pci_dev->id.vendor_id;
772 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
773 hw->allow_unsupported_sfp = 1;
775 /* Initialize the shared code (base driver) */
776 #ifdef RTE_NIC_BYPASS
777 diag = ixgbe_bypass_init_shared_code(hw);
779 diag = ixgbe_init_shared_code(hw);
780 #endif /* RTE_NIC_BYPASS */
782 if (diag != IXGBE_SUCCESS) {
783 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
787 /* pick up the PCI bus settings for reporting later */
788 ixgbe_get_bus_info(hw);
790 /* Unlock any pending hardware semaphore */
791 ixgbe_swfw_lock_reset(hw);
793 /* Initialize DCB configuration*/
794 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
795 ixgbe_dcb_init(hw,dcb_config);
796 /* Get Hardware Flow Control setting */
797 hw->fc.requested_mode = ixgbe_fc_full;
798 hw->fc.current_mode = ixgbe_fc_full;
799 hw->fc.pause_time = IXGBE_FC_PAUSE;
800 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
801 hw->fc.low_water[i] = IXGBE_FC_LO;
802 hw->fc.high_water[i] = IXGBE_FC_HI;
806 /* Make sure we have a good EEPROM before we read from it */
807 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
808 if (diag != IXGBE_SUCCESS) {
809 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
813 #ifdef RTE_NIC_BYPASS
814 diag = ixgbe_bypass_init_hw(hw);
816 diag = ixgbe_init_hw(hw);
817 #endif /* RTE_NIC_BYPASS */
820 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
821 * is called too soon after the kernel driver unbinding/binding occurs.
822 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
823 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
824 * also called. See ixgbe_identify_phy_82599(). The reason for the
825 * failure is not known, and only occuts when virtualisation features
826 * are disabled in the bios. A delay of 100ms was found to be enough by
827 * trial-and-error, and is doubled to be safe.
829 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
831 diag = ixgbe_init_hw(hw);
834 if (diag == IXGBE_ERR_EEPROM_VERSION) {
835 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
836 "LOM. Please be aware there may be issues associated "
837 "with your hardware.");
838 PMD_INIT_LOG(ERR, "If you are experiencing problems "
839 "please contact your Intel or hardware representative "
840 "who provided you with this hardware.");
841 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
842 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
844 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
848 /* disable interrupt */
849 ixgbe_disable_intr(hw);
851 /* reset mappings for queue statistics hw counters*/
852 ixgbe_reset_qstat_mappings(hw);
854 /* Allocate memory for storing MAC addresses */
855 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
856 hw->mac.num_rar_entries, 0);
857 if (eth_dev->data->mac_addrs == NULL) {
859 "Failed to allocate %u bytes needed to store "
861 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
864 /* Copy the permanent MAC address */
865 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
866 ð_dev->data->mac_addrs[0]);
868 /* Allocate memory for storing hash filter MAC addresses */
869 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
870 IXGBE_VMDQ_NUM_UC_MAC, 0);
871 if (eth_dev->data->hash_mac_addrs == NULL) {
873 "Failed to allocate %d bytes needed to store MAC addresses",
874 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
878 /* initialize the vfta */
879 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
881 /* initialize the hw strip bitmap*/
882 memset(hwstrip, 0, sizeof(*hwstrip));
884 /* initialize PF if max_vfs not zero */
885 ixgbe_pf_host_init(eth_dev);
887 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
888 /* let hardware know driver is loaded */
889 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
890 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
891 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
892 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
893 IXGBE_WRITE_FLUSH(hw);
895 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
896 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
897 (int) hw->mac.type, (int) hw->phy.type,
898 (int) hw->phy.sfp_type);
900 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
901 (int) hw->mac.type, (int) hw->phy.type);
903 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
904 eth_dev->data->port_id, pci_dev->id.vendor_id,
905 pci_dev->id.device_id);
907 rte_intr_callback_register(&(pci_dev->intr_handle),
908 ixgbe_dev_interrupt_handler, (void *)eth_dev);
910 /* enable uio intr after callback register */
911 rte_intr_enable(&(pci_dev->intr_handle));
913 /* enable support intr */
914 ixgbe_enable_intr(eth_dev);
916 /* initialize 5tuple filter list */
917 TAILQ_INIT(&filter_info->fivetuple_list);
918 memset(filter_info->fivetuple_mask, 0,
919 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
926 * Negotiate mailbox API version with the PF.
927 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
928 * Then we try to negotiate starting with the most recent one.
929 * If all negotiation attempts fail, then we will proceed with
930 * the default one (ixgbe_mbox_api_10).
933 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
937 /* start with highest supported, proceed down */
938 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
944 i != RTE_DIM(sup_ver) &&
945 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
951 generate_random_mac_addr(struct ether_addr *mac_addr)
955 /* Set Organizationally Unique Identifier (OUI) prefix. */
956 mac_addr->addr_bytes[0] = 0x00;
957 mac_addr->addr_bytes[1] = 0x09;
958 mac_addr->addr_bytes[2] = 0xC0;
959 /* Force indication of locally assigned MAC address. */
960 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
961 /* Generate the last 3 bytes of the MAC address with a random number. */
963 memcpy(&mac_addr->addr_bytes[3], &random, 3);
967 * Virtual Function device init
970 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
971 struct rte_eth_dev *eth_dev)
975 struct rte_pci_device *pci_dev;
976 struct ixgbe_hw *hw =
977 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
978 struct ixgbe_vfta * shadow_vfta =
979 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
980 struct ixgbe_hwstrip *hwstrip =
981 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
982 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
984 PMD_INIT_FUNC_TRACE();
986 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
987 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
988 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
990 /* for secondary processes, we don't initialise any further as primary
991 * has already done this work. Only check we don't need a different
993 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
994 if (eth_dev->data->scattered_rx)
995 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
999 pci_dev = eth_dev->pci_dev;
1001 hw->device_id = pci_dev->id.device_id;
1002 hw->vendor_id = pci_dev->id.vendor_id;
1003 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1005 /* initialize the vfta */
1006 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1008 /* initialize the hw strip bitmap*/
1009 memset(hwstrip, 0, sizeof(*hwstrip));
1011 /* Initialize the shared code (base driver) */
1012 diag = ixgbe_init_shared_code(hw);
1013 if (diag != IXGBE_SUCCESS) {
1014 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1018 /* init_mailbox_params */
1019 hw->mbx.ops.init_params(hw);
1021 /* Disable the interrupts for VF */
1022 ixgbevf_intr_disable(hw);
1024 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1025 diag = hw->mac.ops.reset_hw(hw);
1028 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1029 * the underlying PF driver has not assigned a MAC address to the VF.
1030 * In this case, assign a random MAC address.
1032 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1033 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1037 /* negotiate mailbox API version to use with the PF. */
1038 ixgbevf_negotiate_api(hw);
1040 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1041 ixgbevf_get_queues(hw, &tcs, &tc);
1043 /* Allocate memory for storing MAC addresses */
1044 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1045 hw->mac.num_rar_entries, 0);
1046 if (eth_dev->data->mac_addrs == NULL) {
1048 "Failed to allocate %u bytes needed to store "
1050 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1054 /* Generate a random MAC address, if none was assigned by PF. */
1055 if (is_zero_ether_addr(perm_addr)) {
1056 generate_random_mac_addr(perm_addr);
1057 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1059 rte_free(eth_dev->data->mac_addrs);
1060 eth_dev->data->mac_addrs = NULL;
1063 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1064 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1065 "%02x:%02x:%02x:%02x:%02x:%02x",
1066 perm_addr->addr_bytes[0],
1067 perm_addr->addr_bytes[1],
1068 perm_addr->addr_bytes[2],
1069 perm_addr->addr_bytes[3],
1070 perm_addr->addr_bytes[4],
1071 perm_addr->addr_bytes[5]);
1074 /* Copy the permanent MAC address */
1075 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1077 /* reset the hardware with the new settings */
1078 diag = hw->mac.ops.start_hw(hw);
1084 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1088 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1089 eth_dev->data->port_id, pci_dev->id.vendor_id,
1090 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1095 static struct eth_driver rte_ixgbe_pmd = {
1097 .name = "rte_ixgbe_pmd",
1098 .id_table = pci_id_ixgbe_map,
1099 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1101 .eth_dev_init = eth_ixgbe_dev_init,
1102 .dev_private_size = sizeof(struct ixgbe_adapter),
1106 * virtual function driver struct
1108 static struct eth_driver rte_ixgbevf_pmd = {
1110 .name = "rte_ixgbevf_pmd",
1111 .id_table = pci_id_ixgbevf_map,
1112 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1114 .eth_dev_init = eth_ixgbevf_dev_init,
1115 .dev_private_size = sizeof(struct ixgbe_adapter),
1119 * Driver initialization routine.
1120 * Invoked once at EAL init time.
1121 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1124 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1126 PMD_INIT_FUNC_TRACE();
1128 rte_eth_driver_register(&rte_ixgbe_pmd);
1133 * VF Driver initialization routine.
1134 * Invoked one at EAL init time.
1135 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1138 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1140 PMD_INIT_FUNC_TRACE();
1142 rte_eth_driver_register(&rte_ixgbevf_pmd);
1147 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1149 struct ixgbe_hw *hw =
1150 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1151 struct ixgbe_vfta * shadow_vfta =
1152 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1157 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1158 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1159 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1164 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1166 /* update local VFTA copy */
1167 shadow_vfta->vfta[vid_idx] = vfta;
1173 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1176 ixgbe_vlan_hw_strip_enable(dev, queue);
1178 ixgbe_vlan_hw_strip_disable(dev, queue);
1182 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1184 struct ixgbe_hw *hw =
1185 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1187 /* Only the high 16-bits is valid */
1188 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1192 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1194 struct ixgbe_hw *hw =
1195 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1198 PMD_INIT_FUNC_TRACE();
1200 /* Filter Table Disable */
1201 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1202 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1204 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1208 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1210 struct ixgbe_hw *hw =
1211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212 struct ixgbe_vfta * shadow_vfta =
1213 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1217 PMD_INIT_FUNC_TRACE();
1219 /* Filter Table Enable */
1220 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1221 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1222 vlnctrl |= IXGBE_VLNCTRL_VFE;
1224 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1226 /* write whatever is in local vfta copy */
1227 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1228 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1232 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1234 struct ixgbe_hwstrip *hwstrip =
1235 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1237 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1241 IXGBE_SET_HWSTRIP(hwstrip, queue);
1243 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1247 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1249 struct ixgbe_hw *hw =
1250 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1253 PMD_INIT_FUNC_TRACE();
1255 if (hw->mac.type == ixgbe_mac_82598EB) {
1256 /* No queue level support */
1257 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1261 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1262 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1263 ctrl &= ~IXGBE_RXDCTL_VME;
1264 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1266 /* record those setting for HW strip per queue */
1267 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1271 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1273 struct ixgbe_hw *hw =
1274 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1277 PMD_INIT_FUNC_TRACE();
1279 if (hw->mac.type == ixgbe_mac_82598EB) {
1280 /* No queue level supported */
1281 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1285 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1286 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1287 ctrl |= IXGBE_RXDCTL_VME;
1288 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1290 /* record those setting for HW strip per queue */
1291 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1295 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1297 struct ixgbe_hw *hw =
1298 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1302 PMD_INIT_FUNC_TRACE();
1304 if (hw->mac.type == ixgbe_mac_82598EB) {
1305 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1306 ctrl &= ~IXGBE_VLNCTRL_VME;
1307 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1310 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1311 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1312 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1313 ctrl &= ~IXGBE_RXDCTL_VME;
1314 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1316 /* record those setting for HW strip per queue */
1317 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1323 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1325 struct ixgbe_hw *hw =
1326 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1330 PMD_INIT_FUNC_TRACE();
1332 if (hw->mac.type == ixgbe_mac_82598EB) {
1333 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1334 ctrl |= IXGBE_VLNCTRL_VME;
1335 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1338 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1339 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1340 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1341 ctrl |= IXGBE_RXDCTL_VME;
1342 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1344 /* record those setting for HW strip per queue */
1345 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1351 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1353 struct ixgbe_hw *hw =
1354 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1357 PMD_INIT_FUNC_TRACE();
1359 /* DMATXCTRL: Geric Double VLAN Disable */
1360 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1361 ctrl &= ~IXGBE_DMATXCTL_GDV;
1362 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1364 /* CTRL_EXT: Global Double VLAN Disable */
1365 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1366 ctrl &= ~IXGBE_EXTENDED_VLAN;
1367 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1372 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1374 struct ixgbe_hw *hw =
1375 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378 PMD_INIT_FUNC_TRACE();
1380 /* DMATXCTRL: Geric Double VLAN Enable */
1381 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1382 ctrl |= IXGBE_DMATXCTL_GDV;
1383 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1385 /* CTRL_EXT: Global Double VLAN Enable */
1386 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1387 ctrl |= IXGBE_EXTENDED_VLAN;
1388 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1391 * VET EXT field in the EXVET register = 0x8100 by default
1392 * So no need to change. Same to VT field of DMATXCTL register
1397 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1399 if(mask & ETH_VLAN_STRIP_MASK){
1400 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1401 ixgbe_vlan_hw_strip_enable_all(dev);
1403 ixgbe_vlan_hw_strip_disable_all(dev);
1406 if(mask & ETH_VLAN_FILTER_MASK){
1407 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1408 ixgbe_vlan_hw_filter_enable(dev);
1410 ixgbe_vlan_hw_filter_disable(dev);
1413 if(mask & ETH_VLAN_EXTEND_MASK){
1414 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1415 ixgbe_vlan_hw_extend_enable(dev);
1417 ixgbe_vlan_hw_extend_disable(dev);
1422 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1424 struct ixgbe_hw *hw =
1425 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1427 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1428 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1429 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1433 ixgbe_dev_configure(struct rte_eth_dev *dev)
1435 struct ixgbe_interrupt *intr =
1436 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1438 PMD_INIT_FUNC_TRACE();
1440 /* set flag to update link status after init */
1441 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1447 * Configure device link speed and setup link.
1448 * It returns 0 on success.
1451 ixgbe_dev_start(struct rte_eth_dev *dev)
1453 struct ixgbe_hw *hw =
1454 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1455 struct ixgbe_vf_info *vfinfo =
1456 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1457 int err, link_up = 0, negotiate = 0;
1463 PMD_INIT_FUNC_TRACE();
1465 /* IXGBE devices don't support half duplex */
1466 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1467 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1468 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1469 dev->data->dev_conf.link_duplex,
1470 dev->data->port_id);
1475 hw->adapter_stopped = FALSE;
1476 ixgbe_stop_adapter(hw);
1478 /* reinitialize adapter
1479 * this calls reset and start */
1480 status = ixgbe_pf_reset_hw(hw);
1483 hw->mac.ops.start_hw(hw);
1484 hw->mac.get_link_status = true;
1486 /* configure PF module if SRIOV enabled */
1487 ixgbe_pf_host_configure(dev);
1489 /* initialize transmission unit */
1490 ixgbe_dev_tx_init(dev);
1492 /* This can fail when allocating mbufs for descriptor rings */
1493 err = ixgbe_dev_rx_init(dev);
1495 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1499 err = ixgbe_dev_rxtx_start(dev);
1501 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1505 /* Skip link setup if loopback mode is enabled for 82599. */
1506 if (hw->mac.type == ixgbe_mac_82599EB &&
1507 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1508 goto skip_link_setup;
1510 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1511 err = hw->mac.ops.setup_sfp(hw);
1516 /* Turn on the laser */
1517 ixgbe_enable_tx_laser(hw);
1519 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1522 dev->data->dev_link.link_status = link_up;
1524 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1528 switch(dev->data->dev_conf.link_speed) {
1529 case ETH_LINK_SPEED_AUTONEG:
1530 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1531 IXGBE_LINK_SPEED_82599_AUTONEG :
1532 IXGBE_LINK_SPEED_82598_AUTONEG;
1534 case ETH_LINK_SPEED_100:
1536 * Invalid for 82598 but error will be detected by
1537 * ixgbe_setup_link()
1539 speed = IXGBE_LINK_SPEED_100_FULL;
1541 case ETH_LINK_SPEED_1000:
1542 speed = IXGBE_LINK_SPEED_1GB_FULL;
1544 case ETH_LINK_SPEED_10000:
1545 speed = IXGBE_LINK_SPEED_10GB_FULL;
1548 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1549 dev->data->dev_conf.link_speed,
1550 dev->data->port_id);
1554 err = ixgbe_setup_link(hw, speed, link_up);
1560 /* check if lsc interrupt is enabled */
1561 if (dev->data->dev_conf.intr_conf.lsc != 0)
1562 ixgbe_dev_lsc_interrupt_setup(dev);
1564 /* resume enabled intr since hw reset */
1565 ixgbe_enable_intr(dev);
1567 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1568 ETH_VLAN_EXTEND_MASK;
1569 ixgbe_vlan_offload_set(dev, mask);
1571 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1572 /* Enable vlan filtering for VMDq */
1573 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1576 /* Configure DCB hw */
1577 ixgbe_configure_dcb(dev);
1579 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1580 err = ixgbe_fdir_configure(dev);
1585 /* Restore vf rate limit */
1586 if (vfinfo != NULL) {
1587 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1588 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1589 if (vfinfo[vf].tx_rate[idx] != 0)
1590 ixgbe_set_vf_rate_limit(dev, vf,
1591 vfinfo[vf].tx_rate[idx],
1595 ixgbe_restore_statistics_mapping(dev);
1600 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1601 ixgbe_dev_clear_queues(dev);
1606 * Stop device: disable rx and tx functions to allow for reconfiguring.
1609 ixgbe_dev_stop(struct rte_eth_dev *dev)
1611 struct rte_eth_link link;
1612 struct ixgbe_hw *hw =
1613 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614 struct ixgbe_vf_info *vfinfo =
1615 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1616 struct ixgbe_filter_info *filter_info =
1617 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1618 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1621 PMD_INIT_FUNC_TRACE();
1623 /* disable interrupts */
1624 ixgbe_disable_intr(hw);
1627 ixgbe_pf_reset_hw(hw);
1628 hw->adapter_stopped = FALSE;
1631 ixgbe_stop_adapter(hw);
1633 for (vf = 0; vfinfo != NULL &&
1634 vf < dev->pci_dev->max_vfs; vf++)
1635 vfinfo[vf].clear_to_send = false;
1637 /* Turn off the laser */
1638 ixgbe_disable_tx_laser(hw);
1640 ixgbe_dev_clear_queues(dev);
1642 /* Clear stored conf */
1643 dev->data->scattered_rx = 0;
1645 /* Clear recorded link status */
1646 memset(&link, 0, sizeof(link));
1647 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1649 /* Remove all ntuple filters of the device */
1650 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1651 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1652 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1653 TAILQ_REMOVE(&filter_info->fivetuple_list,
1657 memset(filter_info->fivetuple_mask, 0,
1658 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1663 * Set device link up: enable tx laser.
1666 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1668 struct ixgbe_hw *hw =
1669 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670 if (hw->mac.type == ixgbe_mac_82599EB) {
1671 #ifdef RTE_NIC_BYPASS
1672 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1673 /* Not suported in bypass mode */
1674 PMD_INIT_LOG(ERR, "Set link up is not supported "
1675 "by device id 0x%x", hw->device_id);
1679 /* Turn on the laser */
1680 ixgbe_enable_tx_laser(hw);
1684 PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1690 * Set device link down: disable tx laser.
1693 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1695 struct ixgbe_hw *hw =
1696 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697 if (hw->mac.type == ixgbe_mac_82599EB) {
1698 #ifdef RTE_NIC_BYPASS
1699 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1700 /* Not suported in bypass mode */
1701 PMD_INIT_LOG(ERR, "Set link down is not supported "
1702 "by device id 0x%x", hw->device_id);
1706 /* Turn off the laser */
1707 ixgbe_disable_tx_laser(hw);
1711 PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1717 * Reest and stop device.
1720 ixgbe_dev_close(struct rte_eth_dev *dev)
1722 struct ixgbe_hw *hw =
1723 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725 PMD_INIT_FUNC_TRACE();
1727 ixgbe_pf_reset_hw(hw);
1729 ixgbe_dev_stop(dev);
1730 hw->adapter_stopped = 1;
1732 ixgbe_disable_pcie_master(hw);
1734 /* reprogram the RAR[0] in case user changed it. */
1735 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1739 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1742 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1744 struct ixgbe_hw *hw =
1745 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746 struct ixgbe_hw_stats *hw_stats =
1747 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1748 uint32_t bprc, lxon, lxoff, total;
1749 uint64_t total_missed_rx, total_qbrc, total_qprc;
1752 total_missed_rx = 0;
1756 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1757 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1758 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1759 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1761 for (i = 0; i < 8; i++) {
1763 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1764 /* global total per queue */
1765 hw_stats->mpc[i] += mp;
1766 /* Running comprehensive total for stats display */
1767 total_missed_rx += hw_stats->mpc[i];
1768 if (hw->mac.type == ixgbe_mac_82598EB)
1769 hw_stats->rnbc[i] +=
1770 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1771 hw_stats->pxontxc[i] +=
1772 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1773 hw_stats->pxonrxc[i] +=
1774 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1775 hw_stats->pxofftxc[i] +=
1776 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1777 hw_stats->pxoffrxc[i] +=
1778 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1779 hw_stats->pxon2offc[i] +=
1780 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1782 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1783 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1784 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1785 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1786 hw_stats->qbrc[i] +=
1787 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1788 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1789 hw_stats->qbtc[i] +=
1790 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1791 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1793 total_qprc += hw_stats->qprc[i];
1794 total_qbrc += hw_stats->qbrc[i];
1796 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1797 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1798 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1800 /* Note that gprc counts missed packets */
1801 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1803 if (hw->mac.type != ixgbe_mac_82598EB) {
1804 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1805 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1806 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1807 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1808 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1809 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1810 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1811 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1813 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1814 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1815 /* 82598 only has a counter in the high register */
1816 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1817 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1818 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1822 * Workaround: mprc hardware is incorrectly counting
1823 * broadcasts, so for now we subtract those.
1825 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1826 hw_stats->bprc += bprc;
1827 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1828 if (hw->mac.type == ixgbe_mac_82598EB)
1829 hw_stats->mprc -= bprc;
1831 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1832 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1833 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1834 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1835 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1836 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1838 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1839 hw_stats->lxontxc += lxon;
1840 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1841 hw_stats->lxofftxc += lxoff;
1842 total = lxon + lxoff;
1844 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1845 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1846 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1847 hw_stats->gptc -= total;
1848 hw_stats->mptc -= total;
1849 hw_stats->ptc64 -= total;
1850 hw_stats->gotc -= total * ETHER_MIN_LEN;
1852 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1853 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1854 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1855 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1856 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1857 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1858 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1859 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1860 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1861 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1862 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1863 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1864 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1865 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1866 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1867 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1868 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1869 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1870 /* Only read FCOE on 82599 */
1871 if (hw->mac.type != ixgbe_mac_82598EB) {
1872 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1873 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1874 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1875 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1876 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1882 /* Fill out the rte_eth_stats statistics structure */
1883 stats->ipackets = total_qprc;
1884 stats->ibytes = total_qbrc;
1885 stats->opackets = hw_stats->gptc;
1886 stats->obytes = hw_stats->gotc;
1887 stats->imcasts = hw_stats->mprc;
1889 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1890 stats->q_ipackets[i] = hw_stats->qprc[i];
1891 stats->q_opackets[i] = hw_stats->qptc[i];
1892 stats->q_ibytes[i] = hw_stats->qbrc[i];
1893 stats->q_obytes[i] = hw_stats->qbtc[i];
1894 stats->q_errors[i] = hw_stats->qprdc[i];
1898 stats->ibadcrc = hw_stats->crcerrs;
1899 stats->ibadlen = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1900 stats->imissed = total_missed_rx;
1901 stats->ierrors = stats->ibadcrc +
1904 hw_stats->illerrc + hw_stats->errbc;
1909 /* XON/XOFF pause frames */
1910 stats->tx_pause_xon = hw_stats->lxontxc;
1911 stats->rx_pause_xon = hw_stats->lxonrxc;
1912 stats->tx_pause_xoff = hw_stats->lxofftxc;
1913 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1915 /* Flow Director Stats registers */
1916 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1917 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1918 stats->fdirmatch = hw_stats->fdirmatch;
1919 stats->fdirmiss = hw_stats->fdirmiss;
1923 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1925 struct ixgbe_hw_stats *stats =
1926 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1928 /* HW registers are cleared on read */
1929 ixgbe_dev_stats_get(dev, NULL);
1931 /* Reset software totals */
1932 memset(stats, 0, sizeof(*stats));
1936 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1940 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1942 /* Good Rx packet, include VF loopback */
1943 UPDATE_VF_STAT(IXGBE_VFGPRC,
1944 hw_stats->last_vfgprc, hw_stats->vfgprc);
1946 /* Good Rx octets, include VF loopback */
1947 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1948 hw_stats->last_vfgorc, hw_stats->vfgorc);
1950 /* Good Tx packet, include VF loopback */
1951 UPDATE_VF_STAT(IXGBE_VFGPTC,
1952 hw_stats->last_vfgptc, hw_stats->vfgptc);
1954 /* Good Tx octets, include VF loopback */
1955 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1956 hw_stats->last_vfgotc, hw_stats->vfgotc);
1958 /* Rx Multicst Packet */
1959 UPDATE_VF_STAT(IXGBE_VFMPRC,
1960 hw_stats->last_vfmprc, hw_stats->vfmprc);
1965 stats->ipackets = hw_stats->vfgprc;
1966 stats->ibytes = hw_stats->vfgorc;
1967 stats->opackets = hw_stats->vfgptc;
1968 stats->obytes = hw_stats->vfgotc;
1969 stats->imcasts = hw_stats->vfmprc;
1973 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1975 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1976 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1978 /* Sync HW register to the last stats */
1979 ixgbevf_dev_stats_get(dev, NULL);
1981 /* reset HW current stats*/
1982 hw_stats->vfgprc = 0;
1983 hw_stats->vfgorc = 0;
1984 hw_stats->vfgptc = 0;
1985 hw_stats->vfgotc = 0;
1986 hw_stats->vfmprc = 0;
1991 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1993 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1995 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1996 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1997 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1998 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1999 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2000 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2001 dev_info->max_vfs = dev->pci_dev->max_vfs;
2002 if (hw->mac.type == ixgbe_mac_82598EB)
2003 dev_info->max_vmdq_pools = ETH_16_POOLS;
2005 dev_info->max_vmdq_pools = ETH_64_POOLS;
2006 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2007 dev_info->rx_offload_capa =
2008 DEV_RX_OFFLOAD_VLAN_STRIP |
2009 DEV_RX_OFFLOAD_IPV4_CKSUM |
2010 DEV_RX_OFFLOAD_UDP_CKSUM |
2011 DEV_RX_OFFLOAD_TCP_CKSUM;
2012 dev_info->tx_offload_capa =
2013 DEV_TX_OFFLOAD_VLAN_INSERT |
2014 DEV_TX_OFFLOAD_IPV4_CKSUM |
2015 DEV_TX_OFFLOAD_UDP_CKSUM |
2016 DEV_TX_OFFLOAD_TCP_CKSUM |
2017 DEV_TX_OFFLOAD_SCTP_CKSUM |
2018 DEV_TX_OFFLOAD_TCP_TSO;
2020 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2022 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2023 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2024 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2026 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2030 dev_info->default_txconf = (struct rte_eth_txconf) {
2032 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2033 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2034 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2036 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2037 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2038 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2039 ETH_TXQ_FLAGS_NOOFFLOADS,
2041 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2045 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2046 struct rte_eth_dev_info *dev_info)
2048 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2051 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2052 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2053 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2054 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2055 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2056 dev_info->max_vfs = dev->pci_dev->max_vfs;
2057 if (hw->mac.type == ixgbe_mac_82598EB)
2058 dev_info->max_vmdq_pools = ETH_16_POOLS;
2060 dev_info->max_vmdq_pools = ETH_64_POOLS;
2061 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2062 DEV_RX_OFFLOAD_IPV4_CKSUM |
2063 DEV_RX_OFFLOAD_UDP_CKSUM |
2064 DEV_RX_OFFLOAD_TCP_CKSUM;
2065 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2066 DEV_TX_OFFLOAD_IPV4_CKSUM |
2067 DEV_TX_OFFLOAD_UDP_CKSUM |
2068 DEV_TX_OFFLOAD_TCP_CKSUM |
2069 DEV_TX_OFFLOAD_SCTP_CKSUM;
2071 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2073 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2074 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2075 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2077 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2081 dev_info->default_txconf = (struct rte_eth_txconf) {
2083 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2084 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2085 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2087 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2088 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2089 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2090 ETH_TXQ_FLAGS_NOOFFLOADS,
2094 /* return 0 means link status changed, -1 means not changed */
2096 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2098 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099 struct rte_eth_link link, old;
2100 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2104 link.link_status = 0;
2105 link.link_speed = 0;
2106 link.link_duplex = 0;
2107 memset(&old, 0, sizeof(old));
2108 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2110 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2111 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2112 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2114 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2116 link.link_speed = ETH_LINK_SPEED_100;
2117 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2118 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2119 if (link.link_status == old.link_status)
2124 if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2125 !hw->mac.get_link_status) {
2126 memcpy(&link, &old, sizeof(link));
2131 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2132 if (link.link_status == old.link_status)
2136 link.link_status = 1;
2137 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2139 switch (link_speed) {
2141 case IXGBE_LINK_SPEED_UNKNOWN:
2142 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2143 link.link_speed = ETH_LINK_SPEED_100;
2146 case IXGBE_LINK_SPEED_100_FULL:
2147 link.link_speed = ETH_LINK_SPEED_100;
2150 case IXGBE_LINK_SPEED_1GB_FULL:
2151 link.link_speed = ETH_LINK_SPEED_1000;
2154 case IXGBE_LINK_SPEED_10GB_FULL:
2155 link.link_speed = ETH_LINK_SPEED_10000;
2158 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2160 if (link.link_status == old.link_status)
2167 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2169 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2172 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2173 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2174 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2178 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2180 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2184 fctrl &= (~IXGBE_FCTRL_UPE);
2185 if (dev->data->all_multicast == 1)
2186 fctrl |= IXGBE_FCTRL_MPE;
2188 fctrl &= (~IXGBE_FCTRL_MPE);
2189 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2193 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2195 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2199 fctrl |= IXGBE_FCTRL_MPE;
2200 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2204 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2206 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2209 if (dev->data->promiscuous == 1)
2210 return; /* must remain in all_multicast mode */
2212 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2213 fctrl &= (~IXGBE_FCTRL_MPE);
2214 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2218 * It clears the interrupt causes and enables the interrupt.
2219 * It will be called once only during nic initialized.
2222 * Pointer to struct rte_eth_dev.
2225 * - On success, zero.
2226 * - On failure, a negative value.
2229 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2231 struct ixgbe_interrupt *intr =
2232 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2234 ixgbe_dev_link_status_print(dev);
2235 intr->mask |= IXGBE_EICR_LSC;
2241 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2244 * Pointer to struct rte_eth_dev.
2247 * - On success, zero.
2248 * - On failure, a negative value.
2251 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2254 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2255 struct ixgbe_interrupt *intr =
2256 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2258 /* clear all cause mask */
2259 ixgbe_disable_intr(hw);
2261 /* read-on-clear nic registers here */
2262 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2263 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2266 if (eicr & IXGBE_EICR_LSC) {
2267 /* set flag for async link update */
2268 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2271 if (eicr & IXGBE_EICR_MAILBOX)
2272 intr->flags |= IXGBE_FLAG_MAILBOX;
2278 * It gets and then prints the link status.
2281 * Pointer to struct rte_eth_dev.
2284 * - On success, zero.
2285 * - On failure, a negative value.
2288 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2290 struct rte_eth_link link;
2292 memset(&link, 0, sizeof(link));
2293 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2294 if (link.link_status) {
2295 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2296 (int)(dev->data->port_id),
2297 (unsigned)link.link_speed,
2298 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2299 "full-duplex" : "half-duplex");
2301 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2302 (int)(dev->data->port_id));
2304 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2305 dev->pci_dev->addr.domain,
2306 dev->pci_dev->addr.bus,
2307 dev->pci_dev->addr.devid,
2308 dev->pci_dev->addr.function);
2312 * It executes link_update after knowing an interrupt occurred.
2315 * Pointer to struct rte_eth_dev.
2318 * - On success, zero.
2319 * - On failure, a negative value.
2322 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2324 struct ixgbe_interrupt *intr =
2325 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2327 struct rte_eth_link link;
2328 int intr_enable_delay = false;
2330 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2332 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2333 ixgbe_pf_mbx_process(dev);
2334 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2337 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2338 /* get the link status before link update, for predicting later */
2339 memset(&link, 0, sizeof(link));
2340 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2342 ixgbe_dev_link_update(dev, 0);
2345 if (!link.link_status)
2346 /* handle it 1 sec later, wait it being stable */
2347 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2348 /* likely to down */
2350 /* handle it 4 sec later, wait it being stable */
2351 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2353 ixgbe_dev_link_status_print(dev);
2355 intr_enable_delay = true;
2358 if (intr_enable_delay) {
2359 if (rte_eal_alarm_set(timeout * 1000,
2360 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2361 PMD_DRV_LOG(ERR, "Error setting alarm");
2363 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2364 ixgbe_enable_intr(dev);
2365 rte_intr_enable(&(dev->pci_dev->intr_handle));
2373 * Interrupt handler which shall be registered for alarm callback for delayed
2374 * handling specific interrupt to wait for the stable nic state. As the
2375 * NIC interrupt state is not stable for ixgbe after link is just down,
2376 * it needs to wait 4 seconds to get the stable status.
2379 * Pointer to interrupt handle.
2381 * The address of parameter (struct rte_eth_dev *) regsitered before.
2387 ixgbe_dev_interrupt_delayed_handler(void *param)
2389 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2390 struct ixgbe_interrupt *intr =
2391 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2392 struct ixgbe_hw *hw =
2393 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2397 if (eicr & IXGBE_EICR_MAILBOX)
2398 ixgbe_pf_mbx_process(dev);
2400 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2401 ixgbe_dev_link_update(dev, 0);
2402 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2403 ixgbe_dev_link_status_print(dev);
2404 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2407 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2408 ixgbe_enable_intr(dev);
2409 rte_intr_enable(&(dev->pci_dev->intr_handle));
2413 * Interrupt handler triggered by NIC for handling
2414 * specific interrupt.
2417 * Pointer to interrupt handle.
2419 * The address of parameter (struct rte_eth_dev *) regsitered before.
2425 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2428 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2429 ixgbe_dev_interrupt_get_status(dev);
2430 ixgbe_dev_interrupt_action(dev);
2434 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2436 struct ixgbe_hw *hw;
2438 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2443 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2445 struct ixgbe_hw *hw;
2447 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2452 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2454 struct ixgbe_hw *hw;
2460 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462 fc_conf->pause_time = hw->fc.pause_time;
2463 fc_conf->high_water = hw->fc.high_water[0];
2464 fc_conf->low_water = hw->fc.low_water[0];
2465 fc_conf->send_xon = hw->fc.send_xon;
2466 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2469 * Return rx_pause status according to actual setting of
2472 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2473 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2479 * Return tx_pause status according to actual setting of
2482 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2483 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2488 if (rx_pause && tx_pause)
2489 fc_conf->mode = RTE_FC_FULL;
2491 fc_conf->mode = RTE_FC_RX_PAUSE;
2493 fc_conf->mode = RTE_FC_TX_PAUSE;
2495 fc_conf->mode = RTE_FC_NONE;
2501 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2503 struct ixgbe_hw *hw;
2505 uint32_t rx_buf_size;
2506 uint32_t max_high_water;
2508 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2515 PMD_INIT_FUNC_TRACE();
2517 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518 if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2520 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2521 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2524 * At least reserve one Ethernet frame for watermark
2525 * high_water/low_water in kilo bytes for ixgbe
2527 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2528 if ((fc_conf->high_water > max_high_water) ||
2529 (fc_conf->high_water < fc_conf->low_water)) {
2530 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2531 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2535 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2536 hw->fc.pause_time = fc_conf->pause_time;
2537 hw->fc.high_water[0] = fc_conf->high_water;
2538 hw->fc.low_water[0] = fc_conf->low_water;
2539 hw->fc.send_xon = fc_conf->send_xon;
2541 err = ixgbe_fc_enable(hw);
2543 /* Not negotiated is not an error case */
2544 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2546 /* check if we want to forward MAC frames - driver doesn't have native
2547 * capability to do that, so we'll write the registers ourselves */
2549 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2551 /* set or clear MFLCN.PMCF bit depending on configuration */
2552 if (fc_conf->mac_ctrl_frame_fwd != 0)
2553 mflcn |= IXGBE_MFLCN_PMCF;
2555 mflcn &= ~IXGBE_MFLCN_PMCF;
2557 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2558 IXGBE_WRITE_FLUSH(hw);
2563 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2568 * ixgbe_pfc_enable_generic - Enable flow control
2569 * @hw: pointer to hardware structure
2570 * @tc_num: traffic class number
2571 * Enable flow control according to the current settings.
2574 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2577 uint32_t mflcn_reg, fccfg_reg;
2579 uint32_t fcrtl, fcrth;
2583 /* Validate the water mark configuration */
2584 if (!hw->fc.pause_time) {
2585 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2589 /* Low water mark of zero causes XOFF floods */
2590 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2591 /* High/Low water can not be 0 */
2592 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2593 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2594 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2598 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2599 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2600 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2604 /* Negotiate the fc mode to use */
2605 ixgbe_fc_autoneg(hw);
2607 /* Disable any previous flow control settings */
2608 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2609 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2611 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2612 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2614 switch (hw->fc.current_mode) {
2617 * If the count of enabled RX Priority Flow control >1,
2618 * and the TX pause can not be disabled
2621 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2622 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2623 if (reg & IXGBE_FCRTH_FCEN)
2627 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2629 case ixgbe_fc_rx_pause:
2631 * Rx Flow control is enabled and Tx Flow control is
2632 * disabled by software override. Since there really
2633 * isn't a way to advertise that we are capable of RX
2634 * Pause ONLY, we will advertise that we support both
2635 * symmetric and asymmetric Rx PAUSE. Later, we will
2636 * disable the adapter's ability to send PAUSE frames.
2638 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2640 * If the count of enabled RX Priority Flow control >1,
2641 * and the TX pause can not be disabled
2644 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2645 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2646 if (reg & IXGBE_FCRTH_FCEN)
2650 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2652 case ixgbe_fc_tx_pause:
2654 * Tx Flow control is enabled, and Rx Flow control is
2655 * disabled by software override.
2657 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2660 /* Flow control (both Rx and Tx) is enabled by SW override. */
2661 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2662 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2665 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2666 ret_val = IXGBE_ERR_CONFIG;
2671 /* Set 802.3x based flow control settings. */
2672 mflcn_reg |= IXGBE_MFLCN_DPF;
2673 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2674 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2676 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2677 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2678 hw->fc.high_water[tc_num]) {
2679 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2680 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2681 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2683 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2685 * In order to prevent Tx hangs when the internal Tx
2686 * switch is enabled we must set the high water mark
2687 * to the maximum FCRTH value. This allows the Tx
2688 * switch to function even under heavy Rx workloads.
2690 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2692 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2694 /* Configure pause time (2 TCs per register) */
2695 reg = hw->fc.pause_time * 0x00010001;
2696 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2697 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2699 /* Configure flow control refresh threshold value */
2700 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2707 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2709 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2710 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2712 if(hw->mac.type != ixgbe_mac_82598EB) {
2713 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2719 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2722 uint32_t rx_buf_size;
2723 uint32_t max_high_water;
2725 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2726 struct ixgbe_hw *hw =
2727 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2728 struct ixgbe_dcb_config *dcb_config =
2729 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2731 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2738 PMD_INIT_FUNC_TRACE();
2740 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2741 tc_num = map[pfc_conf->priority];
2742 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2743 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2745 * At least reserve one Ethernet frame for watermark
2746 * high_water/low_water in kilo bytes for ixgbe
2748 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2749 if ((pfc_conf->fc.high_water > max_high_water) ||
2750 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2751 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2752 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2756 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2757 hw->fc.pause_time = pfc_conf->fc.pause_time;
2758 hw->fc.send_xon = pfc_conf->fc.send_xon;
2759 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2760 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2762 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2764 /* Not negotiated is not an error case */
2765 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2768 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2773 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2774 struct rte_eth_rss_reta_entry64 *reta_conf,
2779 uint16_t idx, shift;
2780 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782 PMD_INIT_FUNC_TRACE();
2783 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2784 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2785 "(%d) doesn't match the number hardware can supported "
2786 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2790 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2791 idx = i / RTE_RETA_GROUP_SIZE;
2792 shift = i % RTE_RETA_GROUP_SIZE;
2793 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2797 if (mask == IXGBE_4_BIT_MASK)
2800 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2801 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2802 if (mask & (0x1 << j))
2803 reta |= reta_conf[idx].reta[shift + j] <<
2806 reta |= r & (IXGBE_8_BIT_MASK <<
2809 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2816 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2817 struct rte_eth_rss_reta_entry64 *reta_conf,
2822 uint16_t idx, shift;
2823 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2825 PMD_INIT_FUNC_TRACE();
2826 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2827 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2828 "(%d) doesn't match the number hardware can supported "
2829 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2833 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2834 idx = i / RTE_RETA_GROUP_SIZE;
2835 shift = i % RTE_RETA_GROUP_SIZE;
2836 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2841 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2842 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2843 if (mask & (0x1 << j))
2844 reta_conf[idx].reta[shift + j] =
2845 ((reta >> (CHAR_BIT * j)) &
2854 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2855 uint32_t index, uint32_t pool)
2857 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2858 uint32_t enable_addr = 1;
2860 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2864 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2866 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2868 ixgbe_clear_rar(hw, index);
2872 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2876 struct ixgbe_hw *hw;
2877 struct rte_eth_dev_info dev_info;
2878 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2880 ixgbe_dev_info_get(dev, &dev_info);
2882 /* check that mtu is within the allowed range */
2883 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2886 /* refuse mtu that requires the support of scattered packets when this
2887 * feature has not been enabled before. */
2888 if (!dev->data->scattered_rx &&
2889 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2890 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2893 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2894 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2896 /* switch to jumbo mode if needed */
2897 if (frame_size > ETHER_MAX_LEN) {
2898 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2899 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2901 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2902 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2904 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2906 /* update max frame size */
2907 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2909 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2910 maxfrs &= 0x0000FFFF;
2911 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2912 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2918 * Virtual Function operations
2921 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2923 PMD_INIT_FUNC_TRACE();
2925 /* Clear interrupt mask to stop from interrupts being generated */
2926 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2928 IXGBE_WRITE_FLUSH(hw);
2932 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2934 struct rte_eth_conf* conf = &dev->data->dev_conf;
2936 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2937 dev->data->port_id);
2940 * VF has no ability to enable/disable HW CRC
2941 * Keep the persistent behavior the same as Host PF
2943 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2944 if (!conf->rxmode.hw_strip_crc) {
2945 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2946 conf->rxmode.hw_strip_crc = 1;
2949 if (conf->rxmode.hw_strip_crc) {
2950 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2951 conf->rxmode.hw_strip_crc = 0;
2959 ixgbevf_dev_start(struct rte_eth_dev *dev)
2961 struct ixgbe_hw *hw =
2962 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2965 PMD_INIT_FUNC_TRACE();
2967 hw->mac.ops.reset_hw(hw);
2968 hw->mac.get_link_status = true;
2970 /* negotiate mailbox API version to use with the PF. */
2971 ixgbevf_negotiate_api(hw);
2973 ixgbevf_dev_tx_init(dev);
2975 /* This can fail when allocating mbufs for descriptor rings */
2976 err = ixgbevf_dev_rx_init(dev);
2978 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2979 ixgbe_dev_clear_queues(dev);
2984 ixgbevf_set_vfta_all(dev,1);
2987 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2988 ETH_VLAN_EXTEND_MASK;
2989 ixgbevf_vlan_offload_set(dev, mask);
2991 ixgbevf_dev_rxtx_start(dev);
2997 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2999 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3001 PMD_INIT_FUNC_TRACE();
3003 hw->adapter_stopped = TRUE;
3004 ixgbe_stop_adapter(hw);
3007 * Clear what we set, but we still keep shadow_vfta to
3008 * restore after device starts
3010 ixgbevf_set_vfta_all(dev,0);
3012 /* Clear stored conf */
3013 dev->data->scattered_rx = 0;
3015 ixgbe_dev_clear_queues(dev);
3019 ixgbevf_dev_close(struct rte_eth_dev *dev)
3021 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023 PMD_INIT_FUNC_TRACE();
3027 ixgbevf_dev_stop(dev);
3029 /* reprogram the RAR[0] in case user changed it. */
3030 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3033 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3035 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3036 struct ixgbe_vfta * shadow_vfta =
3037 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3038 int i = 0, j = 0, vfta = 0, mask = 1;
3040 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3041 vfta = shadow_vfta->vfta[i];
3044 for (j = 0; j < 32; j++){
3046 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3055 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3057 struct ixgbe_hw *hw =
3058 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3059 struct ixgbe_vfta * shadow_vfta =
3060 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3061 uint32_t vid_idx = 0;
3062 uint32_t vid_bit = 0;
3065 PMD_INIT_FUNC_TRACE();
3067 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3068 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3070 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3073 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3074 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3076 /* Save what we set and retore it after device reset */
3078 shadow_vfta->vfta[vid_idx] |= vid_bit;
3080 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3086 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3088 struct ixgbe_hw *hw =
3089 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3092 PMD_INIT_FUNC_TRACE();
3094 if(queue >= hw->mac.max_rx_queues)
3097 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3099 ctrl |= IXGBE_RXDCTL_VME;
3101 ctrl &= ~IXGBE_RXDCTL_VME;
3102 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3104 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3108 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3110 struct ixgbe_hw *hw =
3111 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3115 /* VF function only support hw strip feature, others are not support */
3116 if(mask & ETH_VLAN_STRIP_MASK){
3117 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3119 for(i=0; i < hw->mac.max_rx_queues; i++)
3120 ixgbevf_vlan_strip_queue_set(dev,i,on);
3125 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3129 /* we only need to do this if VMDq is enabled */
3130 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3131 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3132 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3140 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3142 uint32_t vector = 0;
3143 switch (hw->mac.mc_filter_type) {
3144 case 0: /* use bits [47:36] of the address */
3145 vector = ((uc_addr->addr_bytes[4] >> 4) |
3146 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3148 case 1: /* use bits [46:35] of the address */
3149 vector = ((uc_addr->addr_bytes[4] >> 3) |
3150 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3152 case 2: /* use bits [45:34] of the address */
3153 vector = ((uc_addr->addr_bytes[4] >> 2) |
3154 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3156 case 3: /* use bits [43:32] of the address */
3157 vector = ((uc_addr->addr_bytes[4]) |
3158 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3160 default: /* Invalid mc_filter_type */
3164 /* vector can only be 12-bits or boundary will be exceeded */
3170 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3178 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3179 const uint32_t ixgbe_uta_bit_shift = 5;
3180 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3181 const uint32_t bit1 = 0x1;
3183 struct ixgbe_hw *hw =
3184 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3185 struct ixgbe_uta_info *uta_info =
3186 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3188 /* The UTA table only exists on 82599 hardware and newer */
3189 if (hw->mac.type < ixgbe_mac_82599EB)
3192 vector = ixgbe_uta_vector(hw,mac_addr);
3193 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3194 uta_shift = vector & ixgbe_uta_bit_mask;
3196 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3200 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3202 uta_info->uta_in_use++;
3203 reg_val |= (bit1 << uta_shift);
3204 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3206 uta_info->uta_in_use--;
3207 reg_val &= ~(bit1 << uta_shift);
3208 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3211 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3213 if (uta_info->uta_in_use > 0)
3214 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3215 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3217 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3223 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3226 struct ixgbe_hw *hw =
3227 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3228 struct ixgbe_uta_info *uta_info =
3229 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3231 /* The UTA table only exists on 82599 hardware and newer */
3232 if (hw->mac.type < ixgbe_mac_82599EB)
3236 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3237 uta_info->uta_shadow[i] = ~0;
3238 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3241 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3242 uta_info->uta_shadow[i] = 0;
3243 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3251 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3253 uint32_t new_val = orig_val;
3255 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3256 new_val |= IXGBE_VMOLR_AUPE;
3257 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3258 new_val |= IXGBE_VMOLR_ROMPE;
3259 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3260 new_val |= IXGBE_VMOLR_ROPE;
3261 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3262 new_val |= IXGBE_VMOLR_BAM;
3263 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3264 new_val |= IXGBE_VMOLR_MPE;
3270 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3271 uint16_t rx_mask, uint8_t on)
3275 struct ixgbe_hw *hw =
3276 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3277 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3279 if (hw->mac.type == ixgbe_mac_82598EB) {
3280 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3281 " on 82599 hardware and newer");
3284 if (ixgbe_vmdq_mode_check(hw) < 0)
3287 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3294 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3300 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3304 const uint8_t bit1 = 0x1;
3306 struct ixgbe_hw *hw =
3307 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3309 if (ixgbe_vmdq_mode_check(hw) < 0)
3312 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3313 reg = IXGBE_READ_REG(hw, addr);
3321 IXGBE_WRITE_REG(hw, addr,reg);
3327 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3331 const uint8_t bit1 = 0x1;
3333 struct ixgbe_hw *hw =
3334 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336 if (ixgbe_vmdq_mode_check(hw) < 0)
3339 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3340 reg = IXGBE_READ_REG(hw, addr);
3348 IXGBE_WRITE_REG(hw, addr,reg);
3354 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3355 uint64_t pool_mask, uint8_t vlan_on)
3359 struct ixgbe_hw *hw =
3360 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362 if (ixgbe_vmdq_mode_check(hw) < 0)
3364 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3365 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3366 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3375 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3376 struct rte_eth_vmdq_mirror_conf *mirror_conf,
3377 uint8_t rule_id, uint8_t on)
3379 uint32_t mr_ctl,vlvf;
3380 uint32_t mp_lsb = 0;
3381 uint32_t mv_msb = 0;
3382 uint32_t mv_lsb = 0;
3383 uint32_t mp_msb = 0;
3386 uint64_t vlan_mask = 0;
3388 const uint8_t pool_mask_offset = 32;
3389 const uint8_t vlan_mask_offset = 32;
3390 const uint8_t dst_pool_offset = 8;
3391 const uint8_t rule_mr_offset = 4;
3392 const uint8_t mirror_rule_mask= 0x0F;
3394 struct ixgbe_mirror_info *mr_info =
3395 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3396 struct ixgbe_hw *hw =
3397 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399 if (ixgbe_vmdq_mode_check(hw) < 0)
3402 /* Check if vlan mask is valid */
3403 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3404 if (mirror_conf->vlan.vlan_mask == 0)
3408 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3409 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3410 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3411 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3412 /* search vlan id related pool vlan filter index */
3413 reg_index = ixgbe_find_vlvf_slot(hw,
3414 mirror_conf->vlan.vlan_id[i]);
3417 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3418 if ((vlvf & IXGBE_VLVF_VIEN) &&
3419 ((vlvf & IXGBE_VLVF_VLANID_MASK)
3420 == mirror_conf->vlan.vlan_id[i]))
3421 vlan_mask |= (1ULL << reg_index);
3428 mv_lsb = vlan_mask & 0xFFFFFFFF;
3429 mv_msb = vlan_mask >> vlan_mask_offset;
3431 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3432 mirror_conf->vlan.vlan_mask;
3433 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3434 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3435 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3436 mirror_conf->vlan.vlan_id[i];
3441 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3442 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3443 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3448 * if enable pool mirror, write related pool mask register,if disable
3449 * pool mirror, clear PFMRVM register
3451 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3453 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3454 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3455 mr_info->mr_conf[rule_id].pool_mask =
3456 mirror_conf->pool_mask;
3461 mr_info->mr_conf[rule_id].pool_mask = 0;
3465 /* read mirror control register and recalculate it */
3466 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3469 mr_ctl |= mirror_conf->rule_type_mask;
3470 mr_ctl &= mirror_rule_mask;
3471 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3473 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3475 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3476 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3478 /* write mirrror control register */
3479 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3481 /* write pool mirrror control register */
3482 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3483 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3484 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3487 /* write VLAN mirrror control register */
3488 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3489 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3490 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3498 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3501 uint32_t lsb_val = 0;
3502 uint32_t msb_val = 0;
3503 const uint8_t rule_mr_offset = 4;
3505 struct ixgbe_hw *hw =
3506 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507 struct ixgbe_mirror_info *mr_info =
3508 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3510 if (ixgbe_vmdq_mode_check(hw) < 0)
3513 memset(&mr_info->mr_conf[rule_id], 0,
3514 sizeof(struct rte_eth_vmdq_mirror_conf));
3516 /* clear PFVMCTL register */
3517 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3519 /* clear pool mask register */
3520 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3521 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3523 /* clear vlan mask register */
3524 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3525 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3530 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3531 uint16_t queue_idx, uint16_t tx_rate)
3533 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3534 uint32_t rf_dec, rf_int;
3536 uint16_t link_speed = dev->data->dev_link.link_speed;
3538 if (queue_idx >= hw->mac.max_tx_queues)
3542 /* Calculate the rate factor values to set */
3543 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3544 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3545 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3547 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3548 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3549 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3550 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3556 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3557 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3560 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3561 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3562 IXGBE_MAX_JUMBO_FRAME_SIZE))
3563 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3564 IXGBE_MMW_SIZE_JUMBO_FRAME);
3566 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3567 IXGBE_MMW_SIZE_DEFAULT);
3569 /* Set RTTBCNRC of queue X */
3570 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3571 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3572 IXGBE_WRITE_FLUSH(hw);
3577 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3578 uint16_t tx_rate, uint64_t q_msk)
3580 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3581 struct ixgbe_vf_info *vfinfo =
3582 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3583 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3584 uint32_t queue_stride =
3585 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3586 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3587 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3588 uint16_t total_rate = 0;
3590 if (queue_end >= hw->mac.max_tx_queues)
3593 if (vfinfo != NULL) {
3594 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3597 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3599 total_rate += vfinfo[vf_idx].tx_rate[idx];
3604 /* Store tx_rate for this vf. */
3605 for (idx = 0; idx < nb_q_per_pool; idx++) {
3606 if (((uint64_t)0x1 << idx) & q_msk) {
3607 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3608 vfinfo[vf].tx_rate[idx] = tx_rate;
3609 total_rate += tx_rate;
3613 if (total_rate > dev->data->dev_link.link_speed) {
3615 * Reset stored TX rate of the VF if it causes exceed
3618 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3622 /* Set RTTBCNRC of each queue/pool for vf X */
3623 for (; queue_idx <= queue_end; queue_idx++) {
3625 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3633 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3634 __attribute__((unused)) uint32_t index,
3635 __attribute__((unused)) uint32_t pool)
3637 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3642 * operation. Trap this case to avoid exhausting the [very limited]
3643 * set of PF resources used to store VF MAC addresses.
3645 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3647 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3650 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3654 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3656 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3657 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3658 struct ether_addr *mac_addr;
3663 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3664 * not support the deletion of a given MAC address.
3665 * Instead, it imposes to delete all MAC addresses, then to add again
3666 * all MAC addresses with the exception of the one to be deleted.
3668 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3671 * Add again all MAC addresses, with the exception of the deleted one
3672 * and of the permanent MAC address.
3674 for (i = 0, mac_addr = dev->data->mac_addrs;
3675 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3676 /* Skip the deleted MAC address */
3679 /* Skip NULL MAC addresses */
3680 if (is_zero_ether_addr(mac_addr))
3682 /* Skip the permanent MAC address */
3683 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3685 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3688 "Adding again MAC address "
3689 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3691 mac_addr->addr_bytes[0],
3692 mac_addr->addr_bytes[1],
3693 mac_addr->addr_bytes[2],
3694 mac_addr->addr_bytes[3],
3695 mac_addr->addr_bytes[4],
3696 mac_addr->addr_bytes[5],
3701 #define MAC_TYPE_FILTER_SUP(type) do {\
3702 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3703 (type) != ixgbe_mac_X550)\
3708 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3709 struct rte_eth_syn_filter *filter,
3712 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3715 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3718 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3721 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3723 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3724 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3726 if (filter->hig_pri)
3727 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3729 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3731 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3733 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3735 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3736 IXGBE_WRITE_FLUSH(hw);
3741 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3742 struct rte_eth_syn_filter *filter)
3744 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3745 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3747 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3748 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3749 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3756 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3757 enum rte_filter_op filter_op,
3760 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3763 MAC_TYPE_FILTER_SUP(hw->mac.type);
3765 if (filter_op == RTE_ETH_FILTER_NOP)
3769 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3774 switch (filter_op) {
3775 case RTE_ETH_FILTER_ADD:
3776 ret = ixgbe_syn_filter_set(dev,
3777 (struct rte_eth_syn_filter *)arg,
3780 case RTE_ETH_FILTER_DELETE:
3781 ret = ixgbe_syn_filter_set(dev,
3782 (struct rte_eth_syn_filter *)arg,
3785 case RTE_ETH_FILTER_GET:
3786 ret = ixgbe_syn_filter_get(dev,
3787 (struct rte_eth_syn_filter *)arg);
3790 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3799 static inline enum ixgbe_5tuple_protocol
3800 convert_protocol_type(uint8_t protocol_value)
3802 if (protocol_value == IPPROTO_TCP)
3803 return IXGBE_FILTER_PROTOCOL_TCP;
3804 else if (protocol_value == IPPROTO_UDP)
3805 return IXGBE_FILTER_PROTOCOL_UDP;
3806 else if (protocol_value == IPPROTO_SCTP)
3807 return IXGBE_FILTER_PROTOCOL_SCTP;
3809 return IXGBE_FILTER_PROTOCOL_NONE;
3812 static inline uint8_t
3813 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3815 if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3817 else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3819 else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3820 return IPPROTO_SCTP;
3826 * add a 5tuple filter
3829 * dev: Pointer to struct rte_eth_dev.
3830 * index: the index the filter allocates.
3831 * filter: ponter to the filter that will be added.
3832 * rx_queue: the queue id the filter assigned to.
3835 * - On success, zero.
3836 * - On failure, a negative value.
3839 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3840 struct ixgbe_5tuple_filter *filter)
3842 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3843 struct ixgbe_filter_info *filter_info =
3844 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3846 uint32_t ftqf, sdpqf;
3847 uint32_t l34timir = 0;
3848 uint8_t mask = 0xff;
3851 * look for an unused 5tuple filter index,
3852 * and insert the filter to list.
3854 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3855 idx = i / (sizeof(uint32_t) * NBBY);
3856 shift = i % (sizeof(uint32_t) * NBBY);
3857 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3858 filter_info->fivetuple_mask[idx] |= 1 << shift;
3860 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3866 if (i >= IXGBE_MAX_FTQF_FILTERS) {
3867 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3871 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3872 IXGBE_SDPQF_DSTPORT_SHIFT);
3873 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3875 ftqf = (uint32_t)(filter->filter_info.proto &
3876 IXGBE_FTQF_PROTOCOL_MASK);
3877 ftqf |= (uint32_t)((filter->filter_info.priority &
3878 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3879 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3880 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3881 if (filter->filter_info.dst_ip_mask == 0)
3882 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3883 if (filter->filter_info.src_port_mask == 0)
3884 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3885 if (filter->filter_info.dst_port_mask == 0)
3886 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3887 if (filter->filter_info.proto_mask == 0)
3888 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3889 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3890 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3891 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3893 IXGBE_WRITE_REG(hw, IXGBE_DAQF(idx), filter->filter_info.dst_ip);
3894 IXGBE_WRITE_REG(hw, IXGBE_SAQF(idx), filter->filter_info.src_ip);
3895 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(idx), sdpqf);
3896 IXGBE_WRITE_REG(hw, IXGBE_FTQF(idx), ftqf);
3898 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3899 l34timir |= (uint32_t)(filter->queue <<
3900 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3901 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3906 * remove a 5tuple filter
3909 * dev: Pointer to struct rte_eth_dev.
3910 * filter: the pointer of the filter will be removed.
3913 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3914 struct ixgbe_5tuple_filter *filter)
3916 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917 struct ixgbe_filter_info *filter_info =
3918 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3919 uint16_t index = filter->index;
3921 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3922 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3923 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3926 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3927 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3928 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3929 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3930 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3934 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3936 struct ixgbe_hw *hw;
3937 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3939 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3941 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3944 /* refuse mtu that requires the support of scattered packets when this
3945 * feature has not been enabled before. */
3946 if (!dev->data->scattered_rx &&
3947 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3948 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3952 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3953 * request of the version 2.0 of the mailbox API.
3954 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3955 * of the mailbox API.
3956 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3957 * prior to 3.11.33 which contains the following change:
3958 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3960 ixgbevf_rlpml_set_vf(hw, max_frame);
3962 /* update max frame size */
3963 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3967 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
3968 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
3972 static inline struct ixgbe_5tuple_filter *
3973 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
3974 struct ixgbe_5tuple_filter_info *key)
3976 struct ixgbe_5tuple_filter *it;
3978 TAILQ_FOREACH(it, filter_list, entries) {
3979 if (memcmp(key, &it->filter_info,
3980 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
3987 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
3989 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3990 struct ixgbe_5tuple_filter_info *filter_info)
3992 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3993 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3994 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3997 switch (filter->dst_ip_mask) {
3999 filter_info->dst_ip_mask = 0;
4000 filter_info->dst_ip = filter->dst_ip;
4003 filter_info->dst_ip_mask = 1;
4006 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4010 switch (filter->src_ip_mask) {
4012 filter_info->src_ip_mask = 0;
4013 filter_info->src_ip = filter->src_ip;
4016 filter_info->src_ip_mask = 1;
4019 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4023 switch (filter->dst_port_mask) {
4025 filter_info->dst_port_mask = 0;
4026 filter_info->dst_port = filter->dst_port;
4029 filter_info->dst_port_mask = 1;
4032 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4036 switch (filter->src_port_mask) {
4038 filter_info->src_port_mask = 0;
4039 filter_info->src_port = filter->src_port;
4042 filter_info->src_port_mask = 1;
4045 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4049 switch (filter->proto_mask) {
4051 filter_info->proto_mask = 0;
4052 filter_info->proto =
4053 convert_protocol_type(filter->proto);
4056 filter_info->proto_mask = 1;
4059 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4063 filter_info->priority = (uint8_t)filter->priority;
4068 * add or delete a ntuple filter
4071 * dev: Pointer to struct rte_eth_dev.
4072 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4073 * add: if true, add filter, if false, remove filter
4076 * - On success, zero.
4077 * - On failure, a negative value.
4080 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4081 struct rte_eth_ntuple_filter *ntuple_filter,
4084 struct ixgbe_filter_info *filter_info =
4085 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4086 struct ixgbe_5tuple_filter_info filter_5tuple;
4087 struct ixgbe_5tuple_filter *filter;
4090 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4091 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4095 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4096 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4100 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4102 if (filter != NULL && add) {
4103 PMD_DRV_LOG(ERR, "filter exists.");
4106 if (filter == NULL && !add) {
4107 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4112 filter = rte_zmalloc("ixgbe_5tuple_filter",
4113 sizeof(struct ixgbe_5tuple_filter), 0);
4116 (void)rte_memcpy(&filter->filter_info,
4118 sizeof(struct ixgbe_5tuple_filter_info));
4119 filter->queue = ntuple_filter->queue;
4120 ret = ixgbe_add_5tuple_filter(dev, filter);
4126 ixgbe_remove_5tuple_filter(dev, filter);
4132 * get a ntuple filter
4135 * dev: Pointer to struct rte_eth_dev.
4136 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4139 * - On success, zero.
4140 * - On failure, a negative value.
4143 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4144 struct rte_eth_ntuple_filter *ntuple_filter)
4146 struct ixgbe_filter_info *filter_info =
4147 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4148 struct ixgbe_5tuple_filter_info filter_5tuple;
4149 struct ixgbe_5tuple_filter *filter;
4152 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4153 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4157 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4158 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4162 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4164 if (filter == NULL) {
4165 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4168 ntuple_filter->queue = filter->queue;
4173 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4174 * @dev: pointer to rte_eth_dev structure
4175 * @filter_op:operation will be taken.
4176 * @arg: a pointer to specific structure corresponding to the filter_op
4179 * - On success, zero.
4180 * - On failure, a negative value.
4183 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4184 enum rte_filter_op filter_op,
4187 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4190 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4192 if (filter_op == RTE_ETH_FILTER_NOP)
4196 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4201 switch (filter_op) {
4202 case RTE_ETH_FILTER_ADD:
4203 ret = ixgbe_add_del_ntuple_filter(dev,
4204 (struct rte_eth_ntuple_filter *)arg,
4207 case RTE_ETH_FILTER_DELETE:
4208 ret = ixgbe_add_del_ntuple_filter(dev,
4209 (struct rte_eth_ntuple_filter *)arg,
4212 case RTE_ETH_FILTER_GET:
4213 ret = ixgbe_get_ntuple_filter(dev,
4214 (struct rte_eth_ntuple_filter *)arg);
4217 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4225 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4230 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4231 if (filter_info->ethertype_filters[i] == ethertype &&
4232 (filter_info->ethertype_mask & (1 << i)))
4239 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4244 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4245 if (!(filter_info->ethertype_mask & (1 << i))) {
4246 filter_info->ethertype_mask |= 1 << i;
4247 filter_info->ethertype_filters[i] = ethertype;
4255 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4258 if (idx >= IXGBE_MAX_ETQF_FILTERS)
4260 filter_info->ethertype_mask &= ~(1 << idx);
4261 filter_info->ethertype_filters[idx] = 0;
4266 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4267 struct rte_eth_ethertype_filter *filter,
4270 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271 struct ixgbe_filter_info *filter_info =
4272 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4277 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4280 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4281 filter->ether_type == ETHER_TYPE_IPv6) {
4282 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4283 " ethertype filter.", filter->ether_type);
4287 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4288 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4291 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4292 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4296 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4297 if (ret >= 0 && add) {
4298 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4299 filter->ether_type);
4302 if (ret < 0 && !add) {
4303 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4304 filter->ether_type);
4309 ret = ixgbe_ethertype_filter_insert(filter_info,
4310 filter->ether_type);
4312 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4315 etqf = IXGBE_ETQF_FILTER_EN;
4316 etqf |= (uint32_t)filter->ether_type;
4317 etqs |= (uint32_t)((filter->queue <<
4318 IXGBE_ETQS_RX_QUEUE_SHIFT) &
4319 IXGBE_ETQS_RX_QUEUE);
4320 etqs |= IXGBE_ETQS_QUEUE_EN;
4322 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4326 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4327 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4328 IXGBE_WRITE_FLUSH(hw);
4334 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4335 struct rte_eth_ethertype_filter *filter)
4337 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4338 struct ixgbe_filter_info *filter_info =
4339 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4340 uint32_t etqf, etqs;
4343 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4345 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4346 filter->ether_type);
4350 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4351 if (etqf & IXGBE_ETQF_FILTER_EN) {
4352 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4353 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4355 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4356 IXGBE_ETQS_RX_QUEUE_SHIFT;
4363 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4364 * @dev: pointer to rte_eth_dev structure
4365 * @filter_op:operation will be taken.
4366 * @arg: a pointer to specific structure corresponding to the filter_op
4369 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4370 enum rte_filter_op filter_op,
4373 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4376 MAC_TYPE_FILTER_SUP(hw->mac.type);
4378 if (filter_op == RTE_ETH_FILTER_NOP)
4382 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4387 switch (filter_op) {
4388 case RTE_ETH_FILTER_ADD:
4389 ret = ixgbe_add_del_ethertype_filter(dev,
4390 (struct rte_eth_ethertype_filter *)arg,
4393 case RTE_ETH_FILTER_DELETE:
4394 ret = ixgbe_add_del_ethertype_filter(dev,
4395 (struct rte_eth_ethertype_filter *)arg,
4398 case RTE_ETH_FILTER_GET:
4399 ret = ixgbe_get_ethertype_filter(dev,
4400 (struct rte_eth_ethertype_filter *)arg);
4403 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4411 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4412 enum rte_filter_type filter_type,
4413 enum rte_filter_op filter_op,
4418 switch (filter_type) {
4419 case RTE_ETH_FILTER_NTUPLE:
4420 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4422 case RTE_ETH_FILTER_ETHERTYPE:
4423 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4425 case RTE_ETH_FILTER_SYN:
4426 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4428 case RTE_ETH_FILTER_FDIR:
4429 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4432 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4440 static struct rte_driver rte_ixgbe_driver = {
4442 .init = rte_ixgbe_pmd_init,
4445 static struct rte_driver rte_ixgbevf_driver = {
4447 .init = rte_ixgbevf_pmd_init,
4450 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4451 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);