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35 #include <sys/queue.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
63 #include "ixgbe_logs.h"
64 #include "ixgbe/ixgbe_api.h"
65 #include "ixgbe/ixgbe_vf.h"
66 #include "ixgbe/ixgbe_common.h"
67 #include "ixgbe_ethdev.h"
70 * High threshold controlling when to start sending XOFF frames. Must be at
71 * least 8 bytes less than receive packet buffer size. This value is in units
74 #define IXGBE_FC_HI 0x80
77 * Low threshold controlling when to start sending XON frames. This value is
78 * in units of 1024 bytes.
80 #define IXGBE_FC_LO 0x40
82 /* Timer value included in XOFF frames. */
83 #define IXGBE_FC_PAUSE 0x680
85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
86 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
88 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
90 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
92 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
93 struct rte_eth_dev *eth_dev);
94 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
95 static int ixgbe_dev_start(struct rte_eth_dev *dev);
96 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
97 static void ixgbe_dev_close(struct rte_eth_dev *dev);
98 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
99 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
100 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
101 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
102 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
103 int wait_to_complete);
104 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
105 struct rte_eth_stats *stats);
106 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
107 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
111 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
112 struct rte_eth_dev_info *dev_info);
113 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
114 uint16_t vlan_id, int on);
115 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
116 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
117 uint16_t queue, bool on);
118 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
120 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
121 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
122 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
123 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
124 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
126 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
127 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
128 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
129 struct rte_eth_fc_conf *fc_conf);
130 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
131 struct rte_eth_pfc_conf *pfc_conf);
132 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
133 struct rte_eth_rss_reta *reta_conf);
134 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
135 struct rte_eth_rss_reta *reta_conf);
136 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
137 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
138 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
139 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
140 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
142 static void ixgbe_dev_interrupt_delayed_handler(void *param);
143 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
144 uint32_t index, uint32_t pool);
145 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
146 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
148 /* For Virtual Function support */
149 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
150 struct rte_eth_dev *eth_dev);
151 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
152 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
153 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
154 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
155 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
156 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
157 struct rte_eth_stats *stats);
158 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
159 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
160 uint16_t vlan_id, int on);
161 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
162 uint16_t queue, int on);
163 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
164 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
167 * Define VF Stats MACRO for Non "cleared on read" register
169 #define UPDATE_VF_STAT(reg, last, cur) \
171 u32 latest = IXGBE_READ_REG(hw, reg); \
172 cur += latest - last; \
176 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
178 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
179 u64 new_msb = IXGBE_READ_REG(hw, msb); \
180 u64 latest = ((new_msb << 32) | new_lsb); \
181 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
185 #define IXGBE_SET_HWSTRIP(h, q) do{\
186 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
187 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
188 (h)->bitmap[idx] |= 1 << bit;\
191 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
192 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
193 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
194 (h)->bitmap[idx] &= ~(1 << bit);\
197 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
198 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
199 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
200 (r) = (h)->bitmap[idx] >> bit & 1;\
204 * The set of PCI devices this driver supports
206 static struct rte_pci_id pci_id_ixgbe_map[] = {
208 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
209 #include "rte_pci_dev_ids.h"
211 { .vendor_id = 0, /* sentinel */ },
216 * The set of PCI devices this driver supports (for 82599 VF)
218 static struct rte_pci_id pci_id_ixgbevf_map[] = {
220 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
221 #include "rte_pci_dev_ids.h"
222 { .vendor_id = 0, /* sentinel */ },
226 static struct eth_dev_ops ixgbe_eth_dev_ops = {
227 .dev_configure = ixgbe_dev_configure,
228 .dev_start = ixgbe_dev_start,
229 .dev_stop = ixgbe_dev_stop,
230 .dev_close = ixgbe_dev_close,
231 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
232 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
233 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
234 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
235 .link_update = ixgbe_dev_link_update,
236 .stats_get = ixgbe_dev_stats_get,
237 .stats_reset = ixgbe_dev_stats_reset,
238 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
239 .dev_infos_get = ixgbe_dev_info_get,
240 .vlan_filter_set = ixgbe_vlan_filter_set,
241 .vlan_tpid_set = ixgbe_vlan_tpid_set,
242 .vlan_offload_set = ixgbe_vlan_offload_set,
243 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
244 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
245 .rx_queue_release = ixgbe_dev_rx_queue_release,
246 .rx_queue_count = ixgbe_dev_rx_queue_count,
247 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
248 .tx_queue_release = ixgbe_dev_tx_queue_release,
249 .dev_led_on = ixgbe_dev_led_on,
250 .dev_led_off = ixgbe_dev_led_off,
251 .flow_ctrl_set = ixgbe_flow_ctrl_set,
252 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
253 .mac_addr_add = ixgbe_add_rar,
254 .mac_addr_remove = ixgbe_remove_rar,
255 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
256 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
257 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
258 .fdir_infos_get = ixgbe_fdir_info_get,
259 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
260 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
261 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
262 .fdir_set_masks = ixgbe_fdir_set_masks,
263 .reta_update = ixgbe_dev_rss_reta_update,
264 .reta_query = ixgbe_dev_rss_reta_query,
268 * dev_ops for virtual function, bare necessities for basic vf
269 * operation have been implemented
271 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
273 .dev_configure = ixgbevf_dev_configure,
274 .dev_start = ixgbevf_dev_start,
275 .dev_stop = ixgbevf_dev_stop,
276 .link_update = ixgbe_dev_link_update,
277 .stats_get = ixgbevf_dev_stats_get,
278 .stats_reset = ixgbevf_dev_stats_reset,
279 .dev_close = ixgbevf_dev_close,
280 .dev_infos_get = ixgbe_dev_info_get,
281 .vlan_filter_set = ixgbevf_vlan_filter_set,
282 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
283 .vlan_offload_set = ixgbevf_vlan_offload_set,
284 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
285 .rx_queue_release = ixgbe_dev_rx_queue_release,
286 .rx_queue_count = ixgbe_dev_rx_queue_count,
287 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
288 .tx_queue_release = ixgbe_dev_tx_queue_release,
292 * Atomically reads the link status information from global
293 * structure rte_eth_dev.
296 * - Pointer to the structure rte_eth_dev to read from.
297 * - Pointer to the buffer to be saved with the link status.
300 * - On success, zero.
301 * - On failure, negative value.
304 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
305 struct rte_eth_link *link)
307 struct rte_eth_link *dst = link;
308 struct rte_eth_link *src = &(dev->data->dev_link);
310 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
311 *(uint64_t *)src) == 0)
318 * Atomically writes the link status information into global
319 * structure rte_eth_dev.
322 * - Pointer to the structure rte_eth_dev to read from.
323 * - Pointer to the buffer to be saved with the link status.
326 * - On success, zero.
327 * - On failure, negative value.
330 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
331 struct rte_eth_link *link)
333 struct rte_eth_link *dst = &(dev->data->dev_link);
334 struct rte_eth_link *src = link;
336 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
337 *(uint64_t *)src) == 0)
344 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
347 ixgbe_is_sfp(struct ixgbe_hw *hw)
349 switch (hw->phy.type) {
350 case ixgbe_phy_sfp_avago:
351 case ixgbe_phy_sfp_ftl:
352 case ixgbe_phy_sfp_intel:
353 case ixgbe_phy_sfp_unknown:
354 case ixgbe_phy_sfp_passive_tyco:
355 case ixgbe_phy_sfp_passive_unknown:
362 static inline int32_t
363 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
368 status = ixgbe_reset_hw(hw);
370 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
371 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
372 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
373 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
374 IXGBE_WRITE_FLUSH(hw);
380 ixgbe_enable_intr(struct rte_eth_dev *dev)
382 struct ixgbe_interrupt *intr =
383 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
384 struct ixgbe_hw *hw =
385 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
387 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
388 IXGBE_WRITE_FLUSH(hw);
392 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
395 ixgbe_disable_intr(struct ixgbe_hw *hw)
397 PMD_INIT_FUNC_TRACE();
399 if (hw->mac.type == ixgbe_mac_82598EB) {
400 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
402 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
403 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
404 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
406 IXGBE_WRITE_FLUSH(hw);
410 * This function resets queue statistics mapping registers.
411 * From Niantic datasheet, Initialization of Statistics section:
412 * "...if software requires the queue counters, the RQSMR and TQSM registers
413 * must be re-programmed following a device reset.
416 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
420 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
421 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
422 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
428 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
433 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
434 #define NB_QMAP_FIELDS_PER_QSM_REG 4
435 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
437 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
438 struct ixgbe_stat_mapping_registers *stat_mappings =
439 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
440 uint32_t qsmr_mask = 0;
441 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
445 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
448 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
449 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
451 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
452 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
453 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
456 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
458 /* Now clear any previous stat_idx set */
459 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
461 stat_mappings->tqsm[n] &= ~clearing_mask;
463 stat_mappings->rqsmr[n] &= ~clearing_mask;
465 q_map = (uint32_t)stat_idx;
466 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
467 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
469 stat_mappings->tqsm[n] |= qsmr_mask;
471 stat_mappings->rqsmr[n] |= qsmr_mask;
473 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
475 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
476 is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
478 /* Now write the mapping in the appropriate register */
480 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
481 stat_mappings->rqsmr[n], n);
482 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
485 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
486 stat_mappings->tqsm[n], n);
487 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
493 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
495 struct ixgbe_stat_mapping_registers *stat_mappings =
496 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
497 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
500 /* write whatever was in stat mapping table to the NIC */
501 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
503 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
506 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
511 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
514 struct ixgbe_dcb_tc_config *tc;
515 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
517 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
518 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
519 for (i = 0; i < dcb_max_tc; i++) {
520 tc = &dcb_config->tc_config[i];
521 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
522 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
523 (uint8_t)(100/dcb_max_tc + (i & 1));
524 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
525 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
526 (uint8_t)(100/dcb_max_tc + (i & 1));
527 tc->pfc = ixgbe_dcb_pfc_disabled;
530 /* Initialize default user to priority mapping, UPx->TC0 */
531 tc = &dcb_config->tc_config[0];
532 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
533 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
534 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
535 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
536 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
538 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
539 dcb_config->pfc_mode_enable = false;
540 dcb_config->vt_mode = true;
541 dcb_config->round_robin_enable = false;
542 /* support all DCB capabilities in 82599 */
543 dcb_config->support.capabilities = 0xFF;
545 /*we only support 4 Tcs for X540*/
546 if (hw->mac.type == ixgbe_mac_X540) {
547 dcb_config->num_tcs.pg_tcs = 4;
548 dcb_config->num_tcs.pfc_tcs = 4;
553 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
554 * It returns 0 on success.
557 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
558 struct rte_eth_dev *eth_dev)
560 struct rte_pci_device *pci_dev;
561 struct ixgbe_hw *hw =
562 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
563 struct ixgbe_vfta * shadow_vfta =
564 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
565 struct ixgbe_hwstrip *hwstrip =
566 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
567 struct ixgbe_dcb_config *dcb_config =
568 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
573 PMD_INIT_FUNC_TRACE();
575 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
576 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
577 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
579 /* for secondary processes, we don't initialise any further as primary
580 * has already done this work. Only check we don't need a different
582 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
583 if (eth_dev->data->scattered_rx)
584 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
587 pci_dev = eth_dev->pci_dev;
589 /* Vendor and Device ID need to be set before init of shared code */
590 hw->device_id = pci_dev->id.device_id;
591 hw->vendor_id = pci_dev->id.vendor_id;
592 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
593 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
594 hw->allow_unsupported_sfp = 1;
597 /* Initialize the shared code */
598 diag = ixgbe_init_shared_code(hw);
599 if (diag != IXGBE_SUCCESS) {
600 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
604 /* Initialize DCB configuration*/
605 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
606 ixgbe_dcb_init(hw,dcb_config);
607 /* Get Hardware Flow Control setting */
608 hw->fc.requested_mode = ixgbe_fc_full;
609 hw->fc.current_mode = ixgbe_fc_full;
610 hw->fc.pause_time = IXGBE_FC_PAUSE;
611 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
612 hw->fc.low_water[i] = IXGBE_FC_LO;
613 hw->fc.high_water[i] = IXGBE_FC_HI;
617 /* Make sure we have a good EEPROM before we read from it */
618 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
619 if (diag != IXGBE_SUCCESS) {
620 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
624 diag = ixgbe_init_hw(hw);
627 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
628 * is called too soon after the kernel driver unbinding/binding occurs.
629 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
630 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
631 * also called. See ixgbe_identify_phy_82599(). The reason for the
632 * failure is not known, and only occuts when virtualisation features
633 * are disabled in the bios. A delay of 100ms was found to be enough by
634 * trial-and-error, and is doubled to be safe.
636 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
638 diag = ixgbe_init_hw(hw);
641 if (diag == IXGBE_ERR_EEPROM_VERSION) {
642 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
643 "LOM. Please be aware there may be issues associated "
644 "with your hardware.\n If you are experiencing problems "
645 "please contact your Intel or hardware representative "
646 "who provided you with this hardware.\n");
647 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
648 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
650 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
654 /* disable interrupt */
655 ixgbe_disable_intr(hw);
657 /* pick up the PCI bus settings for reporting later */
658 ixgbe_get_bus_info(hw);
660 /* reset mappings for queue statistics hw counters*/
661 ixgbe_reset_qstat_mappings(hw);
663 /* Allocate memory for storing MAC addresses */
664 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
665 hw->mac.num_rar_entries, 0);
666 if (eth_dev->data->mac_addrs == NULL) {
668 "Failed to allocate %d bytes needed to store MAC addresses",
669 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
672 /* Copy the permanent MAC address */
673 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
674 ð_dev->data->mac_addrs[0]);
676 /* initialize the vfta */
677 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
679 /* initialize the hw strip bitmap*/
680 memset(hwstrip, 0, sizeof(*hwstrip));
682 /* initialize PF if max_vfs not zero */
683 ixgbe_pf_host_init(eth_dev);
685 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
686 /* let hardware know driver is loaded */
687 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
688 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
689 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
690 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
691 IXGBE_WRITE_FLUSH(hw);
693 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
695 "MAC: %d, PHY: %d, SFP+: %d<n",
696 (int) hw->mac.type, (int) hw->phy.type,
697 (int) hw->phy.sfp_type);
699 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
700 (int) hw->mac.type, (int) hw->phy.type);
702 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
703 eth_dev->data->port_id, pci_dev->id.vendor_id,
704 pci_dev->id.device_id);
706 rte_intr_callback_register(&(pci_dev->intr_handle),
707 ixgbe_dev_interrupt_handler, (void *)eth_dev);
709 /* enable uio intr after callback register */
710 rte_intr_enable(&(pci_dev->intr_handle));
712 /* enable support intr */
713 ixgbe_enable_intr(eth_dev);
719 * Virtual Function device init
722 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
723 struct rte_eth_dev *eth_dev)
725 struct rte_pci_device *pci_dev;
726 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
728 struct ixgbe_vfta * shadow_vfta =
729 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
730 struct ixgbe_hwstrip *hwstrip =
731 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
733 PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
735 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
736 pci_dev = eth_dev->pci_dev;
738 hw->device_id = pci_dev->id.device_id;
739 hw->vendor_id = pci_dev->id.vendor_id;
740 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
742 /* initialize the vfta */
743 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
745 /* initialize the hw strip bitmap*/
746 memset(hwstrip, 0, sizeof(*hwstrip));
748 /* Initialize the shared code */
749 diag = ixgbe_init_shared_code(hw);
750 if (diag != IXGBE_SUCCESS) {
751 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
755 /* init_mailbox_params */
756 hw->mbx.ops.init_params(hw);
758 /* Disable the interrupts for VF */
759 ixgbevf_intr_disable(hw);
761 hw->mac.num_rar_entries = hw->mac.max_rx_queues;
762 diag = hw->mac.ops.reset_hw(hw);
764 if (diag != IXGBE_SUCCESS) {
765 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
766 RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
767 "\tThe most likely cause of this error is that the VM host\n"
768 "\thas not assigned a valid MAC address to this VF device.\n"
769 "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
770 "\ta possible solution to this problem.\n");
774 /* Allocate memory for storing MAC addresses */
775 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
776 hw->mac.num_rar_entries, 0);
777 if (eth_dev->data->mac_addrs == NULL) {
779 "Failed to allocate %d bytes needed to store MAC addresses",
780 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
784 /* Copy the permanent MAC address */
785 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
786 ð_dev->data->mac_addrs[0]);
788 /* reset the hardware with the new settings */
789 diag = hw->mac.ops.start_hw(hw);
795 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
799 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
800 eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
801 "ixgbe_mac_82599_vf");
806 static struct eth_driver rte_ixgbe_pmd = {
808 .name = "rte_ixgbe_pmd",
809 .id_table = pci_id_ixgbe_map,
810 #ifdef RTE_EAL_UNBIND_PORTS
811 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
814 .eth_dev_init = eth_ixgbe_dev_init,
815 .dev_private_size = sizeof(struct ixgbe_adapter),
819 * virtual function driver struct
821 static struct eth_driver rte_ixgbevf_pmd = {
823 .name = "rte_ixgbevf_pmd",
824 .id_table = pci_id_ixgbevf_map,
825 #ifdef RTE_EAL_UNBIND_PORTS
826 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
829 .eth_dev_init = eth_ixgbevf_dev_init,
830 .dev_private_size = sizeof(struct ixgbe_adapter),
834 * Driver initialization routine.
835 * Invoked once at EAL init time.
836 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
839 rte_ixgbe_pmd_init(void)
841 PMD_INIT_FUNC_TRACE();
843 rte_eth_driver_register(&rte_ixgbe_pmd);
848 * VF Driver initialization routine.
849 * Invoked one at EAL init time.
850 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
853 rte_ixgbevf_pmd_init(void)
855 DEBUGFUNC("rte_ixgbevf_pmd_init");
857 rte_eth_driver_register(&rte_ixgbevf_pmd);
862 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
864 struct ixgbe_hw *hw =
865 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
866 struct ixgbe_vfta * shadow_vfta =
867 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
872 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
873 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
874 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
879 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
881 /* update local VFTA copy */
882 shadow_vfta->vfta[vid_idx] = vfta;
888 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
891 ixgbe_vlan_hw_strip_enable(dev, queue);
893 ixgbe_vlan_hw_strip_disable(dev, queue);
897 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
899 struct ixgbe_hw *hw =
900 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
902 /* Only the high 16-bits is valid */
903 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
907 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
909 struct ixgbe_hw *hw =
910 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
913 PMD_INIT_FUNC_TRACE();
915 /* Filter Table Disable */
916 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
917 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
919 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
923 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
925 struct ixgbe_hw *hw =
926 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
927 struct ixgbe_vfta * shadow_vfta =
928 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
932 PMD_INIT_FUNC_TRACE();
934 /* Filter Table Enable */
935 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
936 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
937 vlnctrl |= IXGBE_VLNCTRL_VFE;
939 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
941 /* write whatever is in local vfta copy */
942 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
943 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
947 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
949 struct ixgbe_hwstrip *hwstrip =
950 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
952 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
956 IXGBE_SET_HWSTRIP(hwstrip, queue);
958 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
962 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
964 struct ixgbe_hw *hw =
965 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
968 PMD_INIT_FUNC_TRACE();
970 if (hw->mac.type == ixgbe_mac_82598EB) {
971 /* No queue level support */
972 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
976 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
977 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
978 ctrl &= ~IXGBE_RXDCTL_VME;
979 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
981 /* record those setting for HW strip per queue */
982 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
986 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
988 struct ixgbe_hw *hw =
989 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
992 PMD_INIT_FUNC_TRACE();
994 if (hw->mac.type == ixgbe_mac_82598EB) {
995 /* No queue level supported */
996 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1000 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1001 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1002 ctrl |= IXGBE_RXDCTL_VME;
1003 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1005 /* record those setting for HW strip per queue */
1006 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1010 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1012 struct ixgbe_hw *hw =
1013 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017 PMD_INIT_FUNC_TRACE();
1019 if (hw->mac.type == ixgbe_mac_82598EB) {
1020 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1021 ctrl &= ~IXGBE_VLNCTRL_VME;
1022 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1025 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1026 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1027 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1028 ctrl &= ~IXGBE_RXDCTL_VME;
1029 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1031 /* record those setting for HW strip per queue */
1032 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1038 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1040 struct ixgbe_hw *hw =
1041 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1045 PMD_INIT_FUNC_TRACE();
1047 if (hw->mac.type == ixgbe_mac_82598EB) {
1048 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1049 ctrl |= IXGBE_VLNCTRL_VME;
1050 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1053 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1054 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1055 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1056 ctrl |= IXGBE_RXDCTL_VME;
1057 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1059 /* record those setting for HW strip per queue */
1060 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1066 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1068 struct ixgbe_hw *hw =
1069 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1072 PMD_INIT_FUNC_TRACE();
1074 /* DMATXCTRL: Geric Double VLAN Disable */
1075 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1076 ctrl &= ~IXGBE_DMATXCTL_GDV;
1077 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1079 /* CTRL_EXT: Global Double VLAN Disable */
1080 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1081 ctrl &= ~IXGBE_EXTENDED_VLAN;
1082 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1087 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1089 struct ixgbe_hw *hw =
1090 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093 PMD_INIT_FUNC_TRACE();
1095 /* DMATXCTRL: Geric Double VLAN Enable */
1096 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1097 ctrl |= IXGBE_DMATXCTL_GDV;
1098 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1100 /* CTRL_EXT: Global Double VLAN Enable */
1101 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1102 ctrl |= IXGBE_EXTENDED_VLAN;
1103 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1106 * VET EXT field in the EXVET register = 0x8100 by default
1107 * So no need to change. Same to VT field of DMATXCTL register
1112 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1114 if(mask & ETH_VLAN_STRIP_MASK){
1115 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1116 ixgbe_vlan_hw_strip_enable_all(dev);
1118 ixgbe_vlan_hw_strip_disable_all(dev);
1121 if(mask & ETH_VLAN_FILTER_MASK){
1122 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1123 ixgbe_vlan_hw_filter_enable(dev);
1125 ixgbe_vlan_hw_filter_disable(dev);
1128 if(mask & ETH_VLAN_EXTEND_MASK){
1129 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1130 ixgbe_vlan_hw_extend_enable(dev);
1132 ixgbe_vlan_hw_extend_disable(dev);
1137 ixgbe_dev_configure(struct rte_eth_dev *dev)
1139 struct ixgbe_interrupt *intr =
1140 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1142 PMD_INIT_FUNC_TRACE();
1144 /* set flag to update link status after init */
1145 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1151 * Configure device link speed and setup link.
1152 * It returns 0 on success.
1155 ixgbe_dev_start(struct rte_eth_dev *dev)
1157 struct ixgbe_hw *hw =
1158 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1159 int err, link_up = 0, negotiate = 0;
1164 PMD_INIT_FUNC_TRACE();
1166 /* IXGBE devices don't support half duplex */
1167 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1168 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1169 PMD_INIT_LOG(ERR, "Invalid link_duplex (%u) for port %u\n",
1170 dev->data->dev_conf.link_duplex,
1171 dev->data->port_id);
1176 hw->adapter_stopped = FALSE;
1177 ixgbe_stop_adapter(hw);
1179 /* reinitialize adapter
1180 * this calls reset and start */
1181 status = ixgbe_pf_reset_hw(hw);
1184 hw->mac.ops.start_hw(hw);
1186 /* configure PF module if SRIOV enabled */
1187 ixgbe_pf_host_configure(dev);
1189 /* initialize transmission unit */
1190 ixgbe_dev_tx_init(dev);
1192 /* This can fail when allocating mbufs for descriptor rings */
1193 err = ixgbe_dev_rx_init(dev);
1195 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1199 ixgbe_dev_rxtx_start(dev);
1201 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1202 err = hw->mac.ops.setup_sfp(hw);
1207 /* Turn on the laser */
1208 if (hw->phy.multispeed_fiber)
1209 ixgbe_enable_tx_laser(hw);
1211 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1214 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1218 switch(dev->data->dev_conf.link_speed) {
1219 case ETH_LINK_SPEED_AUTONEG:
1220 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1221 IXGBE_LINK_SPEED_82599_AUTONEG :
1222 IXGBE_LINK_SPEED_82598_AUTONEG;
1224 case ETH_LINK_SPEED_100:
1226 * Invalid for 82598 but error will be detected by
1227 * ixgbe_setup_link()
1229 speed = IXGBE_LINK_SPEED_100_FULL;
1231 case ETH_LINK_SPEED_1000:
1232 speed = IXGBE_LINK_SPEED_1GB_FULL;
1234 case ETH_LINK_SPEED_10000:
1235 speed = IXGBE_LINK_SPEED_10GB_FULL;
1238 PMD_INIT_LOG(ERR, "Invalid link_speed (%u) for port %u\n",
1239 dev->data->dev_conf.link_speed, dev->data->port_id);
1243 err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1247 /* check if lsc interrupt is enabled */
1248 if (dev->data->dev_conf.intr_conf.lsc != 0)
1249 ixgbe_dev_lsc_interrupt_setup(dev);
1251 /* resume enabled intr since hw reset */
1252 ixgbe_enable_intr(dev);
1254 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1255 ETH_VLAN_EXTEND_MASK;
1256 ixgbe_vlan_offload_set(dev, mask);
1258 /* Configure DCB hw */
1259 ixgbe_configure_dcb(dev);
1261 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1262 err = ixgbe_fdir_configure(dev);
1267 ixgbe_restore_statistics_mapping(dev);
1272 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1273 ixgbe_dev_clear_queues(dev);
1278 * Stop device: disable rx and tx functions to allow for reconfiguring.
1281 ixgbe_dev_stop(struct rte_eth_dev *dev)
1283 struct rte_eth_link link;
1284 struct ixgbe_hw *hw =
1285 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1287 PMD_INIT_FUNC_TRACE();
1289 /* disable interrupts */
1290 ixgbe_disable_intr(hw);
1293 ixgbe_pf_reset_hw(hw);
1294 hw->adapter_stopped = FALSE;
1297 ixgbe_stop_adapter(hw);
1299 /* Turn off the laser */
1300 if (hw->phy.multispeed_fiber)
1301 ixgbe_disable_tx_laser(hw);
1303 ixgbe_dev_clear_queues(dev);
1305 /* Clear recorded link status */
1306 memset(&link, 0, sizeof(link));
1307 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1311 * Reest and stop device.
1314 ixgbe_dev_close(struct rte_eth_dev *dev)
1316 struct ixgbe_hw *hw =
1317 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1319 PMD_INIT_FUNC_TRACE();
1321 ixgbe_pf_reset_hw(hw);
1323 ixgbe_dev_stop(dev);
1324 hw->adapter_stopped = 1;
1326 ixgbe_disable_pcie_master(hw);
1328 /* reprogram the RAR[0] in case user changed it. */
1329 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1333 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1336 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1338 struct ixgbe_hw *hw =
1339 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340 struct ixgbe_hw_stats *hw_stats =
1341 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1342 uint32_t bprc, lxon, lxoff, total;
1343 uint64_t total_missed_rx, total_qbrc, total_qprc;
1346 total_missed_rx = 0;
1350 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1351 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1352 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1353 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1355 for (i = 0; i < 8; i++) {
1357 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1358 /* global total per queue */
1359 hw_stats->mpc[i] += mp;
1360 /* Running comprehensive total for stats display */
1361 total_missed_rx += hw_stats->mpc[i];
1362 if (hw->mac.type == ixgbe_mac_82598EB)
1363 hw_stats->rnbc[i] +=
1364 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1365 hw_stats->pxontxc[i] +=
1366 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1367 hw_stats->pxonrxc[i] +=
1368 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1369 hw_stats->pxofftxc[i] +=
1370 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1371 hw_stats->pxoffrxc[i] +=
1372 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1373 hw_stats->pxon2offc[i] +=
1374 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1376 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1377 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1378 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1379 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1380 hw_stats->qbrc[i] +=
1381 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1382 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1383 hw_stats->qbtc[i] +=
1384 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1385 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1387 total_qprc += hw_stats->qprc[i];
1388 total_qbrc += hw_stats->qbrc[i];
1390 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1391 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1392 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1394 /* Note that gprc counts missed packets */
1395 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1397 if (hw->mac.type != ixgbe_mac_82598EB) {
1398 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1399 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1400 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1401 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1402 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1403 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1404 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1405 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1407 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1408 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1409 /* 82598 only has a counter in the high register */
1410 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1411 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1412 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1416 * Workaround: mprc hardware is incorrectly counting
1417 * broadcasts, so for now we subtract those.
1419 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1420 hw_stats->bprc += bprc;
1421 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1422 if (hw->mac.type == ixgbe_mac_82598EB)
1423 hw_stats->mprc -= bprc;
1425 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1426 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1427 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1428 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1429 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1430 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1432 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1433 hw_stats->lxontxc += lxon;
1434 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1435 hw_stats->lxofftxc += lxoff;
1436 total = lxon + lxoff;
1438 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1439 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1440 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1441 hw_stats->gptc -= total;
1442 hw_stats->mptc -= total;
1443 hw_stats->ptc64 -= total;
1444 hw_stats->gotc -= total * ETHER_MIN_LEN;
1446 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1447 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1448 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1449 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1450 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1451 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1452 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1453 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1454 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1455 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1456 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1457 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1458 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1459 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1460 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1461 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1462 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1463 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1464 /* Only read FCOE on 82599 */
1465 if (hw->mac.type != ixgbe_mac_82598EB) {
1466 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1467 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1468 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1469 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1470 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1476 /* Fill out the rte_eth_stats statistics structure */
1477 stats->ipackets = total_qprc;
1478 stats->ibytes = total_qbrc;
1479 stats->opackets = hw_stats->gptc;
1480 stats->obytes = hw_stats->gotc;
1481 stats->imcasts = hw_stats->mprc;
1483 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1484 stats->q_ipackets[i] = hw_stats->qprc[i];
1485 stats->q_opackets[i] = hw_stats->qptc[i];
1486 stats->q_ibytes[i] = hw_stats->qbrc[i];
1487 stats->q_obytes[i] = hw_stats->qbtc[i];
1488 stats->q_errors[i] = hw_stats->qprdc[i];
1492 stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1497 /* Flow Director Stats registers */
1498 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1499 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1500 stats->fdirmatch = hw_stats->fdirmatch;
1501 stats->fdirmiss = hw_stats->fdirmiss;
1505 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1507 struct ixgbe_hw_stats *stats =
1508 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1510 /* HW registers are cleared on read */
1511 ixgbe_dev_stats_get(dev, NULL);
1513 /* Reset software totals */
1514 memset(stats, 0, sizeof(*stats));
1518 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1520 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1522 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1524 /* Good Rx packet, include VF loopback */
1525 UPDATE_VF_STAT(IXGBE_VFGPRC,
1526 hw_stats->last_vfgprc, hw_stats->vfgprc);
1528 /* Good Rx octets, include VF loopback */
1529 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1530 hw_stats->last_vfgorc, hw_stats->vfgorc);
1532 /* Good Tx packet, include VF loopback */
1533 UPDATE_VF_STAT(IXGBE_VFGPTC,
1534 hw_stats->last_vfgptc, hw_stats->vfgptc);
1536 /* Good Tx octets, include VF loopback */
1537 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1538 hw_stats->last_vfgotc, hw_stats->vfgotc);
1540 /* Rx Multicst Packet */
1541 UPDATE_VF_STAT(IXGBE_VFMPRC,
1542 hw_stats->last_vfmprc, hw_stats->vfmprc);
1547 memset(stats, 0, sizeof(*stats));
1548 stats->ipackets = hw_stats->vfgprc;
1549 stats->ibytes = hw_stats->vfgorc;
1550 stats->opackets = hw_stats->vfgptc;
1551 stats->obytes = hw_stats->vfgotc;
1552 stats->imcasts = hw_stats->vfmprc;
1556 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1558 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1559 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1561 /* Sync HW register to the last stats */
1562 ixgbevf_dev_stats_get(dev, NULL);
1564 /* reset HW current stats*/
1565 hw_stats->vfgprc = 0;
1566 hw_stats->vfgorc = 0;
1567 hw_stats->vfgptc = 0;
1568 hw_stats->vfgotc = 0;
1569 hw_stats->vfmprc = 0;
1574 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1576 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1579 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1580 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1581 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1582 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1585 /* return 0 means link status changed, -1 means not changed */
1587 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1589 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1590 struct rte_eth_link link, old;
1591 ixgbe_link_speed link_speed;
1595 link.link_status = 0;
1596 link.link_speed = 0;
1597 link.link_duplex = 0;
1598 memset(&old, 0, sizeof(old));
1599 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1601 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1602 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1603 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1605 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1607 link.link_speed = ETH_LINK_SPEED_100;
1608 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1609 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1610 if (link.link_status == old.link_status)
1616 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1617 if (link.link_status == old.link_status)
1621 link.link_status = 1;
1622 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1624 switch (link_speed) {
1626 case IXGBE_LINK_SPEED_UNKNOWN:
1627 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1628 link.link_speed = ETH_LINK_SPEED_100;
1631 case IXGBE_LINK_SPEED_100_FULL:
1632 link.link_speed = ETH_LINK_SPEED_100;
1635 case IXGBE_LINK_SPEED_1GB_FULL:
1636 link.link_speed = ETH_LINK_SPEED_1000;
1639 case IXGBE_LINK_SPEED_10GB_FULL:
1640 link.link_speed = ETH_LINK_SPEED_10000;
1643 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1645 if (link.link_status == old.link_status)
1652 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1654 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1658 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1659 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1663 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1665 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1668 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1669 fctrl &= (~IXGBE_FCTRL_UPE);
1670 if (dev->data->all_multicast == 1)
1671 fctrl |= IXGBE_FCTRL_MPE;
1673 fctrl &= (~IXGBE_FCTRL_MPE);
1674 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1678 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1680 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1684 fctrl |= IXGBE_FCTRL_MPE;
1685 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1689 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1691 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1694 if (dev->data->promiscuous == 1)
1695 return; /* must remain in all_multicast mode */
1697 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1698 fctrl &= (~IXGBE_FCTRL_MPE);
1699 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1703 * It clears the interrupt causes and enables the interrupt.
1704 * It will be called once only during nic initialized.
1707 * Pointer to struct rte_eth_dev.
1710 * - On success, zero.
1711 * - On failure, a negative value.
1714 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1716 struct ixgbe_interrupt *intr =
1717 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1719 ixgbe_dev_link_status_print(dev);
1720 intr->mask |= IXGBE_EICR_LSC;
1726 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1729 * Pointer to struct rte_eth_dev.
1732 * - On success, zero.
1733 * - On failure, a negative value.
1736 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1739 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740 struct ixgbe_interrupt *intr =
1741 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1743 /* clear all cause mask */
1744 ixgbe_disable_intr(hw);
1746 /* read-on-clear nic registers here */
1747 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1748 PMD_DRV_LOG(INFO, "eicr %x", eicr);
1751 if (eicr & IXGBE_EICR_LSC) {
1752 /* set flag for async link update */
1753 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1756 if (eicr & IXGBE_EICR_MAILBOX)
1757 intr->flags |= IXGBE_FLAG_MAILBOX;
1763 * It gets and then prints the link status.
1766 * Pointer to struct rte_eth_dev.
1769 * - On success, zero.
1770 * - On failure, a negative value.
1773 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1775 struct rte_eth_link link;
1777 memset(&link, 0, sizeof(link));
1778 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1779 if (link.link_status) {
1780 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1781 (int)(dev->data->port_id),
1782 (unsigned)link.link_speed,
1783 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1784 "full-duplex" : "half-duplex");
1786 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1787 (int)(dev->data->port_id));
1789 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1790 dev->pci_dev->addr.domain,
1791 dev->pci_dev->addr.bus,
1792 dev->pci_dev->addr.devid,
1793 dev->pci_dev->addr.function);
1797 * It executes link_update after knowing an interrupt occured.
1800 * Pointer to struct rte_eth_dev.
1803 * - On success, zero.
1804 * - On failure, a negative value.
1807 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1809 struct ixgbe_interrupt *intr =
1810 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1812 struct rte_eth_link link;
1813 int intr_enable_delay = false;
1815 PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1817 if (intr->flags & IXGBE_FLAG_MAILBOX) {
1818 ixgbe_pf_mbx_process(dev);
1819 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1822 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1823 /* get the link status before link update, for predicting later */
1824 memset(&link, 0, sizeof(link));
1825 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1827 ixgbe_dev_link_update(dev, 0);
1830 if (!link.link_status)
1831 /* handle it 1 sec later, wait it being stable */
1832 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1833 /* likely to down */
1835 /* handle it 4 sec later, wait it being stable */
1836 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1838 ixgbe_dev_link_status_print(dev);
1840 intr_enable_delay = true;
1843 if (intr_enable_delay) {
1844 if (rte_eal_alarm_set(timeout * 1000,
1845 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
1846 PMD_DRV_LOG(ERR, "Error setting alarm");
1848 PMD_DRV_LOG(DEBUG, "enable intr immediately");
1849 ixgbe_enable_intr(dev);
1850 rte_intr_enable(&(dev->pci_dev->intr_handle));
1858 * Interrupt handler which shall be registered for alarm callback for delayed
1859 * handling specific interrupt to wait for the stable nic state. As the
1860 * NIC interrupt state is not stable for ixgbe after link is just down,
1861 * it needs to wait 4 seconds to get the stable status.
1864 * Pointer to interrupt handle.
1866 * The address of parameter (struct rte_eth_dev *) regsitered before.
1872 ixgbe_dev_interrupt_delayed_handler(void *param)
1874 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1875 struct ixgbe_interrupt *intr =
1876 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1877 struct ixgbe_hw *hw =
1878 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1881 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1882 if (eicr & IXGBE_EICR_MAILBOX)
1883 ixgbe_pf_mbx_process(dev);
1885 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1886 ixgbe_dev_link_update(dev, 0);
1887 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
1888 ixgbe_dev_link_status_print(dev);
1889 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1892 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
1893 ixgbe_enable_intr(dev);
1894 rte_intr_enable(&(dev->pci_dev->intr_handle));
1898 * Interrupt handler triggered by NIC for handling
1899 * specific interrupt.
1902 * Pointer to interrupt handle.
1904 * The address of parameter (struct rte_eth_dev *) regsitered before.
1910 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1913 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1914 ixgbe_dev_interrupt_get_status(dev);
1915 ixgbe_dev_interrupt_action(dev);
1919 ixgbe_dev_led_on(struct rte_eth_dev *dev)
1921 struct ixgbe_hw *hw;
1923 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1928 ixgbe_dev_led_off(struct rte_eth_dev *dev)
1930 struct ixgbe_hw *hw;
1932 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1937 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1939 struct ixgbe_hw *hw;
1941 uint32_t rx_buf_size;
1942 uint32_t max_high_water;
1943 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
1950 PMD_INIT_FUNC_TRACE();
1952 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
1954 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1957 * At least reserve one Ethernet frame for watermark
1958 * high_water/low_water in kilo bytes for ixgbe
1960 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
1961 if ((fc_conf->high_water > max_high_water) ||
1962 (fc_conf->high_water < fc_conf->low_water)) {
1963 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
1964 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
1968 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
1969 hw->fc.pause_time = fc_conf->pause_time;
1970 hw->fc.high_water[0] = fc_conf->high_water;
1971 hw->fc.low_water[0] = fc_conf->low_water;
1972 hw->fc.send_xon = fc_conf->send_xon;
1974 err = ixgbe_fc_enable(hw);
1975 /* Not negotiated is not an error case */
1976 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
1980 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
1985 * ixgbe_pfc_enable_generic - Enable flow control
1986 * @hw: pointer to hardware structure
1987 * @tc_num: traffic class number
1988 * Enable flow control according to the current settings.
1991 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
1994 uint32_t mflcn_reg, fccfg_reg;
1996 uint32_t fcrtl, fcrth;
2000 /* Validate the water mark configuration */
2001 if (!hw->fc.pause_time) {
2002 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2006 /* Low water mark of zero causes XOFF floods */
2007 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2008 /* High/Low water can not be 0 */
2009 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2010 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2011 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2015 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2016 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2017 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2021 /* Negotiate the fc mode to use */
2022 ixgbe_fc_autoneg(hw);
2024 /* Disable any previous flow control settings */
2025 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2026 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2028 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2029 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2031 switch (hw->fc.current_mode) {
2034 * If the count of enabled RX Priority Flow control >1,
2035 * and the TX pause can not be disabled
2038 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2039 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2040 if (reg & IXGBE_FCRTH_FCEN)
2044 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2046 case ixgbe_fc_rx_pause:
2048 * Rx Flow control is enabled and Tx Flow control is
2049 * disabled by software override. Since there really
2050 * isn't a way to advertise that we are capable of RX
2051 * Pause ONLY, we will advertise that we support both
2052 * symmetric and asymmetric Rx PAUSE. Later, we will
2053 * disable the adapter's ability to send PAUSE frames.
2055 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2057 * If the count of enabled RX Priority Flow control >1,
2058 * and the TX pause can not be disabled
2061 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2062 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2063 if (reg & IXGBE_FCRTH_FCEN)
2067 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2069 case ixgbe_fc_tx_pause:
2071 * Tx Flow control is enabled, and Rx Flow control is
2072 * disabled by software override.
2074 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2077 /* Flow control (both Rx and Tx) is enabled by SW override. */
2078 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2079 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2082 DEBUGOUT("Flow control param set incorrectly\n");
2083 ret_val = IXGBE_ERR_CONFIG;
2088 /* Set 802.3x based flow control settings. */
2089 mflcn_reg |= IXGBE_MFLCN_DPF;
2090 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2091 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2093 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2094 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2095 hw->fc.high_water[tc_num]) {
2096 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2097 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2098 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2100 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2102 * In order to prevent Tx hangs when the internal Tx
2103 * switch is enabled we must set the high water mark
2104 * to the maximum FCRTH value. This allows the Tx
2105 * switch to function even under heavy Rx workloads.
2107 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2109 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2111 /* Configure pause time (2 TCs per register) */
2112 reg = hw->fc.pause_time * 0x00010001;
2113 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2114 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2116 /* Configure flow control refresh threshold value */
2117 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2124 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2129 if(hw->mac.type != ixgbe_mac_82598EB) {
2130 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2136 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2139 uint32_t rx_buf_size;
2140 uint32_t max_high_water;
2142 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2143 struct ixgbe_hw *hw =
2144 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145 struct ixgbe_dcb_config *dcb_config =
2146 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2148 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2155 PMD_INIT_FUNC_TRACE();
2157 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2158 tc_num = map[pfc_conf->priority];
2159 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2160 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2162 * At least reserve one Ethernet frame for watermark
2163 * high_water/low_water in kilo bytes for ixgbe
2165 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2166 if ((pfc_conf->fc.high_water > max_high_water) ||
2167 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2168 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2169 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2173 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2174 hw->fc.pause_time = pfc_conf->fc.pause_time;
2175 hw->fc.send_xon = pfc_conf->fc.send_xon;
2176 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2177 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2179 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2181 /* Not negotiated is not an error case */
2182 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2185 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2190 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2191 struct rte_eth_rss_reta *reta_conf)
2195 struct ixgbe_hw *hw =
2196 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198 PMD_INIT_FUNC_TRACE();
2200 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2201 * 128-entries in 32 registers
2203 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2204 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2205 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2207 mask = (uint8_t)((reta_conf->mask_hi >>
2208 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2212 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2214 for (j = 0; j < 4; j++) {
2215 if (mask & (0x1 << j)) {
2217 reta &= ~(0xFF << 8 * j);
2218 reta |= reta_conf->reta[i + j] << 8*j;
2221 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2229 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2230 struct rte_eth_rss_reta *reta_conf)
2234 struct ixgbe_hw *hw =
2235 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237 PMD_INIT_FUNC_TRACE();
2239 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2240 * 128-entries in 32 registers
2242 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2243 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2244 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2246 mask = (uint8_t)((reta_conf->mask_hi >>
2247 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2250 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2251 for (j = 0; j < 4; j++) {
2252 if (mask & (0x1 << j))
2253 reta_conf->reta[i + j] =
2254 (uint8_t)((reta >> 8 * j) & 0xFF);
2263 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2264 uint32_t index, uint32_t pool)
2266 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2267 uint32_t enable_addr = 1;
2269 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2273 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2275 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277 ixgbe_clear_rar(hw, index);
2281 * Virtual Function operations
2284 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2286 PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2288 /* Clear interrupt mask to stop from interrupts being generated */
2289 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2291 IXGBE_WRITE_FLUSH(hw);
2295 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2297 struct rte_eth_conf* conf = &dev->data->dev_conf;
2299 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2300 dev->data->port_id);
2303 * VF has no ability to enable/disable HW CRC
2304 * Keep the persistent behavior the same as Host PF
2306 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2307 if (!conf->rxmode.hw_strip_crc) {
2308 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2309 conf->rxmode.hw_strip_crc = 1;
2312 if (conf->rxmode.hw_strip_crc) {
2313 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2314 conf->rxmode.hw_strip_crc = 0;
2322 ixgbevf_dev_start(struct rte_eth_dev *dev)
2324 struct ixgbe_hw *hw =
2325 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2330 hw->mac.ops.reset_hw(hw);
2332 ixgbevf_dev_tx_init(dev);
2334 /* This can fail when allocating mbufs for descriptor rings */
2335 err = ixgbevf_dev_rx_init(dev);
2337 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2338 ixgbe_dev_clear_queues(dev);
2343 ixgbevf_set_vfta_all(dev,1);
2346 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2347 ETH_VLAN_EXTEND_MASK;
2348 ixgbevf_vlan_offload_set(dev, mask);
2350 ixgbevf_dev_rxtx_start(dev);
2356 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2358 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2360 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2362 hw->adapter_stopped = TRUE;
2363 ixgbe_stop_adapter(hw);
2366 * Clear what we set, but we still keep shadow_vfta to
2367 * restore after device starts
2369 ixgbevf_set_vfta_all(dev,0);
2371 ixgbe_dev_clear_queues(dev);
2375 ixgbevf_dev_close(struct rte_eth_dev *dev)
2377 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2383 ixgbevf_dev_stop(dev);
2385 /* reprogram the RAR[0] in case user changed it. */
2386 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2389 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2391 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392 struct ixgbe_vfta * shadow_vfta =
2393 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2394 int i = 0, j = 0, vfta = 0, mask = 1;
2396 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2397 vfta = shadow_vfta->vfta[i];
2400 for (j = 0; j < 32; j++){
2402 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2411 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2413 struct ixgbe_hw *hw =
2414 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2415 struct ixgbe_vfta * shadow_vfta =
2416 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2417 uint32_t vid_idx = 0;
2418 uint32_t vid_bit = 0;
2421 PMD_INIT_FUNC_TRACE();
2423 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2424 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2426 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2429 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2430 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2432 /* Save what we set and retore it after device reset */
2434 shadow_vfta->vfta[vid_idx] |= vid_bit;
2436 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2442 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2444 struct ixgbe_hw *hw =
2445 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448 PMD_INIT_FUNC_TRACE();
2450 if(queue >= hw->mac.max_rx_queues)
2453 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2455 ctrl |= IXGBE_RXDCTL_VME;
2457 ctrl &= ~IXGBE_RXDCTL_VME;
2458 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2460 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2464 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2466 struct ixgbe_hw *hw =
2467 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471 /* VF function only support hw strip feature, others are not support */
2472 if(mask & ETH_VLAN_STRIP_MASK){
2473 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2475 for(i=0; i < hw->mac.max_rx_queues; i++)
2476 ixgbevf_vlan_strip_queue_set(dev,i,on);