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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_tailq.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
63 #include "ixgbe_logs.h"
64 #include "ixgbe/ixgbe_api.h"
65 #include "ixgbe/ixgbe_vf.h"
66 #include "ixgbe/ixgbe_common.h"
67 #include "ixgbe_ethdev.h"
68 #include "ixgbe_bypass.h"
71 * High threshold controlling when to start sending XOFF frames. Must be at
72 * least 8 bytes less than receive packet buffer size. This value is in units
75 #define IXGBE_FC_HI 0x80
78 * Low threshold controlling when to start sending XON frames. This value is
79 * in units of 1024 bytes.
81 #define IXGBE_FC_LO 0x40
83 /* Timer value included in XOFF frames. */
84 #define IXGBE_FC_PAUSE 0x680
86 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
87 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
88 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
91 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
93 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
95 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
96 struct rte_eth_dev *eth_dev);
97 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
98 static int ixgbe_dev_start(struct rte_eth_dev *dev);
99 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
100 static void ixgbe_dev_close(struct rte_eth_dev *dev);
101 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
102 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
103 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
104 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
105 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
106 int wait_to_complete);
107 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
108 struct rte_eth_stats *stats);
109 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
110 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
114 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
115 struct rte_eth_dev_info *dev_info);
116 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
117 uint16_t vlan_id, int on);
118 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
119 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
120 uint16_t queue, bool on);
121 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
123 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
124 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
125 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
126 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
127 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
129 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
130 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
131 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
132 struct rte_eth_fc_conf *fc_conf);
133 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
134 struct rte_eth_pfc_conf *pfc_conf);
135 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
136 struct rte_eth_rss_reta *reta_conf);
137 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
138 struct rte_eth_rss_reta *reta_conf);
139 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
140 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
141 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
142 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
143 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
145 static void ixgbe_dev_interrupt_delayed_handler(void *param);
146 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
147 uint32_t index, uint32_t pool);
148 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
149 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
151 /* For Virtual Function support */
152 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
153 struct rte_eth_dev *eth_dev);
154 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
155 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
156 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
157 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
158 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
159 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
160 struct rte_eth_stats *stats);
161 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
162 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
163 uint16_t vlan_id, int on);
164 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
165 uint16_t queue, int on);
166 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
167 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
169 /* For Eth VMDQ APIs support */
170 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
171 ether_addr* mac_addr,uint8_t on);
172 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
173 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
174 uint16_t rx_mask, uint8_t on);
175 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
176 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
177 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
178 uint64_t pool_mask,uint8_t vlan_on);
179 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
180 struct rte_eth_vmdq_mirror_conf *mirror_conf,
181 uint8_t rule_id, uint8_t on);
182 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
186 * Define VF Stats MACRO for Non "cleared on read" register
188 #define UPDATE_VF_STAT(reg, last, cur) \
190 u32 latest = IXGBE_READ_REG(hw, reg); \
191 cur += latest - last; \
195 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
197 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
198 u64 new_msb = IXGBE_READ_REG(hw, msb); \
199 u64 latest = ((new_msb << 32) | new_lsb); \
200 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
204 #define IXGBE_SET_HWSTRIP(h, q) do{\
205 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
206 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
207 (h)->bitmap[idx] |= 1 << bit;\
210 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
211 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
212 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
213 (h)->bitmap[idx] &= ~(1 << bit);\
216 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
217 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
218 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
219 (r) = (h)->bitmap[idx] >> bit & 1;\
223 * The set of PCI devices this driver supports
225 static struct rte_pci_id pci_id_ixgbe_map[] = {
227 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
228 #include "rte_pci_dev_ids.h"
230 { .vendor_id = 0, /* sentinel */ },
235 * The set of PCI devices this driver supports (for 82599 VF)
237 static struct rte_pci_id pci_id_ixgbevf_map[] = {
239 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
240 #include "rte_pci_dev_ids.h"
241 { .vendor_id = 0, /* sentinel */ },
245 static struct eth_dev_ops ixgbe_eth_dev_ops = {
246 .dev_configure = ixgbe_dev_configure,
247 .dev_start = ixgbe_dev_start,
248 .dev_stop = ixgbe_dev_stop,
249 .dev_close = ixgbe_dev_close,
250 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
251 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
252 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
253 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
254 .link_update = ixgbe_dev_link_update,
255 .stats_get = ixgbe_dev_stats_get,
256 .stats_reset = ixgbe_dev_stats_reset,
257 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
258 .dev_infos_get = ixgbe_dev_info_get,
259 .vlan_filter_set = ixgbe_vlan_filter_set,
260 .vlan_tpid_set = ixgbe_vlan_tpid_set,
261 .vlan_offload_set = ixgbe_vlan_offload_set,
262 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
263 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
264 .rx_queue_release = ixgbe_dev_rx_queue_release,
265 .rx_queue_count = ixgbe_dev_rx_queue_count,
266 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
267 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
268 .tx_queue_release = ixgbe_dev_tx_queue_release,
269 .dev_led_on = ixgbe_dev_led_on,
270 .dev_led_off = ixgbe_dev_led_off,
271 .flow_ctrl_set = ixgbe_flow_ctrl_set,
272 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
273 .mac_addr_add = ixgbe_add_rar,
274 .mac_addr_remove = ixgbe_remove_rar,
275 .uc_hash_table_set = ixgbe_uc_hash_table_set,
276 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
277 .mirror_rule_set = ixgbe_mirror_rule_set,
278 .mirror_rule_reset = ixgbe_mirror_rule_reset,
279 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
280 .set_vf_rx = ixgbe_set_pool_rx,
281 .set_vf_tx = ixgbe_set_pool_tx,
282 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
283 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
284 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
285 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
286 .fdir_infos_get = ixgbe_fdir_info_get,
287 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
288 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
289 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
290 .fdir_set_masks = ixgbe_fdir_set_masks,
291 .reta_update = ixgbe_dev_rss_reta_update,
292 .reta_query = ixgbe_dev_rss_reta_query,
293 #ifdef RTE_NIC_BYPASS
294 .bypass_init = ixgbe_bypass_init,
295 .bypass_state_set = ixgbe_bypass_state_store,
296 .bypass_state_show = ixgbe_bypass_state_show,
297 .bypass_event_set = ixgbe_bypass_event_store,
298 .bypass_event_show = ixgbe_bypass_event_show,
299 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
300 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
301 .bypass_ver_show = ixgbe_bypass_ver_show,
302 .bypass_wd_reset = ixgbe_bypass_wd_reset,
303 #endif /* RTE_NIC_BYPASS */
307 * dev_ops for virtual function, bare necessities for basic vf
308 * operation have been implemented
310 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
312 .dev_configure = ixgbevf_dev_configure,
313 .dev_start = ixgbevf_dev_start,
314 .dev_stop = ixgbevf_dev_stop,
315 .link_update = ixgbe_dev_link_update,
316 .stats_get = ixgbevf_dev_stats_get,
317 .stats_reset = ixgbevf_dev_stats_reset,
318 .dev_close = ixgbevf_dev_close,
319 .dev_infos_get = ixgbe_dev_info_get,
320 .vlan_filter_set = ixgbevf_vlan_filter_set,
321 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
322 .vlan_offload_set = ixgbevf_vlan_offload_set,
323 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
324 .rx_queue_release = ixgbe_dev_rx_queue_release,
325 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
326 .tx_queue_release = ixgbe_dev_tx_queue_release,
330 * Atomically reads the link status information from global
331 * structure rte_eth_dev.
334 * - Pointer to the structure rte_eth_dev to read from.
335 * - Pointer to the buffer to be saved with the link status.
338 * - On success, zero.
339 * - On failure, negative value.
342 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
343 struct rte_eth_link *link)
345 struct rte_eth_link *dst = link;
346 struct rte_eth_link *src = &(dev->data->dev_link);
348 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
349 *(uint64_t *)src) == 0)
356 * Atomically writes the link status information into global
357 * structure rte_eth_dev.
360 * - Pointer to the structure rte_eth_dev to read from.
361 * - Pointer to the buffer to be saved with the link status.
364 * - On success, zero.
365 * - On failure, negative value.
368 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
369 struct rte_eth_link *link)
371 struct rte_eth_link *dst = &(dev->data->dev_link);
372 struct rte_eth_link *src = link;
374 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
375 *(uint64_t *)src) == 0)
382 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
385 ixgbe_is_sfp(struct ixgbe_hw *hw)
387 switch (hw->phy.type) {
388 case ixgbe_phy_sfp_avago:
389 case ixgbe_phy_sfp_ftl:
390 case ixgbe_phy_sfp_intel:
391 case ixgbe_phy_sfp_unknown:
392 case ixgbe_phy_sfp_passive_tyco:
393 case ixgbe_phy_sfp_passive_unknown:
400 static inline int32_t
401 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
406 status = ixgbe_reset_hw(hw);
408 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
409 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
410 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
411 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
412 IXGBE_WRITE_FLUSH(hw);
418 ixgbe_enable_intr(struct rte_eth_dev *dev)
420 struct ixgbe_interrupt *intr =
421 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
422 struct ixgbe_hw *hw =
423 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
425 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
426 IXGBE_WRITE_FLUSH(hw);
430 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
433 ixgbe_disable_intr(struct ixgbe_hw *hw)
435 PMD_INIT_FUNC_TRACE();
437 if (hw->mac.type == ixgbe_mac_82598EB) {
438 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
440 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
441 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
442 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
444 IXGBE_WRITE_FLUSH(hw);
448 * This function resets queue statistics mapping registers.
449 * From Niantic datasheet, Initialization of Statistics section:
450 * "...if software requires the queue counters, the RQSMR and TQSM registers
451 * must be re-programmed following a device reset.
454 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
458 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
459 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
460 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
466 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
471 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
472 #define NB_QMAP_FIELDS_PER_QSM_REG 4
473 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
475 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
476 struct ixgbe_stat_mapping_registers *stat_mappings =
477 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
478 uint32_t qsmr_mask = 0;
479 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
483 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
486 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
487 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
489 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
490 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
491 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
494 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
496 /* Now clear any previous stat_idx set */
497 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
499 stat_mappings->tqsm[n] &= ~clearing_mask;
501 stat_mappings->rqsmr[n] &= ~clearing_mask;
503 q_map = (uint32_t)stat_idx;
504 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
505 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
507 stat_mappings->tqsm[n] |= qsmr_mask;
509 stat_mappings->rqsmr[n] |= qsmr_mask;
511 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
513 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
514 is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
516 /* Now write the mapping in the appropriate register */
518 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
519 stat_mappings->rqsmr[n], n);
520 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
523 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
524 stat_mappings->tqsm[n], n);
525 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
531 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
533 struct ixgbe_stat_mapping_registers *stat_mappings =
534 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
535 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
538 /* write whatever was in stat mapping table to the NIC */
539 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
541 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
544 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
549 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
552 struct ixgbe_dcb_tc_config *tc;
553 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
555 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
556 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
557 for (i = 0; i < dcb_max_tc; i++) {
558 tc = &dcb_config->tc_config[i];
559 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
560 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
561 (uint8_t)(100/dcb_max_tc + (i & 1));
562 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
563 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
564 (uint8_t)(100/dcb_max_tc + (i & 1));
565 tc->pfc = ixgbe_dcb_pfc_disabled;
568 /* Initialize default user to priority mapping, UPx->TC0 */
569 tc = &dcb_config->tc_config[0];
570 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
571 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
572 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
573 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
574 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
576 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
577 dcb_config->pfc_mode_enable = false;
578 dcb_config->vt_mode = true;
579 dcb_config->round_robin_enable = false;
580 /* support all DCB capabilities in 82599 */
581 dcb_config->support.capabilities = 0xFF;
583 /*we only support 4 Tcs for X540*/
584 if (hw->mac.type == ixgbe_mac_X540) {
585 dcb_config->num_tcs.pg_tcs = 4;
586 dcb_config->num_tcs.pfc_tcs = 4;
591 * Ensure that all locks are released before first NVM or PHY access
594 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
599 * Phy lock should not fail in this early stage. If this is the case,
600 * it is due to an improper exit of the application.
601 * So force the release of the faulty lock. Release of common lock
602 * is done automatically by swfw_sync function.
604 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
605 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
606 DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
608 ixgbe_release_swfw_semaphore(hw, mask);
611 * These ones are more tricky since they are common to all ports; but
612 * swfw_sync retries last long enough (1s) to be almost sure that if
613 * lock can not be taken it is due to an improper lock of the
616 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
617 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
618 DEBUGOUT("SWFW common locks released");
620 ixgbe_release_swfw_semaphore(hw, mask);
624 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
625 * It returns 0 on success.
628 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
629 struct rte_eth_dev *eth_dev)
631 struct rte_pci_device *pci_dev;
632 struct ixgbe_hw *hw =
633 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
634 struct ixgbe_vfta * shadow_vfta =
635 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
636 struct ixgbe_hwstrip *hwstrip =
637 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
638 struct ixgbe_dcb_config *dcb_config =
639 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
644 PMD_INIT_FUNC_TRACE();
646 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
647 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
648 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
650 /* for secondary processes, we don't initialise any further as primary
651 * has already done this work. Only check we don't need a different
653 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
654 if (eth_dev->data->scattered_rx)
655 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
658 pci_dev = eth_dev->pci_dev;
660 /* Vendor and Device ID need to be set before init of shared code */
661 hw->device_id = pci_dev->id.device_id;
662 hw->vendor_id = pci_dev->id.vendor_id;
663 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
664 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
665 hw->allow_unsupported_sfp = 1;
668 /* Initialize the shared code */
669 #ifdef RTE_NIC_BYPASS
670 diag = ixgbe_bypass_init_shared_code(hw);
672 diag = ixgbe_init_shared_code(hw);
673 #endif /* RTE_NIC_BYPASS */
675 if (diag != IXGBE_SUCCESS) {
676 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
680 /* pick up the PCI bus settings for reporting later */
681 ixgbe_get_bus_info(hw);
683 /* Unlock any pending hardware semaphore */
684 ixgbe_swfw_lock_reset(hw);
686 /* Initialize DCB configuration*/
687 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
688 ixgbe_dcb_init(hw,dcb_config);
689 /* Get Hardware Flow Control setting */
690 hw->fc.requested_mode = ixgbe_fc_full;
691 hw->fc.current_mode = ixgbe_fc_full;
692 hw->fc.pause_time = IXGBE_FC_PAUSE;
693 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
694 hw->fc.low_water[i] = IXGBE_FC_LO;
695 hw->fc.high_water[i] = IXGBE_FC_HI;
699 /* Make sure we have a good EEPROM before we read from it */
700 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
701 if (diag != IXGBE_SUCCESS) {
702 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
706 #ifdef RTE_NIC_BYPASS
707 diag = ixgbe_bypass_init_hw(hw);
709 diag = ixgbe_init_hw(hw);
710 #endif /* RTE_NIC_BYPASS */
713 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
714 * is called too soon after the kernel driver unbinding/binding occurs.
715 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
716 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
717 * also called. See ixgbe_identify_phy_82599(). The reason for the
718 * failure is not known, and only occuts when virtualisation features
719 * are disabled in the bios. A delay of 100ms was found to be enough by
720 * trial-and-error, and is doubled to be safe.
722 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
724 diag = ixgbe_init_hw(hw);
727 if (diag == IXGBE_ERR_EEPROM_VERSION) {
728 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
729 "LOM. Please be aware there may be issues associated "
730 "with your hardware.\n If you are experiencing problems "
731 "please contact your Intel or hardware representative "
732 "who provided you with this hardware.\n");
733 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
734 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
736 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
740 /* disable interrupt */
741 ixgbe_disable_intr(hw);
743 /* reset mappings for queue statistics hw counters*/
744 ixgbe_reset_qstat_mappings(hw);
746 /* Allocate memory for storing MAC addresses */
747 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
748 hw->mac.num_rar_entries, 0);
749 if (eth_dev->data->mac_addrs == NULL) {
751 "Failed to allocate %u bytes needed to store "
753 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
756 /* Copy the permanent MAC address */
757 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
758 ð_dev->data->mac_addrs[0]);
760 /* Allocate memory for storing hash filter MAC addresses */
761 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
762 IXGBE_VMDQ_NUM_UC_MAC, 0);
763 if (eth_dev->data->hash_mac_addrs == NULL) {
765 "Failed to allocate %d bytes needed to store MAC addresses",
766 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
770 /* initialize the vfta */
771 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
773 /* initialize the hw strip bitmap*/
774 memset(hwstrip, 0, sizeof(*hwstrip));
776 /* initialize PF if max_vfs not zero */
777 ixgbe_pf_host_init(eth_dev);
779 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
780 /* let hardware know driver is loaded */
781 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
782 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
783 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
784 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
785 IXGBE_WRITE_FLUSH(hw);
787 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
789 "MAC: %d, PHY: %d, SFP+: %d<n",
790 (int) hw->mac.type, (int) hw->phy.type,
791 (int) hw->phy.sfp_type);
793 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
794 (int) hw->mac.type, (int) hw->phy.type);
796 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
797 eth_dev->data->port_id, pci_dev->id.vendor_id,
798 pci_dev->id.device_id);
800 rte_intr_callback_register(&(pci_dev->intr_handle),
801 ixgbe_dev_interrupt_handler, (void *)eth_dev);
803 /* enable uio intr after callback register */
804 rte_intr_enable(&(pci_dev->intr_handle));
806 /* enable support intr */
807 ixgbe_enable_intr(eth_dev);
812 static void ixgbevf_get_queue_num(struct ixgbe_hw *hw)
814 /* Traffic classes are not supported by now */
815 unsigned int tcs, tc;
818 * Must let PF know we are at mailbox API version 1.1.
819 * Otherwise PF won't answer properly.
820 * In case that PF fails to provide Rx/Tx queue number,
821 * max_tx_queues and max_rx_queues remain to be 1.
823 if (!ixgbevf_negotiate_api_version(hw, ixgbe_mbox_api_11))
824 ixgbevf_get_queues(hw, &tcs, &tc);
828 * Virtual Function device init
831 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
832 struct rte_eth_dev *eth_dev)
834 struct rte_pci_device *pci_dev;
835 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
837 struct ixgbe_vfta * shadow_vfta =
838 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
839 struct ixgbe_hwstrip *hwstrip =
840 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
842 PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
844 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
845 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
846 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
848 /* for secondary processes, we don't initialise any further as primary
849 * has already done this work. Only check we don't need a different
851 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
852 if (eth_dev->data->scattered_rx)
853 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
857 pci_dev = eth_dev->pci_dev;
859 hw->device_id = pci_dev->id.device_id;
860 hw->vendor_id = pci_dev->id.vendor_id;
861 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
863 /* initialize the vfta */
864 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
866 /* initialize the hw strip bitmap*/
867 memset(hwstrip, 0, sizeof(*hwstrip));
869 /* Initialize the shared code */
870 diag = ixgbe_init_shared_code(hw);
871 if (diag != IXGBE_SUCCESS) {
872 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
876 /* init_mailbox_params */
877 hw->mbx.ops.init_params(hw);
879 /* Disable the interrupts for VF */
880 ixgbevf_intr_disable(hw);
882 hw->mac.num_rar_entries = hw->mac.max_rx_queues;
883 diag = hw->mac.ops.reset_hw(hw);
885 if (diag != IXGBE_SUCCESS) {
886 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
887 RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
888 "\tThe most likely cause of this error is that the VM host\n"
889 "\thas not assigned a valid MAC address to this VF device.\n"
890 "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
891 "\ta possible solution to this problem.\n");
895 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
896 ixgbevf_get_queue_num(hw);
898 /* Allocate memory for storing MAC addresses */
899 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
900 hw->mac.num_rar_entries, 0);
901 if (eth_dev->data->mac_addrs == NULL) {
903 "Failed to allocate %u bytes needed to store "
905 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
909 /* Copy the permanent MAC address */
910 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
911 ð_dev->data->mac_addrs[0]);
913 /* reset the hardware with the new settings */
914 diag = hw->mac.ops.start_hw(hw);
920 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
924 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
925 eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
926 "ixgbe_mac_82599_vf");
931 static struct eth_driver rte_ixgbe_pmd = {
933 .name = "rte_ixgbe_pmd",
934 .id_table = pci_id_ixgbe_map,
935 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
937 .eth_dev_init = eth_ixgbe_dev_init,
938 .dev_private_size = sizeof(struct ixgbe_adapter),
942 * virtual function driver struct
944 static struct eth_driver rte_ixgbevf_pmd = {
946 .name = "rte_ixgbevf_pmd",
947 .id_table = pci_id_ixgbevf_map,
948 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
950 .eth_dev_init = eth_ixgbevf_dev_init,
951 .dev_private_size = sizeof(struct ixgbe_adapter),
955 * Driver initialization routine.
956 * Invoked once at EAL init time.
957 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
960 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
962 PMD_INIT_FUNC_TRACE();
964 rte_eth_driver_register(&rte_ixgbe_pmd);
969 * VF Driver initialization routine.
970 * Invoked one at EAL init time.
971 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
974 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
976 DEBUGFUNC("rte_ixgbevf_pmd_init");
978 rte_eth_driver_register(&rte_ixgbevf_pmd);
983 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
985 struct ixgbe_hw *hw =
986 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
987 struct ixgbe_vfta * shadow_vfta =
988 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
993 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
994 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
995 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1000 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1002 /* update local VFTA copy */
1003 shadow_vfta->vfta[vid_idx] = vfta;
1009 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1012 ixgbe_vlan_hw_strip_enable(dev, queue);
1014 ixgbe_vlan_hw_strip_disable(dev, queue);
1018 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1020 struct ixgbe_hw *hw =
1021 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1023 /* Only the high 16-bits is valid */
1024 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1028 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1030 struct ixgbe_hw *hw =
1031 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1034 PMD_INIT_FUNC_TRACE();
1036 /* Filter Table Disable */
1037 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1038 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1040 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1044 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1046 struct ixgbe_hw *hw =
1047 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1048 struct ixgbe_vfta * shadow_vfta =
1049 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1053 PMD_INIT_FUNC_TRACE();
1055 /* Filter Table Enable */
1056 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1057 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1058 vlnctrl |= IXGBE_VLNCTRL_VFE;
1060 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1062 /* write whatever is in local vfta copy */
1063 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1064 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1068 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1070 struct ixgbe_hwstrip *hwstrip =
1071 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1073 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1077 IXGBE_SET_HWSTRIP(hwstrip, queue);
1079 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1083 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1085 struct ixgbe_hw *hw =
1086 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089 PMD_INIT_FUNC_TRACE();
1091 if (hw->mac.type == ixgbe_mac_82598EB) {
1092 /* No queue level support */
1093 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1097 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1098 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1099 ctrl &= ~IXGBE_RXDCTL_VME;
1100 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1102 /* record those setting for HW strip per queue */
1103 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1107 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1109 struct ixgbe_hw *hw =
1110 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1113 PMD_INIT_FUNC_TRACE();
1115 if (hw->mac.type == ixgbe_mac_82598EB) {
1116 /* No queue level supported */
1117 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1121 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1122 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1123 ctrl |= IXGBE_RXDCTL_VME;
1124 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1126 /* record those setting for HW strip per queue */
1127 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1131 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1133 struct ixgbe_hw *hw =
1134 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1138 PMD_INIT_FUNC_TRACE();
1140 if (hw->mac.type == ixgbe_mac_82598EB) {
1141 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1142 ctrl &= ~IXGBE_VLNCTRL_VME;
1143 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1146 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1147 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1148 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1149 ctrl &= ~IXGBE_RXDCTL_VME;
1150 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1152 /* record those setting for HW strip per queue */
1153 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1159 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1161 struct ixgbe_hw *hw =
1162 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1166 PMD_INIT_FUNC_TRACE();
1168 if (hw->mac.type == ixgbe_mac_82598EB) {
1169 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1170 ctrl |= IXGBE_VLNCTRL_VME;
1171 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1174 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1175 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1176 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1177 ctrl |= IXGBE_RXDCTL_VME;
1178 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1180 /* record those setting for HW strip per queue */
1181 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1187 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1189 struct ixgbe_hw *hw =
1190 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1193 PMD_INIT_FUNC_TRACE();
1195 /* DMATXCTRL: Geric Double VLAN Disable */
1196 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1197 ctrl &= ~IXGBE_DMATXCTL_GDV;
1198 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1200 /* CTRL_EXT: Global Double VLAN Disable */
1201 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1202 ctrl &= ~IXGBE_EXTENDED_VLAN;
1203 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1208 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1210 struct ixgbe_hw *hw =
1211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1214 PMD_INIT_FUNC_TRACE();
1216 /* DMATXCTRL: Geric Double VLAN Enable */
1217 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1218 ctrl |= IXGBE_DMATXCTL_GDV;
1219 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1221 /* CTRL_EXT: Global Double VLAN Enable */
1222 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1223 ctrl |= IXGBE_EXTENDED_VLAN;
1224 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1227 * VET EXT field in the EXVET register = 0x8100 by default
1228 * So no need to change. Same to VT field of DMATXCTL register
1233 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1235 if(mask & ETH_VLAN_STRIP_MASK){
1236 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1237 ixgbe_vlan_hw_strip_enable_all(dev);
1239 ixgbe_vlan_hw_strip_disable_all(dev);
1242 if(mask & ETH_VLAN_FILTER_MASK){
1243 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1244 ixgbe_vlan_hw_filter_enable(dev);
1246 ixgbe_vlan_hw_filter_disable(dev);
1249 if(mask & ETH_VLAN_EXTEND_MASK){
1250 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1251 ixgbe_vlan_hw_extend_enable(dev);
1253 ixgbe_vlan_hw_extend_disable(dev);
1258 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1260 struct ixgbe_hw *hw =
1261 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1262 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1263 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1264 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1265 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1269 ixgbe_dev_configure(struct rte_eth_dev *dev)
1271 struct ixgbe_interrupt *intr =
1272 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1274 PMD_INIT_FUNC_TRACE();
1276 /* set flag to update link status after init */
1277 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1283 * Configure device link speed and setup link.
1284 * It returns 0 on success.
1287 ixgbe_dev_start(struct rte_eth_dev *dev)
1289 struct ixgbe_hw *hw =
1290 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291 int err, link_up = 0, negotiate = 0;
1296 PMD_INIT_FUNC_TRACE();
1298 /* IXGBE devices don't support half duplex */
1299 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1300 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1301 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1302 dev->data->dev_conf.link_duplex,
1303 dev->data->port_id);
1308 hw->adapter_stopped = FALSE;
1309 ixgbe_stop_adapter(hw);
1311 /* reinitialize adapter
1312 * this calls reset and start */
1313 status = ixgbe_pf_reset_hw(hw);
1316 hw->mac.ops.start_hw(hw);
1318 /* configure PF module if SRIOV enabled */
1319 ixgbe_pf_host_configure(dev);
1321 /* initialize transmission unit */
1322 ixgbe_dev_tx_init(dev);
1324 /* This can fail when allocating mbufs for descriptor rings */
1325 err = ixgbe_dev_rx_init(dev);
1327 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1331 ixgbe_dev_rxtx_start(dev);
1333 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1334 err = hw->mac.ops.setup_sfp(hw);
1339 /* Turn on the laser */
1340 ixgbe_enable_tx_laser(hw);
1342 /* Skip link setup if loopback mode is enabled for 82599. */
1343 if (hw->mac.type == ixgbe_mac_82599EB &&
1344 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1345 goto skip_link_setup;
1347 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1350 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1354 switch(dev->data->dev_conf.link_speed) {
1355 case ETH_LINK_SPEED_AUTONEG:
1356 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1357 IXGBE_LINK_SPEED_82599_AUTONEG :
1358 IXGBE_LINK_SPEED_82598_AUTONEG;
1360 case ETH_LINK_SPEED_100:
1362 * Invalid for 82598 but error will be detected by
1363 * ixgbe_setup_link()
1365 speed = IXGBE_LINK_SPEED_100_FULL;
1367 case ETH_LINK_SPEED_1000:
1368 speed = IXGBE_LINK_SPEED_1GB_FULL;
1370 case ETH_LINK_SPEED_10000:
1371 speed = IXGBE_LINK_SPEED_10GB_FULL;
1374 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1375 dev->data->dev_conf.link_speed,
1376 dev->data->port_id);
1380 err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1386 /* check if lsc interrupt is enabled */
1387 if (dev->data->dev_conf.intr_conf.lsc != 0)
1388 ixgbe_dev_lsc_interrupt_setup(dev);
1390 /* resume enabled intr since hw reset */
1391 ixgbe_enable_intr(dev);
1393 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1394 ETH_VLAN_EXTEND_MASK;
1395 ixgbe_vlan_offload_set(dev, mask);
1397 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1398 /* Enable vlan filtering for VMDq */
1399 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1402 /* Configure DCB hw */
1403 ixgbe_configure_dcb(dev);
1405 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1406 err = ixgbe_fdir_configure(dev);
1411 ixgbe_restore_statistics_mapping(dev);
1416 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1417 ixgbe_dev_clear_queues(dev);
1422 * Stop device: disable rx and tx functions to allow for reconfiguring.
1425 ixgbe_dev_stop(struct rte_eth_dev *dev)
1427 struct rte_eth_link link;
1428 struct ixgbe_hw *hw =
1429 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1430 struct ixgbe_vf_info *vfinfo =
1431 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1434 PMD_INIT_FUNC_TRACE();
1436 /* disable interrupts */
1437 ixgbe_disable_intr(hw);
1440 ixgbe_pf_reset_hw(hw);
1441 hw->adapter_stopped = FALSE;
1444 ixgbe_stop_adapter(hw);
1446 for (vf = 0; vfinfo != NULL &&
1447 vf < dev->pci_dev->max_vfs; vf++)
1448 vfinfo[vf].clear_to_send = false;
1450 /* Turn off the laser */
1451 ixgbe_disable_tx_laser(hw);
1453 ixgbe_dev_clear_queues(dev);
1455 /* Clear recorded link status */
1456 memset(&link, 0, sizeof(link));
1457 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1461 * Reest and stop device.
1464 ixgbe_dev_close(struct rte_eth_dev *dev)
1466 struct ixgbe_hw *hw =
1467 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1469 PMD_INIT_FUNC_TRACE();
1471 ixgbe_pf_reset_hw(hw);
1473 ixgbe_dev_stop(dev);
1474 hw->adapter_stopped = 1;
1476 ixgbe_disable_pcie_master(hw);
1478 /* reprogram the RAR[0] in case user changed it. */
1479 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1483 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1486 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1488 struct ixgbe_hw *hw =
1489 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490 struct ixgbe_hw_stats *hw_stats =
1491 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1492 uint32_t bprc, lxon, lxoff, total;
1493 uint64_t total_missed_rx, total_qbrc, total_qprc;
1496 total_missed_rx = 0;
1500 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1501 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1502 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1503 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1505 for (i = 0; i < 8; i++) {
1507 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1508 /* global total per queue */
1509 hw_stats->mpc[i] += mp;
1510 /* Running comprehensive total for stats display */
1511 total_missed_rx += hw_stats->mpc[i];
1512 if (hw->mac.type == ixgbe_mac_82598EB)
1513 hw_stats->rnbc[i] +=
1514 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1515 hw_stats->pxontxc[i] +=
1516 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1517 hw_stats->pxonrxc[i] +=
1518 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1519 hw_stats->pxofftxc[i] +=
1520 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1521 hw_stats->pxoffrxc[i] +=
1522 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1523 hw_stats->pxon2offc[i] +=
1524 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1526 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1527 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1528 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1529 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1530 hw_stats->qbrc[i] +=
1531 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1532 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1533 hw_stats->qbtc[i] +=
1534 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1535 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1537 total_qprc += hw_stats->qprc[i];
1538 total_qbrc += hw_stats->qbrc[i];
1540 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1541 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1542 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1544 /* Note that gprc counts missed packets */
1545 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1547 if (hw->mac.type != ixgbe_mac_82598EB) {
1548 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1549 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1550 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1551 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1552 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1553 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1554 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1555 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1557 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1558 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1559 /* 82598 only has a counter in the high register */
1560 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1561 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1562 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1566 * Workaround: mprc hardware is incorrectly counting
1567 * broadcasts, so for now we subtract those.
1569 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1570 hw_stats->bprc += bprc;
1571 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1572 if (hw->mac.type == ixgbe_mac_82598EB)
1573 hw_stats->mprc -= bprc;
1575 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1576 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1577 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1578 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1579 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1580 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1582 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1583 hw_stats->lxontxc += lxon;
1584 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1585 hw_stats->lxofftxc += lxoff;
1586 total = lxon + lxoff;
1588 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1589 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1590 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1591 hw_stats->gptc -= total;
1592 hw_stats->mptc -= total;
1593 hw_stats->ptc64 -= total;
1594 hw_stats->gotc -= total * ETHER_MIN_LEN;
1596 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1597 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1598 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1599 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1600 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1601 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1602 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1603 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1604 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1605 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1606 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1607 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1608 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1609 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1610 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1611 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1612 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1613 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1614 /* Only read FCOE on 82599 */
1615 if (hw->mac.type != ixgbe_mac_82598EB) {
1616 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1617 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1618 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1619 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1620 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1626 /* Fill out the rte_eth_stats statistics structure */
1627 stats->ipackets = total_qprc;
1628 stats->ibytes = total_qbrc;
1629 stats->opackets = hw_stats->gptc;
1630 stats->obytes = hw_stats->gotc;
1631 stats->imcasts = hw_stats->mprc;
1633 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1634 stats->q_ipackets[i] = hw_stats->qprc[i];
1635 stats->q_opackets[i] = hw_stats->qptc[i];
1636 stats->q_ibytes[i] = hw_stats->qbrc[i];
1637 stats->q_obytes[i] = hw_stats->qbtc[i];
1638 stats->q_errors[i] = hw_stats->qprdc[i];
1642 stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1647 /* XON/XOFF pause frames */
1648 stats->tx_pause_xon = hw_stats->lxontxc;
1649 stats->rx_pause_xon = hw_stats->lxonrxc;
1650 stats->tx_pause_xoff = hw_stats->lxofftxc;
1651 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1653 /* Flow Director Stats registers */
1654 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1655 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1656 stats->fdirmatch = hw_stats->fdirmatch;
1657 stats->fdirmiss = hw_stats->fdirmiss;
1661 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1663 struct ixgbe_hw_stats *stats =
1664 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1666 /* HW registers are cleared on read */
1667 ixgbe_dev_stats_get(dev, NULL);
1669 /* Reset software totals */
1670 memset(stats, 0, sizeof(*stats));
1674 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1676 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1678 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1680 /* Good Rx packet, include VF loopback */
1681 UPDATE_VF_STAT(IXGBE_VFGPRC,
1682 hw_stats->last_vfgprc, hw_stats->vfgprc);
1684 /* Good Rx octets, include VF loopback */
1685 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1686 hw_stats->last_vfgorc, hw_stats->vfgorc);
1688 /* Good Tx packet, include VF loopback */
1689 UPDATE_VF_STAT(IXGBE_VFGPTC,
1690 hw_stats->last_vfgptc, hw_stats->vfgptc);
1692 /* Good Tx octets, include VF loopback */
1693 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1694 hw_stats->last_vfgotc, hw_stats->vfgotc);
1696 /* Rx Multicst Packet */
1697 UPDATE_VF_STAT(IXGBE_VFMPRC,
1698 hw_stats->last_vfmprc, hw_stats->vfmprc);
1703 memset(stats, 0, sizeof(*stats));
1704 stats->ipackets = hw_stats->vfgprc;
1705 stats->ibytes = hw_stats->vfgorc;
1706 stats->opackets = hw_stats->vfgptc;
1707 stats->obytes = hw_stats->vfgotc;
1708 stats->imcasts = hw_stats->vfmprc;
1712 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1714 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1715 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1717 /* Sync HW register to the last stats */
1718 ixgbevf_dev_stats_get(dev, NULL);
1720 /* reset HW current stats*/
1721 hw_stats->vfgprc = 0;
1722 hw_stats->vfgorc = 0;
1723 hw_stats->vfgptc = 0;
1724 hw_stats->vfgotc = 0;
1725 hw_stats->vfmprc = 0;
1730 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1732 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1734 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1735 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1736 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1737 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1738 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1739 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1740 dev_info->max_vfs = dev->pci_dev->max_vfs;
1741 if (hw->mac.type == ixgbe_mac_82598EB)
1742 dev_info->max_vmdq_pools = ETH_16_POOLS;
1744 dev_info->max_vmdq_pools = ETH_64_POOLS;
1745 dev_info->rx_offload_capa =
1746 DEV_RX_OFFLOAD_VLAN_STRIP |
1747 DEV_RX_OFFLOAD_IPV4_CKSUM |
1748 DEV_RX_OFFLOAD_UDP_CKSUM |
1749 DEV_RX_OFFLOAD_TCP_CKSUM;
1750 dev_info->tx_offload_capa =
1751 DEV_TX_OFFLOAD_VLAN_INSERT |
1752 DEV_TX_OFFLOAD_IPV4_CKSUM |
1753 DEV_TX_OFFLOAD_UDP_CKSUM |
1754 DEV_TX_OFFLOAD_TCP_CKSUM |
1755 DEV_TX_OFFLOAD_SCTP_CKSUM;
1758 /* return 0 means link status changed, -1 means not changed */
1760 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1762 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1763 struct rte_eth_link link, old;
1764 ixgbe_link_speed link_speed;
1768 link.link_status = 0;
1769 link.link_speed = 0;
1770 link.link_duplex = 0;
1771 memset(&old, 0, sizeof(old));
1772 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1774 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1775 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1776 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1778 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1780 link.link_speed = ETH_LINK_SPEED_100;
1781 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1782 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1783 if (link.link_status == old.link_status)
1789 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1790 if (link.link_status == old.link_status)
1794 link.link_status = 1;
1795 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1797 switch (link_speed) {
1799 case IXGBE_LINK_SPEED_UNKNOWN:
1800 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1801 link.link_speed = ETH_LINK_SPEED_100;
1804 case IXGBE_LINK_SPEED_100_FULL:
1805 link.link_speed = ETH_LINK_SPEED_100;
1808 case IXGBE_LINK_SPEED_1GB_FULL:
1809 link.link_speed = ETH_LINK_SPEED_1000;
1812 case IXGBE_LINK_SPEED_10GB_FULL:
1813 link.link_speed = ETH_LINK_SPEED_10000;
1816 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1818 if (link.link_status == old.link_status)
1825 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1827 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1830 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1831 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1832 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1836 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1838 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1842 fctrl &= (~IXGBE_FCTRL_UPE);
1843 if (dev->data->all_multicast == 1)
1844 fctrl |= IXGBE_FCTRL_MPE;
1846 fctrl &= (~IXGBE_FCTRL_MPE);
1847 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1851 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1853 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1857 fctrl |= IXGBE_FCTRL_MPE;
1858 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1862 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1864 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1867 if (dev->data->promiscuous == 1)
1868 return; /* must remain in all_multicast mode */
1870 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1871 fctrl &= (~IXGBE_FCTRL_MPE);
1872 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1876 * It clears the interrupt causes and enables the interrupt.
1877 * It will be called once only during nic initialized.
1880 * Pointer to struct rte_eth_dev.
1883 * - On success, zero.
1884 * - On failure, a negative value.
1887 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1889 struct ixgbe_interrupt *intr =
1890 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1892 ixgbe_dev_link_status_print(dev);
1893 intr->mask |= IXGBE_EICR_LSC;
1899 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1902 * Pointer to struct rte_eth_dev.
1905 * - On success, zero.
1906 * - On failure, a negative value.
1909 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1912 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 struct ixgbe_interrupt *intr =
1914 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1916 /* clear all cause mask */
1917 ixgbe_disable_intr(hw);
1919 /* read-on-clear nic registers here */
1920 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1921 PMD_DRV_LOG(INFO, "eicr %x", eicr);
1924 if (eicr & IXGBE_EICR_LSC) {
1925 /* set flag for async link update */
1926 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1929 if (eicr & IXGBE_EICR_MAILBOX)
1930 intr->flags |= IXGBE_FLAG_MAILBOX;
1936 * It gets and then prints the link status.
1939 * Pointer to struct rte_eth_dev.
1942 * - On success, zero.
1943 * - On failure, a negative value.
1946 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1948 struct rte_eth_link link;
1950 memset(&link, 0, sizeof(link));
1951 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1952 if (link.link_status) {
1953 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1954 (int)(dev->data->port_id),
1955 (unsigned)link.link_speed,
1956 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1957 "full-duplex" : "half-duplex");
1959 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1960 (int)(dev->data->port_id));
1962 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1963 dev->pci_dev->addr.domain,
1964 dev->pci_dev->addr.bus,
1965 dev->pci_dev->addr.devid,
1966 dev->pci_dev->addr.function);
1970 * It executes link_update after knowing an interrupt occurred.
1973 * Pointer to struct rte_eth_dev.
1976 * - On success, zero.
1977 * - On failure, a negative value.
1980 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1982 struct ixgbe_interrupt *intr =
1983 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1985 struct rte_eth_link link;
1986 int intr_enable_delay = false;
1988 PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1990 if (intr->flags & IXGBE_FLAG_MAILBOX) {
1991 ixgbe_pf_mbx_process(dev);
1992 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1995 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1996 /* get the link status before link update, for predicting later */
1997 memset(&link, 0, sizeof(link));
1998 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2000 ixgbe_dev_link_update(dev, 0);
2003 if (!link.link_status)
2004 /* handle it 1 sec later, wait it being stable */
2005 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2006 /* likely to down */
2008 /* handle it 4 sec later, wait it being stable */
2009 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2011 ixgbe_dev_link_status_print(dev);
2013 intr_enable_delay = true;
2016 if (intr_enable_delay) {
2017 if (rte_eal_alarm_set(timeout * 1000,
2018 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2019 PMD_DRV_LOG(ERR, "Error setting alarm");
2021 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2022 ixgbe_enable_intr(dev);
2023 rte_intr_enable(&(dev->pci_dev->intr_handle));
2031 * Interrupt handler which shall be registered for alarm callback for delayed
2032 * handling specific interrupt to wait for the stable nic state. As the
2033 * NIC interrupt state is not stable for ixgbe after link is just down,
2034 * it needs to wait 4 seconds to get the stable status.
2037 * Pointer to interrupt handle.
2039 * The address of parameter (struct rte_eth_dev *) regsitered before.
2045 ixgbe_dev_interrupt_delayed_handler(void *param)
2047 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2048 struct ixgbe_interrupt *intr =
2049 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2050 struct ixgbe_hw *hw =
2051 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2055 if (eicr & IXGBE_EICR_MAILBOX)
2056 ixgbe_pf_mbx_process(dev);
2058 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2059 ixgbe_dev_link_update(dev, 0);
2060 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2061 ixgbe_dev_link_status_print(dev);
2062 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2065 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2066 ixgbe_enable_intr(dev);
2067 rte_intr_enable(&(dev->pci_dev->intr_handle));
2071 * Interrupt handler triggered by NIC for handling
2072 * specific interrupt.
2075 * Pointer to interrupt handle.
2077 * The address of parameter (struct rte_eth_dev *) regsitered before.
2083 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2086 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2087 ixgbe_dev_interrupt_get_status(dev);
2088 ixgbe_dev_interrupt_action(dev);
2092 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2094 struct ixgbe_hw *hw;
2096 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2097 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2101 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2103 struct ixgbe_hw *hw;
2105 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2110 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2112 struct ixgbe_hw *hw;
2114 uint32_t rx_buf_size;
2115 uint32_t max_high_water;
2117 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2124 PMD_INIT_FUNC_TRACE();
2126 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2128 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2131 * At least reserve one Ethernet frame for watermark
2132 * high_water/low_water in kilo bytes for ixgbe
2134 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2135 if ((fc_conf->high_water > max_high_water) ||
2136 (fc_conf->high_water < fc_conf->low_water)) {
2137 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2138 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2142 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2143 hw->fc.pause_time = fc_conf->pause_time;
2144 hw->fc.high_water[0] = fc_conf->high_water;
2145 hw->fc.low_water[0] = fc_conf->low_water;
2146 hw->fc.send_xon = fc_conf->send_xon;
2148 err = ixgbe_fc_enable(hw);
2150 /* Not negotiated is not an error case */
2151 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2153 /* check if we want to forward MAC frames - driver doesn't have native
2154 * capability to do that, so we'll write the registers ourselves */
2156 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2158 /* set or clear MFLCN.PMCF bit depending on configuration */
2159 if (fc_conf->mac_ctrl_frame_fwd != 0)
2160 mflcn |= IXGBE_MFLCN_PMCF;
2162 mflcn &= ~IXGBE_MFLCN_PMCF;
2164 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2165 IXGBE_WRITE_FLUSH(hw);
2170 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2175 * ixgbe_pfc_enable_generic - Enable flow control
2176 * @hw: pointer to hardware structure
2177 * @tc_num: traffic class number
2178 * Enable flow control according to the current settings.
2181 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2184 uint32_t mflcn_reg, fccfg_reg;
2186 uint32_t fcrtl, fcrth;
2190 /* Validate the water mark configuration */
2191 if (!hw->fc.pause_time) {
2192 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2196 /* Low water mark of zero causes XOFF floods */
2197 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2198 /* High/Low water can not be 0 */
2199 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2200 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2201 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2205 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2206 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2207 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2211 /* Negotiate the fc mode to use */
2212 ixgbe_fc_autoneg(hw);
2214 /* Disable any previous flow control settings */
2215 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2216 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2218 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2219 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2221 switch (hw->fc.current_mode) {
2224 * If the count of enabled RX Priority Flow control >1,
2225 * and the TX pause can not be disabled
2228 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2229 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2230 if (reg & IXGBE_FCRTH_FCEN)
2234 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2236 case ixgbe_fc_rx_pause:
2238 * Rx Flow control is enabled and Tx Flow control is
2239 * disabled by software override. Since there really
2240 * isn't a way to advertise that we are capable of RX
2241 * Pause ONLY, we will advertise that we support both
2242 * symmetric and asymmetric Rx PAUSE. Later, we will
2243 * disable the adapter's ability to send PAUSE frames.
2245 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2247 * If the count of enabled RX Priority Flow control >1,
2248 * and the TX pause can not be disabled
2251 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2252 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2253 if (reg & IXGBE_FCRTH_FCEN)
2257 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2259 case ixgbe_fc_tx_pause:
2261 * Tx Flow control is enabled, and Rx Flow control is
2262 * disabled by software override.
2264 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2267 /* Flow control (both Rx and Tx) is enabled by SW override. */
2268 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2269 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2272 DEBUGOUT("Flow control param set incorrectly\n");
2273 ret_val = IXGBE_ERR_CONFIG;
2278 /* Set 802.3x based flow control settings. */
2279 mflcn_reg |= IXGBE_MFLCN_DPF;
2280 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2281 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2283 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2284 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2285 hw->fc.high_water[tc_num]) {
2286 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2287 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2288 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2290 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2292 * In order to prevent Tx hangs when the internal Tx
2293 * switch is enabled we must set the high water mark
2294 * to the maximum FCRTH value. This allows the Tx
2295 * switch to function even under heavy Rx workloads.
2297 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2299 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2301 /* Configure pause time (2 TCs per register) */
2302 reg = hw->fc.pause_time * 0x00010001;
2303 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2304 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2306 /* Configure flow control refresh threshold value */
2307 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2314 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2316 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2319 if(hw->mac.type != ixgbe_mac_82598EB) {
2320 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2326 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2329 uint32_t rx_buf_size;
2330 uint32_t max_high_water;
2332 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2333 struct ixgbe_hw *hw =
2334 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2335 struct ixgbe_dcb_config *dcb_config =
2336 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2338 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2345 PMD_INIT_FUNC_TRACE();
2347 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2348 tc_num = map[pfc_conf->priority];
2349 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2350 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2352 * At least reserve one Ethernet frame for watermark
2353 * high_water/low_water in kilo bytes for ixgbe
2355 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2356 if ((pfc_conf->fc.high_water > max_high_water) ||
2357 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2358 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2359 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2363 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2364 hw->fc.pause_time = pfc_conf->fc.pause_time;
2365 hw->fc.send_xon = pfc_conf->fc.send_xon;
2366 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2367 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2369 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2371 /* Not negotiated is not an error case */
2372 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2375 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2380 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2381 struct rte_eth_rss_reta *reta_conf)
2385 struct ixgbe_hw *hw =
2386 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388 PMD_INIT_FUNC_TRACE();
2390 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2391 * 128-entries in 32 registers
2393 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2394 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2395 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2397 mask = (uint8_t)((reta_conf->mask_hi >>
2398 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2402 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2404 for (j = 0; j < 4; j++) {
2405 if (mask & (0x1 << j)) {
2407 reta &= ~(0xFF << 8 * j);
2408 reta |= reta_conf->reta[i + j] << 8*j;
2411 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2419 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2420 struct rte_eth_rss_reta *reta_conf)
2424 struct ixgbe_hw *hw =
2425 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427 PMD_INIT_FUNC_TRACE();
2429 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2430 * 128-entries in 32 registers
2432 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2433 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2434 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2436 mask = (uint8_t)((reta_conf->mask_hi >>
2437 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2440 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2441 for (j = 0; j < 4; j++) {
2442 if (mask & (0x1 << j))
2443 reta_conf->reta[i + j] =
2444 (uint8_t)((reta >> 8 * j) & 0xFF);
2453 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2454 uint32_t index, uint32_t pool)
2456 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457 uint32_t enable_addr = 1;
2459 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2463 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2465 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2467 ixgbe_clear_rar(hw, index);
2471 * Virtual Function operations
2474 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2476 PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2478 /* Clear interrupt mask to stop from interrupts being generated */
2479 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2481 IXGBE_WRITE_FLUSH(hw);
2485 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2487 struct rte_eth_conf* conf = &dev->data->dev_conf;
2489 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2490 dev->data->port_id);
2493 * VF has no ability to enable/disable HW CRC
2494 * Keep the persistent behavior the same as Host PF
2496 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2497 if (!conf->rxmode.hw_strip_crc) {
2498 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2499 conf->rxmode.hw_strip_crc = 1;
2502 if (conf->rxmode.hw_strip_crc) {
2503 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2504 conf->rxmode.hw_strip_crc = 0;
2512 ixgbevf_dev_start(struct rte_eth_dev *dev)
2514 struct ixgbe_hw *hw =
2515 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2520 hw->mac.ops.reset_hw(hw);
2522 ixgbevf_dev_tx_init(dev);
2524 /* This can fail when allocating mbufs for descriptor rings */
2525 err = ixgbevf_dev_rx_init(dev);
2527 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2528 ixgbe_dev_clear_queues(dev);
2533 ixgbevf_set_vfta_all(dev,1);
2536 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2537 ETH_VLAN_EXTEND_MASK;
2538 ixgbevf_vlan_offload_set(dev, mask);
2540 ixgbevf_dev_rxtx_start(dev);
2546 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2548 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2550 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2552 hw->adapter_stopped = TRUE;
2553 ixgbe_stop_adapter(hw);
2556 * Clear what we set, but we still keep shadow_vfta to
2557 * restore after device starts
2559 ixgbevf_set_vfta_all(dev,0);
2561 ixgbe_dev_clear_queues(dev);
2565 ixgbevf_dev_close(struct rte_eth_dev *dev)
2567 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2573 ixgbevf_dev_stop(dev);
2575 /* reprogram the RAR[0] in case user changed it. */
2576 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2579 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2581 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2582 struct ixgbe_vfta * shadow_vfta =
2583 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2584 int i = 0, j = 0, vfta = 0, mask = 1;
2586 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2587 vfta = shadow_vfta->vfta[i];
2590 for (j = 0; j < 32; j++){
2592 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2601 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2603 struct ixgbe_hw *hw =
2604 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605 struct ixgbe_vfta * shadow_vfta =
2606 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2607 uint32_t vid_idx = 0;
2608 uint32_t vid_bit = 0;
2611 PMD_INIT_FUNC_TRACE();
2613 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2614 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2616 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2619 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2620 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2622 /* Save what we set and retore it after device reset */
2624 shadow_vfta->vfta[vid_idx] |= vid_bit;
2626 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2632 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2634 struct ixgbe_hw *hw =
2635 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2638 PMD_INIT_FUNC_TRACE();
2640 if(queue >= hw->mac.max_rx_queues)
2643 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2645 ctrl |= IXGBE_RXDCTL_VME;
2647 ctrl &= ~IXGBE_RXDCTL_VME;
2648 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2650 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2654 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2656 struct ixgbe_hw *hw =
2657 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2661 /* VF function only support hw strip feature, others are not support */
2662 if(mask & ETH_VLAN_STRIP_MASK){
2663 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2665 for(i=0; i < hw->mac.max_rx_queues; i++)
2666 ixgbevf_vlan_strip_queue_set(dev,i,on);
2671 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2675 /* we only need to do this if VMDq is enabled */
2676 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2677 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2678 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2686 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2688 uint32_t vector = 0;
2689 switch (hw->mac.mc_filter_type) {
2690 case 0: /* use bits [47:36] of the address */
2691 vector = ((uc_addr->addr_bytes[4] >> 4) |
2692 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2694 case 1: /* use bits [46:35] of the address */
2695 vector = ((uc_addr->addr_bytes[4] >> 3) |
2696 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2698 case 2: /* use bits [45:34] of the address */
2699 vector = ((uc_addr->addr_bytes[4] >> 2) |
2700 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2702 case 3: /* use bits [43:32] of the address */
2703 vector = ((uc_addr->addr_bytes[4]) |
2704 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2706 default: /* Invalid mc_filter_type */
2710 /* vector can only be 12-bits or boundary will be exceeded */
2716 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2724 const uint32_t ixgbe_uta_idx_mask = 0x7F;
2725 const uint32_t ixgbe_uta_bit_shift = 5;
2726 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2727 const uint32_t bit1 = 0x1;
2729 struct ixgbe_hw *hw =
2730 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2731 struct ixgbe_uta_info *uta_info =
2732 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2734 /* The UTA table only exists on 82599 hardware and newer */
2735 if (hw->mac.type < ixgbe_mac_82599EB)
2738 vector = ixgbe_uta_vector(hw,mac_addr);
2739 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2740 uta_shift = vector & ixgbe_uta_bit_mask;
2742 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2746 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2748 uta_info->uta_in_use++;
2749 reg_val |= (bit1 << uta_shift);
2750 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2752 uta_info->uta_in_use--;
2753 reg_val &= ~(bit1 << uta_shift);
2754 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2757 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2759 if (uta_info->uta_in_use > 0)
2760 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2761 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2763 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2769 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2772 struct ixgbe_hw *hw =
2773 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774 struct ixgbe_uta_info *uta_info =
2775 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2777 /* The UTA table only exists on 82599 hardware and newer */
2778 if (hw->mac.type < ixgbe_mac_82599EB)
2782 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2783 uta_info->uta_shadow[i] = ~0;
2784 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2787 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2788 uta_info->uta_shadow[i] = 0;
2789 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2796 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2797 uint16_t rx_mask, uint8_t on)
2801 struct ixgbe_hw *hw =
2802 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2805 if (hw->mac.type == ixgbe_mac_82598EB) {
2806 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2807 " on 82599 hardware and newer\n");
2810 if (ixgbe_vmdq_mode_check(hw) < 0)
2813 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2814 val |= IXGBE_VMOLR_AUPE;
2815 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2816 val |= IXGBE_VMOLR_ROMPE;
2817 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2818 val |= IXGBE_VMOLR_ROPE;
2819 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2820 val |= IXGBE_VMOLR_BAM;
2821 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2822 val |= IXGBE_VMOLR_MPE;
2829 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2835 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2839 const uint8_t bit1 = 0x1;
2841 struct ixgbe_hw *hw =
2842 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844 if (ixgbe_vmdq_mode_check(hw) < 0)
2847 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2848 reg = IXGBE_READ_REG(hw, addr);
2856 IXGBE_WRITE_REG(hw, addr,reg);
2862 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2866 const uint8_t bit1 = 0x1;
2868 struct ixgbe_hw *hw =
2869 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871 if (ixgbe_vmdq_mode_check(hw) < 0)
2874 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2875 reg = IXGBE_READ_REG(hw, addr);
2883 IXGBE_WRITE_REG(hw, addr,reg);
2889 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2890 uint64_t pool_mask, uint8_t vlan_on)
2894 struct ixgbe_hw *hw =
2895 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897 if (ixgbe_vmdq_mode_check(hw) < 0)
2899 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2900 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2901 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2910 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2911 struct rte_eth_vmdq_mirror_conf *mirror_conf,
2912 uint8_t rule_id, uint8_t on)
2914 uint32_t mr_ctl,vlvf;
2915 uint32_t mp_lsb = 0;
2916 uint32_t mv_msb = 0;
2917 uint32_t mv_lsb = 0;
2918 uint32_t mp_msb = 0;
2921 uint64_t vlan_mask = 0;
2923 const uint8_t pool_mask_offset = 32;
2924 const uint8_t vlan_mask_offset = 32;
2925 const uint8_t dst_pool_offset = 8;
2926 const uint8_t rule_mr_offset = 4;
2927 const uint8_t mirror_rule_mask= 0x0F;
2929 struct ixgbe_mirror_info *mr_info =
2930 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2931 struct ixgbe_hw *hw =
2932 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934 if (ixgbe_vmdq_mode_check(hw) < 0)
2937 /* Check if vlan mask is valid */
2938 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2939 if (mirror_conf->vlan.vlan_mask == 0)
2943 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2944 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2945 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2946 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2947 /* search vlan id related pool vlan filter index */
2948 reg_index = ixgbe_find_vlvf_slot(hw,
2949 mirror_conf->vlan.vlan_id[i]);
2952 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2953 if ((vlvf & IXGBE_VLVF_VIEN) &&
2954 ((vlvf & IXGBE_VLVF_VLANID_MASK)
2955 == mirror_conf->vlan.vlan_id[i]))
2956 vlan_mask |= (1ULL << reg_index);
2963 mv_lsb = vlan_mask & 0xFFFFFFFF;
2964 mv_msb = vlan_mask >> vlan_mask_offset;
2966 mr_info->mr_conf[rule_id].vlan.vlan_mask =
2967 mirror_conf->vlan.vlan_mask;
2968 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2969 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2970 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2971 mirror_conf->vlan.vlan_id[i];
2976 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
2977 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
2978 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
2983 * if enable pool mirror, write related pool mask register,if disable
2984 * pool mirror, clear PFMRVM register
2986 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2988 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
2989 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
2990 mr_info->mr_conf[rule_id].pool_mask =
2991 mirror_conf->pool_mask;
2996 mr_info->mr_conf[rule_id].pool_mask = 0;
3000 /* read mirror control register and recalculate it */
3001 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3004 mr_ctl |= mirror_conf->rule_type_mask;
3005 mr_ctl &= mirror_rule_mask;
3006 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3008 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3010 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3011 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3013 /* write mirrror control register */
3014 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3016 /* write pool mirrror control register */
3017 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3018 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3019 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3022 /* write VLAN mirrror control register */
3023 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3024 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3025 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3033 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3036 uint32_t lsb_val = 0;
3037 uint32_t msb_val = 0;
3038 const uint8_t rule_mr_offset = 4;
3040 struct ixgbe_hw *hw =
3041 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3042 struct ixgbe_mirror_info *mr_info =
3043 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3045 if (ixgbe_vmdq_mode_check(hw) < 0)
3048 memset(&mr_info->mr_conf[rule_id], 0,
3049 sizeof(struct rte_eth_vmdq_mirror_conf));
3051 /* clear PFVMCTL register */
3052 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3054 /* clear pool mask register */
3055 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3056 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3058 /* clear vlan mask register */
3059 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3060 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3065 static struct rte_driver rte_ixgbe_driver = {
3067 .init = rte_ixgbe_pmd_init,
3070 static struct rte_driver rte_ixgbevf_driver = {
3072 .init = rte_ixgbevf_pmd_init,
3075 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3076 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);