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35 #include <sys/queue.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
63 #include "ixgbe_logs.h"
64 #include "ixgbe/ixgbe_api.h"
65 #include "ixgbe/ixgbe_vf.h"
66 #include "ixgbe/ixgbe_common.h"
67 #include "ixgbe_ethdev.h"
70 * High threshold controlling when to start sending XOFF frames. Must be at
71 * least 8 bytes less than receive packet buffer size. This value is in units
74 #define IXGBE_FC_HI 0x80
77 * Low threshold controlling when to start sending XON frames. This value is
78 * in units of 1024 bytes.
80 #define IXGBE_FC_LO 0x40
82 /* Timer value included in XOFF frames. */
83 #define IXGBE_FC_PAUSE 0x680
85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
86 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
88 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
90 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
91 struct rte_eth_dev *eth_dev);
92 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
93 static int ixgbe_dev_start(struct rte_eth_dev *dev);
94 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
95 static void ixgbe_dev_close(struct rte_eth_dev *dev);
96 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
97 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
98 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
99 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
100 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
101 int wait_to_complete);
102 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
103 struct rte_eth_stats *stats);
104 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
105 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
109 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
110 struct rte_eth_dev_info *dev_info);
111 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
112 uint16_t vlan_id, int on);
113 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
114 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
115 uint16_t queue, bool on);
116 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
118 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
119 static void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
120 static void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
121 static void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
122 static void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
123 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
124 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
125 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
126 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
128 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
129 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
130 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
131 struct rte_eth_fc_conf *fc_conf);
132 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
133 struct rte_eth_pfc_conf *pfc_conf);
134 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
135 static int ixgbe_dev_interrupt_setup(struct rte_eth_dev *dev);
136 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
137 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
138 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
140 static void ixgbe_dev_interrupt_delayed_handler(void *param);
141 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
142 uint32_t index, uint32_t pool);
143 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
144 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
146 /* For Virtual Function support */
147 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
148 struct rte_eth_dev *eth_dev);
149 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
150 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
151 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
152 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
153 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
154 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
155 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
156 uint16_t vlan_id, int on);
157 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
158 uint16_t queue, int on);
159 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
160 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
164 * * Define VF Stats MACRO for Non "cleared on read" register
166 #define UPDATE_VF_STAT(reg, last, cur) \
168 u32 latest = IXGBE_READ_REG(hw, reg); \
169 cur += latest - last; \
173 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
175 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
176 u64 new_msb = IXGBE_READ_REG(hw, msb); \
177 u64 latest = ((new_msb << 32) | new_lsb); \
178 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
182 #define IXGBE_SET_HWSTRIP(h, q) do{\
183 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
184 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
185 (h)->bitmap[idx] |= 1 << bit;\
188 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
189 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
190 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
191 (h)->bitmap[idx] &= ~(1 << bit);\
194 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
195 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
196 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
197 (r) = (h)->bitmap[idx] >> bit & 1;\
201 * The set of PCI devices this driver supports
203 static struct rte_pci_id pci_id_ixgbe_map[] = {
205 #undef RTE_LIBRTE_IGB_PMD
206 #define RTE_PCI_DEV_ID_DECL(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
207 #include "rte_pci_dev_ids.h"
209 { .vendor_id = 0, /* sentinel */ },
214 * The set of PCI devices this driver supports (for 82599 VF)
216 static struct rte_pci_id pci_id_ixgbevf_map[] = {
218 .vendor_id = PCI_VENDOR_ID_INTEL,
219 .device_id = IXGBE_DEV_ID_82599_VF,
220 .subsystem_vendor_id = PCI_ANY_ID,
221 .subsystem_device_id = PCI_ANY_ID,
223 { .vendor_id = 0, /* sentinel */ },
226 static struct eth_dev_ops ixgbe_eth_dev_ops = {
227 .dev_configure = ixgbe_dev_configure,
228 .dev_start = ixgbe_dev_start,
229 .dev_stop = ixgbe_dev_stop,
230 .dev_close = ixgbe_dev_close,
231 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
232 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
233 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
234 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
235 .link_update = ixgbe_dev_link_update,
236 .stats_get = ixgbe_dev_stats_get,
237 .stats_reset = ixgbe_dev_stats_reset,
238 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
239 .dev_infos_get = ixgbe_dev_info_get,
240 .vlan_filter_set = ixgbe_vlan_filter_set,
241 .vlan_tpid_set = ixgbe_vlan_tpid_set,
242 .vlan_offload_set = ixgbe_vlan_offload_set,
243 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
244 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
245 .rx_queue_release = ixgbe_dev_rx_queue_release,
246 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
247 .tx_queue_release = ixgbe_dev_tx_queue_release,
248 .dev_led_on = ixgbe_dev_led_on,
249 .dev_led_off = ixgbe_dev_led_off,
250 .flow_ctrl_set = ixgbe_flow_ctrl_set,
251 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
252 .mac_addr_add = ixgbe_add_rar,
253 .mac_addr_remove = ixgbe_remove_rar,
254 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
255 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
256 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
257 .fdir_infos_get = ixgbe_fdir_info_get,
258 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
259 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
260 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
261 .fdir_set_masks = ixgbe_fdir_set_masks,
265 * dev_ops for virtual function, bare necessities for basic vf
266 * operation have been implemented
268 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
270 .dev_configure = ixgbevf_dev_configure,
271 .dev_start = ixgbevf_dev_start,
272 .dev_stop = ixgbevf_dev_stop,
273 .link_update = ixgbe_dev_link_update,
274 .stats_get = ixgbevf_dev_stats_get,
275 .stats_reset = ixgbevf_dev_stats_reset,
276 .dev_close = ixgbevf_dev_stop,
278 .dev_infos_get = ixgbe_dev_info_get,
279 .vlan_filter_set = ixgbevf_vlan_filter_set,
280 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
281 .vlan_offload_set = ixgbevf_vlan_offload_set,
282 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
283 .rx_queue_release = ixgbe_dev_rx_queue_release,
284 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
285 .tx_queue_release = ixgbe_dev_tx_queue_release,
289 * Atomically reads the link status information from global
290 * structure rte_eth_dev.
293 * - Pointer to the structure rte_eth_dev to read from.
294 * - Pointer to the buffer to be saved with the link status.
297 * - On success, zero.
298 * - On failure, negative value.
301 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
302 struct rte_eth_link *link)
304 struct rte_eth_link *dst = link;
305 struct rte_eth_link *src = &(dev->data->dev_link);
307 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
308 *(uint64_t *)src) == 0)
315 * Atomically writes the link status information into global
316 * structure rte_eth_dev.
319 * - Pointer to the structure rte_eth_dev to read from.
320 * - Pointer to the buffer to be saved with the link status.
323 * - On success, zero.
324 * - On failure, negative value.
327 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
328 struct rte_eth_link *link)
330 struct rte_eth_link *dst = &(dev->data->dev_link);
331 struct rte_eth_link *src = link;
333 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
334 *(uint64_t *)src) == 0)
341 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
344 ixgbe_is_sfp(struct ixgbe_hw *hw)
346 switch (hw->phy.type) {
347 case ixgbe_phy_sfp_avago:
348 case ixgbe_phy_sfp_ftl:
349 case ixgbe_phy_sfp_intel:
350 case ixgbe_phy_sfp_unknown:
351 case ixgbe_phy_sfp_passive_tyco:
352 case ixgbe_phy_sfp_passive_unknown:
360 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
363 ixgbe_disable_intr(struct ixgbe_hw *hw)
365 PMD_INIT_FUNC_TRACE();
367 if (hw->mac.type == ixgbe_mac_82598EB) {
368 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
370 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
371 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
372 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
374 IXGBE_WRITE_FLUSH(hw);
378 * This function resets queue statistics mapping registers.
379 * From Niantic datasheet, Initialization of Statistics section:
380 * "...if software requires the queue counters, the RQSMR and TQSM registers
381 * must be re-programmed following a device reset.
384 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
388 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
389 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
390 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
396 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
401 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
402 #define NB_QMAP_FIELDS_PER_QSM_REG 4
403 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
405 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
406 struct ixgbe_stat_mapping_registers *stat_mappings =
407 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
408 uint32_t qsmr_mask = 0;
409 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
413 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
416 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
417 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
419 n = queue_id / NB_QMAP_FIELDS_PER_QSM_REG;
420 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
421 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
424 offset = queue_id % NB_QMAP_FIELDS_PER_QSM_REG;
426 /* Now clear any previous stat_idx set */
427 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
429 stat_mappings->tqsm[n] &= ~clearing_mask;
431 stat_mappings->rqsmr[n] &= ~clearing_mask;
433 q_map = (uint32_t)stat_idx;
434 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
435 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
437 stat_mappings->tqsm[n] |= qsmr_mask;
439 stat_mappings->rqsmr[n] |= qsmr_mask;
441 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
443 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
444 is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
446 /* Now write the mapping in the appropriate register */
448 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
449 stat_mappings->rqsmr[n], n);
450 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
453 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
454 stat_mappings->tqsm[n], n);
455 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
461 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
463 struct ixgbe_stat_mapping_registers *stat_mappings =
464 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
465 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
468 /* write whatever was in stat mapping table to the NIC */
469 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
471 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
474 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
479 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
482 struct ixgbe_dcb_tc_config *tc;
483 int dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
485 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
486 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
487 for (i = 0; i < dcb_max_tc; i++) {
488 tc = &dcb_config->tc_config[i];
489 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
490 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 100/dcb_max_tc + (i & 1);
491 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
492 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 100/dcb_max_tc + (i & 1);
493 tc->pfc = ixgbe_dcb_pfc_disabled;
496 /* Initialize default user to priority mapping, UPx->TC0 */
497 tc = &dcb_config->tc_config[0];
498 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
499 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
500 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
501 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
502 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
504 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
505 dcb_config->pfc_mode_enable = false;
506 dcb_config->vt_mode = true;
507 dcb_config->round_robin_enable = false;
508 /* support all DCB capabilities in 82599 */
509 dcb_config->support.capabilities = 0xFF;
511 /*we only support 4 Tcs for X540*/
512 if (hw->mac.type == ixgbe_mac_X540) {
513 dcb_config->num_tcs.pg_tcs = 4;
514 dcb_config->num_tcs.pfc_tcs = 4;
519 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
520 * It returns 0 on success.
523 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
524 struct rte_eth_dev *eth_dev)
526 struct rte_pci_device *pci_dev;
527 struct ixgbe_hw *hw =
528 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
529 struct ixgbe_vfta * shadow_vfta =
530 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
531 struct ixgbe_hwstrip *hwstrip =
532 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
533 struct ixgbe_dcb_config *dcb_config =
534 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
539 PMD_INIT_FUNC_TRACE();
541 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
542 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
543 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
545 /* for secondary processes, we don't initialise any further as primary
546 * has already done this work. Only check we don't need a different
548 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
549 if (eth_dev->data->scattered_rx)
550 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
553 pci_dev = eth_dev->pci_dev;
555 /* Vendor and Device ID need to be set before init of shared code */
556 hw->device_id = pci_dev->id.device_id;
557 hw->vendor_id = pci_dev->id.vendor_id;
558 hw->hw_addr = (void *)pci_dev->mem_resource.addr;
560 /* Initialize the shared code */
561 diag = ixgbe_init_shared_code(hw);
562 if (diag != IXGBE_SUCCESS) {
563 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
567 /* Initialize DCB configuration*/
568 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
569 ixgbe_dcb_init(hw,dcb_config);
570 /* Get Hardware Flow Control setting */
571 hw->fc.requested_mode = ixgbe_fc_full;
572 hw->fc.current_mode = ixgbe_fc_full;
573 hw->fc.pause_time = IXGBE_FC_PAUSE;
574 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
575 hw->fc.low_water[i] = IXGBE_FC_LO;
576 hw->fc.high_water[i] = IXGBE_FC_HI;
580 ixgbe_disable_intr(hw);
582 /* Make sure we have a good EEPROM before we read from it */
583 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
584 if (diag != IXGBE_SUCCESS) {
585 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
589 diag = ixgbe_init_hw(hw);
592 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
593 * is called too soon after the kernel driver unbinding/binding occurs.
594 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
595 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
596 * also called. See ixgbe_identify_phy_82599(). The reason for the
597 * failure is not known, and only occuts when virtualisation features
598 * are disabled in the bios. A delay of 100ms was found to be enough by
599 * trial-and-error, and is doubled to be safe.
601 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
603 diag = ixgbe_init_hw(hw);
606 if (diag == IXGBE_ERR_EEPROM_VERSION) {
607 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
608 "LOM. Please be aware there may be issues associated "
609 "with your hardware.\n If you are experiencing problems "
610 "please contact your Intel or hardware representative "
611 "who provided you with this hardware.\n");
612 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
613 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
615 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
619 /* pick up the PCI bus settings for reporting later */
620 ixgbe_get_bus_info(hw);
622 /* reset mappings for queue statistics hw counters*/
623 ixgbe_reset_qstat_mappings(hw);
625 /* Allocate memory for storing MAC addresses */
626 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
627 hw->mac.num_rar_entries, 0);
628 if (eth_dev->data->mac_addrs == NULL) {
630 "Failed to allocate %d bytes needed to store MAC addresses",
631 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
634 /* Copy the permanent MAC address */
635 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
636 ð_dev->data->mac_addrs[0]);
638 /* initialize the vfta */
639 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
641 /* initialize the hw strip bitmap*/
642 memset(hwstrip, 0, sizeof(*hwstrip));
644 /* let hardware know driver is loaded */
645 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
646 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
647 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
649 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
651 "MAC: %d, PHY: %d, SFP+: %d<n",
652 (int) hw->mac.type, (int) hw->phy.type,
653 (int) hw->phy.sfp_type);
655 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
656 (int) hw->mac.type, (int) hw->phy.type);
658 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
659 eth_dev->data->port_id, pci_dev->id.vendor_id,
660 pci_dev->id.device_id);
662 rte_intr_callback_register(&(pci_dev->intr_handle),
663 ixgbe_dev_interrupt_handler, (void *)eth_dev);
669 * Virtual Function device init
672 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
673 struct rte_eth_dev *eth_dev)
675 struct rte_pci_device *pci_dev;
676 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
678 struct ixgbe_vfta * shadow_vfta =
679 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
680 struct ixgbe_hwstrip *hwstrip =
681 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
683 PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
685 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
686 pci_dev = eth_dev->pci_dev;
688 hw->device_id = pci_dev->id.device_id;
689 hw->vendor_id = pci_dev->id.vendor_id;
690 hw->hw_addr = (void *)pci_dev->mem_resource.addr;
692 /* initialize the vfta */
693 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
695 /* initialize the hw strip bitmap*/
696 memset(hwstrip, 0, sizeof(*hwstrip));
698 /* Initialize the shared code */
699 diag = ixgbe_init_shared_code(hw);
700 if (diag != IXGBE_SUCCESS) {
701 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
705 /* init_mailbox_params */
706 hw->mbx.ops.init_params(hw);
708 /* Disable the interrupts for VF */
709 ixgbevf_intr_disable(hw);
711 hw->mac.num_rar_entries = hw->mac.max_rx_queues;
712 diag = hw->mac.ops.reset_hw(hw);
714 /* Allocate memory for storing MAC addresses */
715 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
716 hw->mac.num_rar_entries, 0);
717 if (eth_dev->data->mac_addrs == NULL) {
719 "Failed to allocate %d bytes needed to store MAC addresses",
720 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
723 /* Copy the permanent MAC address */
724 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
725 ð_dev->data->mac_addrs[0]);
727 /* reset the hardware with the new settings */
728 diag = hw->mac.ops.start_hw(hw);
734 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
738 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
739 eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
740 "ixgbe_mac_82599_vf");
745 static struct eth_driver rte_ixgbe_pmd = {
747 .name = "rte_ixgbe_pmd",
748 .id_table = pci_id_ixgbe_map,
749 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
751 .eth_dev_init = eth_ixgbe_dev_init,
752 .dev_private_size = sizeof(struct ixgbe_adapter),
756 * virtual function driver struct
758 static struct eth_driver rte_ixgbevf_pmd = {
760 .name = "rte_ixgbevf_pmd",
761 .id_table = pci_id_ixgbevf_map,
762 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
764 .eth_dev_init = eth_ixgbevf_dev_init,
765 .dev_private_size = sizeof(struct ixgbe_adapter),
769 * Driver initialization routine.
770 * Invoked once at EAL init time.
771 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
774 rte_ixgbe_pmd_init(void)
776 PMD_INIT_FUNC_TRACE();
778 rte_eth_driver_register(&rte_ixgbe_pmd);
783 * VF Driver initialization routine.
784 * Invoked one at EAL init time.
785 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
788 rte_ixgbevf_pmd_init(void)
790 DEBUGFUNC("rte_ixgbevf_pmd_init");
792 rte_eth_driver_register(&rte_ixgbevf_pmd);
797 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
799 struct ixgbe_hw *hw =
800 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
801 struct ixgbe_vfta * shadow_vfta =
802 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
807 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
808 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
809 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
814 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
816 /* update local VFTA copy */
817 shadow_vfta->vfta[vid_idx] = vfta;
823 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
826 ixgbe_vlan_hw_strip_enable(dev, queue);
828 ixgbe_vlan_hw_strip_disable(dev, queue);
832 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
834 struct ixgbe_hw *hw =
835 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
837 /* Only the high 16-bits is valid */
838 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
842 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
844 struct ixgbe_hw *hw =
845 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
848 PMD_INIT_FUNC_TRACE();
850 /* Filter Table Disable */
851 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
852 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
854 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
858 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
860 struct ixgbe_hw *hw =
861 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
862 struct ixgbe_vfta * shadow_vfta =
863 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
867 PMD_INIT_FUNC_TRACE();
869 /* Filter Table Enable */
870 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
871 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
872 vlnctrl |= IXGBE_VLNCTRL_VFE;
874 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
876 /* write whatever is in local vfta copy */
877 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
878 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
882 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
884 struct ixgbe_hwstrip *hwstrip =
885 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
887 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
891 IXGBE_SET_HWSTRIP(hwstrip, queue);
893 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
897 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
899 struct ixgbe_hw *hw =
900 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
903 PMD_INIT_FUNC_TRACE();
905 if (hw->mac.type == ixgbe_mac_82598EB) {
906 /* No queue level support */
907 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
911 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
912 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
913 ctrl &= ~IXGBE_RXDCTL_VME;
914 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
916 /* record those setting for HW strip per queue */
917 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
921 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
923 struct ixgbe_hw *hw =
924 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
927 PMD_INIT_FUNC_TRACE();
929 if (hw->mac.type == ixgbe_mac_82598EB) {
930 /* No queue level supported */
931 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
935 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
936 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
937 ctrl |= IXGBE_RXDCTL_VME;
938 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
940 /* record those setting for HW strip per queue */
941 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
945 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
947 struct ixgbe_hw *hw =
948 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
952 PMD_INIT_FUNC_TRACE();
954 if (hw->mac.type == ixgbe_mac_82598EB) {
955 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
956 ctrl &= ~IXGBE_VLNCTRL_VME;
957 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
960 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
961 for (i = 0; i < dev->data->nb_rx_queues; i++) {
962 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
963 ctrl &= ~IXGBE_RXDCTL_VME;
964 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
966 /* record those setting for HW strip per queue */
967 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
973 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
975 struct ixgbe_hw *hw =
976 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
980 PMD_INIT_FUNC_TRACE();
982 if (hw->mac.type == ixgbe_mac_82598EB) {
983 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
984 ctrl |= IXGBE_VLNCTRL_VME;
985 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
988 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
989 for (i = 0; i < dev->data->nb_rx_queues; i++) {
990 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
991 ctrl |= IXGBE_RXDCTL_VME;
992 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
994 /* record those setting for HW strip per queue */
995 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1001 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1003 struct ixgbe_hw *hw =
1004 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1007 PMD_INIT_FUNC_TRACE();
1009 /* DMATXCTRL: Geric Double VLAN Disable */
1010 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1011 ctrl &= ~IXGBE_DMATXCTL_GDV;
1012 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1014 /* CTRL_EXT: Global Double VLAN Disable */
1015 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1016 ctrl &= ~IXGBE_EXTENDED_VLAN;
1017 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1022 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1024 struct ixgbe_hw *hw =
1025 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1028 PMD_INIT_FUNC_TRACE();
1030 /* DMATXCTRL: Geric Double VLAN Enable */
1031 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1032 ctrl |= IXGBE_DMATXCTL_GDV;
1033 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1035 /* CTRL_EXT: Global Double VLAN Enable */
1036 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1037 ctrl |= IXGBE_EXTENDED_VLAN;
1038 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1041 * VET EXT field in the EXVET register = 0x8100 by default
1042 * So no need to change. Same to VT field of DMATXCTL register
1047 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1049 if(mask & ETH_VLAN_STRIP_MASK){
1050 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1051 ixgbe_vlan_hw_strip_enable_all(dev);
1053 ixgbe_vlan_hw_strip_disable_all(dev);
1056 if(mask & ETH_VLAN_FILTER_MASK){
1057 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1058 ixgbe_vlan_hw_filter_enable(dev);
1060 ixgbe_vlan_hw_filter_disable(dev);
1063 if(mask & ETH_VLAN_EXTEND_MASK){
1064 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1065 ixgbe_vlan_hw_extend_enable(dev);
1067 ixgbe_vlan_hw_extend_disable(dev);
1072 ixgbe_dev_configure(struct rte_eth_dev *dev)
1074 struct ixgbe_interrupt *intr =
1075 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1077 PMD_INIT_FUNC_TRACE();
1079 /* set flag to update link status after init */
1080 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1086 * Configure device link speed and setup link.
1087 * It returns 0 on success.
1090 ixgbe_dev_start(struct rte_eth_dev *dev)
1092 struct ixgbe_hw *hw =
1093 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1094 int err, link_up = 0, negotiate = 0;
1097 PMD_INIT_FUNC_TRACE();
1099 /* IXGBE devices don't support half duplex */
1100 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1101 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1102 PMD_INIT_LOG(ERR, "Invalid link_duplex (%u) for port %u\n",
1103 dev->data->dev_conf.link_duplex,
1104 dev->data->port_id);
1109 hw->adapter_stopped = FALSE;
1110 ixgbe_stop_adapter(hw);
1112 /* reinitialize adapter
1113 * this calls reset and start */
1116 /* initialize transmission unit */
1117 ixgbe_dev_tx_init(dev);
1119 /* This can fail when allocating mbufs for descriptor rings */
1120 err = ixgbe_dev_rx_init(dev);
1122 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1126 ixgbe_dev_rxtx_start(dev);
1128 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1129 err = hw->mac.ops.setup_sfp(hw);
1134 /* Turn on the laser */
1135 if (hw->phy.multispeed_fiber)
1136 ixgbe_enable_tx_laser(hw);
1138 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1141 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1145 switch(dev->data->dev_conf.link_speed) {
1146 case ETH_LINK_SPEED_AUTONEG:
1147 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1148 IXGBE_LINK_SPEED_82599_AUTONEG :
1149 IXGBE_LINK_SPEED_82598_AUTONEG;
1151 case ETH_LINK_SPEED_100:
1153 * Invalid for 82598 but error will be detected by
1154 * ixgbe_setup_link()
1156 speed = IXGBE_LINK_SPEED_100_FULL;
1158 case ETH_LINK_SPEED_1000:
1159 speed = IXGBE_LINK_SPEED_1GB_FULL;
1161 case ETH_LINK_SPEED_10000:
1162 speed = IXGBE_LINK_SPEED_10GB_FULL;
1165 PMD_INIT_LOG(ERR, "Invalid link_speed (%u) for port %u\n",
1166 dev->data->dev_conf.link_speed, dev->data->port_id);
1170 err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1174 /* check if lsc interrupt is enabled */
1175 if (dev->data->dev_conf.intr_conf.lsc != 0) {
1176 err = ixgbe_dev_interrupt_setup(dev);
1181 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1182 ETH_VLAN_EXTEND_MASK;
1183 ixgbe_vlan_offload_set(dev, mask);
1185 /* Configure DCB hw */
1186 ixgbe_configure_dcb(dev);
1188 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1189 err = ixgbe_fdir_configure(dev);
1194 ixgbe_restore_statistics_mapping(dev);
1199 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1200 ixgbe_dev_clear_queues(dev);
1205 * Stop device: disable rx and tx functions to allow for reconfiguring.
1208 ixgbe_dev_stop(struct rte_eth_dev *dev)
1210 struct rte_eth_link link;
1211 struct ixgbe_hw *hw =
1212 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1214 PMD_INIT_FUNC_TRACE();
1216 /* disable interrupts */
1217 ixgbe_disable_intr(hw);
1221 hw->adapter_stopped = FALSE;
1224 ixgbe_stop_adapter(hw);
1226 /* Turn off the laser */
1227 if (hw->phy.multispeed_fiber)
1228 ixgbe_disable_tx_laser(hw);
1230 ixgbe_dev_clear_queues(dev);
1232 /* Clear recorded link status */
1233 memset(&link, 0, sizeof(link));
1234 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1238 * Reest and stop device.
1241 ixgbe_dev_close(struct rte_eth_dev *dev)
1243 struct ixgbe_hw *hw =
1244 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246 PMD_INIT_FUNC_TRACE();
1251 ixgbe_dev_stop(dev);
1252 hw->adapter_stopped = 1;
1254 ixgbe_disable_pcie_master(hw);
1256 /* reprogram the RAR[0] in case user changed it. */
1257 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1261 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1264 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1266 struct ixgbe_hw *hw =
1267 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1268 struct ixgbe_hw_stats *hw_stats =
1269 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1270 uint32_t bprc, lxon, lxoff, total;
1271 uint64_t total_missed_rx, total_qbrc, total_qprc;
1274 total_missed_rx = 0;
1278 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1279 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1280 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1281 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1283 for (i = 0; i < 8; i++) {
1285 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1286 /* global total per queue */
1287 hw_stats->mpc[i] += mp;
1288 /* Running comprehensive total for stats display */
1289 total_missed_rx += hw_stats->mpc[i];
1290 if (hw->mac.type == ixgbe_mac_82598EB)
1291 hw_stats->rnbc[i] +=
1292 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1293 hw_stats->pxontxc[i] +=
1294 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1295 hw_stats->pxonrxc[i] +=
1296 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1297 hw_stats->pxofftxc[i] +=
1298 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1299 hw_stats->pxoffrxc[i] +=
1300 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1301 hw_stats->pxon2offc[i] +=
1302 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1304 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1305 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1306 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1307 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1308 hw_stats->qbrc[i] +=
1309 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1310 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1311 hw_stats->qbtc[i] +=
1312 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1313 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1315 total_qprc += hw_stats->qprc[i];
1316 total_qbrc += hw_stats->qbrc[i];
1318 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1319 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1320 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1322 /* Note that gprc counts missed packets */
1323 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1325 if (hw->mac.type != ixgbe_mac_82598EB) {
1326 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL) +
1327 ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1328 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL) +
1329 ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1330 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL) +
1331 ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1332 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1333 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1335 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1336 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1337 /* 82598 only has a counter in the high register */
1338 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1339 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1340 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1344 * Workaround: mprc hardware is incorrectly counting
1345 * broadcasts, so for now we subtract those.
1347 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1348 hw_stats->bprc += bprc;
1349 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1350 if (hw->mac.type == ixgbe_mac_82598EB)
1351 hw_stats->mprc -= bprc;
1353 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1354 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1355 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1356 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1357 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1358 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1360 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1361 hw_stats->lxontxc += lxon;
1362 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1363 hw_stats->lxofftxc += lxoff;
1364 total = lxon + lxoff;
1366 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1367 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1368 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1369 hw_stats->gptc -= total;
1370 hw_stats->mptc -= total;
1371 hw_stats->ptc64 -= total;
1372 hw_stats->gotc -= total * ETHER_MIN_LEN;
1374 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1375 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1376 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1377 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1378 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1379 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1380 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1381 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1382 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1383 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1384 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1385 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1386 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1387 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1388 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1389 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1390 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1391 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1392 /* Only read FCOE on 82599 */
1393 if (hw->mac.type != ixgbe_mac_82598EB) {
1394 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1395 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1396 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1397 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1398 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1404 /* Fill out the rte_eth_stats statistics structure */
1405 stats->ipackets = total_qprc;
1406 stats->ibytes = total_qbrc;
1407 stats->opackets = hw_stats->gptc;
1408 stats->obytes = hw_stats->gotc;
1409 stats->imcasts = hw_stats->mprc;
1411 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1412 stats->q_ipackets[i] = hw_stats->qprc[i];
1413 stats->q_opackets[i] = hw_stats->qptc[i];
1414 stats->q_ibytes[i] = hw_stats->qbrc[i];
1415 stats->q_obytes[i] = hw_stats->qbtc[i];
1416 stats->q_errors[i] = hw_stats->qprdc[i];
1420 stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1425 /* Flow Director Stats registers */
1426 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1427 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1428 stats->fdirmatch = hw_stats->fdirmatch;
1429 stats->fdirmiss = hw_stats->fdirmiss;
1433 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1435 struct ixgbe_hw_stats *stats =
1436 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1438 /* HW registers are cleared on read */
1439 ixgbe_dev_stats_get(dev, NULL);
1441 /* Reset software totals */
1442 memset(stats, 0, sizeof(*stats));
1446 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1448 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1449 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1450 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1452 /* Good Rx packet, include VF loopback */
1453 UPDATE_VF_STAT(IXGBE_VFGPRC,
1454 hw_stats->last_vfgprc, hw_stats->vfgprc);
1456 /* Good Rx octets, include VF loopback */
1457 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1458 hw_stats->last_vfgorc, hw_stats->vfgorc);
1460 /* Good Tx packet, include VF loopback */
1461 UPDATE_VF_STAT(IXGBE_VFGPTC,
1462 hw_stats->last_vfgptc, hw_stats->vfgptc);
1464 /* Good Tx octets, include VF loopback */
1465 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1466 hw_stats->last_vfgotc, hw_stats->vfgotc);
1468 /* Rx Multicst Packet */
1469 UPDATE_VF_STAT(IXGBE_VFMPRC,
1470 hw_stats->last_vfmprc, hw_stats->vfmprc);
1475 memset(stats, 0, sizeof(*stats));
1476 stats->ipackets = hw_stats->vfgprc;
1477 stats->ibytes = hw_stats->vfgorc;
1478 stats->opackets = hw_stats->vfgptc;
1479 stats->obytes = hw_stats->vfgotc;
1480 stats->imcasts = hw_stats->vfmprc;
1484 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1486 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1487 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1489 /* Sync HW register to the last stats */
1490 ixgbevf_dev_stats_get(dev, NULL);
1492 /* reset HW current stats*/
1493 hw_stats->vfgprc = 0;
1494 hw_stats->vfgorc = 0;
1495 hw_stats->vfgptc = 0;
1496 hw_stats->vfgotc = 0;
1497 hw_stats->vfmprc = 0;
1502 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1504 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506 dev_info->max_rx_queues = hw->mac.max_rx_queues;
1507 dev_info->max_tx_queues = hw->mac.max_tx_queues;
1508 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1509 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1510 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1513 /* return 0 means link status changed, -1 means not changed */
1515 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1517 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518 struct rte_eth_link link, old;
1519 ixgbe_link_speed link_speed;
1523 link.link_status = 0;
1524 link.link_speed = 0;
1525 link.link_duplex = 0;
1526 memset(&old, 0, sizeof(old));
1527 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1529 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1530 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1531 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1533 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1535 link.link_speed = ETH_LINK_SPEED_100;
1536 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1537 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1538 if (link.link_status == old.link_status)
1544 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1545 if (link.link_status == old.link_status)
1549 link.link_status = 1;
1550 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1552 switch (link_speed) {
1554 case IXGBE_LINK_SPEED_UNKNOWN:
1555 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1556 link.link_speed = ETH_LINK_SPEED_100;
1559 case IXGBE_LINK_SPEED_100_FULL:
1560 link.link_speed = ETH_LINK_SPEED_100;
1563 case IXGBE_LINK_SPEED_1GB_FULL:
1564 link.link_speed = ETH_LINK_SPEED_1000;
1567 case IXGBE_LINK_SPEED_10GB_FULL:
1568 link.link_speed = ETH_LINK_SPEED_10000;
1571 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1573 if (link.link_status == old.link_status)
1580 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1582 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1586 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1587 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1591 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1593 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1597 fctrl &= (~IXGBE_FCTRL_UPE);
1598 if (dev->data->all_multicast == 1)
1599 fctrl |= IXGBE_FCTRL_MPE;
1601 fctrl &= (~IXGBE_FCTRL_MPE);
1602 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1606 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1608 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1612 fctrl |= IXGBE_FCTRL_MPE;
1613 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1617 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1619 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1622 if (dev->data->promiscuous == 1)
1623 return; /* must remain in all_multicast mode */
1625 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1626 fctrl &= (~IXGBE_FCTRL_MPE);
1627 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1631 * It clears the interrupt causes and enables the interrupt.
1632 * It will be called once only during nic initialized.
1635 * Pointer to struct rte_eth_dev.
1638 * - On success, zero.
1639 * - On failure, a negative value.
1642 ixgbe_dev_interrupt_setup(struct rte_eth_dev *dev)
1644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646 ixgbe_dev_link_status_print(dev);
1647 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_LSC);
1648 IXGBE_WRITE_FLUSH(hw);
1649 rte_intr_enable(&(dev->pci_dev->intr_handle));
1655 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1658 * Pointer to struct rte_eth_dev.
1661 * - On success, zero.
1662 * - On failure, a negative value.
1665 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1668 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1669 struct ixgbe_interrupt *intr =
1670 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1672 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_LSC);
1673 IXGBE_WRITE_FLUSH(hw);
1675 /* read-on-clear nic registers here */
1676 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1677 PMD_INIT_LOG(INFO, "eicr %x", eicr);
1678 if (eicr & IXGBE_EICR_LSC) {
1679 /* set flag for async link update */
1680 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1687 * It gets and then prints the link status.
1690 * Pointer to struct rte_eth_dev.
1693 * - On success, zero.
1694 * - On failure, a negative value.
1697 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1699 struct rte_eth_link link;
1701 memset(&link, 0, sizeof(link));
1702 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1703 if (link.link_status) {
1704 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1705 (int)(dev->data->port_id),
1706 (unsigned)link.link_speed,
1707 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1708 "full-duplex" : "half-duplex");
1710 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1711 (int)(dev->data->port_id));
1713 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1714 dev->pci_dev->addr.domain,
1715 dev->pci_dev->addr.bus,
1716 dev->pci_dev->addr.devid,
1717 dev->pci_dev->addr.function);
1721 * It executes link_update after knowing an interrupt occured.
1724 * Pointer to struct rte_eth_dev.
1727 * - On success, zero.
1728 * - On failure, a negative value.
1731 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1733 struct ixgbe_interrupt *intr =
1734 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1736 if (!(intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
1739 ixgbe_dev_link_update(dev, 0);
1745 * Interrupt handler which shall be registered for alarm callback for delayed
1746 * handling specific interrupt to wait for the stable nic state. As the
1747 * NIC interrupt state is not stable for ixgbe after link is just down,
1748 * it needs to wait 4 seconds to get the stable status.
1751 * Pointer to interrupt handle.
1753 * The address of parameter (struct rte_eth_dev *) regsitered before.
1759 ixgbe_dev_interrupt_delayed_handler(void *param)
1761 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1762 struct ixgbe_interrupt *intr =
1763 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1764 struct ixgbe_hw *hw =
1765 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767 IXGBE_READ_REG(hw, IXGBE_EICR);
1768 ixgbe_dev_interrupt_action(dev);
1769 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1770 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
1771 rte_intr_enable(&(dev->pci_dev->intr_handle));
1772 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_LSC);
1773 IXGBE_WRITE_FLUSH(hw);
1774 ixgbe_dev_link_status_print(dev);
1775 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1780 * Interrupt handler triggered by NIC for handling
1781 * specific interrupt.
1784 * Pointer to interrupt handle.
1786 * The address of parameter (struct rte_eth_dev *) regsitered before.
1792 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle, void *param)
1795 struct rte_eth_link link;
1796 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1797 struct ixgbe_interrupt *intr =
1798 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1800 /* get the link status before link update, for predicting later */
1801 memset(&link, 0, sizeof(link));
1802 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1803 ixgbe_dev_interrupt_get_status(dev);
1804 ixgbe_dev_interrupt_action(dev);
1806 if (!(intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
1810 if (!link.link_status)
1811 /* handle it 1 sec later, wait it being stable */
1812 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1813 /* likely to down */
1815 /* handle it 4 sec later, wait it being stable */
1816 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1818 ixgbe_dev_link_status_print(dev);
1819 if (rte_eal_alarm_set(timeout * 1000,
1820 ixgbe_dev_interrupt_delayed_handler, param) < 0)
1821 PMD_INIT_LOG(ERR, "Error setting alarm");
1825 ixgbe_dev_led_on(struct rte_eth_dev *dev)
1827 struct ixgbe_hw *hw;
1829 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1830 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1834 ixgbe_dev_led_off(struct rte_eth_dev *dev)
1836 struct ixgbe_hw *hw;
1838 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1843 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1845 struct ixgbe_hw *hw;
1847 uint32_t rx_buf_size;
1848 uint32_t max_high_water;
1849 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
1856 PMD_INIT_FUNC_TRACE();
1858 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
1860 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1863 * At least reserve one Ethernet frame for watermark
1864 * high_water/low_water in kilo bytes for ixgbe
1866 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
1867 if ((fc_conf->high_water > max_high_water) ||
1868 (fc_conf->high_water < fc_conf->low_water)) {
1869 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
1870 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
1874 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
1875 hw->fc.pause_time = fc_conf->pause_time;
1876 hw->fc.high_water[0] = fc_conf->high_water;
1877 hw->fc.low_water[0] = fc_conf->low_water;
1878 hw->fc.send_xon = fc_conf->send_xon;
1880 err = ixgbe_fc_enable(hw);
1881 /* Not negotiated is not an error case */
1882 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
1886 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
1891 * ixgbe_pfc_enable_generic - Enable flow control
1892 * @hw: pointer to hardware structure
1893 * @tc_num: traffic class number
1894 * Enable flow control according to the current settings.
1897 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
1900 uint32_t mflcn_reg, fccfg_reg;
1902 uint32_t fcrtl, fcrth;
1906 /* Validate the water mark configuration */
1907 if (!hw->fc.pause_time) {
1908 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1912 /* Low water mark of zero causes XOFF floods */
1913 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1914 /* High/Low water can not be 0 */
1915 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
1916 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
1917 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1921 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
1922 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
1923 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1927 /* Negotiate the fc mode to use */
1928 ixgbe_fc_autoneg(hw);
1930 /* Disable any previous flow control settings */
1931 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1932 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
1934 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1935 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1937 switch (hw->fc.current_mode) {
1940 * If the count of enabled RX Priority Flow control >1,
1941 * and the TX pause can not be disabled
1944 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1945 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
1946 if (reg & IXGBE_FCRTH_FCEN)
1950 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
1952 case ixgbe_fc_rx_pause:
1954 * Rx Flow control is enabled and Tx Flow control is
1955 * disabled by software override. Since there really
1956 * isn't a way to advertise that we are capable of RX
1957 * Pause ONLY, we will advertise that we support both
1958 * symmetric and asymmetric Rx PAUSE. Later, we will
1959 * disable the adapter's ability to send PAUSE frames.
1961 mflcn_reg |= IXGBE_MFLCN_RPFCE;
1963 * If the count of enabled RX Priority Flow control >1,
1964 * and the TX pause can not be disabled
1967 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1968 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
1969 if (reg & IXGBE_FCRTH_FCEN)
1973 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
1975 case ixgbe_fc_tx_pause:
1977 * Tx Flow control is enabled, and Rx Flow control is
1978 * disabled by software override.
1980 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
1983 /* Flow control (both Rx and Tx) is enabled by SW override. */
1984 mflcn_reg |= IXGBE_MFLCN_RPFCE;
1985 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
1988 DEBUGOUT("Flow control param set incorrectly\n");
1989 ret_val = IXGBE_ERR_CONFIG;
1994 /* Set 802.3x based flow control settings. */
1995 mflcn_reg |= IXGBE_MFLCN_DPF;
1996 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1997 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1999 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2000 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2001 hw->fc.high_water[tc_num]) {
2002 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2003 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2004 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2006 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2008 * In order to prevent Tx hangs when the internal Tx
2009 * switch is enabled we must set the high water mark
2010 * to the maximum FCRTH value. This allows the Tx
2011 * switch to function even under heavy Rx workloads.
2013 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2015 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2017 /* Configure pause time (2 TCs per register) */
2018 reg = hw->fc.pause_time * 0x00010001;
2019 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2020 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2022 /* Configure flow control refresh threshold value */
2023 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2030 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2032 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2035 if(hw->mac.type != ixgbe_mac_82598EB) {
2036 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2042 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2045 uint32_t rx_buf_size;
2046 uint32_t max_high_water;
2048 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2049 struct ixgbe_hw *hw =
2050 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051 struct ixgbe_dcb_config *dcb_config =
2052 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2054 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2061 PMD_INIT_FUNC_TRACE();
2063 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2064 tc_num = map[pfc_conf->priority];
2065 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2066 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2068 * At least reserve one Ethernet frame for watermark
2069 * high_water/low_water in kilo bytes for ixgbe
2071 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2072 if ((pfc_conf->fc.high_water > max_high_water) ||
2073 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2074 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2075 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2079 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2080 hw->fc.pause_time = pfc_conf->fc.pause_time;
2081 hw->fc.send_xon = pfc_conf->fc.send_xon;
2082 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2083 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2085 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2087 /* Not negotiated is not an error case */
2088 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2091 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2096 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2097 uint32_t index, uint32_t pool)
2099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100 uint32_t enable_addr = 1;
2102 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2106 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2108 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110 ixgbe_clear_rar(hw, index);
2114 * Virtual Function operations
2117 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2119 PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2121 /* Clear interrupt mask to stop from interrupts being generated */
2122 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2124 IXGBE_WRITE_FLUSH(hw);
2128 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2130 struct rte_eth_conf* conf = &dev->data->dev_conf;
2133 if (!conf->rxmode.hw_strip_crc) {
2135 * VF has no ability to enable/disable HW CRC
2136 * Keep the persistent behavior the same as Host PF
2138 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2139 conf->rxmode.hw_strip_crc = 1;
2146 ixgbevf_dev_start(struct rte_eth_dev *dev)
2149 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2151 ixgbevf_dev_tx_init(dev);
2152 err = ixgbevf_dev_rx_init(dev);
2154 ixgbe_dev_clear_queues(dev);
2155 PMD_INIT_LOG(ERR,"Unable to initialize RX hardware\n");
2160 ixgbevf_set_vfta_all(dev,1);
2163 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2164 ETH_VLAN_EXTEND_MASK;
2165 ixgbevf_vlan_offload_set(dev, mask);
2167 ixgbevf_dev_rxtx_start(dev);
2173 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2175 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2180 hw->adapter_stopped = 0;
2181 ixgbe_stop_adapter(hw);
2182 /* reprogram the RAR[0] in case user changed it. */
2183 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2186 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2188 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189 struct ixgbe_vfta * shadow_vfta =
2190 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2191 int i = 0, j = 0, vfta = 0, mask = 1;
2193 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2194 vfta = shadow_vfta->vfta[i];
2197 for (j = 0; j < 32; j++){
2199 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2208 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2210 struct ixgbe_hw *hw =
2211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212 struct ixgbe_vfta * shadow_vfta =
2213 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2214 uint32_t vid_idx = 0;
2215 uint32_t vid_bit = 0;
2218 PMD_INIT_FUNC_TRACE();
2220 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2221 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2223 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2226 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2227 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2229 /* Save what we set and retore it after device reset */
2231 shadow_vfta->vfta[vid_idx] |= vid_bit;
2233 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2239 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2241 struct ixgbe_hw *hw =
2242 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245 PMD_INIT_FUNC_TRACE();
2247 if(queue >= hw->mac.max_rx_queues)
2250 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2252 ctrl |= IXGBE_RXDCTL_VME;
2254 ctrl &= ~IXGBE_RXDCTL_VME;
2255 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2257 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2261 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2263 struct ixgbe_hw *hw =
2264 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2267 /* VF function only support hw strip feature, others are not support */
2268 if(mask & ETH_VLAN_STRIP_MASK){
2269 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2271 for(i=0; i < hw->mac.max_rx_queues; i++)
2272 ixgbevf_vlan_strip_queue_set(dev,i,on);