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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
65 #include "ixgbe_logs.h"
66 #include "ixgbe/ixgbe_api.h"
67 #include "ixgbe/ixgbe_vf.h"
68 #include "ixgbe/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
74 * High threshold controlling when to start sending XOFF frames. Must be at
75 * least 8 bytes less than receive packet buffer size. This value is in units
78 #define IXGBE_FC_HI 0x80
81 * Low threshold controlling when to start sending XON frames. This value is
82 * in units of 1024 bytes.
84 #define IXGBE_FC_LO 0x40
86 /* Timer value included in XOFF frames. */
87 #define IXGBE_FC_PAUSE 0x680
89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
90 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
91 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
93 #define IXGBE_MMW_SIZE_DEFAULT 0x4
94 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
97 * Default values for RX/TX configuration
99 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
100 #define IXGBE_DEFAULT_RX_PTHRESH 8
101 #define IXGBE_DEFAULT_RX_HTHRESH 8
102 #define IXGBE_DEFAULT_RX_WTHRESH 0
104 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
105 #define IXGBE_DEFAULT_TX_PTHRESH 32
106 #define IXGBE_DEFAULT_TX_HTHRESH 0
107 #define IXGBE_DEFAULT_TX_WTHRESH 0
108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
110 /* Bit shift and mask */
111 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
112 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
113 #define IXGBE_8_BIT_WIDTH CHAR_BIT
114 #define IXGBE_8_BIT_MASK UINT8_MAX
116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
121 struct rte_eth_dev *eth_dev);
122 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
123 static int ixgbe_dev_start(struct rte_eth_dev *dev);
124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
125 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
126 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
133 int wait_to_complete);
134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
135 struct rte_eth_stats *stats);
136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
142 struct rte_eth_dev_info *dev_info);
143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
144 struct rte_eth_dev_info *dev_info);
145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
148 uint16_t vlan_id, int on);
149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
151 uint16_t queue, bool on);
152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
163 struct rte_eth_fc_conf *fc_conf);
164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
165 struct rte_eth_fc_conf *fc_conf);
166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
167 struct rte_eth_pfc_conf *pfc_conf);
168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
169 struct rte_eth_rss_reta_entry64 *reta_conf,
171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
172 struct rte_eth_rss_reta_entry64 *reta_conf,
174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
182 uint32_t index, uint32_t pool);
183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
186 /* For Virtual Function support */
187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
188 struct rte_eth_dev *eth_dev);
189 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
190 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
195 struct rte_eth_stats *stats);
196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
198 uint16_t vlan_id, int on);
199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
200 uint16_t queue, int on);
201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
204 /* For Eth VMDQ APIs support */
205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
206 ether_addr* mac_addr,uint8_t on);
207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
208 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
209 uint16_t rx_mask, uint8_t on);
210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
213 uint64_t pool_mask,uint8_t vlan_on);
214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
215 struct rte_eth_vmdq_mirror_conf *mirror_conf,
216 uint8_t rule_id, uint8_t on);
217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
221 uint16_t queue_idx, uint16_t tx_rate);
222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
223 uint16_t tx_rate, uint64_t q_msk);
225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
226 struct ether_addr *mac_addr,
227 uint32_t index, uint32_t pool);
228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
229 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
230 struct rte_syn_filter *filter, uint16_t rx_queue);
231 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
232 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
233 struct rte_syn_filter *filter, uint16_t *rx_queue);
234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
235 struct rte_5tuple_filter *filter, uint16_t rx_queue);
236 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
238 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
239 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
241 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
242 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
243 struct rte_eth_ethertype_filter *filter,
245 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
246 enum rte_filter_op filter_op,
248 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
249 struct rte_eth_ethertype_filter *filter);
250 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
251 enum rte_filter_type filter_type,
252 enum rte_filter_op filter_op,
256 * Define VF Stats MACRO for Non "cleared on read" register
258 #define UPDATE_VF_STAT(reg, last, cur) \
260 u32 latest = IXGBE_READ_REG(hw, reg); \
261 cur += latest - last; \
265 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
267 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
268 u64 new_msb = IXGBE_READ_REG(hw, msb); \
269 u64 latest = ((new_msb << 32) | new_lsb); \
270 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
274 #define IXGBE_SET_HWSTRIP(h, q) do{\
275 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
276 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
277 (h)->bitmap[idx] |= 1 << bit;\
280 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
281 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
282 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
283 (h)->bitmap[idx] &= ~(1 << bit);\
286 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
287 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
288 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
289 (r) = (h)->bitmap[idx] >> bit & 1;\
293 * The set of PCI devices this driver supports
295 static struct rte_pci_id pci_id_ixgbe_map[] = {
297 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
298 #include "rte_pci_dev_ids.h"
300 { .vendor_id = 0, /* sentinel */ },
305 * The set of PCI devices this driver supports (for 82599 VF)
307 static struct rte_pci_id pci_id_ixgbevf_map[] = {
309 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
310 #include "rte_pci_dev_ids.h"
311 { .vendor_id = 0, /* sentinel */ },
315 static struct eth_dev_ops ixgbe_eth_dev_ops = {
316 .dev_configure = ixgbe_dev_configure,
317 .dev_start = ixgbe_dev_start,
318 .dev_stop = ixgbe_dev_stop,
319 .dev_set_link_up = ixgbe_dev_set_link_up,
320 .dev_set_link_down = ixgbe_dev_set_link_down,
321 .dev_close = ixgbe_dev_close,
322 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
323 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
324 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
325 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
326 .link_update = ixgbe_dev_link_update,
327 .stats_get = ixgbe_dev_stats_get,
328 .stats_reset = ixgbe_dev_stats_reset,
329 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
330 .dev_infos_get = ixgbe_dev_info_get,
331 .mtu_set = ixgbe_dev_mtu_set,
332 .vlan_filter_set = ixgbe_vlan_filter_set,
333 .vlan_tpid_set = ixgbe_vlan_tpid_set,
334 .vlan_offload_set = ixgbe_vlan_offload_set,
335 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
336 .rx_queue_start = ixgbe_dev_rx_queue_start,
337 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
338 .tx_queue_start = ixgbe_dev_tx_queue_start,
339 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
340 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
341 .rx_queue_release = ixgbe_dev_rx_queue_release,
342 .rx_queue_count = ixgbe_dev_rx_queue_count,
343 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
344 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
345 .tx_queue_release = ixgbe_dev_tx_queue_release,
346 .dev_led_on = ixgbe_dev_led_on,
347 .dev_led_off = ixgbe_dev_led_off,
348 .flow_ctrl_get = ixgbe_flow_ctrl_get,
349 .flow_ctrl_set = ixgbe_flow_ctrl_set,
350 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
351 .mac_addr_add = ixgbe_add_rar,
352 .mac_addr_remove = ixgbe_remove_rar,
353 .uc_hash_table_set = ixgbe_uc_hash_table_set,
354 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
355 .mirror_rule_set = ixgbe_mirror_rule_set,
356 .mirror_rule_reset = ixgbe_mirror_rule_reset,
357 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
358 .set_vf_rx = ixgbe_set_pool_rx,
359 .set_vf_tx = ixgbe_set_pool_tx,
360 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
361 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
362 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
363 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
364 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
365 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
366 .fdir_infos_get = ixgbe_fdir_info_get,
367 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
368 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
369 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
370 .fdir_set_masks = ixgbe_fdir_set_masks,
371 .reta_update = ixgbe_dev_rss_reta_update,
372 .reta_query = ixgbe_dev_rss_reta_query,
373 #ifdef RTE_NIC_BYPASS
374 .bypass_init = ixgbe_bypass_init,
375 .bypass_state_set = ixgbe_bypass_state_store,
376 .bypass_state_show = ixgbe_bypass_state_show,
377 .bypass_event_set = ixgbe_bypass_event_store,
378 .bypass_event_show = ixgbe_bypass_event_show,
379 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
380 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
381 .bypass_ver_show = ixgbe_bypass_ver_show,
382 .bypass_wd_reset = ixgbe_bypass_wd_reset,
383 #endif /* RTE_NIC_BYPASS */
384 .rss_hash_update = ixgbe_dev_rss_hash_update,
385 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
386 .add_syn_filter = ixgbe_add_syn_filter,
387 .remove_syn_filter = ixgbe_remove_syn_filter,
388 .get_syn_filter = ixgbe_get_syn_filter,
389 .add_5tuple_filter = ixgbe_add_5tuple_filter,
390 .remove_5tuple_filter = ixgbe_remove_5tuple_filter,
391 .get_5tuple_filter = ixgbe_get_5tuple_filter,
392 .filter_ctrl = ixgbe_dev_filter_ctrl,
396 * dev_ops for virtual function, bare necessities for basic vf
397 * operation have been implemented
399 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
401 .dev_configure = ixgbevf_dev_configure,
402 .dev_start = ixgbevf_dev_start,
403 .dev_stop = ixgbevf_dev_stop,
404 .link_update = ixgbe_dev_link_update,
405 .stats_get = ixgbevf_dev_stats_get,
406 .stats_reset = ixgbevf_dev_stats_reset,
407 .dev_close = ixgbevf_dev_close,
408 .dev_infos_get = ixgbevf_dev_info_get,
409 .mtu_set = ixgbevf_dev_set_mtu,
410 .vlan_filter_set = ixgbevf_vlan_filter_set,
411 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
412 .vlan_offload_set = ixgbevf_vlan_offload_set,
413 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
414 .rx_queue_release = ixgbe_dev_rx_queue_release,
415 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
416 .tx_queue_release = ixgbe_dev_tx_queue_release,
417 .mac_addr_add = ixgbevf_add_mac_addr,
418 .mac_addr_remove = ixgbevf_remove_mac_addr,
422 * Atomically reads the link status information from global
423 * structure rte_eth_dev.
426 * - Pointer to the structure rte_eth_dev to read from.
427 * - Pointer to the buffer to be saved with the link status.
430 * - On success, zero.
431 * - On failure, negative value.
434 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
435 struct rte_eth_link *link)
437 struct rte_eth_link *dst = link;
438 struct rte_eth_link *src = &(dev->data->dev_link);
440 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
441 *(uint64_t *)src) == 0)
448 * Atomically writes the link status information into global
449 * structure rte_eth_dev.
452 * - Pointer to the structure rte_eth_dev to read from.
453 * - Pointer to the buffer to be saved with the link status.
456 * - On success, zero.
457 * - On failure, negative value.
460 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
461 struct rte_eth_link *link)
463 struct rte_eth_link *dst = &(dev->data->dev_link);
464 struct rte_eth_link *src = link;
466 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
467 *(uint64_t *)src) == 0)
474 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
477 ixgbe_is_sfp(struct ixgbe_hw *hw)
479 switch (hw->phy.type) {
480 case ixgbe_phy_sfp_avago:
481 case ixgbe_phy_sfp_ftl:
482 case ixgbe_phy_sfp_intel:
483 case ixgbe_phy_sfp_unknown:
484 case ixgbe_phy_sfp_passive_tyco:
485 case ixgbe_phy_sfp_passive_unknown:
492 static inline int32_t
493 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
498 status = ixgbe_reset_hw(hw);
500 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
501 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
502 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
503 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
504 IXGBE_WRITE_FLUSH(hw);
510 ixgbe_enable_intr(struct rte_eth_dev *dev)
512 struct ixgbe_interrupt *intr =
513 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
514 struct ixgbe_hw *hw =
515 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
517 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
518 IXGBE_WRITE_FLUSH(hw);
522 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
525 ixgbe_disable_intr(struct ixgbe_hw *hw)
527 PMD_INIT_FUNC_TRACE();
529 if (hw->mac.type == ixgbe_mac_82598EB) {
530 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
532 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
533 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
534 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
536 IXGBE_WRITE_FLUSH(hw);
540 * This function resets queue statistics mapping registers.
541 * From Niantic datasheet, Initialization of Statistics section:
542 * "...if software requires the queue counters, the RQSMR and TQSM registers
543 * must be re-programmed following a device reset.
546 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
550 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
551 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
552 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
558 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
563 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
564 #define NB_QMAP_FIELDS_PER_QSM_REG 4
565 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
567 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
568 struct ixgbe_stat_mapping_registers *stat_mappings =
569 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
570 uint32_t qsmr_mask = 0;
571 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
575 if ((hw->mac.type != ixgbe_mac_82599EB) &&
576 (hw->mac.type != ixgbe_mac_X540) &&
577 (hw->mac.type != ixgbe_mac_X550) &&
578 (hw->mac.type != ixgbe_mac_X550EM_x))
581 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
582 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
585 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
586 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
587 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
590 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
592 /* Now clear any previous stat_idx set */
593 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
595 stat_mappings->tqsm[n] &= ~clearing_mask;
597 stat_mappings->rqsmr[n] &= ~clearing_mask;
599 q_map = (uint32_t)stat_idx;
600 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
601 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
603 stat_mappings->tqsm[n] |= qsmr_mask;
605 stat_mappings->rqsmr[n] |= qsmr_mask;
607 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
608 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
610 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
611 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
613 /* Now write the mapping in the appropriate register */
615 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
616 stat_mappings->rqsmr[n], n);
617 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
620 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
621 stat_mappings->tqsm[n], n);
622 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
628 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
630 struct ixgbe_stat_mapping_registers *stat_mappings =
631 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
632 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
635 /* write whatever was in stat mapping table to the NIC */
636 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
638 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
641 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
646 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
649 struct ixgbe_dcb_tc_config *tc;
650 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
652 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
653 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
654 for (i = 0; i < dcb_max_tc; i++) {
655 tc = &dcb_config->tc_config[i];
656 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
657 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
658 (uint8_t)(100/dcb_max_tc + (i & 1));
659 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
660 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
661 (uint8_t)(100/dcb_max_tc + (i & 1));
662 tc->pfc = ixgbe_dcb_pfc_disabled;
665 /* Initialize default user to priority mapping, UPx->TC0 */
666 tc = &dcb_config->tc_config[0];
667 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
668 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
669 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
670 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
671 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
673 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
674 dcb_config->pfc_mode_enable = false;
675 dcb_config->vt_mode = true;
676 dcb_config->round_robin_enable = false;
677 /* support all DCB capabilities in 82599 */
678 dcb_config->support.capabilities = 0xFF;
680 /*we only support 4 Tcs for X540, X550 */
681 if (hw->mac.type == ixgbe_mac_X540 ||
682 hw->mac.type == ixgbe_mac_X550 ||
683 hw->mac.type == ixgbe_mac_X550EM_x) {
684 dcb_config->num_tcs.pg_tcs = 4;
685 dcb_config->num_tcs.pfc_tcs = 4;
690 * Ensure that all locks are released before first NVM or PHY access
693 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
698 * Phy lock should not fail in this early stage. If this is the case,
699 * it is due to an improper exit of the application.
700 * So force the release of the faulty lock. Release of common lock
701 * is done automatically by swfw_sync function.
703 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
704 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
705 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
707 ixgbe_release_swfw_semaphore(hw, mask);
710 * These ones are more tricky since they are common to all ports; but
711 * swfw_sync retries last long enough (1s) to be almost sure that if
712 * lock can not be taken it is due to an improper lock of the
715 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
716 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
717 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
719 ixgbe_release_swfw_semaphore(hw, mask);
723 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
724 * It returns 0 on success.
727 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
728 struct rte_eth_dev *eth_dev)
730 struct rte_pci_device *pci_dev;
731 struct ixgbe_hw *hw =
732 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
733 struct ixgbe_vfta * shadow_vfta =
734 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
735 struct ixgbe_hwstrip *hwstrip =
736 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
737 struct ixgbe_dcb_config *dcb_config =
738 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
743 PMD_INIT_FUNC_TRACE();
745 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
746 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
747 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
750 * For secondary processes, we don't initialise any further as primary
751 * has already done this work. Only check we don't need a different
752 * RX and TX function.
754 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
755 struct igb_tx_queue *txq;
756 /* TX queue function in primary, set by last queue initialized
757 * Tx queue may not initialized by primary process */
758 if (eth_dev->data->tx_queues) {
759 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
760 set_tx_function(eth_dev, txq);
762 /* Use default TX function if we get here */
763 PMD_INIT_LOG(INFO, "No TX queues configured yet. "
764 "Using default TX function.");
767 if (eth_dev->data->scattered_rx)
768 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
771 pci_dev = eth_dev->pci_dev;
773 /* Vendor and Device ID need to be set before init of shared code */
774 hw->device_id = pci_dev->id.device_id;
775 hw->vendor_id = pci_dev->id.vendor_id;
776 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
777 hw->allow_unsupported_sfp = 1;
779 /* Initialize the shared code (base driver) */
780 #ifdef RTE_NIC_BYPASS
781 diag = ixgbe_bypass_init_shared_code(hw);
783 diag = ixgbe_init_shared_code(hw);
784 #endif /* RTE_NIC_BYPASS */
786 if (diag != IXGBE_SUCCESS) {
787 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
791 /* pick up the PCI bus settings for reporting later */
792 ixgbe_get_bus_info(hw);
794 /* Unlock any pending hardware semaphore */
795 ixgbe_swfw_lock_reset(hw);
797 /* Initialize DCB configuration*/
798 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
799 ixgbe_dcb_init(hw,dcb_config);
800 /* Get Hardware Flow Control setting */
801 hw->fc.requested_mode = ixgbe_fc_full;
802 hw->fc.current_mode = ixgbe_fc_full;
803 hw->fc.pause_time = IXGBE_FC_PAUSE;
804 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
805 hw->fc.low_water[i] = IXGBE_FC_LO;
806 hw->fc.high_water[i] = IXGBE_FC_HI;
810 /* Make sure we have a good EEPROM before we read from it */
811 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
812 if (diag != IXGBE_SUCCESS) {
813 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
817 #ifdef RTE_NIC_BYPASS
818 diag = ixgbe_bypass_init_hw(hw);
820 diag = ixgbe_init_hw(hw);
821 #endif /* RTE_NIC_BYPASS */
824 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
825 * is called too soon after the kernel driver unbinding/binding occurs.
826 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
827 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
828 * also called. See ixgbe_identify_phy_82599(). The reason for the
829 * failure is not known, and only occuts when virtualisation features
830 * are disabled in the bios. A delay of 100ms was found to be enough by
831 * trial-and-error, and is doubled to be safe.
833 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
835 diag = ixgbe_init_hw(hw);
838 if (diag == IXGBE_ERR_EEPROM_VERSION) {
839 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
840 "LOM. Please be aware there may be issues associated "
841 "with your hardware.");
842 PMD_INIT_LOG(ERR, "If you are experiencing problems "
843 "please contact your Intel or hardware representative "
844 "who provided you with this hardware.");
845 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
846 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
848 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
852 /* disable interrupt */
853 ixgbe_disable_intr(hw);
855 /* reset mappings for queue statistics hw counters*/
856 ixgbe_reset_qstat_mappings(hw);
858 /* Allocate memory for storing MAC addresses */
859 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
860 hw->mac.num_rar_entries, 0);
861 if (eth_dev->data->mac_addrs == NULL) {
863 "Failed to allocate %u bytes needed to store "
865 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
868 /* Copy the permanent MAC address */
869 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
870 ð_dev->data->mac_addrs[0]);
872 /* Allocate memory for storing hash filter MAC addresses */
873 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
874 IXGBE_VMDQ_NUM_UC_MAC, 0);
875 if (eth_dev->data->hash_mac_addrs == NULL) {
877 "Failed to allocate %d bytes needed to store MAC addresses",
878 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
882 /* initialize the vfta */
883 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
885 /* initialize the hw strip bitmap*/
886 memset(hwstrip, 0, sizeof(*hwstrip));
888 /* initialize PF if max_vfs not zero */
889 ixgbe_pf_host_init(eth_dev);
891 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
892 /* let hardware know driver is loaded */
893 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
894 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
895 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
896 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
897 IXGBE_WRITE_FLUSH(hw);
899 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
900 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
901 (int) hw->mac.type, (int) hw->phy.type,
902 (int) hw->phy.sfp_type);
904 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
905 (int) hw->mac.type, (int) hw->phy.type);
907 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
908 eth_dev->data->port_id, pci_dev->id.vendor_id,
909 pci_dev->id.device_id);
911 rte_intr_callback_register(&(pci_dev->intr_handle),
912 ixgbe_dev_interrupt_handler, (void *)eth_dev);
914 /* enable uio intr after callback register */
915 rte_intr_enable(&(pci_dev->intr_handle));
917 /* enable support intr */
918 ixgbe_enable_intr(eth_dev);
925 * Negotiate mailbox API version with the PF.
926 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
927 * Then we try to negotiate starting with the most recent one.
928 * If all negotiation attempts fail, then we will proceed with
929 * the default one (ixgbe_mbox_api_10).
932 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
936 /* start with highest supported, proceed down */
937 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
943 i != RTE_DIM(sup_ver) &&
944 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
950 generate_random_mac_addr(struct ether_addr *mac_addr)
954 /* Set Organizationally Unique Identifier (OUI) prefix. */
955 mac_addr->addr_bytes[0] = 0x00;
956 mac_addr->addr_bytes[1] = 0x09;
957 mac_addr->addr_bytes[2] = 0xC0;
958 /* Force indication of locally assigned MAC address. */
959 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
960 /* Generate the last 3 bytes of the MAC address with a random number. */
962 memcpy(&mac_addr->addr_bytes[3], &random, 3);
966 * Virtual Function device init
969 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
970 struct rte_eth_dev *eth_dev)
974 struct rte_pci_device *pci_dev;
975 struct ixgbe_hw *hw =
976 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
977 struct ixgbe_vfta * shadow_vfta =
978 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
979 struct ixgbe_hwstrip *hwstrip =
980 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
981 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
983 PMD_INIT_FUNC_TRACE();
985 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
986 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
987 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
989 /* for secondary processes, we don't initialise any further as primary
990 * has already done this work. Only check we don't need a different
992 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
993 if (eth_dev->data->scattered_rx)
994 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
998 pci_dev = eth_dev->pci_dev;
1000 hw->device_id = pci_dev->id.device_id;
1001 hw->vendor_id = pci_dev->id.vendor_id;
1002 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1004 /* initialize the vfta */
1005 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1007 /* initialize the hw strip bitmap*/
1008 memset(hwstrip, 0, sizeof(*hwstrip));
1010 /* Initialize the shared code (base driver) */
1011 diag = ixgbe_init_shared_code(hw);
1012 if (diag != IXGBE_SUCCESS) {
1013 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1017 /* init_mailbox_params */
1018 hw->mbx.ops.init_params(hw);
1020 /* Disable the interrupts for VF */
1021 ixgbevf_intr_disable(hw);
1023 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1024 diag = hw->mac.ops.reset_hw(hw);
1027 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1028 * the underlying PF driver has not assigned a MAC address to the VF.
1029 * In this case, assign a random MAC address.
1031 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1032 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1036 /* negotiate mailbox API version to use with the PF. */
1037 ixgbevf_negotiate_api(hw);
1039 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1040 ixgbevf_get_queues(hw, &tcs, &tc);
1042 /* Allocate memory for storing MAC addresses */
1043 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1044 hw->mac.num_rar_entries, 0);
1045 if (eth_dev->data->mac_addrs == NULL) {
1047 "Failed to allocate %u bytes needed to store "
1049 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1053 /* Generate a random MAC address, if none was assigned by PF. */
1054 if (is_zero_ether_addr(perm_addr)) {
1055 generate_random_mac_addr(perm_addr);
1056 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1058 rte_free(eth_dev->data->mac_addrs);
1059 eth_dev->data->mac_addrs = NULL;
1062 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1063 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1064 "%02x:%02x:%02x:%02x:%02x:%02x",
1065 perm_addr->addr_bytes[0],
1066 perm_addr->addr_bytes[1],
1067 perm_addr->addr_bytes[2],
1068 perm_addr->addr_bytes[3],
1069 perm_addr->addr_bytes[4],
1070 perm_addr->addr_bytes[5]);
1073 /* Copy the permanent MAC address */
1074 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1076 /* reset the hardware with the new settings */
1077 diag = hw->mac.ops.start_hw(hw);
1083 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1087 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1088 eth_dev->data->port_id, pci_dev->id.vendor_id,
1089 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1094 static struct eth_driver rte_ixgbe_pmd = {
1096 .name = "rte_ixgbe_pmd",
1097 .id_table = pci_id_ixgbe_map,
1098 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1100 .eth_dev_init = eth_ixgbe_dev_init,
1101 .dev_private_size = sizeof(struct ixgbe_adapter),
1105 * virtual function driver struct
1107 static struct eth_driver rte_ixgbevf_pmd = {
1109 .name = "rte_ixgbevf_pmd",
1110 .id_table = pci_id_ixgbevf_map,
1111 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1113 .eth_dev_init = eth_ixgbevf_dev_init,
1114 .dev_private_size = sizeof(struct ixgbe_adapter),
1118 * Driver initialization routine.
1119 * Invoked once at EAL init time.
1120 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1123 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1125 PMD_INIT_FUNC_TRACE();
1127 rte_eth_driver_register(&rte_ixgbe_pmd);
1132 * VF Driver initialization routine.
1133 * Invoked one at EAL init time.
1134 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1137 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1139 PMD_INIT_FUNC_TRACE();
1141 rte_eth_driver_register(&rte_ixgbevf_pmd);
1146 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1148 struct ixgbe_hw *hw =
1149 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1150 struct ixgbe_vfta * shadow_vfta =
1151 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1156 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1157 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1158 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1163 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1165 /* update local VFTA copy */
1166 shadow_vfta->vfta[vid_idx] = vfta;
1172 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1175 ixgbe_vlan_hw_strip_enable(dev, queue);
1177 ixgbe_vlan_hw_strip_disable(dev, queue);
1181 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1183 struct ixgbe_hw *hw =
1184 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186 /* Only the high 16-bits is valid */
1187 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1191 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1193 struct ixgbe_hw *hw =
1194 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1197 PMD_INIT_FUNC_TRACE();
1199 /* Filter Table Disable */
1200 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1201 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1203 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1207 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1209 struct ixgbe_hw *hw =
1210 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211 struct ixgbe_vfta * shadow_vfta =
1212 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1216 PMD_INIT_FUNC_TRACE();
1218 /* Filter Table Enable */
1219 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1220 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1221 vlnctrl |= IXGBE_VLNCTRL_VFE;
1223 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1225 /* write whatever is in local vfta copy */
1226 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1227 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1231 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1233 struct ixgbe_hwstrip *hwstrip =
1234 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1236 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1240 IXGBE_SET_HWSTRIP(hwstrip, queue);
1242 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1246 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1248 struct ixgbe_hw *hw =
1249 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1252 PMD_INIT_FUNC_TRACE();
1254 if (hw->mac.type == ixgbe_mac_82598EB) {
1255 /* No queue level support */
1256 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1260 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1261 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1262 ctrl &= ~IXGBE_RXDCTL_VME;
1263 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1265 /* record those setting for HW strip per queue */
1266 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1270 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1272 struct ixgbe_hw *hw =
1273 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276 PMD_INIT_FUNC_TRACE();
1278 if (hw->mac.type == ixgbe_mac_82598EB) {
1279 /* No queue level supported */
1280 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1284 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1285 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1286 ctrl |= IXGBE_RXDCTL_VME;
1287 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1289 /* record those setting for HW strip per queue */
1290 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1294 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1296 struct ixgbe_hw *hw =
1297 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301 PMD_INIT_FUNC_TRACE();
1303 if (hw->mac.type == ixgbe_mac_82598EB) {
1304 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1305 ctrl &= ~IXGBE_VLNCTRL_VME;
1306 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1309 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1310 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1311 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1312 ctrl &= ~IXGBE_RXDCTL_VME;
1313 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1315 /* record those setting for HW strip per queue */
1316 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1322 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1324 struct ixgbe_hw *hw =
1325 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1329 PMD_INIT_FUNC_TRACE();
1331 if (hw->mac.type == ixgbe_mac_82598EB) {
1332 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1333 ctrl |= IXGBE_VLNCTRL_VME;
1334 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1337 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1338 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1339 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1340 ctrl |= IXGBE_RXDCTL_VME;
1341 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1343 /* record those setting for HW strip per queue */
1344 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1350 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1352 struct ixgbe_hw *hw =
1353 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1356 PMD_INIT_FUNC_TRACE();
1358 /* DMATXCTRL: Geric Double VLAN Disable */
1359 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1360 ctrl &= ~IXGBE_DMATXCTL_GDV;
1361 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1363 /* CTRL_EXT: Global Double VLAN Disable */
1364 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1365 ctrl &= ~IXGBE_EXTENDED_VLAN;
1366 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1371 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1373 struct ixgbe_hw *hw =
1374 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1377 PMD_INIT_FUNC_TRACE();
1379 /* DMATXCTRL: Geric Double VLAN Enable */
1380 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1381 ctrl |= IXGBE_DMATXCTL_GDV;
1382 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1384 /* CTRL_EXT: Global Double VLAN Enable */
1385 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1386 ctrl |= IXGBE_EXTENDED_VLAN;
1387 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1390 * VET EXT field in the EXVET register = 0x8100 by default
1391 * So no need to change. Same to VT field of DMATXCTL register
1396 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1398 if(mask & ETH_VLAN_STRIP_MASK){
1399 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1400 ixgbe_vlan_hw_strip_enable_all(dev);
1402 ixgbe_vlan_hw_strip_disable_all(dev);
1405 if(mask & ETH_VLAN_FILTER_MASK){
1406 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1407 ixgbe_vlan_hw_filter_enable(dev);
1409 ixgbe_vlan_hw_filter_disable(dev);
1412 if(mask & ETH_VLAN_EXTEND_MASK){
1413 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1414 ixgbe_vlan_hw_extend_enable(dev);
1416 ixgbe_vlan_hw_extend_disable(dev);
1421 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1423 struct ixgbe_hw *hw =
1424 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1425 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1426 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1427 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1428 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1432 ixgbe_dev_configure(struct rte_eth_dev *dev)
1434 struct ixgbe_interrupt *intr =
1435 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1437 PMD_INIT_FUNC_TRACE();
1439 /* set flag to update link status after init */
1440 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1446 * Configure device link speed and setup link.
1447 * It returns 0 on success.
1450 ixgbe_dev_start(struct rte_eth_dev *dev)
1452 struct ixgbe_hw *hw =
1453 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454 struct ixgbe_vf_info *vfinfo =
1455 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1456 int err, link_up = 0, negotiate = 0;
1462 PMD_INIT_FUNC_TRACE();
1464 /* IXGBE devices don't support half duplex */
1465 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1466 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1467 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1468 dev->data->dev_conf.link_duplex,
1469 dev->data->port_id);
1474 hw->adapter_stopped = FALSE;
1475 ixgbe_stop_adapter(hw);
1477 /* reinitialize adapter
1478 * this calls reset and start */
1479 status = ixgbe_pf_reset_hw(hw);
1482 hw->mac.ops.start_hw(hw);
1483 hw->mac.get_link_status = true;
1485 /* configure PF module if SRIOV enabled */
1486 ixgbe_pf_host_configure(dev);
1488 /* initialize transmission unit */
1489 ixgbe_dev_tx_init(dev);
1491 /* This can fail when allocating mbufs for descriptor rings */
1492 err = ixgbe_dev_rx_init(dev);
1494 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1498 err = ixgbe_dev_rxtx_start(dev);
1500 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1504 /* Skip link setup if loopback mode is enabled for 82599. */
1505 if (hw->mac.type == ixgbe_mac_82599EB &&
1506 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1507 goto skip_link_setup;
1509 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1510 err = hw->mac.ops.setup_sfp(hw);
1515 /* Turn on the laser */
1516 ixgbe_enable_tx_laser(hw);
1518 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1521 dev->data->dev_link.link_status = link_up;
1523 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1527 switch(dev->data->dev_conf.link_speed) {
1528 case ETH_LINK_SPEED_AUTONEG:
1529 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1530 IXGBE_LINK_SPEED_82599_AUTONEG :
1531 IXGBE_LINK_SPEED_82598_AUTONEG;
1533 case ETH_LINK_SPEED_100:
1535 * Invalid for 82598 but error will be detected by
1536 * ixgbe_setup_link()
1538 speed = IXGBE_LINK_SPEED_100_FULL;
1540 case ETH_LINK_SPEED_1000:
1541 speed = IXGBE_LINK_SPEED_1GB_FULL;
1543 case ETH_LINK_SPEED_10000:
1544 speed = IXGBE_LINK_SPEED_10GB_FULL;
1547 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1548 dev->data->dev_conf.link_speed,
1549 dev->data->port_id);
1553 err = ixgbe_setup_link(hw, speed, link_up);
1559 /* check if lsc interrupt is enabled */
1560 if (dev->data->dev_conf.intr_conf.lsc != 0)
1561 ixgbe_dev_lsc_interrupt_setup(dev);
1563 /* resume enabled intr since hw reset */
1564 ixgbe_enable_intr(dev);
1566 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1567 ETH_VLAN_EXTEND_MASK;
1568 ixgbe_vlan_offload_set(dev, mask);
1570 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1571 /* Enable vlan filtering for VMDq */
1572 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1575 /* Configure DCB hw */
1576 ixgbe_configure_dcb(dev);
1578 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1579 err = ixgbe_fdir_configure(dev);
1584 /* Restore vf rate limit */
1585 if (vfinfo != NULL) {
1586 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1587 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1588 if (vfinfo[vf].tx_rate[idx] != 0)
1589 ixgbe_set_vf_rate_limit(dev, vf,
1590 vfinfo[vf].tx_rate[idx],
1594 ixgbe_restore_statistics_mapping(dev);
1599 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1600 ixgbe_dev_clear_queues(dev);
1605 * Stop device: disable rx and tx functions to allow for reconfiguring.
1608 ixgbe_dev_stop(struct rte_eth_dev *dev)
1610 struct rte_eth_link link;
1611 struct ixgbe_hw *hw =
1612 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613 struct ixgbe_vf_info *vfinfo =
1614 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1617 PMD_INIT_FUNC_TRACE();
1619 /* disable interrupts */
1620 ixgbe_disable_intr(hw);
1623 ixgbe_pf_reset_hw(hw);
1624 hw->adapter_stopped = FALSE;
1627 ixgbe_stop_adapter(hw);
1629 for (vf = 0; vfinfo != NULL &&
1630 vf < dev->pci_dev->max_vfs; vf++)
1631 vfinfo[vf].clear_to_send = false;
1633 /* Turn off the laser */
1634 ixgbe_disable_tx_laser(hw);
1636 ixgbe_dev_clear_queues(dev);
1638 /* Clear stored conf */
1639 dev->data->scattered_rx = 0;
1641 /* Clear recorded link status */
1642 memset(&link, 0, sizeof(link));
1643 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1647 * Set device link up: enable tx laser.
1650 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1652 struct ixgbe_hw *hw =
1653 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654 if (hw->mac.type == ixgbe_mac_82599EB) {
1655 #ifdef RTE_NIC_BYPASS
1656 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1657 /* Not suported in bypass mode */
1658 PMD_INIT_LOG(ERR, "Set link up is not supported "
1659 "by device id 0x%x", hw->device_id);
1663 /* Turn on the laser */
1664 ixgbe_enable_tx_laser(hw);
1668 PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1674 * Set device link down: disable tx laser.
1677 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1679 struct ixgbe_hw *hw =
1680 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681 if (hw->mac.type == ixgbe_mac_82599EB) {
1682 #ifdef RTE_NIC_BYPASS
1683 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1684 /* Not suported in bypass mode */
1685 PMD_INIT_LOG(ERR, "Set link down is not supported "
1686 "by device id 0x%x", hw->device_id);
1690 /* Turn off the laser */
1691 ixgbe_disable_tx_laser(hw);
1695 PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1701 * Reest and stop device.
1704 ixgbe_dev_close(struct rte_eth_dev *dev)
1706 struct ixgbe_hw *hw =
1707 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709 PMD_INIT_FUNC_TRACE();
1711 ixgbe_pf_reset_hw(hw);
1713 ixgbe_dev_stop(dev);
1714 hw->adapter_stopped = 1;
1716 ixgbe_disable_pcie_master(hw);
1718 /* reprogram the RAR[0] in case user changed it. */
1719 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1723 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1726 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1728 struct ixgbe_hw *hw =
1729 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1730 struct ixgbe_hw_stats *hw_stats =
1731 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1732 uint32_t bprc, lxon, lxoff, total;
1733 uint64_t total_missed_rx, total_qbrc, total_qprc;
1736 total_missed_rx = 0;
1740 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1741 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1742 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1743 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1745 for (i = 0; i < 8; i++) {
1747 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1748 /* global total per queue */
1749 hw_stats->mpc[i] += mp;
1750 /* Running comprehensive total for stats display */
1751 total_missed_rx += hw_stats->mpc[i];
1752 if (hw->mac.type == ixgbe_mac_82598EB)
1753 hw_stats->rnbc[i] +=
1754 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1755 hw_stats->pxontxc[i] +=
1756 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1757 hw_stats->pxonrxc[i] +=
1758 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1759 hw_stats->pxofftxc[i] +=
1760 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1761 hw_stats->pxoffrxc[i] +=
1762 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1763 hw_stats->pxon2offc[i] +=
1764 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1766 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1767 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1768 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1769 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1770 hw_stats->qbrc[i] +=
1771 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1772 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1773 hw_stats->qbtc[i] +=
1774 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1775 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1777 total_qprc += hw_stats->qprc[i];
1778 total_qbrc += hw_stats->qbrc[i];
1780 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1781 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1782 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1784 /* Note that gprc counts missed packets */
1785 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1787 if (hw->mac.type != ixgbe_mac_82598EB) {
1788 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1789 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1790 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1791 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1792 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1793 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1794 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1795 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1797 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1798 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1799 /* 82598 only has a counter in the high register */
1800 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1801 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1802 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1806 * Workaround: mprc hardware is incorrectly counting
1807 * broadcasts, so for now we subtract those.
1809 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1810 hw_stats->bprc += bprc;
1811 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1812 if (hw->mac.type == ixgbe_mac_82598EB)
1813 hw_stats->mprc -= bprc;
1815 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1816 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1817 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1818 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1819 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1820 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1822 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1823 hw_stats->lxontxc += lxon;
1824 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1825 hw_stats->lxofftxc += lxoff;
1826 total = lxon + lxoff;
1828 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1829 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1830 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1831 hw_stats->gptc -= total;
1832 hw_stats->mptc -= total;
1833 hw_stats->ptc64 -= total;
1834 hw_stats->gotc -= total * ETHER_MIN_LEN;
1836 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1837 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1838 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1839 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1840 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1841 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1842 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1843 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1844 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1845 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1846 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1847 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1848 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1849 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1850 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1851 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1852 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1853 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1854 /* Only read FCOE on 82599 */
1855 if (hw->mac.type != ixgbe_mac_82598EB) {
1856 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1857 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1858 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1859 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1860 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1866 /* Fill out the rte_eth_stats statistics structure */
1867 stats->ipackets = total_qprc;
1868 stats->ibytes = total_qbrc;
1869 stats->opackets = hw_stats->gptc;
1870 stats->obytes = hw_stats->gotc;
1871 stats->imcasts = hw_stats->mprc;
1873 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1874 stats->q_ipackets[i] = hw_stats->qprc[i];
1875 stats->q_opackets[i] = hw_stats->qptc[i];
1876 stats->q_ibytes[i] = hw_stats->qbrc[i];
1877 stats->q_obytes[i] = hw_stats->qbtc[i];
1878 stats->q_errors[i] = hw_stats->qprdc[i];
1882 stats->ibadcrc = hw_stats->crcerrs;
1883 stats->ibadlen = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1884 stats->imissed = total_missed_rx;
1885 stats->ierrors = stats->ibadcrc +
1888 hw_stats->illerrc + hw_stats->errbc;
1893 /* XON/XOFF pause frames */
1894 stats->tx_pause_xon = hw_stats->lxontxc;
1895 stats->rx_pause_xon = hw_stats->lxonrxc;
1896 stats->tx_pause_xoff = hw_stats->lxofftxc;
1897 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1899 /* Flow Director Stats registers */
1900 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1901 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1902 stats->fdirmatch = hw_stats->fdirmatch;
1903 stats->fdirmiss = hw_stats->fdirmiss;
1907 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1909 struct ixgbe_hw_stats *stats =
1910 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1912 /* HW registers are cleared on read */
1913 ixgbe_dev_stats_get(dev, NULL);
1915 /* Reset software totals */
1916 memset(stats, 0, sizeof(*stats));
1920 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1922 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1924 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1926 /* Good Rx packet, include VF loopback */
1927 UPDATE_VF_STAT(IXGBE_VFGPRC,
1928 hw_stats->last_vfgprc, hw_stats->vfgprc);
1930 /* Good Rx octets, include VF loopback */
1931 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1932 hw_stats->last_vfgorc, hw_stats->vfgorc);
1934 /* Good Tx packet, include VF loopback */
1935 UPDATE_VF_STAT(IXGBE_VFGPTC,
1936 hw_stats->last_vfgptc, hw_stats->vfgptc);
1938 /* Good Tx octets, include VF loopback */
1939 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1940 hw_stats->last_vfgotc, hw_stats->vfgotc);
1942 /* Rx Multicst Packet */
1943 UPDATE_VF_STAT(IXGBE_VFMPRC,
1944 hw_stats->last_vfmprc, hw_stats->vfmprc);
1949 stats->ipackets = hw_stats->vfgprc;
1950 stats->ibytes = hw_stats->vfgorc;
1951 stats->opackets = hw_stats->vfgptc;
1952 stats->obytes = hw_stats->vfgotc;
1953 stats->imcasts = hw_stats->vfmprc;
1957 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1959 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1960 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1962 /* Sync HW register to the last stats */
1963 ixgbevf_dev_stats_get(dev, NULL);
1965 /* reset HW current stats*/
1966 hw_stats->vfgprc = 0;
1967 hw_stats->vfgorc = 0;
1968 hw_stats->vfgptc = 0;
1969 hw_stats->vfgotc = 0;
1970 hw_stats->vfmprc = 0;
1975 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1977 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1980 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1981 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1982 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1983 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1984 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1985 dev_info->max_vfs = dev->pci_dev->max_vfs;
1986 if (hw->mac.type == ixgbe_mac_82598EB)
1987 dev_info->max_vmdq_pools = ETH_16_POOLS;
1989 dev_info->max_vmdq_pools = ETH_64_POOLS;
1990 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1991 dev_info->rx_offload_capa =
1992 DEV_RX_OFFLOAD_VLAN_STRIP |
1993 DEV_RX_OFFLOAD_IPV4_CKSUM |
1994 DEV_RX_OFFLOAD_UDP_CKSUM |
1995 DEV_RX_OFFLOAD_TCP_CKSUM;
1996 dev_info->tx_offload_capa =
1997 DEV_TX_OFFLOAD_VLAN_INSERT |
1998 DEV_TX_OFFLOAD_IPV4_CKSUM |
1999 DEV_TX_OFFLOAD_UDP_CKSUM |
2000 DEV_TX_OFFLOAD_TCP_CKSUM |
2001 DEV_TX_OFFLOAD_SCTP_CKSUM |
2002 DEV_TX_OFFLOAD_TCP_TSO;
2004 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2006 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2007 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2008 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2010 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2014 dev_info->default_txconf = (struct rte_eth_txconf) {
2016 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2017 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2018 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2020 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2021 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2022 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2023 ETH_TXQ_FLAGS_NOOFFLOADS,
2025 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2029 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2030 struct rte_eth_dev_info *dev_info)
2032 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2034 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2035 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2036 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2037 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2038 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2039 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2040 dev_info->max_vfs = dev->pci_dev->max_vfs;
2041 if (hw->mac.type == ixgbe_mac_82598EB)
2042 dev_info->max_vmdq_pools = ETH_16_POOLS;
2044 dev_info->max_vmdq_pools = ETH_64_POOLS;
2045 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2046 DEV_RX_OFFLOAD_IPV4_CKSUM |
2047 DEV_RX_OFFLOAD_UDP_CKSUM |
2048 DEV_RX_OFFLOAD_TCP_CKSUM;
2049 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2050 DEV_TX_OFFLOAD_IPV4_CKSUM |
2051 DEV_TX_OFFLOAD_UDP_CKSUM |
2052 DEV_TX_OFFLOAD_TCP_CKSUM |
2053 DEV_TX_OFFLOAD_SCTP_CKSUM;
2055 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2057 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2058 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2059 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2061 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2065 dev_info->default_txconf = (struct rte_eth_txconf) {
2067 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2068 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2069 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2071 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2072 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2073 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2074 ETH_TXQ_FLAGS_NOOFFLOADS,
2078 /* return 0 means link status changed, -1 means not changed */
2080 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2082 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083 struct rte_eth_link link, old;
2084 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2088 link.link_status = 0;
2089 link.link_speed = 0;
2090 link.link_duplex = 0;
2091 memset(&old, 0, sizeof(old));
2092 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2094 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2095 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2096 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2098 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2100 link.link_speed = ETH_LINK_SPEED_100;
2101 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2102 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2103 if (link.link_status == old.link_status)
2108 if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2109 !hw->mac.get_link_status) {
2110 memcpy(&link, &old, sizeof(link));
2115 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2116 if (link.link_status == old.link_status)
2120 link.link_status = 1;
2121 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2123 switch (link_speed) {
2125 case IXGBE_LINK_SPEED_UNKNOWN:
2126 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2127 link.link_speed = ETH_LINK_SPEED_100;
2130 case IXGBE_LINK_SPEED_100_FULL:
2131 link.link_speed = ETH_LINK_SPEED_100;
2134 case IXGBE_LINK_SPEED_1GB_FULL:
2135 link.link_speed = ETH_LINK_SPEED_1000;
2138 case IXGBE_LINK_SPEED_10GB_FULL:
2139 link.link_speed = ETH_LINK_SPEED_10000;
2142 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2144 if (link.link_status == old.link_status)
2151 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2153 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2157 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2158 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2162 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2164 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2168 fctrl &= (~IXGBE_FCTRL_UPE);
2169 if (dev->data->all_multicast == 1)
2170 fctrl |= IXGBE_FCTRL_MPE;
2172 fctrl &= (~IXGBE_FCTRL_MPE);
2173 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2177 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2179 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2183 fctrl |= IXGBE_FCTRL_MPE;
2184 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2188 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2190 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193 if (dev->data->promiscuous == 1)
2194 return; /* must remain in all_multicast mode */
2196 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2197 fctrl &= (~IXGBE_FCTRL_MPE);
2198 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2202 * It clears the interrupt causes and enables the interrupt.
2203 * It will be called once only during nic initialized.
2206 * Pointer to struct rte_eth_dev.
2209 * - On success, zero.
2210 * - On failure, a negative value.
2213 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2215 struct ixgbe_interrupt *intr =
2216 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2218 ixgbe_dev_link_status_print(dev);
2219 intr->mask |= IXGBE_EICR_LSC;
2225 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2228 * Pointer to struct rte_eth_dev.
2231 * - On success, zero.
2232 * - On failure, a negative value.
2235 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2238 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 struct ixgbe_interrupt *intr =
2240 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2242 /* clear all cause mask */
2243 ixgbe_disable_intr(hw);
2245 /* read-on-clear nic registers here */
2246 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2247 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2250 if (eicr & IXGBE_EICR_LSC) {
2251 /* set flag for async link update */
2252 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2255 if (eicr & IXGBE_EICR_MAILBOX)
2256 intr->flags |= IXGBE_FLAG_MAILBOX;
2262 * It gets and then prints the link status.
2265 * Pointer to struct rte_eth_dev.
2268 * - On success, zero.
2269 * - On failure, a negative value.
2272 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2274 struct rte_eth_link link;
2276 memset(&link, 0, sizeof(link));
2277 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2278 if (link.link_status) {
2279 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2280 (int)(dev->data->port_id),
2281 (unsigned)link.link_speed,
2282 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2283 "full-duplex" : "half-duplex");
2285 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2286 (int)(dev->data->port_id));
2288 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2289 dev->pci_dev->addr.domain,
2290 dev->pci_dev->addr.bus,
2291 dev->pci_dev->addr.devid,
2292 dev->pci_dev->addr.function);
2296 * It executes link_update after knowing an interrupt occurred.
2299 * Pointer to struct rte_eth_dev.
2302 * - On success, zero.
2303 * - On failure, a negative value.
2306 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2308 struct ixgbe_interrupt *intr =
2309 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2311 struct rte_eth_link link;
2312 int intr_enable_delay = false;
2314 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2316 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2317 ixgbe_pf_mbx_process(dev);
2318 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2321 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2322 /* get the link status before link update, for predicting later */
2323 memset(&link, 0, sizeof(link));
2324 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2326 ixgbe_dev_link_update(dev, 0);
2329 if (!link.link_status)
2330 /* handle it 1 sec later, wait it being stable */
2331 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2332 /* likely to down */
2334 /* handle it 4 sec later, wait it being stable */
2335 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2337 ixgbe_dev_link_status_print(dev);
2339 intr_enable_delay = true;
2342 if (intr_enable_delay) {
2343 if (rte_eal_alarm_set(timeout * 1000,
2344 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2345 PMD_DRV_LOG(ERR, "Error setting alarm");
2347 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2348 ixgbe_enable_intr(dev);
2349 rte_intr_enable(&(dev->pci_dev->intr_handle));
2357 * Interrupt handler which shall be registered for alarm callback for delayed
2358 * handling specific interrupt to wait for the stable nic state. As the
2359 * NIC interrupt state is not stable for ixgbe after link is just down,
2360 * it needs to wait 4 seconds to get the stable status.
2363 * Pointer to interrupt handle.
2365 * The address of parameter (struct rte_eth_dev *) regsitered before.
2371 ixgbe_dev_interrupt_delayed_handler(void *param)
2373 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2374 struct ixgbe_interrupt *intr =
2375 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2376 struct ixgbe_hw *hw =
2377 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2381 if (eicr & IXGBE_EICR_MAILBOX)
2382 ixgbe_pf_mbx_process(dev);
2384 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2385 ixgbe_dev_link_update(dev, 0);
2386 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2387 ixgbe_dev_link_status_print(dev);
2388 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2391 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2392 ixgbe_enable_intr(dev);
2393 rte_intr_enable(&(dev->pci_dev->intr_handle));
2397 * Interrupt handler triggered by NIC for handling
2398 * specific interrupt.
2401 * Pointer to interrupt handle.
2403 * The address of parameter (struct rte_eth_dev *) regsitered before.
2409 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2412 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2413 ixgbe_dev_interrupt_get_status(dev);
2414 ixgbe_dev_interrupt_action(dev);
2418 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2420 struct ixgbe_hw *hw;
2422 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2427 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2429 struct ixgbe_hw *hw;
2431 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2432 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2436 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2438 struct ixgbe_hw *hw;
2444 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446 fc_conf->pause_time = hw->fc.pause_time;
2447 fc_conf->high_water = hw->fc.high_water[0];
2448 fc_conf->low_water = hw->fc.low_water[0];
2449 fc_conf->send_xon = hw->fc.send_xon;
2450 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2453 * Return rx_pause status according to actual setting of
2456 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2457 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2463 * Return tx_pause status according to actual setting of
2466 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2467 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2472 if (rx_pause && tx_pause)
2473 fc_conf->mode = RTE_FC_FULL;
2475 fc_conf->mode = RTE_FC_RX_PAUSE;
2477 fc_conf->mode = RTE_FC_TX_PAUSE;
2479 fc_conf->mode = RTE_FC_NONE;
2485 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2487 struct ixgbe_hw *hw;
2489 uint32_t rx_buf_size;
2490 uint32_t max_high_water;
2492 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2499 PMD_INIT_FUNC_TRACE();
2501 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2502 if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2504 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2505 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2508 * At least reserve one Ethernet frame for watermark
2509 * high_water/low_water in kilo bytes for ixgbe
2511 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2512 if ((fc_conf->high_water > max_high_water) ||
2513 (fc_conf->high_water < fc_conf->low_water)) {
2514 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2515 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2519 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2520 hw->fc.pause_time = fc_conf->pause_time;
2521 hw->fc.high_water[0] = fc_conf->high_water;
2522 hw->fc.low_water[0] = fc_conf->low_water;
2523 hw->fc.send_xon = fc_conf->send_xon;
2525 err = ixgbe_fc_enable(hw);
2527 /* Not negotiated is not an error case */
2528 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2530 /* check if we want to forward MAC frames - driver doesn't have native
2531 * capability to do that, so we'll write the registers ourselves */
2533 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2535 /* set or clear MFLCN.PMCF bit depending on configuration */
2536 if (fc_conf->mac_ctrl_frame_fwd != 0)
2537 mflcn |= IXGBE_MFLCN_PMCF;
2539 mflcn &= ~IXGBE_MFLCN_PMCF;
2541 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2542 IXGBE_WRITE_FLUSH(hw);
2547 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2552 * ixgbe_pfc_enable_generic - Enable flow control
2553 * @hw: pointer to hardware structure
2554 * @tc_num: traffic class number
2555 * Enable flow control according to the current settings.
2558 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2561 uint32_t mflcn_reg, fccfg_reg;
2563 uint32_t fcrtl, fcrth;
2567 /* Validate the water mark configuration */
2568 if (!hw->fc.pause_time) {
2569 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2573 /* Low water mark of zero causes XOFF floods */
2574 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2575 /* High/Low water can not be 0 */
2576 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2577 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2578 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2582 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2583 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2584 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2588 /* Negotiate the fc mode to use */
2589 ixgbe_fc_autoneg(hw);
2591 /* Disable any previous flow control settings */
2592 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2593 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2595 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2596 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2598 switch (hw->fc.current_mode) {
2601 * If the count of enabled RX Priority Flow control >1,
2602 * and the TX pause can not be disabled
2605 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2606 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2607 if (reg & IXGBE_FCRTH_FCEN)
2611 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2613 case ixgbe_fc_rx_pause:
2615 * Rx Flow control is enabled and Tx Flow control is
2616 * disabled by software override. Since there really
2617 * isn't a way to advertise that we are capable of RX
2618 * Pause ONLY, we will advertise that we support both
2619 * symmetric and asymmetric Rx PAUSE. Later, we will
2620 * disable the adapter's ability to send PAUSE frames.
2622 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2624 * If the count of enabled RX Priority Flow control >1,
2625 * and the TX pause can not be disabled
2628 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2629 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2630 if (reg & IXGBE_FCRTH_FCEN)
2634 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2636 case ixgbe_fc_tx_pause:
2638 * Tx Flow control is enabled, and Rx Flow control is
2639 * disabled by software override.
2641 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2644 /* Flow control (both Rx and Tx) is enabled by SW override. */
2645 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2646 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2649 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2650 ret_val = IXGBE_ERR_CONFIG;
2655 /* Set 802.3x based flow control settings. */
2656 mflcn_reg |= IXGBE_MFLCN_DPF;
2657 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2658 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2660 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2661 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2662 hw->fc.high_water[tc_num]) {
2663 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2664 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2665 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2667 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2669 * In order to prevent Tx hangs when the internal Tx
2670 * switch is enabled we must set the high water mark
2671 * to the maximum FCRTH value. This allows the Tx
2672 * switch to function even under heavy Rx workloads.
2674 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2676 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2678 /* Configure pause time (2 TCs per register) */
2679 reg = hw->fc.pause_time * 0x00010001;
2680 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2681 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2683 /* Configure flow control refresh threshold value */
2684 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2691 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2693 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2694 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2696 if(hw->mac.type != ixgbe_mac_82598EB) {
2697 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2703 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2706 uint32_t rx_buf_size;
2707 uint32_t max_high_water;
2709 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2710 struct ixgbe_hw *hw =
2711 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712 struct ixgbe_dcb_config *dcb_config =
2713 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2715 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2722 PMD_INIT_FUNC_TRACE();
2724 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2725 tc_num = map[pfc_conf->priority];
2726 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2727 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2729 * At least reserve one Ethernet frame for watermark
2730 * high_water/low_water in kilo bytes for ixgbe
2732 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2733 if ((pfc_conf->fc.high_water > max_high_water) ||
2734 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2735 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2736 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2740 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2741 hw->fc.pause_time = pfc_conf->fc.pause_time;
2742 hw->fc.send_xon = pfc_conf->fc.send_xon;
2743 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2744 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2746 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2748 /* Not negotiated is not an error case */
2749 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2752 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2757 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2758 struct rte_eth_rss_reta_entry64 *reta_conf,
2763 uint16_t idx, shift;
2764 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766 PMD_INIT_FUNC_TRACE();
2767 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2768 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2769 "(%d) doesn't match the number hardware can supported "
2770 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2774 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2775 idx = i / RTE_RETA_GROUP_SIZE;
2776 shift = i % RTE_RETA_GROUP_SIZE;
2777 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2781 if (mask == IXGBE_4_BIT_MASK)
2784 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2785 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2786 if (mask & (0x1 << j))
2787 reta |= reta_conf[idx].reta[shift + j] <<
2790 reta |= r & (IXGBE_8_BIT_MASK <<
2793 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2800 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2801 struct rte_eth_rss_reta_entry64 *reta_conf,
2806 uint16_t idx, shift;
2807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2809 PMD_INIT_FUNC_TRACE();
2810 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2811 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2812 "(%d) doesn't match the number hardware can supported "
2813 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2817 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2818 idx = i / RTE_RETA_GROUP_SIZE;
2819 shift = i % RTE_RETA_GROUP_SIZE;
2820 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2825 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2826 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2827 if (mask & (0x1 << j))
2828 reta_conf[idx].reta[shift + j] =
2829 ((reta >> (CHAR_BIT * j)) &
2838 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2839 uint32_t index, uint32_t pool)
2841 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 uint32_t enable_addr = 1;
2844 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2848 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2850 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2852 ixgbe_clear_rar(hw, index);
2856 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2860 struct ixgbe_hw *hw;
2861 struct rte_eth_dev_info dev_info;
2862 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2864 ixgbe_dev_info_get(dev, &dev_info);
2866 /* check that mtu is within the allowed range */
2867 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2870 /* refuse mtu that requires the support of scattered packets when this
2871 * feature has not been enabled before. */
2872 if (!dev->data->scattered_rx &&
2873 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2874 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2877 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2880 /* switch to jumbo mode if needed */
2881 if (frame_size > ETHER_MAX_LEN) {
2882 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2883 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2885 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2886 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2888 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2890 /* update max frame size */
2891 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2893 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2894 maxfrs &= 0x0000FFFF;
2895 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2896 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2902 * Virtual Function operations
2905 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2907 PMD_INIT_FUNC_TRACE();
2909 /* Clear interrupt mask to stop from interrupts being generated */
2910 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2912 IXGBE_WRITE_FLUSH(hw);
2916 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2918 struct rte_eth_conf* conf = &dev->data->dev_conf;
2920 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2921 dev->data->port_id);
2924 * VF has no ability to enable/disable HW CRC
2925 * Keep the persistent behavior the same as Host PF
2927 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2928 if (!conf->rxmode.hw_strip_crc) {
2929 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2930 conf->rxmode.hw_strip_crc = 1;
2933 if (conf->rxmode.hw_strip_crc) {
2934 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2935 conf->rxmode.hw_strip_crc = 0;
2943 ixgbevf_dev_start(struct rte_eth_dev *dev)
2945 struct ixgbe_hw *hw =
2946 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949 PMD_INIT_FUNC_TRACE();
2951 hw->mac.ops.reset_hw(hw);
2952 hw->mac.get_link_status = true;
2954 /* negotiate mailbox API version to use with the PF. */
2955 ixgbevf_negotiate_api(hw);
2957 ixgbevf_dev_tx_init(dev);
2959 /* This can fail when allocating mbufs for descriptor rings */
2960 err = ixgbevf_dev_rx_init(dev);
2962 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2963 ixgbe_dev_clear_queues(dev);
2968 ixgbevf_set_vfta_all(dev,1);
2971 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2972 ETH_VLAN_EXTEND_MASK;
2973 ixgbevf_vlan_offload_set(dev, mask);
2975 ixgbevf_dev_rxtx_start(dev);
2981 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2983 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2985 PMD_INIT_FUNC_TRACE();
2987 hw->adapter_stopped = TRUE;
2988 ixgbe_stop_adapter(hw);
2991 * Clear what we set, but we still keep shadow_vfta to
2992 * restore after device starts
2994 ixgbevf_set_vfta_all(dev,0);
2996 /* Clear stored conf */
2997 dev->data->scattered_rx = 0;
2999 ixgbe_dev_clear_queues(dev);
3003 ixgbevf_dev_close(struct rte_eth_dev *dev)
3005 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3007 PMD_INIT_FUNC_TRACE();
3011 ixgbevf_dev_stop(dev);
3013 /* reprogram the RAR[0] in case user changed it. */
3014 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3017 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3020 struct ixgbe_vfta * shadow_vfta =
3021 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3022 int i = 0, j = 0, vfta = 0, mask = 1;
3024 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3025 vfta = shadow_vfta->vfta[i];
3028 for (j = 0; j < 32; j++){
3030 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3039 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3041 struct ixgbe_hw *hw =
3042 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3043 struct ixgbe_vfta * shadow_vfta =
3044 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3045 uint32_t vid_idx = 0;
3046 uint32_t vid_bit = 0;
3049 PMD_INIT_FUNC_TRACE();
3051 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3052 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3054 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3057 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3058 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3060 /* Save what we set and retore it after device reset */
3062 shadow_vfta->vfta[vid_idx] |= vid_bit;
3064 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3070 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3072 struct ixgbe_hw *hw =
3073 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076 PMD_INIT_FUNC_TRACE();
3078 if(queue >= hw->mac.max_rx_queues)
3081 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3083 ctrl |= IXGBE_RXDCTL_VME;
3085 ctrl &= ~IXGBE_RXDCTL_VME;
3086 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3088 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3092 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3094 struct ixgbe_hw *hw =
3095 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3099 /* VF function only support hw strip feature, others are not support */
3100 if(mask & ETH_VLAN_STRIP_MASK){
3101 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3103 for(i=0; i < hw->mac.max_rx_queues; i++)
3104 ixgbevf_vlan_strip_queue_set(dev,i,on);
3109 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3113 /* we only need to do this if VMDq is enabled */
3114 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3115 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3116 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3124 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3126 uint32_t vector = 0;
3127 switch (hw->mac.mc_filter_type) {
3128 case 0: /* use bits [47:36] of the address */
3129 vector = ((uc_addr->addr_bytes[4] >> 4) |
3130 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3132 case 1: /* use bits [46:35] of the address */
3133 vector = ((uc_addr->addr_bytes[4] >> 3) |
3134 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3136 case 2: /* use bits [45:34] of the address */
3137 vector = ((uc_addr->addr_bytes[4] >> 2) |
3138 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3140 case 3: /* use bits [43:32] of the address */
3141 vector = ((uc_addr->addr_bytes[4]) |
3142 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3144 default: /* Invalid mc_filter_type */
3148 /* vector can only be 12-bits or boundary will be exceeded */
3154 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3162 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3163 const uint32_t ixgbe_uta_bit_shift = 5;
3164 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3165 const uint32_t bit1 = 0x1;
3167 struct ixgbe_hw *hw =
3168 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169 struct ixgbe_uta_info *uta_info =
3170 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3172 /* The UTA table only exists on 82599 hardware and newer */
3173 if (hw->mac.type < ixgbe_mac_82599EB)
3176 vector = ixgbe_uta_vector(hw,mac_addr);
3177 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3178 uta_shift = vector & ixgbe_uta_bit_mask;
3180 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3184 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3186 uta_info->uta_in_use++;
3187 reg_val |= (bit1 << uta_shift);
3188 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3190 uta_info->uta_in_use--;
3191 reg_val &= ~(bit1 << uta_shift);
3192 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3195 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3197 if (uta_info->uta_in_use > 0)
3198 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3199 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3201 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3207 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3210 struct ixgbe_hw *hw =
3211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212 struct ixgbe_uta_info *uta_info =
3213 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3215 /* The UTA table only exists on 82599 hardware and newer */
3216 if (hw->mac.type < ixgbe_mac_82599EB)
3220 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3221 uta_info->uta_shadow[i] = ~0;
3222 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3225 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3226 uta_info->uta_shadow[i] = 0;
3227 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3235 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3237 uint32_t new_val = orig_val;
3239 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3240 new_val |= IXGBE_VMOLR_AUPE;
3241 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3242 new_val |= IXGBE_VMOLR_ROMPE;
3243 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3244 new_val |= IXGBE_VMOLR_ROPE;
3245 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3246 new_val |= IXGBE_VMOLR_BAM;
3247 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3248 new_val |= IXGBE_VMOLR_MPE;
3254 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3255 uint16_t rx_mask, uint8_t on)
3259 struct ixgbe_hw *hw =
3260 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3261 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3263 if (hw->mac.type == ixgbe_mac_82598EB) {
3264 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3265 " on 82599 hardware and newer");
3268 if (ixgbe_vmdq_mode_check(hw) < 0)
3271 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3278 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3284 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3288 const uint8_t bit1 = 0x1;
3290 struct ixgbe_hw *hw =
3291 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3293 if (ixgbe_vmdq_mode_check(hw) < 0)
3296 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3297 reg = IXGBE_READ_REG(hw, addr);
3305 IXGBE_WRITE_REG(hw, addr,reg);
3311 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3315 const uint8_t bit1 = 0x1;
3317 struct ixgbe_hw *hw =
3318 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3320 if (ixgbe_vmdq_mode_check(hw) < 0)
3323 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3324 reg = IXGBE_READ_REG(hw, addr);
3332 IXGBE_WRITE_REG(hw, addr,reg);
3338 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3339 uint64_t pool_mask, uint8_t vlan_on)
3343 struct ixgbe_hw *hw =
3344 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3346 if (ixgbe_vmdq_mode_check(hw) < 0)
3348 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3349 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3350 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3359 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3360 struct rte_eth_vmdq_mirror_conf *mirror_conf,
3361 uint8_t rule_id, uint8_t on)
3363 uint32_t mr_ctl,vlvf;
3364 uint32_t mp_lsb = 0;
3365 uint32_t mv_msb = 0;
3366 uint32_t mv_lsb = 0;
3367 uint32_t mp_msb = 0;
3370 uint64_t vlan_mask = 0;
3372 const uint8_t pool_mask_offset = 32;
3373 const uint8_t vlan_mask_offset = 32;
3374 const uint8_t dst_pool_offset = 8;
3375 const uint8_t rule_mr_offset = 4;
3376 const uint8_t mirror_rule_mask= 0x0F;
3378 struct ixgbe_mirror_info *mr_info =
3379 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3380 struct ixgbe_hw *hw =
3381 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3383 if (ixgbe_vmdq_mode_check(hw) < 0)
3386 /* Check if vlan mask is valid */
3387 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3388 if (mirror_conf->vlan.vlan_mask == 0)
3392 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3393 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3394 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3395 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3396 /* search vlan id related pool vlan filter index */
3397 reg_index = ixgbe_find_vlvf_slot(hw,
3398 mirror_conf->vlan.vlan_id[i]);
3401 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3402 if ((vlvf & IXGBE_VLVF_VIEN) &&
3403 ((vlvf & IXGBE_VLVF_VLANID_MASK)
3404 == mirror_conf->vlan.vlan_id[i]))
3405 vlan_mask |= (1ULL << reg_index);
3412 mv_lsb = vlan_mask & 0xFFFFFFFF;
3413 mv_msb = vlan_mask >> vlan_mask_offset;
3415 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3416 mirror_conf->vlan.vlan_mask;
3417 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3418 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3419 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3420 mirror_conf->vlan.vlan_id[i];
3425 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3426 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3427 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3432 * if enable pool mirror, write related pool mask register,if disable
3433 * pool mirror, clear PFMRVM register
3435 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3437 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3438 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3439 mr_info->mr_conf[rule_id].pool_mask =
3440 mirror_conf->pool_mask;
3445 mr_info->mr_conf[rule_id].pool_mask = 0;
3449 /* read mirror control register and recalculate it */
3450 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3453 mr_ctl |= mirror_conf->rule_type_mask;
3454 mr_ctl &= mirror_rule_mask;
3455 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3457 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3459 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3460 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3462 /* write mirrror control register */
3463 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3465 /* write pool mirrror control register */
3466 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3467 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3468 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3471 /* write VLAN mirrror control register */
3472 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3473 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3474 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3482 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3485 uint32_t lsb_val = 0;
3486 uint32_t msb_val = 0;
3487 const uint8_t rule_mr_offset = 4;
3489 struct ixgbe_hw *hw =
3490 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3491 struct ixgbe_mirror_info *mr_info =
3492 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3494 if (ixgbe_vmdq_mode_check(hw) < 0)
3497 memset(&mr_info->mr_conf[rule_id], 0,
3498 sizeof(struct rte_eth_vmdq_mirror_conf));
3500 /* clear PFVMCTL register */
3501 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3503 /* clear pool mask register */
3504 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3505 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3507 /* clear vlan mask register */
3508 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3509 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3514 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3515 uint16_t queue_idx, uint16_t tx_rate)
3517 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518 uint32_t rf_dec, rf_int;
3520 uint16_t link_speed = dev->data->dev_link.link_speed;
3522 if (queue_idx >= hw->mac.max_tx_queues)
3526 /* Calculate the rate factor values to set */
3527 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3528 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3529 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3531 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3532 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3533 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3534 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3540 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3541 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3544 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3545 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3546 IXGBE_MAX_JUMBO_FRAME_SIZE))
3547 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3548 IXGBE_MMW_SIZE_JUMBO_FRAME);
3550 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3551 IXGBE_MMW_SIZE_DEFAULT);
3553 /* Set RTTBCNRC of queue X */
3554 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3555 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3556 IXGBE_WRITE_FLUSH(hw);
3561 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3562 uint16_t tx_rate, uint64_t q_msk)
3564 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565 struct ixgbe_vf_info *vfinfo =
3566 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3567 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3568 uint32_t queue_stride =
3569 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3570 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3571 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3572 uint16_t total_rate = 0;
3574 if (queue_end >= hw->mac.max_tx_queues)
3577 if (vfinfo != NULL) {
3578 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3581 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3583 total_rate += vfinfo[vf_idx].tx_rate[idx];
3588 /* Store tx_rate for this vf. */
3589 for (idx = 0; idx < nb_q_per_pool; idx++) {
3590 if (((uint64_t)0x1 << idx) & q_msk) {
3591 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3592 vfinfo[vf].tx_rate[idx] = tx_rate;
3593 total_rate += tx_rate;
3597 if (total_rate > dev->data->dev_link.link_speed) {
3599 * Reset stored TX rate of the VF if it causes exceed
3602 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3606 /* Set RTTBCNRC of each queue/pool for vf X */
3607 for (; queue_idx <= queue_end; queue_idx++) {
3609 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3617 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3618 __attribute__((unused)) uint32_t index,
3619 __attribute__((unused)) uint32_t pool)
3621 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3625 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3626 * operation. Trap this case to avoid exhausting the [very limited]
3627 * set of PF resources used to store VF MAC addresses.
3629 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3631 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3634 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3638 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3640 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3642 struct ether_addr *mac_addr;
3647 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3648 * not support the deletion of a given MAC address.
3649 * Instead, it imposes to delete all MAC addresses, then to add again
3650 * all MAC addresses with the exception of the one to be deleted.
3652 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3655 * Add again all MAC addresses, with the exception of the deleted one
3656 * and of the permanent MAC address.
3658 for (i = 0, mac_addr = dev->data->mac_addrs;
3659 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3660 /* Skip the deleted MAC address */
3663 /* Skip NULL MAC addresses */
3664 if (is_zero_ether_addr(mac_addr))
3666 /* Skip the permanent MAC address */
3667 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3669 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3672 "Adding again MAC address "
3673 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3675 mac_addr->addr_bytes[0],
3676 mac_addr->addr_bytes[1],
3677 mac_addr->addr_bytes[2],
3678 mac_addr->addr_bytes[3],
3679 mac_addr->addr_bytes[4],
3680 mac_addr->addr_bytes[5],
3689 * dev: Pointer to struct rte_eth_dev.
3690 * filter: ponter to the filter that will be added.
3691 * rx_queue: the queue id the filter assigned to.
3694 * - On success, zero.
3695 * - On failure, a negative value.
3698 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3699 struct rte_syn_filter *filter, uint16_t rx_queue)
3701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704 if (hw->mac.type != ixgbe_mac_82599EB)
3707 if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3710 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3712 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3715 synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3716 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3718 if (filter->hig_pri)
3719 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3721 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3723 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3731 * dev: Pointer to struct rte_eth_dev.
3734 * - On success, zero.
3735 * - On failure, a negative value.
3738 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3740 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3743 if (hw->mac.type != ixgbe_mac_82599EB)
3746 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3748 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3750 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3755 * get the syn filter's info
3758 * dev: Pointer to struct rte_eth_dev.
3759 * filter: ponter to the filter that returns.
3760 * *rx_queue: pointer to the queue id the filter assigned to.
3763 * - On success, zero.
3764 * - On failure, a negative value.
3767 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3768 struct rte_syn_filter *filter, uint16_t *rx_queue)
3771 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3774 if (hw->mac.type != ixgbe_mac_82599EB)
3777 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3778 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3779 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3780 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3786 static inline enum ixgbe_5tuple_protocol
3787 convert_protocol_type(uint8_t protocol_value)
3789 if (protocol_value == IPPROTO_TCP)
3790 return IXGBE_FILTER_PROTOCOL_TCP;
3791 else if (protocol_value == IPPROTO_UDP)
3792 return IXGBE_FILTER_PROTOCOL_UDP;
3793 else if (protocol_value == IPPROTO_SCTP)
3794 return IXGBE_FILTER_PROTOCOL_SCTP;
3796 return IXGBE_FILTER_PROTOCOL_NONE;
3799 static inline uint8_t
3800 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3802 if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3804 else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3806 else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3807 return IPPROTO_SCTP;
3813 * add a 5tuple filter
3816 * dev: Pointer to struct rte_eth_dev.
3817 * index: the index the filter allocates.
3818 * filter: ponter to the filter that will be added.
3819 * rx_queue: the queue id the filter assigned to.
3822 * - On success, zero.
3823 * - On failure, a negative value.
3826 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3827 struct rte_5tuple_filter *filter, uint16_t rx_queue)
3829 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3830 uint32_t ftqf, sdpqf = 0;
3831 uint32_t l34timir = 0;
3832 uint8_t mask = 0xff;
3834 if (hw->mac.type != ixgbe_mac_82599EB)
3837 if (index >= IXGBE_MAX_FTQF_FILTERS ||
3838 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3839 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3840 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3841 return -EINVAL; /* filter index is out of range. */
3843 if (filter->tcp_flags) {
3844 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3848 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3849 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3850 return -EINVAL; /* filter index is in use. */
3853 sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3854 sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3856 ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3857 IXGBE_FTQF_PROTOCOL_MASK);
3858 ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3859 IXGBE_FTQF_PRIORITY_SHIFT);
3860 if (filter->src_ip_mask == 0) /* 0 means compare. */
3861 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3862 if (filter->dst_ip_mask == 0)
3863 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3864 if (filter->src_port_mask == 0)
3865 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3866 if (filter->dst_port_mask == 0)
3867 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3868 if (filter->protocol_mask == 0)
3869 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3870 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3871 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3872 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3874 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3875 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3876 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3877 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3879 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3880 l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3881 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3886 * remove a 5tuple filter
3889 * dev: Pointer to struct rte_eth_dev.
3890 * index: the index the filter allocates.
3893 * - On success, zero.
3894 * - On failure, a negative value.
3897 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3902 if (hw->mac.type != ixgbe_mac_82599EB)
3905 if (index >= IXGBE_MAX_FTQF_FILTERS)
3906 return -EINVAL; /* filter index is out of range. */
3908 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3909 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3910 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3911 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3912 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3917 * get a 5tuple filter
3920 * dev: Pointer to struct rte_eth_dev.
3921 * index: the index the filter allocates
3922 * filter: ponter to the filter that returns.
3923 * *rx_queue: pointer of the queue id the filter assigned to.
3926 * - On success, zero.
3927 * - On failure, a negative value.
3930 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3931 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3933 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3934 uint32_t sdpqf, ftqf, l34timir;
3936 enum ixgbe_5tuple_protocol proto;
3938 if (hw->mac.type != ixgbe_mac_82599EB)
3941 if (index >= IXGBE_MAX_FTQF_FILTERS)
3942 return -EINVAL; /* filter index is out of range. */
3944 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3945 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3946 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3947 filter->protocol = revert_protocol_type(proto);
3948 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3949 IXGBE_FTQF_PRIORITY_MASK;
3950 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3951 IXGBE_FTQF_5TUPLE_MASK_MASK);
3952 filter->src_ip_mask =
3953 (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3954 filter->dst_ip_mask =
3955 (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3956 filter->src_port_mask =
3957 (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3958 filter->dst_port_mask =
3959 (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3960 filter->protocol_mask =
3961 (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3963 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3964 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3965 IXGBE_SDPQF_DSTPORT_SHIFT;
3966 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3967 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3968 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3970 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3971 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3972 IXGBE_L34T_IMIR_QUEUE_SHIFT;
3979 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3981 struct ixgbe_hw *hw;
3982 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3984 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3986 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3989 /* refuse mtu that requires the support of scattered packets when this
3990 * feature has not been enabled before. */
3991 if (!dev->data->scattered_rx &&
3992 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3993 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3997 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3998 * request of the version 2.0 of the mailbox API.
3999 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4000 * of the mailbox API.
4001 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4002 * prior to 3.11.33 which contains the following change:
4003 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4005 ixgbevf_rlpml_set_vf(hw, max_frame);
4007 /* update max frame size */
4008 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4012 #define MAC_TYPE_FILTER_SUP(type) do {\
4013 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4014 (type) != ixgbe_mac_X550)\
4019 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4024 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4025 if (filter_info->ethertype_filters[i] == ethertype &&
4026 (filter_info->ethertype_mask & (1 << i)))
4033 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4038 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4039 if (!(filter_info->ethertype_mask & (1 << i))) {
4040 filter_info->ethertype_mask |= 1 << i;
4041 filter_info->ethertype_filters[i] = ethertype;
4049 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4052 if (idx >= IXGBE_MAX_ETQF_FILTERS)
4054 filter_info->ethertype_mask &= ~(1 << idx);
4055 filter_info->ethertype_filters[idx] = 0;
4060 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4061 struct rte_eth_ethertype_filter *filter,
4064 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065 struct ixgbe_filter_info *filter_info =
4066 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4071 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4074 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4075 filter->ether_type == ETHER_TYPE_IPv6) {
4076 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4077 " ethertype filter.", filter->ether_type);
4081 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4082 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4085 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4086 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4090 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4091 if (ret >= 0 && add) {
4092 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4093 filter->ether_type);
4096 if (ret < 0 && !add) {
4097 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4098 filter->ether_type);
4103 ret = ixgbe_ethertype_filter_insert(filter_info,
4104 filter->ether_type);
4106 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4109 etqf = IXGBE_ETQF_FILTER_EN;
4110 etqf |= (uint32_t)filter->ether_type;
4111 etqs |= (uint32_t)((filter->queue <<
4112 IXGBE_ETQS_RX_QUEUE_SHIFT) &
4113 IXGBE_ETQS_RX_QUEUE);
4114 etqs |= IXGBE_ETQS_QUEUE_EN;
4116 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4120 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4121 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4122 IXGBE_WRITE_FLUSH(hw);
4128 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4129 struct rte_eth_ethertype_filter *filter)
4131 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4132 struct ixgbe_filter_info *filter_info =
4133 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4134 uint32_t etqf, etqs;
4137 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4139 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4140 filter->ether_type);
4144 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4145 if (etqf & IXGBE_ETQF_FILTER_EN) {
4146 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4147 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4149 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4150 IXGBE_ETQS_RX_QUEUE_SHIFT;
4157 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4158 * @dev: pointer to rte_eth_dev structure
4159 * @filter_op:operation will be taken.
4160 * @arg: a pointer to specific structure corresponding to the filter_op
4163 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4164 enum rte_filter_op filter_op,
4167 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4170 MAC_TYPE_FILTER_SUP(hw->mac.type);
4172 if (filter_op == RTE_ETH_FILTER_NOP)
4176 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4181 switch (filter_op) {
4182 case RTE_ETH_FILTER_ADD:
4183 ret = ixgbe_add_del_ethertype_filter(dev,
4184 (struct rte_eth_ethertype_filter *)arg,
4187 case RTE_ETH_FILTER_DELETE:
4188 ret = ixgbe_add_del_ethertype_filter(dev,
4189 (struct rte_eth_ethertype_filter *)arg,
4192 case RTE_ETH_FILTER_GET:
4193 ret = ixgbe_get_ethertype_filter(dev,
4194 (struct rte_eth_ethertype_filter *)arg);
4197 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4205 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4206 enum rte_filter_type filter_type,
4207 enum rte_filter_op filter_op,
4212 switch (filter_type) {
4213 case RTE_ETH_FILTER_ETHERTYPE:
4214 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4217 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4225 static struct rte_driver rte_ixgbe_driver = {
4227 .init = rte_ixgbe_pmd_init,
4230 static struct rte_driver rte_ixgbevf_driver = {
4232 .init = rte_ixgbevf_pmd_init,
4235 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4236 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);