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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_tailq.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
62 #include "ixgbe_logs.h"
63 #include "ixgbe/ixgbe_api.h"
64 #include "ixgbe/ixgbe_vf.h"
65 #include "ixgbe/ixgbe_common.h"
66 #include "ixgbe_ethdev.h"
69 * High threshold controlling when to start sending XOFF frames. Must be at
70 * least 8 bytes less than receive packet buffer size. This value is in units
73 #define IXGBE_FC_HI 0x80
76 * Low threshold controlling when to start sending XON frames. This value is
77 * in units of 1024 bytes.
79 #define IXGBE_FC_LO 0x40
81 /* Timer value included in XOFF frames. */
82 #define IXGBE_FC_PAUSE 0x680
84 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
85 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
87 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
89 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
91 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
92 struct rte_eth_dev *eth_dev);
93 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
94 static int ixgbe_dev_start(struct rte_eth_dev *dev);
95 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
96 static void ixgbe_dev_close(struct rte_eth_dev *dev);
97 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
98 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
99 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
100 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
101 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
102 int wait_to_complete);
103 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
104 struct rte_eth_stats *stats);
105 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
106 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
110 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
111 struct rte_eth_dev_info *dev_info);
112 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
113 uint16_t vlan_id, int on);
114 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
115 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
116 uint16_t queue, bool on);
117 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
119 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
120 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
121 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
122 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
123 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
125 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
126 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
127 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
128 struct rte_eth_fc_conf *fc_conf);
129 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
130 struct rte_eth_pfc_conf *pfc_conf);
131 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
132 struct rte_eth_rss_reta *reta_conf);
133 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
134 struct rte_eth_rss_reta *reta_conf);
135 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
136 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
137 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
138 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
139 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
141 static void ixgbe_dev_interrupt_delayed_handler(void *param);
142 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
143 uint32_t index, uint32_t pool);
144 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
145 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
147 /* For Virtual Function support */
148 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
149 struct rte_eth_dev *eth_dev);
150 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
151 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
152 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
153 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
154 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
155 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
156 struct rte_eth_stats *stats);
157 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
158 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
159 uint16_t vlan_id, int on);
160 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
161 uint16_t queue, int on);
162 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
163 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
166 * Define VF Stats MACRO for Non "cleared on read" register
168 #define UPDATE_VF_STAT(reg, last, cur) \
170 u32 latest = IXGBE_READ_REG(hw, reg); \
171 cur += latest - last; \
175 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
177 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
178 u64 new_msb = IXGBE_READ_REG(hw, msb); \
179 u64 latest = ((new_msb << 32) | new_lsb); \
180 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
184 #define IXGBE_SET_HWSTRIP(h, q) do{\
185 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
186 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
187 (h)->bitmap[idx] |= 1 << bit;\
190 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
191 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
192 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
193 (h)->bitmap[idx] &= ~(1 << bit);\
196 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
197 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
198 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
199 (r) = (h)->bitmap[idx] >> bit & 1;\
203 * The set of PCI devices this driver supports
205 static struct rte_pci_id pci_id_ixgbe_map[] = {
207 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
208 #include "rte_pci_dev_ids.h"
210 { .vendor_id = 0, /* sentinel */ },
215 * The set of PCI devices this driver supports (for 82599 VF)
217 static struct rte_pci_id pci_id_ixgbevf_map[] = {
219 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
220 #include "rte_pci_dev_ids.h"
221 { .vendor_id = 0, /* sentinel */ },
225 static struct eth_dev_ops ixgbe_eth_dev_ops = {
226 .dev_configure = ixgbe_dev_configure,
227 .dev_start = ixgbe_dev_start,
228 .dev_stop = ixgbe_dev_stop,
229 .dev_close = ixgbe_dev_close,
230 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
231 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
232 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
233 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
234 .link_update = ixgbe_dev_link_update,
235 .stats_get = ixgbe_dev_stats_get,
236 .stats_reset = ixgbe_dev_stats_reset,
237 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
238 .dev_infos_get = ixgbe_dev_info_get,
239 .vlan_filter_set = ixgbe_vlan_filter_set,
240 .vlan_tpid_set = ixgbe_vlan_tpid_set,
241 .vlan_offload_set = ixgbe_vlan_offload_set,
242 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
243 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
244 .rx_queue_release = ixgbe_dev_rx_queue_release,
245 .rx_queue_count = ixgbe_dev_rx_queue_count,
246 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
247 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
248 .tx_queue_release = ixgbe_dev_tx_queue_release,
249 .dev_led_on = ixgbe_dev_led_on,
250 .dev_led_off = ixgbe_dev_led_off,
251 .flow_ctrl_set = ixgbe_flow_ctrl_set,
252 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
253 .mac_addr_add = ixgbe_add_rar,
254 .mac_addr_remove = ixgbe_remove_rar,
255 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
256 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
257 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
258 .fdir_infos_get = ixgbe_fdir_info_get,
259 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
260 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
261 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
262 .fdir_set_masks = ixgbe_fdir_set_masks,
263 .reta_update = ixgbe_dev_rss_reta_update,
264 .reta_query = ixgbe_dev_rss_reta_query,
268 * dev_ops for virtual function, bare necessities for basic vf
269 * operation have been implemented
271 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
273 .dev_configure = ixgbevf_dev_configure,
274 .dev_start = ixgbevf_dev_start,
275 .dev_stop = ixgbevf_dev_stop,
276 .link_update = ixgbe_dev_link_update,
277 .stats_get = ixgbevf_dev_stats_get,
278 .stats_reset = ixgbevf_dev_stats_reset,
279 .dev_close = ixgbevf_dev_close,
280 .dev_infos_get = ixgbe_dev_info_get,
281 .vlan_filter_set = ixgbevf_vlan_filter_set,
282 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
283 .vlan_offload_set = ixgbevf_vlan_offload_set,
284 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
285 .rx_queue_release = ixgbe_dev_rx_queue_release,
286 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
287 .tx_queue_release = ixgbe_dev_tx_queue_release,
291 * Atomically reads the link status information from global
292 * structure rte_eth_dev.
295 * - Pointer to the structure rte_eth_dev to read from.
296 * - Pointer to the buffer to be saved with the link status.
299 * - On success, zero.
300 * - On failure, negative value.
303 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
304 struct rte_eth_link *link)
306 struct rte_eth_link *dst = link;
307 struct rte_eth_link *src = &(dev->data->dev_link);
309 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
310 *(uint64_t *)src) == 0)
317 * Atomically writes the link status information into global
318 * structure rte_eth_dev.
321 * - Pointer to the structure rte_eth_dev to read from.
322 * - Pointer to the buffer to be saved with the link status.
325 * - On success, zero.
326 * - On failure, negative value.
329 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
330 struct rte_eth_link *link)
332 struct rte_eth_link *dst = &(dev->data->dev_link);
333 struct rte_eth_link *src = link;
335 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
336 *(uint64_t *)src) == 0)
343 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
346 ixgbe_is_sfp(struct ixgbe_hw *hw)
348 switch (hw->phy.type) {
349 case ixgbe_phy_sfp_avago:
350 case ixgbe_phy_sfp_ftl:
351 case ixgbe_phy_sfp_intel:
352 case ixgbe_phy_sfp_unknown:
353 case ixgbe_phy_sfp_passive_tyco:
354 case ixgbe_phy_sfp_passive_unknown:
361 static inline int32_t
362 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
367 status = ixgbe_reset_hw(hw);
369 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
370 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
371 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
372 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
373 IXGBE_WRITE_FLUSH(hw);
379 ixgbe_enable_intr(struct rte_eth_dev *dev)
381 struct ixgbe_interrupt *intr =
382 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
383 struct ixgbe_hw *hw =
384 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
386 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
387 IXGBE_WRITE_FLUSH(hw);
391 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
394 ixgbe_disable_intr(struct ixgbe_hw *hw)
396 PMD_INIT_FUNC_TRACE();
398 if (hw->mac.type == ixgbe_mac_82598EB) {
399 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
401 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
402 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
403 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
405 IXGBE_WRITE_FLUSH(hw);
409 * This function resets queue statistics mapping registers.
410 * From Niantic datasheet, Initialization of Statistics section:
411 * "...if software requires the queue counters, the RQSMR and TQSM registers
412 * must be re-programmed following a device reset.
415 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
419 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
420 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
421 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
427 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
432 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
433 #define NB_QMAP_FIELDS_PER_QSM_REG 4
434 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
436 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
437 struct ixgbe_stat_mapping_registers *stat_mappings =
438 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
439 uint32_t qsmr_mask = 0;
440 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
444 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
447 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
448 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
450 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
451 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
452 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
455 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
457 /* Now clear any previous stat_idx set */
458 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
460 stat_mappings->tqsm[n] &= ~clearing_mask;
462 stat_mappings->rqsmr[n] &= ~clearing_mask;
464 q_map = (uint32_t)stat_idx;
465 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
466 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
468 stat_mappings->tqsm[n] |= qsmr_mask;
470 stat_mappings->rqsmr[n] |= qsmr_mask;
472 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
474 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
475 is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
477 /* Now write the mapping in the appropriate register */
479 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
480 stat_mappings->rqsmr[n], n);
481 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
484 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
485 stat_mappings->tqsm[n], n);
486 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
492 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
494 struct ixgbe_stat_mapping_registers *stat_mappings =
495 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
496 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
499 /* write whatever was in stat mapping table to the NIC */
500 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
502 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
505 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
510 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
513 struct ixgbe_dcb_tc_config *tc;
514 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
516 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
517 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
518 for (i = 0; i < dcb_max_tc; i++) {
519 tc = &dcb_config->tc_config[i];
520 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
521 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
522 (uint8_t)(100/dcb_max_tc + (i & 1));
523 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
524 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
525 (uint8_t)(100/dcb_max_tc + (i & 1));
526 tc->pfc = ixgbe_dcb_pfc_disabled;
529 /* Initialize default user to priority mapping, UPx->TC0 */
530 tc = &dcb_config->tc_config[0];
531 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
532 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
533 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
534 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
535 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
537 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
538 dcb_config->pfc_mode_enable = false;
539 dcb_config->vt_mode = true;
540 dcb_config->round_robin_enable = false;
541 /* support all DCB capabilities in 82599 */
542 dcb_config->support.capabilities = 0xFF;
544 /*we only support 4 Tcs for X540*/
545 if (hw->mac.type == ixgbe_mac_X540) {
546 dcb_config->num_tcs.pg_tcs = 4;
547 dcb_config->num_tcs.pfc_tcs = 4;
552 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
553 * It returns 0 on success.
556 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
557 struct rte_eth_dev *eth_dev)
559 struct rte_pci_device *pci_dev;
560 struct ixgbe_hw *hw =
561 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
562 struct ixgbe_vfta * shadow_vfta =
563 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
564 struct ixgbe_hwstrip *hwstrip =
565 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
566 struct ixgbe_dcb_config *dcb_config =
567 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
572 PMD_INIT_FUNC_TRACE();
574 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
575 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
576 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
578 /* for secondary processes, we don't initialise any further as primary
579 * has already done this work. Only check we don't need a different
581 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
582 if (eth_dev->data->scattered_rx)
583 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
586 pci_dev = eth_dev->pci_dev;
588 /* Vendor and Device ID need to be set before init of shared code */
589 hw->device_id = pci_dev->id.device_id;
590 hw->vendor_id = pci_dev->id.vendor_id;
591 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
592 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
593 hw->allow_unsupported_sfp = 1;
596 /* Initialize the shared code */
597 diag = ixgbe_init_shared_code(hw);
598 if (diag != IXGBE_SUCCESS) {
599 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
603 /* Initialize DCB configuration*/
604 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
605 ixgbe_dcb_init(hw,dcb_config);
606 /* Get Hardware Flow Control setting */
607 hw->fc.requested_mode = ixgbe_fc_full;
608 hw->fc.current_mode = ixgbe_fc_full;
609 hw->fc.pause_time = IXGBE_FC_PAUSE;
610 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
611 hw->fc.low_water[i] = IXGBE_FC_LO;
612 hw->fc.high_water[i] = IXGBE_FC_HI;
616 /* Make sure we have a good EEPROM before we read from it */
617 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
618 if (diag != IXGBE_SUCCESS) {
619 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
623 diag = ixgbe_init_hw(hw);
626 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
627 * is called too soon after the kernel driver unbinding/binding occurs.
628 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
629 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
630 * also called. See ixgbe_identify_phy_82599(). The reason for the
631 * failure is not known, and only occuts when virtualisation features
632 * are disabled in the bios. A delay of 100ms was found to be enough by
633 * trial-and-error, and is doubled to be safe.
635 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
637 diag = ixgbe_init_hw(hw);
640 if (diag == IXGBE_ERR_EEPROM_VERSION) {
641 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
642 "LOM. Please be aware there may be issues associated "
643 "with your hardware.\n If you are experiencing problems "
644 "please contact your Intel or hardware representative "
645 "who provided you with this hardware.\n");
646 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
647 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
649 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
653 /* disable interrupt */
654 ixgbe_disable_intr(hw);
656 /* pick up the PCI bus settings for reporting later */
657 ixgbe_get_bus_info(hw);
659 /* reset mappings for queue statistics hw counters*/
660 ixgbe_reset_qstat_mappings(hw);
662 /* Allocate memory for storing MAC addresses */
663 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
664 hw->mac.num_rar_entries, 0);
665 if (eth_dev->data->mac_addrs == NULL) {
667 "Failed to allocate %d bytes needed to store MAC addresses",
668 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
671 /* Copy the permanent MAC address */
672 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
673 ð_dev->data->mac_addrs[0]);
675 /* initialize the vfta */
676 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
678 /* initialize the hw strip bitmap*/
679 memset(hwstrip, 0, sizeof(*hwstrip));
681 /* initialize PF if max_vfs not zero */
682 ixgbe_pf_host_init(eth_dev);
684 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
685 /* let hardware know driver is loaded */
686 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
687 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
688 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
689 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
690 IXGBE_WRITE_FLUSH(hw);
692 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
694 "MAC: %d, PHY: %d, SFP+: %d<n",
695 (int) hw->mac.type, (int) hw->phy.type,
696 (int) hw->phy.sfp_type);
698 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
699 (int) hw->mac.type, (int) hw->phy.type);
701 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
702 eth_dev->data->port_id, pci_dev->id.vendor_id,
703 pci_dev->id.device_id);
705 rte_intr_callback_register(&(pci_dev->intr_handle),
706 ixgbe_dev_interrupt_handler, (void *)eth_dev);
708 /* enable uio intr after callback register */
709 rte_intr_enable(&(pci_dev->intr_handle));
711 /* enable support intr */
712 ixgbe_enable_intr(eth_dev);
718 * Virtual Function device init
721 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
722 struct rte_eth_dev *eth_dev)
724 struct rte_pci_device *pci_dev;
725 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
727 struct ixgbe_vfta * shadow_vfta =
728 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
729 struct ixgbe_hwstrip *hwstrip =
730 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
732 PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
734 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
735 pci_dev = eth_dev->pci_dev;
737 hw->device_id = pci_dev->id.device_id;
738 hw->vendor_id = pci_dev->id.vendor_id;
739 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
741 /* initialize the vfta */
742 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
744 /* initialize the hw strip bitmap*/
745 memset(hwstrip, 0, sizeof(*hwstrip));
747 /* Initialize the shared code */
748 diag = ixgbe_init_shared_code(hw);
749 if (diag != IXGBE_SUCCESS) {
750 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
754 /* init_mailbox_params */
755 hw->mbx.ops.init_params(hw);
757 /* Disable the interrupts for VF */
758 ixgbevf_intr_disable(hw);
760 hw->mac.num_rar_entries = hw->mac.max_rx_queues;
761 diag = hw->mac.ops.reset_hw(hw);
763 if (diag != IXGBE_SUCCESS) {
764 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
765 RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
766 "\tThe most likely cause of this error is that the VM host\n"
767 "\thas not assigned a valid MAC address to this VF device.\n"
768 "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
769 "\ta possible solution to this problem.\n");
773 /* Allocate memory for storing MAC addresses */
774 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
775 hw->mac.num_rar_entries, 0);
776 if (eth_dev->data->mac_addrs == NULL) {
778 "Failed to allocate %d bytes needed to store MAC addresses",
779 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
783 /* Copy the permanent MAC address */
784 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
785 ð_dev->data->mac_addrs[0]);
787 /* reset the hardware with the new settings */
788 diag = hw->mac.ops.start_hw(hw);
794 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
798 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
799 eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
800 "ixgbe_mac_82599_vf");
805 static struct eth_driver rte_ixgbe_pmd = {
807 .name = "rte_ixgbe_pmd",
808 .id_table = pci_id_ixgbe_map,
809 #ifdef RTE_EAL_UNBIND_PORTS
810 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
813 .eth_dev_init = eth_ixgbe_dev_init,
814 .dev_private_size = sizeof(struct ixgbe_adapter),
818 * virtual function driver struct
820 static struct eth_driver rte_ixgbevf_pmd = {
822 .name = "rte_ixgbevf_pmd",
823 .id_table = pci_id_ixgbevf_map,
824 #ifdef RTE_EAL_UNBIND_PORTS
825 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
828 .eth_dev_init = eth_ixgbevf_dev_init,
829 .dev_private_size = sizeof(struct ixgbe_adapter),
833 * Driver initialization routine.
834 * Invoked once at EAL init time.
835 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
838 rte_ixgbe_pmd_init(void)
840 PMD_INIT_FUNC_TRACE();
842 rte_eth_driver_register(&rte_ixgbe_pmd);
847 * VF Driver initialization routine.
848 * Invoked one at EAL init time.
849 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
852 rte_ixgbevf_pmd_init(void)
854 DEBUGFUNC("rte_ixgbevf_pmd_init");
856 rte_eth_driver_register(&rte_ixgbevf_pmd);
861 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
863 struct ixgbe_hw *hw =
864 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
865 struct ixgbe_vfta * shadow_vfta =
866 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
871 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
872 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
873 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
878 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
880 /* update local VFTA copy */
881 shadow_vfta->vfta[vid_idx] = vfta;
887 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
890 ixgbe_vlan_hw_strip_enable(dev, queue);
892 ixgbe_vlan_hw_strip_disable(dev, queue);
896 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
898 struct ixgbe_hw *hw =
899 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
901 /* Only the high 16-bits is valid */
902 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
906 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
908 struct ixgbe_hw *hw =
909 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
912 PMD_INIT_FUNC_TRACE();
914 /* Filter Table Disable */
915 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
916 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
918 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
922 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
924 struct ixgbe_hw *hw =
925 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
926 struct ixgbe_vfta * shadow_vfta =
927 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
931 PMD_INIT_FUNC_TRACE();
933 /* Filter Table Enable */
934 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
935 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
936 vlnctrl |= IXGBE_VLNCTRL_VFE;
938 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
940 /* write whatever is in local vfta copy */
941 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
942 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
946 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
948 struct ixgbe_hwstrip *hwstrip =
949 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
951 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
955 IXGBE_SET_HWSTRIP(hwstrip, queue);
957 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
961 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
963 struct ixgbe_hw *hw =
964 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
967 PMD_INIT_FUNC_TRACE();
969 if (hw->mac.type == ixgbe_mac_82598EB) {
970 /* No queue level support */
971 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
975 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
976 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
977 ctrl &= ~IXGBE_RXDCTL_VME;
978 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
980 /* record those setting for HW strip per queue */
981 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
985 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
987 struct ixgbe_hw *hw =
988 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
991 PMD_INIT_FUNC_TRACE();
993 if (hw->mac.type == ixgbe_mac_82598EB) {
994 /* No queue level supported */
995 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
999 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1000 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1001 ctrl |= IXGBE_RXDCTL_VME;
1002 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1004 /* record those setting for HW strip per queue */
1005 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1009 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1011 struct ixgbe_hw *hw =
1012 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1016 PMD_INIT_FUNC_TRACE();
1018 if (hw->mac.type == ixgbe_mac_82598EB) {
1019 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1020 ctrl &= ~IXGBE_VLNCTRL_VME;
1021 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1024 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1025 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1026 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1027 ctrl &= ~IXGBE_RXDCTL_VME;
1028 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1030 /* record those setting for HW strip per queue */
1031 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1037 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1039 struct ixgbe_hw *hw =
1040 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044 PMD_INIT_FUNC_TRACE();
1046 if (hw->mac.type == ixgbe_mac_82598EB) {
1047 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1048 ctrl |= IXGBE_VLNCTRL_VME;
1049 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1052 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1053 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1054 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1055 ctrl |= IXGBE_RXDCTL_VME;
1056 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1058 /* record those setting for HW strip per queue */
1059 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1065 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1067 struct ixgbe_hw *hw =
1068 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1071 PMD_INIT_FUNC_TRACE();
1073 /* DMATXCTRL: Geric Double VLAN Disable */
1074 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1075 ctrl &= ~IXGBE_DMATXCTL_GDV;
1076 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1078 /* CTRL_EXT: Global Double VLAN Disable */
1079 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1080 ctrl &= ~IXGBE_EXTENDED_VLAN;
1081 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1086 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1088 struct ixgbe_hw *hw =
1089 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1092 PMD_INIT_FUNC_TRACE();
1094 /* DMATXCTRL: Geric Double VLAN Enable */
1095 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1096 ctrl |= IXGBE_DMATXCTL_GDV;
1097 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1099 /* CTRL_EXT: Global Double VLAN Enable */
1100 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1101 ctrl |= IXGBE_EXTENDED_VLAN;
1102 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1105 * VET EXT field in the EXVET register = 0x8100 by default
1106 * So no need to change. Same to VT field of DMATXCTL register
1111 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1113 if(mask & ETH_VLAN_STRIP_MASK){
1114 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1115 ixgbe_vlan_hw_strip_enable_all(dev);
1117 ixgbe_vlan_hw_strip_disable_all(dev);
1120 if(mask & ETH_VLAN_FILTER_MASK){
1121 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1122 ixgbe_vlan_hw_filter_enable(dev);
1124 ixgbe_vlan_hw_filter_disable(dev);
1127 if(mask & ETH_VLAN_EXTEND_MASK){
1128 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1129 ixgbe_vlan_hw_extend_enable(dev);
1131 ixgbe_vlan_hw_extend_disable(dev);
1136 ixgbe_dev_configure(struct rte_eth_dev *dev)
1138 struct ixgbe_interrupt *intr =
1139 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1141 PMD_INIT_FUNC_TRACE();
1143 /* set flag to update link status after init */
1144 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1150 * Configure device link speed and setup link.
1151 * It returns 0 on success.
1154 ixgbe_dev_start(struct rte_eth_dev *dev)
1156 struct ixgbe_hw *hw =
1157 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1158 int err, link_up = 0, negotiate = 0;
1163 PMD_INIT_FUNC_TRACE();
1165 /* IXGBE devices don't support half duplex */
1166 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1167 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1168 PMD_INIT_LOG(ERR, "Invalid link_duplex (%u) for port %u\n",
1169 dev->data->dev_conf.link_duplex,
1170 dev->data->port_id);
1175 hw->adapter_stopped = FALSE;
1176 ixgbe_stop_adapter(hw);
1178 /* reinitialize adapter
1179 * this calls reset and start */
1180 status = ixgbe_pf_reset_hw(hw);
1183 hw->mac.ops.start_hw(hw);
1185 /* configure PF module if SRIOV enabled */
1186 ixgbe_pf_host_configure(dev);
1188 /* initialize transmission unit */
1189 ixgbe_dev_tx_init(dev);
1191 /* This can fail when allocating mbufs for descriptor rings */
1192 err = ixgbe_dev_rx_init(dev);
1194 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1198 ixgbe_dev_rxtx_start(dev);
1200 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1201 err = hw->mac.ops.setup_sfp(hw);
1206 /* Turn on the laser */
1207 ixgbe_enable_tx_laser(hw);
1209 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1212 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1216 switch(dev->data->dev_conf.link_speed) {
1217 case ETH_LINK_SPEED_AUTONEG:
1218 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1219 IXGBE_LINK_SPEED_82599_AUTONEG :
1220 IXGBE_LINK_SPEED_82598_AUTONEG;
1222 case ETH_LINK_SPEED_100:
1224 * Invalid for 82598 but error will be detected by
1225 * ixgbe_setup_link()
1227 speed = IXGBE_LINK_SPEED_100_FULL;
1229 case ETH_LINK_SPEED_1000:
1230 speed = IXGBE_LINK_SPEED_1GB_FULL;
1232 case ETH_LINK_SPEED_10000:
1233 speed = IXGBE_LINK_SPEED_10GB_FULL;
1236 PMD_INIT_LOG(ERR, "Invalid link_speed (%u) for port %u\n",
1237 dev->data->dev_conf.link_speed, dev->data->port_id);
1241 err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1245 /* check if lsc interrupt is enabled */
1246 if (dev->data->dev_conf.intr_conf.lsc != 0)
1247 ixgbe_dev_lsc_interrupt_setup(dev);
1249 /* resume enabled intr since hw reset */
1250 ixgbe_enable_intr(dev);
1252 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1253 ETH_VLAN_EXTEND_MASK;
1254 ixgbe_vlan_offload_set(dev, mask);
1256 /* Configure DCB hw */
1257 ixgbe_configure_dcb(dev);
1259 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1260 err = ixgbe_fdir_configure(dev);
1265 ixgbe_restore_statistics_mapping(dev);
1270 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1271 ixgbe_dev_clear_queues(dev);
1276 * Stop device: disable rx and tx functions to allow for reconfiguring.
1279 ixgbe_dev_stop(struct rte_eth_dev *dev)
1281 struct rte_eth_link link;
1282 struct ixgbe_hw *hw =
1283 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285 PMD_INIT_FUNC_TRACE();
1287 /* disable interrupts */
1288 ixgbe_disable_intr(hw);
1291 ixgbe_pf_reset_hw(hw);
1292 hw->adapter_stopped = FALSE;
1295 ixgbe_stop_adapter(hw);
1297 /* Turn off the laser */
1298 ixgbe_disable_tx_laser(hw);
1300 ixgbe_dev_clear_queues(dev);
1302 /* Clear recorded link status */
1303 memset(&link, 0, sizeof(link));
1304 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1308 * Reest and stop device.
1311 ixgbe_dev_close(struct rte_eth_dev *dev)
1313 struct ixgbe_hw *hw =
1314 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316 PMD_INIT_FUNC_TRACE();
1318 ixgbe_pf_reset_hw(hw);
1320 ixgbe_dev_stop(dev);
1321 hw->adapter_stopped = 1;
1323 ixgbe_disable_pcie_master(hw);
1325 /* reprogram the RAR[0] in case user changed it. */
1326 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1330 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1333 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1335 struct ixgbe_hw *hw =
1336 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337 struct ixgbe_hw_stats *hw_stats =
1338 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1339 uint32_t bprc, lxon, lxoff, total;
1340 uint64_t total_missed_rx, total_qbrc, total_qprc;
1343 total_missed_rx = 0;
1347 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1348 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1349 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1350 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1352 for (i = 0; i < 8; i++) {
1354 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1355 /* global total per queue */
1356 hw_stats->mpc[i] += mp;
1357 /* Running comprehensive total for stats display */
1358 total_missed_rx += hw_stats->mpc[i];
1359 if (hw->mac.type == ixgbe_mac_82598EB)
1360 hw_stats->rnbc[i] +=
1361 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1362 hw_stats->pxontxc[i] +=
1363 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1364 hw_stats->pxonrxc[i] +=
1365 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1366 hw_stats->pxofftxc[i] +=
1367 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1368 hw_stats->pxoffrxc[i] +=
1369 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1370 hw_stats->pxon2offc[i] +=
1371 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1373 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1374 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1375 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1376 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1377 hw_stats->qbrc[i] +=
1378 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1379 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1380 hw_stats->qbtc[i] +=
1381 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1382 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1384 total_qprc += hw_stats->qprc[i];
1385 total_qbrc += hw_stats->qbrc[i];
1387 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1388 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1389 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1391 /* Note that gprc counts missed packets */
1392 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1394 if (hw->mac.type != ixgbe_mac_82598EB) {
1395 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1396 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1397 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1398 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1399 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1400 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1401 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1402 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1404 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1405 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1406 /* 82598 only has a counter in the high register */
1407 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1408 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1409 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1413 * Workaround: mprc hardware is incorrectly counting
1414 * broadcasts, so for now we subtract those.
1416 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1417 hw_stats->bprc += bprc;
1418 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1419 if (hw->mac.type == ixgbe_mac_82598EB)
1420 hw_stats->mprc -= bprc;
1422 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1423 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1424 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1425 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1426 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1427 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1429 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1430 hw_stats->lxontxc += lxon;
1431 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1432 hw_stats->lxofftxc += lxoff;
1433 total = lxon + lxoff;
1435 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1436 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1437 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1438 hw_stats->gptc -= total;
1439 hw_stats->mptc -= total;
1440 hw_stats->ptc64 -= total;
1441 hw_stats->gotc -= total * ETHER_MIN_LEN;
1443 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1444 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1445 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1446 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1447 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1448 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1449 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1450 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1451 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1452 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1453 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1454 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1455 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1456 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1457 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1458 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1459 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1460 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1461 /* Only read FCOE on 82599 */
1462 if (hw->mac.type != ixgbe_mac_82598EB) {
1463 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1464 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1465 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1466 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1467 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1473 /* Fill out the rte_eth_stats statistics structure */
1474 stats->ipackets = total_qprc;
1475 stats->ibytes = total_qbrc;
1476 stats->opackets = hw_stats->gptc;
1477 stats->obytes = hw_stats->gotc;
1478 stats->imcasts = hw_stats->mprc;
1480 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1481 stats->q_ipackets[i] = hw_stats->qprc[i];
1482 stats->q_opackets[i] = hw_stats->qptc[i];
1483 stats->q_ibytes[i] = hw_stats->qbrc[i];
1484 stats->q_obytes[i] = hw_stats->qbtc[i];
1485 stats->q_errors[i] = hw_stats->qprdc[i];
1489 stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1494 /* Flow Director Stats registers */
1495 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1496 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1497 stats->fdirmatch = hw_stats->fdirmatch;
1498 stats->fdirmiss = hw_stats->fdirmiss;
1502 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1504 struct ixgbe_hw_stats *stats =
1505 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1507 /* HW registers are cleared on read */
1508 ixgbe_dev_stats_get(dev, NULL);
1510 /* Reset software totals */
1511 memset(stats, 0, sizeof(*stats));
1515 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1517 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1519 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1521 /* Good Rx packet, include VF loopback */
1522 UPDATE_VF_STAT(IXGBE_VFGPRC,
1523 hw_stats->last_vfgprc, hw_stats->vfgprc);
1525 /* Good Rx octets, include VF loopback */
1526 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1527 hw_stats->last_vfgorc, hw_stats->vfgorc);
1529 /* Good Tx packet, include VF loopback */
1530 UPDATE_VF_STAT(IXGBE_VFGPTC,
1531 hw_stats->last_vfgptc, hw_stats->vfgptc);
1533 /* Good Tx octets, include VF loopback */
1534 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1535 hw_stats->last_vfgotc, hw_stats->vfgotc);
1537 /* Rx Multicst Packet */
1538 UPDATE_VF_STAT(IXGBE_VFMPRC,
1539 hw_stats->last_vfmprc, hw_stats->vfmprc);
1544 memset(stats, 0, sizeof(*stats));
1545 stats->ipackets = hw_stats->vfgprc;
1546 stats->ibytes = hw_stats->vfgorc;
1547 stats->opackets = hw_stats->vfgptc;
1548 stats->obytes = hw_stats->vfgotc;
1549 stats->imcasts = hw_stats->vfmprc;
1553 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1555 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1556 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1558 /* Sync HW register to the last stats */
1559 ixgbevf_dev_stats_get(dev, NULL);
1561 /* reset HW current stats*/
1562 hw_stats->vfgprc = 0;
1563 hw_stats->vfgorc = 0;
1564 hw_stats->vfgptc = 0;
1565 hw_stats->vfgotc = 0;
1566 hw_stats->vfmprc = 0;
1571 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1573 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1575 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1576 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1577 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1578 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1579 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1582 /* return 0 means link status changed, -1 means not changed */
1584 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587 struct rte_eth_link link, old;
1588 ixgbe_link_speed link_speed;
1592 link.link_status = 0;
1593 link.link_speed = 0;
1594 link.link_duplex = 0;
1595 memset(&old, 0, sizeof(old));
1596 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1598 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1599 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1600 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1602 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1604 link.link_speed = ETH_LINK_SPEED_100;
1605 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1606 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1607 if (link.link_status == old.link_status)
1613 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1614 if (link.link_status == old.link_status)
1618 link.link_status = 1;
1619 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1621 switch (link_speed) {
1623 case IXGBE_LINK_SPEED_UNKNOWN:
1624 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1625 link.link_speed = ETH_LINK_SPEED_100;
1628 case IXGBE_LINK_SPEED_100_FULL:
1629 link.link_speed = ETH_LINK_SPEED_100;
1632 case IXGBE_LINK_SPEED_1GB_FULL:
1633 link.link_speed = ETH_LINK_SPEED_1000;
1636 case IXGBE_LINK_SPEED_10GB_FULL:
1637 link.link_speed = ETH_LINK_SPEED_10000;
1640 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1642 if (link.link_status == old.link_status)
1649 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1651 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1655 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1656 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1660 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1662 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1666 fctrl &= (~IXGBE_FCTRL_UPE);
1667 if (dev->data->all_multicast == 1)
1668 fctrl |= IXGBE_FCTRL_MPE;
1670 fctrl &= (~IXGBE_FCTRL_MPE);
1671 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1675 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1677 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1681 fctrl |= IXGBE_FCTRL_MPE;
1682 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1686 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1688 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691 if (dev->data->promiscuous == 1)
1692 return; /* must remain in all_multicast mode */
1694 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1695 fctrl &= (~IXGBE_FCTRL_MPE);
1696 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1700 * It clears the interrupt causes and enables the interrupt.
1701 * It will be called once only during nic initialized.
1704 * Pointer to struct rte_eth_dev.
1707 * - On success, zero.
1708 * - On failure, a negative value.
1711 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1713 struct ixgbe_interrupt *intr =
1714 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1716 ixgbe_dev_link_status_print(dev);
1717 intr->mask |= IXGBE_EICR_LSC;
1723 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1726 * Pointer to struct rte_eth_dev.
1729 * - On success, zero.
1730 * - On failure, a negative value.
1733 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1736 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737 struct ixgbe_interrupt *intr =
1738 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1740 /* clear all cause mask */
1741 ixgbe_disable_intr(hw);
1743 /* read-on-clear nic registers here */
1744 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1745 PMD_DRV_LOG(INFO, "eicr %x", eicr);
1748 if (eicr & IXGBE_EICR_LSC) {
1749 /* set flag for async link update */
1750 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1753 if (eicr & IXGBE_EICR_MAILBOX)
1754 intr->flags |= IXGBE_FLAG_MAILBOX;
1760 * It gets and then prints the link status.
1763 * Pointer to struct rte_eth_dev.
1766 * - On success, zero.
1767 * - On failure, a negative value.
1770 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1772 struct rte_eth_link link;
1774 memset(&link, 0, sizeof(link));
1775 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1776 if (link.link_status) {
1777 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1778 (int)(dev->data->port_id),
1779 (unsigned)link.link_speed,
1780 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1781 "full-duplex" : "half-duplex");
1783 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1784 (int)(dev->data->port_id));
1786 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1787 dev->pci_dev->addr.domain,
1788 dev->pci_dev->addr.bus,
1789 dev->pci_dev->addr.devid,
1790 dev->pci_dev->addr.function);
1794 * It executes link_update after knowing an interrupt occured.
1797 * Pointer to struct rte_eth_dev.
1800 * - On success, zero.
1801 * - On failure, a negative value.
1804 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1806 struct ixgbe_interrupt *intr =
1807 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1809 struct rte_eth_link link;
1810 int intr_enable_delay = false;
1812 PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1814 if (intr->flags & IXGBE_FLAG_MAILBOX) {
1815 ixgbe_pf_mbx_process(dev);
1816 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1819 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1820 /* get the link status before link update, for predicting later */
1821 memset(&link, 0, sizeof(link));
1822 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1824 ixgbe_dev_link_update(dev, 0);
1827 if (!link.link_status)
1828 /* handle it 1 sec later, wait it being stable */
1829 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1830 /* likely to down */
1832 /* handle it 4 sec later, wait it being stable */
1833 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1835 ixgbe_dev_link_status_print(dev);
1837 intr_enable_delay = true;
1840 if (intr_enable_delay) {
1841 if (rte_eal_alarm_set(timeout * 1000,
1842 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
1843 PMD_DRV_LOG(ERR, "Error setting alarm");
1845 PMD_DRV_LOG(DEBUG, "enable intr immediately");
1846 ixgbe_enable_intr(dev);
1847 rte_intr_enable(&(dev->pci_dev->intr_handle));
1855 * Interrupt handler which shall be registered for alarm callback for delayed
1856 * handling specific interrupt to wait for the stable nic state. As the
1857 * NIC interrupt state is not stable for ixgbe after link is just down,
1858 * it needs to wait 4 seconds to get the stable status.
1861 * Pointer to interrupt handle.
1863 * The address of parameter (struct rte_eth_dev *) regsitered before.
1869 ixgbe_dev_interrupt_delayed_handler(void *param)
1871 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1872 struct ixgbe_interrupt *intr =
1873 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1874 struct ixgbe_hw *hw =
1875 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1878 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1879 if (eicr & IXGBE_EICR_MAILBOX)
1880 ixgbe_pf_mbx_process(dev);
1882 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1883 ixgbe_dev_link_update(dev, 0);
1884 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
1885 ixgbe_dev_link_status_print(dev);
1886 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1889 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
1890 ixgbe_enable_intr(dev);
1891 rte_intr_enable(&(dev->pci_dev->intr_handle));
1895 * Interrupt handler triggered by NIC for handling
1896 * specific interrupt.
1899 * Pointer to interrupt handle.
1901 * The address of parameter (struct rte_eth_dev *) regsitered before.
1907 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1910 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1911 ixgbe_dev_interrupt_get_status(dev);
1912 ixgbe_dev_interrupt_action(dev);
1916 ixgbe_dev_led_on(struct rte_eth_dev *dev)
1918 struct ixgbe_hw *hw;
1920 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1925 ixgbe_dev_led_off(struct rte_eth_dev *dev)
1927 struct ixgbe_hw *hw;
1929 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1934 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1936 struct ixgbe_hw *hw;
1938 uint32_t rx_buf_size;
1939 uint32_t max_high_water;
1940 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
1947 PMD_INIT_FUNC_TRACE();
1949 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
1951 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1954 * At least reserve one Ethernet frame for watermark
1955 * high_water/low_water in kilo bytes for ixgbe
1957 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
1958 if ((fc_conf->high_water > max_high_water) ||
1959 (fc_conf->high_water < fc_conf->low_water)) {
1960 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
1961 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
1965 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
1966 hw->fc.pause_time = fc_conf->pause_time;
1967 hw->fc.high_water[0] = fc_conf->high_water;
1968 hw->fc.low_water[0] = fc_conf->low_water;
1969 hw->fc.send_xon = fc_conf->send_xon;
1971 err = ixgbe_fc_enable(hw);
1972 /* Not negotiated is not an error case */
1973 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
1977 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
1982 * ixgbe_pfc_enable_generic - Enable flow control
1983 * @hw: pointer to hardware structure
1984 * @tc_num: traffic class number
1985 * Enable flow control according to the current settings.
1988 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
1991 uint32_t mflcn_reg, fccfg_reg;
1993 uint32_t fcrtl, fcrth;
1997 /* Validate the water mark configuration */
1998 if (!hw->fc.pause_time) {
1999 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2003 /* Low water mark of zero causes XOFF floods */
2004 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2005 /* High/Low water can not be 0 */
2006 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2007 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2008 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2012 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2013 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2014 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2018 /* Negotiate the fc mode to use */
2019 ixgbe_fc_autoneg(hw);
2021 /* Disable any previous flow control settings */
2022 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2023 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2025 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2026 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2028 switch (hw->fc.current_mode) {
2031 * If the count of enabled RX Priority Flow control >1,
2032 * and the TX pause can not be disabled
2035 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2036 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2037 if (reg & IXGBE_FCRTH_FCEN)
2041 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2043 case ixgbe_fc_rx_pause:
2045 * Rx Flow control is enabled and Tx Flow control is
2046 * disabled by software override. Since there really
2047 * isn't a way to advertise that we are capable of RX
2048 * Pause ONLY, we will advertise that we support both
2049 * symmetric and asymmetric Rx PAUSE. Later, we will
2050 * disable the adapter's ability to send PAUSE frames.
2052 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2054 * If the count of enabled RX Priority Flow control >1,
2055 * and the TX pause can not be disabled
2058 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2059 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2060 if (reg & IXGBE_FCRTH_FCEN)
2064 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2066 case ixgbe_fc_tx_pause:
2068 * Tx Flow control is enabled, and Rx Flow control is
2069 * disabled by software override.
2071 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2074 /* Flow control (both Rx and Tx) is enabled by SW override. */
2075 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2076 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2079 DEBUGOUT("Flow control param set incorrectly\n");
2080 ret_val = IXGBE_ERR_CONFIG;
2085 /* Set 802.3x based flow control settings. */
2086 mflcn_reg |= IXGBE_MFLCN_DPF;
2087 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2088 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2090 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2091 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2092 hw->fc.high_water[tc_num]) {
2093 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2094 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2095 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2097 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2099 * In order to prevent Tx hangs when the internal Tx
2100 * switch is enabled we must set the high water mark
2101 * to the maximum FCRTH value. This allows the Tx
2102 * switch to function even under heavy Rx workloads.
2104 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2106 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2108 /* Configure pause time (2 TCs per register) */
2109 reg = hw->fc.pause_time * 0x00010001;
2110 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2111 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2113 /* Configure flow control refresh threshold value */
2114 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2121 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2123 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2124 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2126 if(hw->mac.type != ixgbe_mac_82598EB) {
2127 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2133 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2136 uint32_t rx_buf_size;
2137 uint32_t max_high_water;
2139 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2140 struct ixgbe_hw *hw =
2141 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142 struct ixgbe_dcb_config *dcb_config =
2143 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2145 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2152 PMD_INIT_FUNC_TRACE();
2154 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2155 tc_num = map[pfc_conf->priority];
2156 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2157 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2159 * At least reserve one Ethernet frame for watermark
2160 * high_water/low_water in kilo bytes for ixgbe
2162 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2163 if ((pfc_conf->fc.high_water > max_high_water) ||
2164 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2165 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2166 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2170 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2171 hw->fc.pause_time = pfc_conf->fc.pause_time;
2172 hw->fc.send_xon = pfc_conf->fc.send_xon;
2173 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2174 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2176 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2178 /* Not negotiated is not an error case */
2179 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2182 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2187 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2188 struct rte_eth_rss_reta *reta_conf)
2192 struct ixgbe_hw *hw =
2193 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195 PMD_INIT_FUNC_TRACE();
2197 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2198 * 128-entries in 32 registers
2200 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2201 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2202 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2204 mask = (uint8_t)((reta_conf->mask_hi >>
2205 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2209 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2211 for (j = 0; j < 4; j++) {
2212 if (mask & (0x1 << j)) {
2214 reta &= ~(0xFF << 8 * j);
2215 reta |= reta_conf->reta[i + j] << 8*j;
2218 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2226 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2227 struct rte_eth_rss_reta *reta_conf)
2231 struct ixgbe_hw *hw =
2232 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2234 PMD_INIT_FUNC_TRACE();
2236 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2237 * 128-entries in 32 registers
2239 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2240 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2241 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2243 mask = (uint8_t)((reta_conf->mask_hi >>
2244 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2247 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2248 for (j = 0; j < 4; j++) {
2249 if (mask & (0x1 << j))
2250 reta_conf->reta[i + j] =
2251 (uint8_t)((reta >> 8 * j) & 0xFF);
2260 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2261 uint32_t index, uint32_t pool)
2263 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2264 uint32_t enable_addr = 1;
2266 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2270 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2272 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274 ixgbe_clear_rar(hw, index);
2278 * Virtual Function operations
2281 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2283 PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2285 /* Clear interrupt mask to stop from interrupts being generated */
2286 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2288 IXGBE_WRITE_FLUSH(hw);
2292 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2294 struct rte_eth_conf* conf = &dev->data->dev_conf;
2296 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2297 dev->data->port_id);
2300 * VF has no ability to enable/disable HW CRC
2301 * Keep the persistent behavior the same as Host PF
2303 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2304 if (!conf->rxmode.hw_strip_crc) {
2305 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2306 conf->rxmode.hw_strip_crc = 1;
2309 if (conf->rxmode.hw_strip_crc) {
2310 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2311 conf->rxmode.hw_strip_crc = 0;
2319 ixgbevf_dev_start(struct rte_eth_dev *dev)
2321 struct ixgbe_hw *hw =
2322 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2325 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2327 hw->mac.ops.reset_hw(hw);
2329 ixgbevf_dev_tx_init(dev);
2331 /* This can fail when allocating mbufs for descriptor rings */
2332 err = ixgbevf_dev_rx_init(dev);
2334 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2335 ixgbe_dev_clear_queues(dev);
2340 ixgbevf_set_vfta_all(dev,1);
2343 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2344 ETH_VLAN_EXTEND_MASK;
2345 ixgbevf_vlan_offload_set(dev, mask);
2347 ixgbevf_dev_rxtx_start(dev);
2353 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2355 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2357 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2359 hw->adapter_stopped = TRUE;
2360 ixgbe_stop_adapter(hw);
2363 * Clear what we set, but we still keep shadow_vfta to
2364 * restore after device starts
2366 ixgbevf_set_vfta_all(dev,0);
2368 ixgbe_dev_clear_queues(dev);
2372 ixgbevf_dev_close(struct rte_eth_dev *dev)
2374 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2380 ixgbevf_dev_stop(dev);
2382 /* reprogram the RAR[0] in case user changed it. */
2383 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2386 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2388 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 struct ixgbe_vfta * shadow_vfta =
2390 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2391 int i = 0, j = 0, vfta = 0, mask = 1;
2393 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2394 vfta = shadow_vfta->vfta[i];
2397 for (j = 0; j < 32; j++){
2399 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2408 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2410 struct ixgbe_hw *hw =
2411 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412 struct ixgbe_vfta * shadow_vfta =
2413 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2414 uint32_t vid_idx = 0;
2415 uint32_t vid_bit = 0;
2418 PMD_INIT_FUNC_TRACE();
2420 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2421 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2423 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2426 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2427 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2429 /* Save what we set and retore it after device reset */
2431 shadow_vfta->vfta[vid_idx] |= vid_bit;
2433 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2439 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2441 struct ixgbe_hw *hw =
2442 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445 PMD_INIT_FUNC_TRACE();
2447 if(queue >= hw->mac.max_rx_queues)
2450 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2452 ctrl |= IXGBE_RXDCTL_VME;
2454 ctrl &= ~IXGBE_RXDCTL_VME;
2455 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2457 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2461 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2463 struct ixgbe_hw *hw =
2464 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468 /* VF function only support hw strip feature, others are not support */
2469 if(mask & ETH_VLAN_STRIP_MASK){
2470 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2472 for(i=0; i < hw->mac.max_rx_queues; i++)
2473 ixgbevf_vlan_strip_queue_set(dev,i,on);