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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
65 #include "ixgbe_logs.h"
66 #include "ixgbe/ixgbe_api.h"
67 #include "ixgbe/ixgbe_vf.h"
68 #include "ixgbe/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
73 * High threshold controlling when to start sending XOFF frames. Must be at
74 * least 8 bytes less than receive packet buffer size. This value is in units
77 #define IXGBE_FC_HI 0x80
80 * Low threshold controlling when to start sending XON frames. This value is
81 * in units of 1024 bytes.
83 #define IXGBE_FC_LO 0x40
85 /* Timer value included in XOFF frames. */
86 #define IXGBE_FC_PAUSE 0x680
88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
89 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
90 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
92 #define IXGBE_MMW_SIZE_DEFAULT 0x4
93 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
96 * Default values for RX/TX configuration
98 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
99 #define IXGBE_DEFAULT_RX_PTHRESH 8
100 #define IXGBE_DEFAULT_RX_HTHRESH 8
101 #define IXGBE_DEFAULT_RX_WTHRESH 0
103 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
104 #define IXGBE_DEFAULT_TX_PTHRESH 32
105 #define IXGBE_DEFAULT_TX_HTHRESH 0
106 #define IXGBE_DEFAULT_TX_WTHRESH 0
107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
109 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
111 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
113 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
114 struct rte_eth_dev *eth_dev);
115 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
116 static int ixgbe_dev_start(struct rte_eth_dev *dev);
117 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
118 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
119 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
120 static void ixgbe_dev_close(struct rte_eth_dev *dev);
121 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
122 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
123 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
124 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
125 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
126 int wait_to_complete);
127 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
128 struct rte_eth_stats *stats);
129 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
130 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
134 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
135 struct rte_eth_dev_info *dev_info);
137 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
139 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
140 uint16_t vlan_id, int on);
141 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
142 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
143 uint16_t queue, bool on);
144 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
146 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
147 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
148 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
149 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
150 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
152 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
153 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
154 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
155 struct rte_eth_fc_conf *fc_conf);
156 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
157 struct rte_eth_fc_conf *fc_conf);
158 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
159 struct rte_eth_pfc_conf *pfc_conf);
160 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
161 struct rte_eth_rss_reta *reta_conf);
162 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
163 struct rte_eth_rss_reta *reta_conf);
164 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
165 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
166 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
167 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
168 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
170 static void ixgbe_dev_interrupt_delayed_handler(void *param);
171 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
172 uint32_t index, uint32_t pool);
173 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
174 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
176 /* For Virtual Function support */
177 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
178 struct rte_eth_dev *eth_dev);
179 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
180 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
181 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
182 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
183 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
184 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
185 struct rte_eth_stats *stats);
186 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
187 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
188 uint16_t vlan_id, int on);
189 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
190 uint16_t queue, int on);
191 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
192 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
194 /* For Eth VMDQ APIs support */
195 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
196 ether_addr* mac_addr,uint8_t on);
197 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
198 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
199 uint16_t rx_mask, uint8_t on);
200 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
201 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
202 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
203 uint64_t pool_mask,uint8_t vlan_on);
204 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
205 struct rte_eth_vmdq_mirror_conf *mirror_conf,
206 uint8_t rule_id, uint8_t on);
207 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
210 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
211 uint16_t queue_idx, uint16_t tx_rate);
212 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
213 uint16_t tx_rate, uint64_t q_msk);
215 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
216 struct ether_addr *mac_addr,
217 uint32_t index, uint32_t pool);
218 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
219 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
220 struct rte_syn_filter *filter, uint16_t rx_queue);
221 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
222 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
223 struct rte_syn_filter *filter, uint16_t *rx_queue);
224 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
225 struct rte_ethertype_filter *filter, uint16_t rx_queue);
226 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
228 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
229 struct rte_ethertype_filter *filter, uint16_t *rx_queue);
230 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
231 struct rte_5tuple_filter *filter, uint16_t rx_queue);
232 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
234 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
235 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
237 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
240 * Define VF Stats MACRO for Non "cleared on read" register
242 #define UPDATE_VF_STAT(reg, last, cur) \
244 u32 latest = IXGBE_READ_REG(hw, reg); \
245 cur += latest - last; \
249 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
251 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
252 u64 new_msb = IXGBE_READ_REG(hw, msb); \
253 u64 latest = ((new_msb << 32) | new_lsb); \
254 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
258 #define IXGBE_SET_HWSTRIP(h, q) do{\
259 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
260 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
261 (h)->bitmap[idx] |= 1 << bit;\
264 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
265 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
266 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
267 (h)->bitmap[idx] &= ~(1 << bit);\
270 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
271 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
272 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
273 (r) = (h)->bitmap[idx] >> bit & 1;\
277 * The set of PCI devices this driver supports
279 static struct rte_pci_id pci_id_ixgbe_map[] = {
281 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
282 #include "rte_pci_dev_ids.h"
284 { .vendor_id = 0, /* sentinel */ },
289 * The set of PCI devices this driver supports (for 82599 VF)
291 static struct rte_pci_id pci_id_ixgbevf_map[] = {
293 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
294 #include "rte_pci_dev_ids.h"
295 { .vendor_id = 0, /* sentinel */ },
299 static struct eth_dev_ops ixgbe_eth_dev_ops = {
300 .dev_configure = ixgbe_dev_configure,
301 .dev_start = ixgbe_dev_start,
302 .dev_stop = ixgbe_dev_stop,
303 .dev_set_link_up = ixgbe_dev_set_link_up,
304 .dev_set_link_down = ixgbe_dev_set_link_down,
305 .dev_close = ixgbe_dev_close,
306 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
307 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
308 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
309 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
310 .link_update = ixgbe_dev_link_update,
311 .stats_get = ixgbe_dev_stats_get,
312 .stats_reset = ixgbe_dev_stats_reset,
313 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
314 .dev_infos_get = ixgbe_dev_info_get,
315 .mtu_set = ixgbe_dev_mtu_set,
316 .vlan_filter_set = ixgbe_vlan_filter_set,
317 .vlan_tpid_set = ixgbe_vlan_tpid_set,
318 .vlan_offload_set = ixgbe_vlan_offload_set,
319 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
320 .rx_queue_start = ixgbe_dev_rx_queue_start,
321 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
322 .tx_queue_start = ixgbe_dev_tx_queue_start,
323 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
324 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
325 .rx_queue_release = ixgbe_dev_rx_queue_release,
326 .rx_queue_count = ixgbe_dev_rx_queue_count,
327 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
328 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
329 .tx_queue_release = ixgbe_dev_tx_queue_release,
330 .dev_led_on = ixgbe_dev_led_on,
331 .dev_led_off = ixgbe_dev_led_off,
332 .flow_ctrl_get = ixgbe_flow_ctrl_get,
333 .flow_ctrl_set = ixgbe_flow_ctrl_set,
334 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
335 .mac_addr_add = ixgbe_add_rar,
336 .mac_addr_remove = ixgbe_remove_rar,
337 .uc_hash_table_set = ixgbe_uc_hash_table_set,
338 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
339 .mirror_rule_set = ixgbe_mirror_rule_set,
340 .mirror_rule_reset = ixgbe_mirror_rule_reset,
341 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
342 .set_vf_rx = ixgbe_set_pool_rx,
343 .set_vf_tx = ixgbe_set_pool_tx,
344 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
345 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
346 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
347 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
348 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
349 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
350 .fdir_infos_get = ixgbe_fdir_info_get,
351 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
352 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
353 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
354 .fdir_set_masks = ixgbe_fdir_set_masks,
355 .reta_update = ixgbe_dev_rss_reta_update,
356 .reta_query = ixgbe_dev_rss_reta_query,
357 #ifdef RTE_NIC_BYPASS
358 .bypass_init = ixgbe_bypass_init,
359 .bypass_state_set = ixgbe_bypass_state_store,
360 .bypass_state_show = ixgbe_bypass_state_show,
361 .bypass_event_set = ixgbe_bypass_event_store,
362 .bypass_event_show = ixgbe_bypass_event_show,
363 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
364 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
365 .bypass_ver_show = ixgbe_bypass_ver_show,
366 .bypass_wd_reset = ixgbe_bypass_wd_reset,
367 #endif /* RTE_NIC_BYPASS */
368 .rss_hash_update = ixgbe_dev_rss_hash_update,
369 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
370 .add_syn_filter = ixgbe_add_syn_filter,
371 .remove_syn_filter = ixgbe_remove_syn_filter,
372 .get_syn_filter = ixgbe_get_syn_filter,
373 .add_ethertype_filter = ixgbe_add_ethertype_filter,
374 .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
375 .get_ethertype_filter = ixgbe_get_ethertype_filter,
376 .add_5tuple_filter = ixgbe_add_5tuple_filter,
377 .remove_5tuple_filter = ixgbe_remove_5tuple_filter,
378 .get_5tuple_filter = ixgbe_get_5tuple_filter,
382 * dev_ops for virtual function, bare necessities for basic vf
383 * operation have been implemented
385 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
387 .dev_configure = ixgbevf_dev_configure,
388 .dev_start = ixgbevf_dev_start,
389 .dev_stop = ixgbevf_dev_stop,
390 .link_update = ixgbe_dev_link_update,
391 .stats_get = ixgbevf_dev_stats_get,
392 .stats_reset = ixgbevf_dev_stats_reset,
393 .dev_close = ixgbevf_dev_close,
394 .dev_infos_get = ixgbe_dev_info_get,
395 .mtu_set = ixgbevf_dev_set_mtu,
396 .vlan_filter_set = ixgbevf_vlan_filter_set,
397 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
398 .vlan_offload_set = ixgbevf_vlan_offload_set,
399 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
400 .rx_queue_release = ixgbe_dev_rx_queue_release,
401 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
402 .tx_queue_release = ixgbe_dev_tx_queue_release,
403 .mac_addr_add = ixgbevf_add_mac_addr,
404 .mac_addr_remove = ixgbevf_remove_mac_addr,
408 * Atomically reads the link status information from global
409 * structure rte_eth_dev.
412 * - Pointer to the structure rte_eth_dev to read from.
413 * - Pointer to the buffer to be saved with the link status.
416 * - On success, zero.
417 * - On failure, negative value.
420 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
421 struct rte_eth_link *link)
423 struct rte_eth_link *dst = link;
424 struct rte_eth_link *src = &(dev->data->dev_link);
426 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
427 *(uint64_t *)src) == 0)
434 * Atomically writes the link status information into global
435 * structure rte_eth_dev.
438 * - Pointer to the structure rte_eth_dev to read from.
439 * - Pointer to the buffer to be saved with the link status.
442 * - On success, zero.
443 * - On failure, negative value.
446 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
447 struct rte_eth_link *link)
449 struct rte_eth_link *dst = &(dev->data->dev_link);
450 struct rte_eth_link *src = link;
452 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
453 *(uint64_t *)src) == 0)
460 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
463 ixgbe_is_sfp(struct ixgbe_hw *hw)
465 switch (hw->phy.type) {
466 case ixgbe_phy_sfp_avago:
467 case ixgbe_phy_sfp_ftl:
468 case ixgbe_phy_sfp_intel:
469 case ixgbe_phy_sfp_unknown:
470 case ixgbe_phy_sfp_passive_tyco:
471 case ixgbe_phy_sfp_passive_unknown:
478 static inline int32_t
479 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
484 status = ixgbe_reset_hw(hw);
486 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
487 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
488 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
489 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
490 IXGBE_WRITE_FLUSH(hw);
496 ixgbe_enable_intr(struct rte_eth_dev *dev)
498 struct ixgbe_interrupt *intr =
499 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
500 struct ixgbe_hw *hw =
501 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
503 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
504 IXGBE_WRITE_FLUSH(hw);
508 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
511 ixgbe_disable_intr(struct ixgbe_hw *hw)
513 PMD_INIT_FUNC_TRACE();
515 if (hw->mac.type == ixgbe_mac_82598EB) {
516 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
518 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
519 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
520 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
522 IXGBE_WRITE_FLUSH(hw);
526 * This function resets queue statistics mapping registers.
527 * From Niantic datasheet, Initialization of Statistics section:
528 * "...if software requires the queue counters, the RQSMR and TQSM registers
529 * must be re-programmed following a device reset.
532 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
536 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
537 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
538 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
544 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
549 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
550 #define NB_QMAP_FIELDS_PER_QSM_REG 4
551 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
553 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
554 struct ixgbe_stat_mapping_registers *stat_mappings =
555 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
556 uint32_t qsmr_mask = 0;
557 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
561 if ((hw->mac.type != ixgbe_mac_82599EB) &&
562 (hw->mac.type != ixgbe_mac_X540) &&
563 (hw->mac.type != ixgbe_mac_X550) &&
564 (hw->mac.type != ixgbe_mac_X550EM_x))
567 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
568 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
571 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
572 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
573 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
576 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
578 /* Now clear any previous stat_idx set */
579 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
581 stat_mappings->tqsm[n] &= ~clearing_mask;
583 stat_mappings->rqsmr[n] &= ~clearing_mask;
585 q_map = (uint32_t)stat_idx;
586 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
587 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
589 stat_mappings->tqsm[n] |= qsmr_mask;
591 stat_mappings->rqsmr[n] |= qsmr_mask;
593 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
594 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
596 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
597 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
599 /* Now write the mapping in the appropriate register */
601 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
602 stat_mappings->rqsmr[n], n);
603 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
606 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
607 stat_mappings->tqsm[n], n);
608 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
614 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
616 struct ixgbe_stat_mapping_registers *stat_mappings =
617 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
618 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
621 /* write whatever was in stat mapping table to the NIC */
622 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
624 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
627 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
632 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
635 struct ixgbe_dcb_tc_config *tc;
636 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
638 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
639 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
640 for (i = 0; i < dcb_max_tc; i++) {
641 tc = &dcb_config->tc_config[i];
642 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
643 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
644 (uint8_t)(100/dcb_max_tc + (i & 1));
645 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
646 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
647 (uint8_t)(100/dcb_max_tc + (i & 1));
648 tc->pfc = ixgbe_dcb_pfc_disabled;
651 /* Initialize default user to priority mapping, UPx->TC0 */
652 tc = &dcb_config->tc_config[0];
653 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
654 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
655 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
656 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
657 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
659 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
660 dcb_config->pfc_mode_enable = false;
661 dcb_config->vt_mode = true;
662 dcb_config->round_robin_enable = false;
663 /* support all DCB capabilities in 82599 */
664 dcb_config->support.capabilities = 0xFF;
666 /*we only support 4 Tcs for X540, X550 */
667 if (hw->mac.type == ixgbe_mac_X540 ||
668 hw->mac.type == ixgbe_mac_X550 ||
669 hw->mac.type == ixgbe_mac_X550EM_x) {
670 dcb_config->num_tcs.pg_tcs = 4;
671 dcb_config->num_tcs.pfc_tcs = 4;
676 * Ensure that all locks are released before first NVM or PHY access
679 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
684 * Phy lock should not fail in this early stage. If this is the case,
685 * it is due to an improper exit of the application.
686 * So force the release of the faulty lock. Release of common lock
687 * is done automatically by swfw_sync function.
689 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
690 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
691 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
693 ixgbe_release_swfw_semaphore(hw, mask);
696 * These ones are more tricky since they are common to all ports; but
697 * swfw_sync retries last long enough (1s) to be almost sure that if
698 * lock can not be taken it is due to an improper lock of the
701 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
702 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
703 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
705 ixgbe_release_swfw_semaphore(hw, mask);
709 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
710 * It returns 0 on success.
713 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
714 struct rte_eth_dev *eth_dev)
716 struct rte_pci_device *pci_dev;
717 struct ixgbe_hw *hw =
718 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
719 struct ixgbe_vfta * shadow_vfta =
720 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
721 struct ixgbe_hwstrip *hwstrip =
722 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
723 struct ixgbe_dcb_config *dcb_config =
724 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
729 PMD_INIT_FUNC_TRACE();
731 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
732 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
733 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
735 /* for secondary processes, we don't initialise any further as primary
736 * has already done this work. Only check we don't need a different
738 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
739 if (eth_dev->data->scattered_rx)
740 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
743 pci_dev = eth_dev->pci_dev;
745 /* Vendor and Device ID need to be set before init of shared code */
746 hw->device_id = pci_dev->id.device_id;
747 hw->vendor_id = pci_dev->id.vendor_id;
748 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
749 hw->allow_unsupported_sfp = 1;
751 /* Initialize the shared code (base driver) */
752 #ifdef RTE_NIC_BYPASS
753 diag = ixgbe_bypass_init_shared_code(hw);
755 diag = ixgbe_init_shared_code(hw);
756 #endif /* RTE_NIC_BYPASS */
758 if (diag != IXGBE_SUCCESS) {
759 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
763 /* pick up the PCI bus settings for reporting later */
764 ixgbe_get_bus_info(hw);
766 /* Unlock any pending hardware semaphore */
767 ixgbe_swfw_lock_reset(hw);
769 /* Initialize DCB configuration*/
770 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
771 ixgbe_dcb_init(hw,dcb_config);
772 /* Get Hardware Flow Control setting */
773 hw->fc.requested_mode = ixgbe_fc_full;
774 hw->fc.current_mode = ixgbe_fc_full;
775 hw->fc.pause_time = IXGBE_FC_PAUSE;
776 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
777 hw->fc.low_water[i] = IXGBE_FC_LO;
778 hw->fc.high_water[i] = IXGBE_FC_HI;
782 /* Make sure we have a good EEPROM before we read from it */
783 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
784 if (diag != IXGBE_SUCCESS) {
785 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
789 #ifdef RTE_NIC_BYPASS
790 diag = ixgbe_bypass_init_hw(hw);
792 diag = ixgbe_init_hw(hw);
793 #endif /* RTE_NIC_BYPASS */
796 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
797 * is called too soon after the kernel driver unbinding/binding occurs.
798 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
799 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
800 * also called. See ixgbe_identify_phy_82599(). The reason for the
801 * failure is not known, and only occuts when virtualisation features
802 * are disabled in the bios. A delay of 100ms was found to be enough by
803 * trial-and-error, and is doubled to be safe.
805 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
807 diag = ixgbe_init_hw(hw);
810 if (diag == IXGBE_ERR_EEPROM_VERSION) {
811 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
812 "LOM. Please be aware there may be issues associated "
813 "with your hardware.");
814 PMD_INIT_LOG(ERR, "If you are experiencing problems "
815 "please contact your Intel or hardware representative "
816 "who provided you with this hardware.");
817 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
818 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
820 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
824 /* disable interrupt */
825 ixgbe_disable_intr(hw);
827 /* reset mappings for queue statistics hw counters*/
828 ixgbe_reset_qstat_mappings(hw);
830 /* Allocate memory for storing MAC addresses */
831 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
832 hw->mac.num_rar_entries, 0);
833 if (eth_dev->data->mac_addrs == NULL) {
835 "Failed to allocate %u bytes needed to store "
837 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
840 /* Copy the permanent MAC address */
841 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
842 ð_dev->data->mac_addrs[0]);
844 /* Allocate memory for storing hash filter MAC addresses */
845 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
846 IXGBE_VMDQ_NUM_UC_MAC, 0);
847 if (eth_dev->data->hash_mac_addrs == NULL) {
849 "Failed to allocate %d bytes needed to store MAC addresses",
850 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
854 /* initialize the vfta */
855 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
857 /* initialize the hw strip bitmap*/
858 memset(hwstrip, 0, sizeof(*hwstrip));
860 /* initialize PF if max_vfs not zero */
861 ixgbe_pf_host_init(eth_dev);
863 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
864 /* let hardware know driver is loaded */
865 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
866 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
867 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
868 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
869 IXGBE_WRITE_FLUSH(hw);
871 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
872 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
873 (int) hw->mac.type, (int) hw->phy.type,
874 (int) hw->phy.sfp_type);
876 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
877 (int) hw->mac.type, (int) hw->phy.type);
879 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
880 eth_dev->data->port_id, pci_dev->id.vendor_id,
881 pci_dev->id.device_id);
883 rte_intr_callback_register(&(pci_dev->intr_handle),
884 ixgbe_dev_interrupt_handler, (void *)eth_dev);
886 /* enable uio intr after callback register */
887 rte_intr_enable(&(pci_dev->intr_handle));
889 /* enable support intr */
890 ixgbe_enable_intr(eth_dev);
897 * Negotiate mailbox API version with the PF.
898 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
899 * Then we try to negotiate starting with the most recent one.
900 * If all negotiation attempts fail, then we will proceed with
901 * the default one (ixgbe_mbox_api_10).
904 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
908 /* start with highest supported, proceed down */
909 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
915 i != RTE_DIM(sup_ver) &&
916 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
922 generate_random_mac_addr(struct ether_addr *mac_addr)
926 /* Set Organizationally Unique Identifier (OUI) prefix. */
927 mac_addr->addr_bytes[0] = 0x00;
928 mac_addr->addr_bytes[1] = 0x09;
929 mac_addr->addr_bytes[2] = 0xC0;
930 /* Force indication of locally assigned MAC address. */
931 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
932 /* Generate the last 3 bytes of the MAC address with a random number. */
934 memcpy(&mac_addr->addr_bytes[3], &random, 3);
938 * Virtual Function device init
941 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
942 struct rte_eth_dev *eth_dev)
946 struct rte_pci_device *pci_dev;
947 struct ixgbe_hw *hw =
948 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
949 struct ixgbe_vfta * shadow_vfta =
950 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
951 struct ixgbe_hwstrip *hwstrip =
952 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
953 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
955 PMD_INIT_FUNC_TRACE();
957 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
958 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
959 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
961 /* for secondary processes, we don't initialise any further as primary
962 * has already done this work. Only check we don't need a different
964 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
965 if (eth_dev->data->scattered_rx)
966 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
970 pci_dev = eth_dev->pci_dev;
972 hw->device_id = pci_dev->id.device_id;
973 hw->vendor_id = pci_dev->id.vendor_id;
974 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
976 /* initialize the vfta */
977 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
979 /* initialize the hw strip bitmap*/
980 memset(hwstrip, 0, sizeof(*hwstrip));
982 /* Initialize the shared code (base driver) */
983 diag = ixgbe_init_shared_code(hw);
984 if (diag != IXGBE_SUCCESS) {
985 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
989 /* init_mailbox_params */
990 hw->mbx.ops.init_params(hw);
992 /* Disable the interrupts for VF */
993 ixgbevf_intr_disable(hw);
995 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
996 diag = hw->mac.ops.reset_hw(hw);
999 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1000 * the underlying PF driver has not assigned a MAC address to the VF.
1001 * In this case, assign a random MAC address.
1003 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1004 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1008 /* negotiate mailbox API version to use with the PF. */
1009 ixgbevf_negotiate_api(hw);
1011 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1012 ixgbevf_get_queues(hw, &tcs, &tc);
1014 /* Allocate memory for storing MAC addresses */
1015 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1016 hw->mac.num_rar_entries, 0);
1017 if (eth_dev->data->mac_addrs == NULL) {
1019 "Failed to allocate %u bytes needed to store "
1021 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1025 /* Generate a random MAC address, if none was assigned by PF. */
1026 if (is_zero_ether_addr(perm_addr)) {
1027 generate_random_mac_addr(perm_addr);
1028 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1030 rte_free(eth_dev->data->mac_addrs);
1031 eth_dev->data->mac_addrs = NULL;
1034 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1035 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1036 "%02x:%02x:%02x:%02x:%02x:%02x",
1037 perm_addr->addr_bytes[0],
1038 perm_addr->addr_bytes[1],
1039 perm_addr->addr_bytes[2],
1040 perm_addr->addr_bytes[3],
1041 perm_addr->addr_bytes[4],
1042 perm_addr->addr_bytes[5]);
1045 /* Copy the permanent MAC address */
1046 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1048 /* reset the hardware with the new settings */
1049 diag = hw->mac.ops.start_hw(hw);
1055 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1059 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1060 eth_dev->data->port_id, pci_dev->id.vendor_id,
1061 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1066 static struct eth_driver rte_ixgbe_pmd = {
1068 .name = "rte_ixgbe_pmd",
1069 .id_table = pci_id_ixgbe_map,
1070 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1072 .eth_dev_init = eth_ixgbe_dev_init,
1073 .dev_private_size = sizeof(struct ixgbe_adapter),
1077 * virtual function driver struct
1079 static struct eth_driver rte_ixgbevf_pmd = {
1081 .name = "rte_ixgbevf_pmd",
1082 .id_table = pci_id_ixgbevf_map,
1083 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1085 .eth_dev_init = eth_ixgbevf_dev_init,
1086 .dev_private_size = sizeof(struct ixgbe_adapter),
1090 * Driver initialization routine.
1091 * Invoked once at EAL init time.
1092 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1095 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1097 PMD_INIT_FUNC_TRACE();
1099 rte_eth_driver_register(&rte_ixgbe_pmd);
1104 * VF Driver initialization routine.
1105 * Invoked one at EAL init time.
1106 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1109 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1111 PMD_INIT_FUNC_TRACE();
1113 rte_eth_driver_register(&rte_ixgbevf_pmd);
1118 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1120 struct ixgbe_hw *hw =
1121 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1122 struct ixgbe_vfta * shadow_vfta =
1123 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1128 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1129 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1130 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1135 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1137 /* update local VFTA copy */
1138 shadow_vfta->vfta[vid_idx] = vfta;
1144 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1147 ixgbe_vlan_hw_strip_enable(dev, queue);
1149 ixgbe_vlan_hw_strip_disable(dev, queue);
1153 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1155 struct ixgbe_hw *hw =
1156 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1158 /* Only the high 16-bits is valid */
1159 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1163 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1165 struct ixgbe_hw *hw =
1166 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1169 PMD_INIT_FUNC_TRACE();
1171 /* Filter Table Disable */
1172 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1173 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1175 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1179 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1181 struct ixgbe_hw *hw =
1182 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183 struct ixgbe_vfta * shadow_vfta =
1184 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1188 PMD_INIT_FUNC_TRACE();
1190 /* Filter Table Enable */
1191 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1192 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1193 vlnctrl |= IXGBE_VLNCTRL_VFE;
1195 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1197 /* write whatever is in local vfta copy */
1198 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1199 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1203 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1205 struct ixgbe_hwstrip *hwstrip =
1206 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1208 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1212 IXGBE_SET_HWSTRIP(hwstrip, queue);
1214 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1218 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1220 struct ixgbe_hw *hw =
1221 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 PMD_INIT_FUNC_TRACE();
1226 if (hw->mac.type == ixgbe_mac_82598EB) {
1227 /* No queue level support */
1228 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1232 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1233 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1234 ctrl &= ~IXGBE_RXDCTL_VME;
1235 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1237 /* record those setting for HW strip per queue */
1238 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1242 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1244 struct ixgbe_hw *hw =
1245 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1248 PMD_INIT_FUNC_TRACE();
1250 if (hw->mac.type == ixgbe_mac_82598EB) {
1251 /* No queue level supported */
1252 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1256 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1257 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1258 ctrl |= IXGBE_RXDCTL_VME;
1259 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1261 /* record those setting for HW strip per queue */
1262 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1266 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1268 struct ixgbe_hw *hw =
1269 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273 PMD_INIT_FUNC_TRACE();
1275 if (hw->mac.type == ixgbe_mac_82598EB) {
1276 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1277 ctrl &= ~IXGBE_VLNCTRL_VME;
1278 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1281 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1282 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1283 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1284 ctrl &= ~IXGBE_RXDCTL_VME;
1285 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1287 /* record those setting for HW strip per queue */
1288 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1294 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1296 struct ixgbe_hw *hw =
1297 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301 PMD_INIT_FUNC_TRACE();
1303 if (hw->mac.type == ixgbe_mac_82598EB) {
1304 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1305 ctrl |= IXGBE_VLNCTRL_VME;
1306 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1309 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1310 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1311 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1312 ctrl |= IXGBE_RXDCTL_VME;
1313 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1315 /* record those setting for HW strip per queue */
1316 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1322 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1324 struct ixgbe_hw *hw =
1325 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1328 PMD_INIT_FUNC_TRACE();
1330 /* DMATXCTRL: Geric Double VLAN Disable */
1331 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1332 ctrl &= ~IXGBE_DMATXCTL_GDV;
1333 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1335 /* CTRL_EXT: Global Double VLAN Disable */
1336 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1337 ctrl &= ~IXGBE_EXTENDED_VLAN;
1338 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1343 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1345 struct ixgbe_hw *hw =
1346 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349 PMD_INIT_FUNC_TRACE();
1351 /* DMATXCTRL: Geric Double VLAN Enable */
1352 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1353 ctrl |= IXGBE_DMATXCTL_GDV;
1354 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1356 /* CTRL_EXT: Global Double VLAN Enable */
1357 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1358 ctrl |= IXGBE_EXTENDED_VLAN;
1359 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1362 * VET EXT field in the EXVET register = 0x8100 by default
1363 * So no need to change. Same to VT field of DMATXCTL register
1368 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1370 if(mask & ETH_VLAN_STRIP_MASK){
1371 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1372 ixgbe_vlan_hw_strip_enable_all(dev);
1374 ixgbe_vlan_hw_strip_disable_all(dev);
1377 if(mask & ETH_VLAN_FILTER_MASK){
1378 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1379 ixgbe_vlan_hw_filter_enable(dev);
1381 ixgbe_vlan_hw_filter_disable(dev);
1384 if(mask & ETH_VLAN_EXTEND_MASK){
1385 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1386 ixgbe_vlan_hw_extend_enable(dev);
1388 ixgbe_vlan_hw_extend_disable(dev);
1393 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1395 struct ixgbe_hw *hw =
1396 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1398 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1399 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1400 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1404 ixgbe_dev_configure(struct rte_eth_dev *dev)
1406 struct ixgbe_interrupt *intr =
1407 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1409 PMD_INIT_FUNC_TRACE();
1411 /* set flag to update link status after init */
1412 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1418 * Configure device link speed and setup link.
1419 * It returns 0 on success.
1422 ixgbe_dev_start(struct rte_eth_dev *dev)
1424 struct ixgbe_hw *hw =
1425 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426 struct ixgbe_vf_info *vfinfo =
1427 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1428 int err, link_up = 0, negotiate = 0;
1434 PMD_INIT_FUNC_TRACE();
1436 /* IXGBE devices don't support half duplex */
1437 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1438 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1439 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1440 dev->data->dev_conf.link_duplex,
1441 dev->data->port_id);
1446 hw->adapter_stopped = FALSE;
1447 ixgbe_stop_adapter(hw);
1449 /* reinitialize adapter
1450 * this calls reset and start */
1451 status = ixgbe_pf_reset_hw(hw);
1454 hw->mac.ops.start_hw(hw);
1456 /* configure PF module if SRIOV enabled */
1457 ixgbe_pf_host_configure(dev);
1459 /* initialize transmission unit */
1460 ixgbe_dev_tx_init(dev);
1462 /* This can fail when allocating mbufs for descriptor rings */
1463 err = ixgbe_dev_rx_init(dev);
1465 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1469 ixgbe_dev_rxtx_start(dev);
1471 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1472 err = hw->mac.ops.setup_sfp(hw);
1477 /* Turn on the laser */
1478 ixgbe_enable_tx_laser(hw);
1480 /* Skip link setup if loopback mode is enabled for 82599. */
1481 if (hw->mac.type == ixgbe_mac_82599EB &&
1482 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1483 goto skip_link_setup;
1485 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1488 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1492 switch(dev->data->dev_conf.link_speed) {
1493 case ETH_LINK_SPEED_AUTONEG:
1494 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1495 IXGBE_LINK_SPEED_82599_AUTONEG :
1496 IXGBE_LINK_SPEED_82598_AUTONEG;
1498 case ETH_LINK_SPEED_100:
1500 * Invalid for 82598 but error will be detected by
1501 * ixgbe_setup_link()
1503 speed = IXGBE_LINK_SPEED_100_FULL;
1505 case ETH_LINK_SPEED_1000:
1506 speed = IXGBE_LINK_SPEED_1GB_FULL;
1508 case ETH_LINK_SPEED_10000:
1509 speed = IXGBE_LINK_SPEED_10GB_FULL;
1512 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1513 dev->data->dev_conf.link_speed,
1514 dev->data->port_id);
1518 err = ixgbe_setup_link(hw, speed, link_up);
1524 /* check if lsc interrupt is enabled */
1525 if (dev->data->dev_conf.intr_conf.lsc != 0)
1526 ixgbe_dev_lsc_interrupt_setup(dev);
1528 /* resume enabled intr since hw reset */
1529 ixgbe_enable_intr(dev);
1531 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1532 ETH_VLAN_EXTEND_MASK;
1533 ixgbe_vlan_offload_set(dev, mask);
1535 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1536 /* Enable vlan filtering for VMDq */
1537 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1540 /* Configure DCB hw */
1541 ixgbe_configure_dcb(dev);
1543 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1544 err = ixgbe_fdir_configure(dev);
1549 /* Restore vf rate limit */
1550 if (vfinfo != NULL) {
1551 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1552 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1553 if (vfinfo[vf].tx_rate[idx] != 0)
1554 ixgbe_set_vf_rate_limit(dev, vf,
1555 vfinfo[vf].tx_rate[idx],
1559 ixgbe_restore_statistics_mapping(dev);
1564 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1565 ixgbe_dev_clear_queues(dev);
1570 * Stop device: disable rx and tx functions to allow for reconfiguring.
1573 ixgbe_dev_stop(struct rte_eth_dev *dev)
1575 struct rte_eth_link link;
1576 struct ixgbe_hw *hw =
1577 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578 struct ixgbe_vf_info *vfinfo =
1579 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1582 PMD_INIT_FUNC_TRACE();
1584 /* disable interrupts */
1585 ixgbe_disable_intr(hw);
1588 ixgbe_pf_reset_hw(hw);
1589 hw->adapter_stopped = FALSE;
1592 ixgbe_stop_adapter(hw);
1594 for (vf = 0; vfinfo != NULL &&
1595 vf < dev->pci_dev->max_vfs; vf++)
1596 vfinfo[vf].clear_to_send = false;
1598 /* Turn off the laser */
1599 ixgbe_disable_tx_laser(hw);
1601 ixgbe_dev_clear_queues(dev);
1603 /* Clear recorded link status */
1604 memset(&link, 0, sizeof(link));
1605 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1609 * Set device link up: enable tx laser.
1612 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1614 struct ixgbe_hw *hw =
1615 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616 if (hw->mac.type == ixgbe_mac_82599EB) {
1617 #ifdef RTE_NIC_BYPASS
1618 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1619 /* Not suported in bypass mode */
1620 PMD_INIT_LOG(ERR, "Set link up is not supported "
1621 "by device id 0x%x", hw->device_id);
1625 /* Turn on the laser */
1626 ixgbe_enable_tx_laser(hw);
1630 PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1636 * Set device link down: disable tx laser.
1639 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1641 struct ixgbe_hw *hw =
1642 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1643 if (hw->mac.type == ixgbe_mac_82599EB) {
1644 #ifdef RTE_NIC_BYPASS
1645 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1646 /* Not suported in bypass mode */
1647 PMD_INIT_LOG(ERR, "Set link down is not supported "
1648 "by device id 0x%x", hw->device_id);
1652 /* Turn off the laser */
1653 ixgbe_disable_tx_laser(hw);
1657 PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1663 * Reest and stop device.
1666 ixgbe_dev_close(struct rte_eth_dev *dev)
1668 struct ixgbe_hw *hw =
1669 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1671 PMD_INIT_FUNC_TRACE();
1673 ixgbe_pf_reset_hw(hw);
1675 ixgbe_dev_stop(dev);
1676 hw->adapter_stopped = 1;
1678 ixgbe_disable_pcie_master(hw);
1680 /* reprogram the RAR[0] in case user changed it. */
1681 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1685 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1688 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1690 struct ixgbe_hw *hw =
1691 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692 struct ixgbe_hw_stats *hw_stats =
1693 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1694 uint32_t bprc, lxon, lxoff, total;
1695 uint64_t total_missed_rx, total_qbrc, total_qprc;
1698 total_missed_rx = 0;
1702 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1703 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1704 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1705 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1707 for (i = 0; i < 8; i++) {
1709 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1710 /* global total per queue */
1711 hw_stats->mpc[i] += mp;
1712 /* Running comprehensive total for stats display */
1713 total_missed_rx += hw_stats->mpc[i];
1714 if (hw->mac.type == ixgbe_mac_82598EB)
1715 hw_stats->rnbc[i] +=
1716 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1717 hw_stats->pxontxc[i] +=
1718 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1719 hw_stats->pxonrxc[i] +=
1720 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1721 hw_stats->pxofftxc[i] +=
1722 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1723 hw_stats->pxoffrxc[i] +=
1724 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1725 hw_stats->pxon2offc[i] +=
1726 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1728 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1729 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1730 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1731 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1732 hw_stats->qbrc[i] +=
1733 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1734 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1735 hw_stats->qbtc[i] +=
1736 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1737 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1739 total_qprc += hw_stats->qprc[i];
1740 total_qbrc += hw_stats->qbrc[i];
1742 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1743 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1744 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1746 /* Note that gprc counts missed packets */
1747 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1749 if (hw->mac.type != ixgbe_mac_82598EB) {
1750 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1751 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1752 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1753 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1754 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1755 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1756 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1757 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1759 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1760 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1761 /* 82598 only has a counter in the high register */
1762 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1763 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1764 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1768 * Workaround: mprc hardware is incorrectly counting
1769 * broadcasts, so for now we subtract those.
1771 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1772 hw_stats->bprc += bprc;
1773 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1774 if (hw->mac.type == ixgbe_mac_82598EB)
1775 hw_stats->mprc -= bprc;
1777 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1778 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1779 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1780 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1781 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1782 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1784 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1785 hw_stats->lxontxc += lxon;
1786 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1787 hw_stats->lxofftxc += lxoff;
1788 total = lxon + lxoff;
1790 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1791 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1792 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1793 hw_stats->gptc -= total;
1794 hw_stats->mptc -= total;
1795 hw_stats->ptc64 -= total;
1796 hw_stats->gotc -= total * ETHER_MIN_LEN;
1798 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1799 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1800 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1801 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1802 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1803 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1804 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1805 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1806 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1807 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1808 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1809 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1810 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1811 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1812 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1813 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1814 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1815 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1816 /* Only read FCOE on 82599 */
1817 if (hw->mac.type != ixgbe_mac_82598EB) {
1818 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1819 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1820 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1821 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1822 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1828 /* Fill out the rte_eth_stats statistics structure */
1829 stats->ipackets = total_qprc;
1830 stats->ibytes = total_qbrc;
1831 stats->opackets = hw_stats->gptc;
1832 stats->obytes = hw_stats->gotc;
1833 stats->imcasts = hw_stats->mprc;
1835 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1836 stats->q_ipackets[i] = hw_stats->qprc[i];
1837 stats->q_opackets[i] = hw_stats->qptc[i];
1838 stats->q_ibytes[i] = hw_stats->qbrc[i];
1839 stats->q_obytes[i] = hw_stats->qbtc[i];
1840 stats->q_errors[i] = hw_stats->qprdc[i];
1844 stats->ibadcrc = hw_stats->crcerrs;
1845 stats->ibadlen = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1846 stats->imissed = total_missed_rx;
1847 stats->ierrors = stats->ibadcrc +
1850 hw_stats->illerrc + hw_stats->errbc;
1855 /* XON/XOFF pause frames */
1856 stats->tx_pause_xon = hw_stats->lxontxc;
1857 stats->rx_pause_xon = hw_stats->lxonrxc;
1858 stats->tx_pause_xoff = hw_stats->lxofftxc;
1859 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1861 /* Flow Director Stats registers */
1862 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1863 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1864 stats->fdirmatch = hw_stats->fdirmatch;
1865 stats->fdirmiss = hw_stats->fdirmiss;
1869 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1871 struct ixgbe_hw_stats *stats =
1872 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1874 /* HW registers are cleared on read */
1875 ixgbe_dev_stats_get(dev, NULL);
1877 /* Reset software totals */
1878 memset(stats, 0, sizeof(*stats));
1882 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1884 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1886 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1888 /* Good Rx packet, include VF loopback */
1889 UPDATE_VF_STAT(IXGBE_VFGPRC,
1890 hw_stats->last_vfgprc, hw_stats->vfgprc);
1892 /* Good Rx octets, include VF loopback */
1893 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1894 hw_stats->last_vfgorc, hw_stats->vfgorc);
1896 /* Good Tx packet, include VF loopback */
1897 UPDATE_VF_STAT(IXGBE_VFGPTC,
1898 hw_stats->last_vfgptc, hw_stats->vfgptc);
1900 /* Good Tx octets, include VF loopback */
1901 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1902 hw_stats->last_vfgotc, hw_stats->vfgotc);
1904 /* Rx Multicst Packet */
1905 UPDATE_VF_STAT(IXGBE_VFMPRC,
1906 hw_stats->last_vfmprc, hw_stats->vfmprc);
1911 memset(stats, 0, sizeof(*stats));
1912 stats->ipackets = hw_stats->vfgprc;
1913 stats->ibytes = hw_stats->vfgorc;
1914 stats->opackets = hw_stats->vfgptc;
1915 stats->obytes = hw_stats->vfgotc;
1916 stats->imcasts = hw_stats->vfmprc;
1920 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1922 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1923 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1925 /* Sync HW register to the last stats */
1926 ixgbevf_dev_stats_get(dev, NULL);
1928 /* reset HW current stats*/
1929 hw_stats->vfgprc = 0;
1930 hw_stats->vfgorc = 0;
1931 hw_stats->vfgptc = 0;
1932 hw_stats->vfgotc = 0;
1933 hw_stats->vfmprc = 0;
1938 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1940 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1943 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1944 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1945 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1946 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1947 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1948 dev_info->max_vfs = dev->pci_dev->max_vfs;
1949 if (hw->mac.type == ixgbe_mac_82598EB)
1950 dev_info->max_vmdq_pools = ETH_16_POOLS;
1952 dev_info->max_vmdq_pools = ETH_64_POOLS;
1953 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1954 dev_info->rx_offload_capa =
1955 DEV_RX_OFFLOAD_VLAN_STRIP |
1956 DEV_RX_OFFLOAD_IPV4_CKSUM |
1957 DEV_RX_OFFLOAD_UDP_CKSUM |
1958 DEV_RX_OFFLOAD_TCP_CKSUM;
1959 dev_info->tx_offload_capa =
1960 DEV_TX_OFFLOAD_VLAN_INSERT |
1961 DEV_TX_OFFLOAD_IPV4_CKSUM |
1962 DEV_TX_OFFLOAD_UDP_CKSUM |
1963 DEV_TX_OFFLOAD_TCP_CKSUM |
1964 DEV_TX_OFFLOAD_SCTP_CKSUM;
1966 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1968 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
1969 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
1970 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
1972 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
1977 dev_info->default_txconf = (struct rte_eth_txconf) {
1979 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
1980 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
1981 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
1983 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
1984 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
1985 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
1989 /* return 0 means link status changed, -1 means not changed */
1991 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1993 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994 struct rte_eth_link link, old;
1995 ixgbe_link_speed link_speed;
1999 link.link_status = 0;
2000 link.link_speed = 0;
2001 link.link_duplex = 0;
2002 memset(&old, 0, sizeof(old));
2003 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2005 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2006 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2007 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2009 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2011 link.link_speed = ETH_LINK_SPEED_100;
2012 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2013 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2014 if (link.link_status == old.link_status)
2020 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2021 if (link.link_status == old.link_status)
2025 link.link_status = 1;
2026 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2028 switch (link_speed) {
2030 case IXGBE_LINK_SPEED_UNKNOWN:
2031 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2032 link.link_speed = ETH_LINK_SPEED_100;
2035 case IXGBE_LINK_SPEED_100_FULL:
2036 link.link_speed = ETH_LINK_SPEED_100;
2039 case IXGBE_LINK_SPEED_1GB_FULL:
2040 link.link_speed = ETH_LINK_SPEED_1000;
2043 case IXGBE_LINK_SPEED_10GB_FULL:
2044 link.link_speed = ETH_LINK_SPEED_10000;
2047 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2049 if (link.link_status == old.link_status)
2056 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2058 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2061 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2062 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2063 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2067 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2069 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2073 fctrl &= (~IXGBE_FCTRL_UPE);
2074 if (dev->data->all_multicast == 1)
2075 fctrl |= IXGBE_FCTRL_MPE;
2077 fctrl &= (~IXGBE_FCTRL_MPE);
2078 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2082 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2084 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2088 fctrl |= IXGBE_FCTRL_MPE;
2089 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2093 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2095 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098 if (dev->data->promiscuous == 1)
2099 return; /* must remain in all_multicast mode */
2101 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2102 fctrl &= (~IXGBE_FCTRL_MPE);
2103 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2107 * It clears the interrupt causes and enables the interrupt.
2108 * It will be called once only during nic initialized.
2111 * Pointer to struct rte_eth_dev.
2114 * - On success, zero.
2115 * - On failure, a negative value.
2118 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2120 struct ixgbe_interrupt *intr =
2121 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2123 ixgbe_dev_link_status_print(dev);
2124 intr->mask |= IXGBE_EICR_LSC;
2130 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2133 * Pointer to struct rte_eth_dev.
2136 * - On success, zero.
2137 * - On failure, a negative value.
2140 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2143 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144 struct ixgbe_interrupt *intr =
2145 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2147 /* clear all cause mask */
2148 ixgbe_disable_intr(hw);
2150 /* read-on-clear nic registers here */
2151 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2152 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2155 if (eicr & IXGBE_EICR_LSC) {
2156 /* set flag for async link update */
2157 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2160 if (eicr & IXGBE_EICR_MAILBOX)
2161 intr->flags |= IXGBE_FLAG_MAILBOX;
2167 * It gets and then prints the link status.
2170 * Pointer to struct rte_eth_dev.
2173 * - On success, zero.
2174 * - On failure, a negative value.
2177 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2179 struct rte_eth_link link;
2181 memset(&link, 0, sizeof(link));
2182 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2183 if (link.link_status) {
2184 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2185 (int)(dev->data->port_id),
2186 (unsigned)link.link_speed,
2187 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2188 "full-duplex" : "half-duplex");
2190 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2191 (int)(dev->data->port_id));
2193 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2194 dev->pci_dev->addr.domain,
2195 dev->pci_dev->addr.bus,
2196 dev->pci_dev->addr.devid,
2197 dev->pci_dev->addr.function);
2201 * It executes link_update after knowing an interrupt occurred.
2204 * Pointer to struct rte_eth_dev.
2207 * - On success, zero.
2208 * - On failure, a negative value.
2211 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2213 struct ixgbe_interrupt *intr =
2214 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2216 struct rte_eth_link link;
2217 int intr_enable_delay = false;
2219 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2221 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2222 ixgbe_pf_mbx_process(dev);
2223 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2226 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2227 /* get the link status before link update, for predicting later */
2228 memset(&link, 0, sizeof(link));
2229 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2231 ixgbe_dev_link_update(dev, 0);
2234 if (!link.link_status)
2235 /* handle it 1 sec later, wait it being stable */
2236 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2237 /* likely to down */
2239 /* handle it 4 sec later, wait it being stable */
2240 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2242 ixgbe_dev_link_status_print(dev);
2244 intr_enable_delay = true;
2247 if (intr_enable_delay) {
2248 if (rte_eal_alarm_set(timeout * 1000,
2249 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2250 PMD_DRV_LOG(ERR, "Error setting alarm");
2252 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2253 ixgbe_enable_intr(dev);
2254 rte_intr_enable(&(dev->pci_dev->intr_handle));
2262 * Interrupt handler which shall be registered for alarm callback for delayed
2263 * handling specific interrupt to wait for the stable nic state. As the
2264 * NIC interrupt state is not stable for ixgbe after link is just down,
2265 * it needs to wait 4 seconds to get the stable status.
2268 * Pointer to interrupt handle.
2270 * The address of parameter (struct rte_eth_dev *) regsitered before.
2276 ixgbe_dev_interrupt_delayed_handler(void *param)
2278 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2279 struct ixgbe_interrupt *intr =
2280 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2281 struct ixgbe_hw *hw =
2282 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2285 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2286 if (eicr & IXGBE_EICR_MAILBOX)
2287 ixgbe_pf_mbx_process(dev);
2289 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2290 ixgbe_dev_link_update(dev, 0);
2291 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2292 ixgbe_dev_link_status_print(dev);
2293 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2296 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2297 ixgbe_enable_intr(dev);
2298 rte_intr_enable(&(dev->pci_dev->intr_handle));
2302 * Interrupt handler triggered by NIC for handling
2303 * specific interrupt.
2306 * Pointer to interrupt handle.
2308 * The address of parameter (struct rte_eth_dev *) regsitered before.
2314 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2317 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2318 ixgbe_dev_interrupt_get_status(dev);
2319 ixgbe_dev_interrupt_action(dev);
2323 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2325 struct ixgbe_hw *hw;
2327 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2332 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2334 struct ixgbe_hw *hw;
2336 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2337 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2341 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2343 struct ixgbe_hw *hw;
2349 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351 fc_conf->pause_time = hw->fc.pause_time;
2352 fc_conf->high_water = hw->fc.high_water[0];
2353 fc_conf->low_water = hw->fc.low_water[0];
2354 fc_conf->send_xon = hw->fc.send_xon;
2355 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2358 * Return rx_pause status according to actual setting of
2361 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2362 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2368 * Return tx_pause status according to actual setting of
2371 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2372 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2377 if (rx_pause && tx_pause)
2378 fc_conf->mode = RTE_FC_FULL;
2380 fc_conf->mode = RTE_FC_RX_PAUSE;
2382 fc_conf->mode = RTE_FC_TX_PAUSE;
2384 fc_conf->mode = RTE_FC_NONE;
2390 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2392 struct ixgbe_hw *hw;
2394 uint32_t rx_buf_size;
2395 uint32_t max_high_water;
2397 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2404 PMD_INIT_FUNC_TRACE();
2406 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407 if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2409 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2410 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2413 * At least reserve one Ethernet frame for watermark
2414 * high_water/low_water in kilo bytes for ixgbe
2416 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2417 if ((fc_conf->high_water > max_high_water) ||
2418 (fc_conf->high_water < fc_conf->low_water)) {
2419 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2420 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2424 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2425 hw->fc.pause_time = fc_conf->pause_time;
2426 hw->fc.high_water[0] = fc_conf->high_water;
2427 hw->fc.low_water[0] = fc_conf->low_water;
2428 hw->fc.send_xon = fc_conf->send_xon;
2430 err = ixgbe_fc_enable(hw);
2432 /* Not negotiated is not an error case */
2433 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2435 /* check if we want to forward MAC frames - driver doesn't have native
2436 * capability to do that, so we'll write the registers ourselves */
2438 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2440 /* set or clear MFLCN.PMCF bit depending on configuration */
2441 if (fc_conf->mac_ctrl_frame_fwd != 0)
2442 mflcn |= IXGBE_MFLCN_PMCF;
2444 mflcn &= ~IXGBE_MFLCN_PMCF;
2446 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2447 IXGBE_WRITE_FLUSH(hw);
2452 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2457 * ixgbe_pfc_enable_generic - Enable flow control
2458 * @hw: pointer to hardware structure
2459 * @tc_num: traffic class number
2460 * Enable flow control according to the current settings.
2463 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2466 uint32_t mflcn_reg, fccfg_reg;
2468 uint32_t fcrtl, fcrth;
2472 /* Validate the water mark configuration */
2473 if (!hw->fc.pause_time) {
2474 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2478 /* Low water mark of zero causes XOFF floods */
2479 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2480 /* High/Low water can not be 0 */
2481 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2482 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2483 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2487 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2488 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2489 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2493 /* Negotiate the fc mode to use */
2494 ixgbe_fc_autoneg(hw);
2496 /* Disable any previous flow control settings */
2497 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2498 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2500 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2501 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2503 switch (hw->fc.current_mode) {
2506 * If the count of enabled RX Priority Flow control >1,
2507 * and the TX pause can not be disabled
2510 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2511 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2512 if (reg & IXGBE_FCRTH_FCEN)
2516 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2518 case ixgbe_fc_rx_pause:
2520 * Rx Flow control is enabled and Tx Flow control is
2521 * disabled by software override. Since there really
2522 * isn't a way to advertise that we are capable of RX
2523 * Pause ONLY, we will advertise that we support both
2524 * symmetric and asymmetric Rx PAUSE. Later, we will
2525 * disable the adapter's ability to send PAUSE frames.
2527 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2529 * If the count of enabled RX Priority Flow control >1,
2530 * and the TX pause can not be disabled
2533 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2534 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2535 if (reg & IXGBE_FCRTH_FCEN)
2539 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2541 case ixgbe_fc_tx_pause:
2543 * Tx Flow control is enabled, and Rx Flow control is
2544 * disabled by software override.
2546 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2549 /* Flow control (both Rx and Tx) is enabled by SW override. */
2550 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2551 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2554 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2555 ret_val = IXGBE_ERR_CONFIG;
2560 /* Set 802.3x based flow control settings. */
2561 mflcn_reg |= IXGBE_MFLCN_DPF;
2562 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2563 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2565 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2566 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2567 hw->fc.high_water[tc_num]) {
2568 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2569 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2570 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2572 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2574 * In order to prevent Tx hangs when the internal Tx
2575 * switch is enabled we must set the high water mark
2576 * to the maximum FCRTH value. This allows the Tx
2577 * switch to function even under heavy Rx workloads.
2579 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2581 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2583 /* Configure pause time (2 TCs per register) */
2584 reg = hw->fc.pause_time * 0x00010001;
2585 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2586 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2588 /* Configure flow control refresh threshold value */
2589 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2596 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2598 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2599 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2601 if(hw->mac.type != ixgbe_mac_82598EB) {
2602 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2608 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2611 uint32_t rx_buf_size;
2612 uint32_t max_high_water;
2614 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2615 struct ixgbe_hw *hw =
2616 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2617 struct ixgbe_dcb_config *dcb_config =
2618 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2620 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2627 PMD_INIT_FUNC_TRACE();
2629 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2630 tc_num = map[pfc_conf->priority];
2631 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2632 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2634 * At least reserve one Ethernet frame for watermark
2635 * high_water/low_water in kilo bytes for ixgbe
2637 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2638 if ((pfc_conf->fc.high_water > max_high_water) ||
2639 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2640 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2641 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2645 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2646 hw->fc.pause_time = pfc_conf->fc.pause_time;
2647 hw->fc.send_xon = pfc_conf->fc.send_xon;
2648 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2649 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2651 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2653 /* Not negotiated is not an error case */
2654 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2657 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2662 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2663 struct rte_eth_rss_reta *reta_conf)
2667 struct ixgbe_hw *hw =
2668 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2670 PMD_INIT_FUNC_TRACE();
2672 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2673 * 128-entries in 32 registers
2675 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2676 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2677 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2679 mask = (uint8_t)((reta_conf->mask_hi >>
2680 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2684 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2686 for (j = 0; j < 4; j++) {
2687 if (mask & (0x1 << j)) {
2689 reta &= ~(0xFF << 8 * j);
2690 reta |= reta_conf->reta[i + j] << 8*j;
2693 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2701 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2702 struct rte_eth_rss_reta *reta_conf)
2706 struct ixgbe_hw *hw =
2707 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2709 PMD_INIT_FUNC_TRACE();
2711 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2712 * 128-entries in 32 registers
2714 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2715 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2716 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2718 mask = (uint8_t)((reta_conf->mask_hi >>
2719 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2722 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2723 for (j = 0; j < 4; j++) {
2724 if (mask & (0x1 << j))
2725 reta_conf->reta[i + j] =
2726 (uint8_t)((reta >> 8 * j) & 0xFF);
2735 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2736 uint32_t index, uint32_t pool)
2738 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2739 uint32_t enable_addr = 1;
2741 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2745 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2747 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2749 ixgbe_clear_rar(hw, index);
2753 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2757 struct ixgbe_hw *hw;
2758 struct rte_eth_dev_info dev_info;
2759 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2761 ixgbe_dev_info_get(dev, &dev_info);
2763 /* check that mtu is within the allowed range */
2764 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2767 /* refuse mtu that requires the support of scattered packets when this
2768 * feature has not been enabled before. */
2769 if (!dev->data->scattered_rx &&
2770 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2771 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2774 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2775 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2777 /* switch to jumbo mode if needed */
2778 if (frame_size > ETHER_MAX_LEN) {
2779 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2780 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2782 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2783 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2785 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2787 /* update max frame size */
2788 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2790 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2791 maxfrs &= 0x0000FFFF;
2792 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2793 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2799 * Virtual Function operations
2802 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2804 PMD_INIT_FUNC_TRACE();
2806 /* Clear interrupt mask to stop from interrupts being generated */
2807 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2809 IXGBE_WRITE_FLUSH(hw);
2813 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2815 struct rte_eth_conf* conf = &dev->data->dev_conf;
2817 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2818 dev->data->port_id);
2821 * VF has no ability to enable/disable HW CRC
2822 * Keep the persistent behavior the same as Host PF
2824 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2825 if (!conf->rxmode.hw_strip_crc) {
2826 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2827 conf->rxmode.hw_strip_crc = 1;
2830 if (conf->rxmode.hw_strip_crc) {
2831 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2832 conf->rxmode.hw_strip_crc = 0;
2840 ixgbevf_dev_start(struct rte_eth_dev *dev)
2842 struct ixgbe_hw *hw =
2843 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846 PMD_INIT_FUNC_TRACE();
2848 hw->mac.ops.reset_hw(hw);
2850 /* negotiate mailbox API version to use with the PF. */
2851 ixgbevf_negotiate_api(hw);
2853 ixgbevf_dev_tx_init(dev);
2855 /* This can fail when allocating mbufs for descriptor rings */
2856 err = ixgbevf_dev_rx_init(dev);
2858 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2859 ixgbe_dev_clear_queues(dev);
2864 ixgbevf_set_vfta_all(dev,1);
2867 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2868 ETH_VLAN_EXTEND_MASK;
2869 ixgbevf_vlan_offload_set(dev, mask);
2871 ixgbevf_dev_rxtx_start(dev);
2877 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2879 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881 PMD_INIT_FUNC_TRACE();
2883 hw->adapter_stopped = TRUE;
2884 ixgbe_stop_adapter(hw);
2887 * Clear what we set, but we still keep shadow_vfta to
2888 * restore after device starts
2890 ixgbevf_set_vfta_all(dev,0);
2892 ixgbe_dev_clear_queues(dev);
2896 ixgbevf_dev_close(struct rte_eth_dev *dev)
2898 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900 PMD_INIT_FUNC_TRACE();
2904 ixgbevf_dev_stop(dev);
2906 /* reprogram the RAR[0] in case user changed it. */
2907 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2910 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2912 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2913 struct ixgbe_vfta * shadow_vfta =
2914 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2915 int i = 0, j = 0, vfta = 0, mask = 1;
2917 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2918 vfta = shadow_vfta->vfta[i];
2921 for (j = 0; j < 32; j++){
2923 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2932 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2934 struct ixgbe_hw *hw =
2935 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936 struct ixgbe_vfta * shadow_vfta =
2937 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2938 uint32_t vid_idx = 0;
2939 uint32_t vid_bit = 0;
2942 PMD_INIT_FUNC_TRACE();
2944 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2945 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2947 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2950 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2951 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2953 /* Save what we set and retore it after device reset */
2955 shadow_vfta->vfta[vid_idx] |= vid_bit;
2957 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2963 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2965 struct ixgbe_hw *hw =
2966 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969 PMD_INIT_FUNC_TRACE();
2971 if(queue >= hw->mac.max_rx_queues)
2974 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2976 ctrl |= IXGBE_RXDCTL_VME;
2978 ctrl &= ~IXGBE_RXDCTL_VME;
2979 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2981 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2985 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2987 struct ixgbe_hw *hw =
2988 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2992 /* VF function only support hw strip feature, others are not support */
2993 if(mask & ETH_VLAN_STRIP_MASK){
2994 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2996 for(i=0; i < hw->mac.max_rx_queues; i++)
2997 ixgbevf_vlan_strip_queue_set(dev,i,on);
3002 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3006 /* we only need to do this if VMDq is enabled */
3007 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3008 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3009 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3017 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3019 uint32_t vector = 0;
3020 switch (hw->mac.mc_filter_type) {
3021 case 0: /* use bits [47:36] of the address */
3022 vector = ((uc_addr->addr_bytes[4] >> 4) |
3023 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3025 case 1: /* use bits [46:35] of the address */
3026 vector = ((uc_addr->addr_bytes[4] >> 3) |
3027 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3029 case 2: /* use bits [45:34] of the address */
3030 vector = ((uc_addr->addr_bytes[4] >> 2) |
3031 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3033 case 3: /* use bits [43:32] of the address */
3034 vector = ((uc_addr->addr_bytes[4]) |
3035 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3037 default: /* Invalid mc_filter_type */
3041 /* vector can only be 12-bits or boundary will be exceeded */
3047 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3055 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3056 const uint32_t ixgbe_uta_bit_shift = 5;
3057 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3058 const uint32_t bit1 = 0x1;
3060 struct ixgbe_hw *hw =
3061 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3062 struct ixgbe_uta_info *uta_info =
3063 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3065 /* The UTA table only exists on 82599 hardware and newer */
3066 if (hw->mac.type < ixgbe_mac_82599EB)
3069 vector = ixgbe_uta_vector(hw,mac_addr);
3070 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3071 uta_shift = vector & ixgbe_uta_bit_mask;
3073 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3077 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3079 uta_info->uta_in_use++;
3080 reg_val |= (bit1 << uta_shift);
3081 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3083 uta_info->uta_in_use--;
3084 reg_val &= ~(bit1 << uta_shift);
3085 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3088 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3090 if (uta_info->uta_in_use > 0)
3091 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3092 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3094 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3100 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3103 struct ixgbe_hw *hw =
3104 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3105 struct ixgbe_uta_info *uta_info =
3106 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3108 /* The UTA table only exists on 82599 hardware and newer */
3109 if (hw->mac.type < ixgbe_mac_82599EB)
3113 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3114 uta_info->uta_shadow[i] = ~0;
3115 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3118 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3119 uta_info->uta_shadow[i] = 0;
3120 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3128 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3130 uint32_t new_val = orig_val;
3132 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3133 new_val |= IXGBE_VMOLR_AUPE;
3134 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3135 new_val |= IXGBE_VMOLR_ROMPE;
3136 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3137 new_val |= IXGBE_VMOLR_ROPE;
3138 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3139 new_val |= IXGBE_VMOLR_BAM;
3140 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3141 new_val |= IXGBE_VMOLR_MPE;
3147 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3148 uint16_t rx_mask, uint8_t on)
3152 struct ixgbe_hw *hw =
3153 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3154 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3156 if (hw->mac.type == ixgbe_mac_82598EB) {
3157 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3158 " on 82599 hardware and newer");
3161 if (ixgbe_vmdq_mode_check(hw) < 0)
3164 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3171 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3177 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3181 const uint8_t bit1 = 0x1;
3183 struct ixgbe_hw *hw =
3184 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3186 if (ixgbe_vmdq_mode_check(hw) < 0)
3189 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3190 reg = IXGBE_READ_REG(hw, addr);
3198 IXGBE_WRITE_REG(hw, addr,reg);
3204 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3208 const uint8_t bit1 = 0x1;
3210 struct ixgbe_hw *hw =
3211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3213 if (ixgbe_vmdq_mode_check(hw) < 0)
3216 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3217 reg = IXGBE_READ_REG(hw, addr);
3225 IXGBE_WRITE_REG(hw, addr,reg);
3231 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3232 uint64_t pool_mask, uint8_t vlan_on)
3236 struct ixgbe_hw *hw =
3237 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3239 if (ixgbe_vmdq_mode_check(hw) < 0)
3241 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3242 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3243 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3252 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3253 struct rte_eth_vmdq_mirror_conf *mirror_conf,
3254 uint8_t rule_id, uint8_t on)
3256 uint32_t mr_ctl,vlvf;
3257 uint32_t mp_lsb = 0;
3258 uint32_t mv_msb = 0;
3259 uint32_t mv_lsb = 0;
3260 uint32_t mp_msb = 0;
3263 uint64_t vlan_mask = 0;
3265 const uint8_t pool_mask_offset = 32;
3266 const uint8_t vlan_mask_offset = 32;
3267 const uint8_t dst_pool_offset = 8;
3268 const uint8_t rule_mr_offset = 4;
3269 const uint8_t mirror_rule_mask= 0x0F;
3271 struct ixgbe_mirror_info *mr_info =
3272 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3273 struct ixgbe_hw *hw =
3274 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3276 if (ixgbe_vmdq_mode_check(hw) < 0)
3279 /* Check if vlan mask is valid */
3280 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3281 if (mirror_conf->vlan.vlan_mask == 0)
3285 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3286 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3287 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3288 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3289 /* search vlan id related pool vlan filter index */
3290 reg_index = ixgbe_find_vlvf_slot(hw,
3291 mirror_conf->vlan.vlan_id[i]);
3294 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3295 if ((vlvf & IXGBE_VLVF_VIEN) &&
3296 ((vlvf & IXGBE_VLVF_VLANID_MASK)
3297 == mirror_conf->vlan.vlan_id[i]))
3298 vlan_mask |= (1ULL << reg_index);
3305 mv_lsb = vlan_mask & 0xFFFFFFFF;
3306 mv_msb = vlan_mask >> vlan_mask_offset;
3308 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3309 mirror_conf->vlan.vlan_mask;
3310 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3311 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3312 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3313 mirror_conf->vlan.vlan_id[i];
3318 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3319 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3320 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3325 * if enable pool mirror, write related pool mask register,if disable
3326 * pool mirror, clear PFMRVM register
3328 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3330 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3331 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3332 mr_info->mr_conf[rule_id].pool_mask =
3333 mirror_conf->pool_mask;
3338 mr_info->mr_conf[rule_id].pool_mask = 0;
3342 /* read mirror control register and recalculate it */
3343 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3346 mr_ctl |= mirror_conf->rule_type_mask;
3347 mr_ctl &= mirror_rule_mask;
3348 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3350 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3352 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3353 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3355 /* write mirrror control register */
3356 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3358 /* write pool mirrror control register */
3359 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3360 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3361 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3364 /* write VLAN mirrror control register */
3365 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3366 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3367 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3375 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3378 uint32_t lsb_val = 0;
3379 uint32_t msb_val = 0;
3380 const uint8_t rule_mr_offset = 4;
3382 struct ixgbe_hw *hw =
3383 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3384 struct ixgbe_mirror_info *mr_info =
3385 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3387 if (ixgbe_vmdq_mode_check(hw) < 0)
3390 memset(&mr_info->mr_conf[rule_id], 0,
3391 sizeof(struct rte_eth_vmdq_mirror_conf));
3393 /* clear PFVMCTL register */
3394 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3396 /* clear pool mask register */
3397 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3398 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3400 /* clear vlan mask register */
3401 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3402 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3407 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3408 uint16_t queue_idx, uint16_t tx_rate)
3410 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3411 uint32_t rf_dec, rf_int;
3413 uint16_t link_speed = dev->data->dev_link.link_speed;
3415 if (queue_idx >= hw->mac.max_tx_queues)
3419 /* Calculate the rate factor values to set */
3420 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3421 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3422 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3424 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3425 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3426 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3427 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3433 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3434 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3437 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3438 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3439 IXGBE_MAX_JUMBO_FRAME_SIZE))
3440 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3441 IXGBE_MMW_SIZE_JUMBO_FRAME);
3443 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3444 IXGBE_MMW_SIZE_DEFAULT);
3446 /* Set RTTBCNRC of queue X */
3447 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3448 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3449 IXGBE_WRITE_FLUSH(hw);
3454 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3455 uint16_t tx_rate, uint64_t q_msk)
3457 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458 struct ixgbe_vf_info *vfinfo =
3459 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3460 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3461 uint32_t queue_stride =
3462 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3463 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3464 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3465 uint16_t total_rate = 0;
3467 if (queue_end >= hw->mac.max_tx_queues)
3470 if (vfinfo != NULL) {
3471 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3474 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3476 total_rate += vfinfo[vf_idx].tx_rate[idx];
3481 /* Store tx_rate for this vf. */
3482 for (idx = 0; idx < nb_q_per_pool; idx++) {
3483 if (((uint64_t)0x1 << idx) & q_msk) {
3484 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3485 vfinfo[vf].tx_rate[idx] = tx_rate;
3486 total_rate += tx_rate;
3490 if (total_rate > dev->data->dev_link.link_speed) {
3492 * Reset stored TX rate of the VF if it causes exceed
3495 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3499 /* Set RTTBCNRC of each queue/pool for vf X */
3500 for (; queue_idx <= queue_end; queue_idx++) {
3502 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3510 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3511 __attribute__((unused)) uint32_t index,
3512 __attribute__((unused)) uint32_t pool)
3514 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3519 * operation. Trap this case to avoid exhausting the [very limited]
3520 * set of PF resources used to store VF MAC addresses.
3522 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3524 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3527 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3531 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3533 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3534 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3535 struct ether_addr *mac_addr;
3540 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3541 * not support the deletion of a given MAC address.
3542 * Instead, it imposes to delete all MAC addresses, then to add again
3543 * all MAC addresses with the exception of the one to be deleted.
3545 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3548 * Add again all MAC addresses, with the exception of the deleted one
3549 * and of the permanent MAC address.
3551 for (i = 0, mac_addr = dev->data->mac_addrs;
3552 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3553 /* Skip the deleted MAC address */
3556 /* Skip NULL MAC addresses */
3557 if (is_zero_ether_addr(mac_addr))
3559 /* Skip the permanent MAC address */
3560 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3562 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3565 "Adding again MAC address "
3566 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3568 mac_addr->addr_bytes[0],
3569 mac_addr->addr_bytes[1],
3570 mac_addr->addr_bytes[2],
3571 mac_addr->addr_bytes[3],
3572 mac_addr->addr_bytes[4],
3573 mac_addr->addr_bytes[5],
3582 * dev: Pointer to struct rte_eth_dev.
3583 * filter: ponter to the filter that will be added.
3584 * rx_queue: the queue id the filter assigned to.
3587 * - On success, zero.
3588 * - On failure, a negative value.
3591 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3592 struct rte_syn_filter *filter, uint16_t rx_queue)
3594 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3597 if (hw->mac.type != ixgbe_mac_82599EB)
3600 if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3603 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3605 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3608 synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3609 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3611 if (filter->hig_pri)
3612 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3614 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3616 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3624 * dev: Pointer to struct rte_eth_dev.
3627 * - On success, zero.
3628 * - On failure, a negative value.
3631 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3633 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3636 if (hw->mac.type != ixgbe_mac_82599EB)
3639 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3641 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3643 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3648 * get the syn filter's info
3651 * dev: Pointer to struct rte_eth_dev.
3652 * filter: ponter to the filter that returns.
3653 * *rx_queue: pointer to the queue id the filter assigned to.
3656 * - On success, zero.
3657 * - On failure, a negative value.
3660 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3661 struct rte_syn_filter *filter, uint16_t *rx_queue)
3664 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3667 if (hw->mac.type != ixgbe_mac_82599EB)
3670 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3671 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3672 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3673 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3680 * add an ethertype filter
3683 * dev: Pointer to struct rte_eth_dev.
3684 * index: the index the filter allocates.
3685 * filter: ponter to the filter that will be added.
3686 * rx_queue: the queue id the filter assigned to.
3689 * - On success, zero.
3690 * - On failure, a negative value.
3693 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3694 uint16_t index, struct rte_ethertype_filter *filter,
3697 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698 uint32_t etqf, etqs = 0;
3700 if (hw->mac.type != ixgbe_mac_82599EB)
3703 if (index >= IXGBE_MAX_ETQF_FILTERS ||
3704 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3707 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3708 if (etqf & IXGBE_ETQF_FILTER_EN)
3709 return -EINVAL; /* filter index is in use. */
3712 etqf |= IXGBE_ETQF_FILTER_EN;
3713 etqf |= (uint32_t)filter->ethertype;
3715 if (filter->priority_en) {
3716 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3718 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3719 etqf |= IXGBE_ETQF_UP_EN;
3721 etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3722 etqs |= IXGBE_ETQS_QUEUE_EN;
3724 IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3725 IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3730 * remove an ethertype filter
3733 * dev: Pointer to struct rte_eth_dev.
3734 * index: the index the filter allocates.
3737 * - On success, zero.
3738 * - On failure, a negative value.
3741 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3744 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3746 if (hw->mac.type != ixgbe_mac_82599EB)
3749 if (index >= IXGBE_MAX_ETQF_FILTERS)
3752 IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3753 IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3759 * get an ethertype filter
3762 * dev: Pointer to struct rte_eth_dev.
3763 * index: the index the filter allocates.
3764 * filter: ponter to the filter that will be gotten.
3765 * *rx_queue: the ponited of the queue id the filter assigned to.
3768 * - On success, zero.
3769 * - On failure, a negative value.
3772 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3773 uint16_t index, struct rte_ethertype_filter *filter,
3776 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3777 uint32_t etqf, etqs;
3779 if (hw->mac.type != ixgbe_mac_82599EB)
3782 if (index >= IXGBE_MAX_ETQF_FILTERS)
3785 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3786 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3787 if (etqf & IXGBE_ETQF_FILTER_EN) {
3788 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3789 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3790 if (filter->priority_en)
3791 filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3792 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3798 static inline enum ixgbe_5tuple_protocol
3799 convert_protocol_type(uint8_t protocol_value)
3801 if (protocol_value == IPPROTO_TCP)
3802 return IXGBE_FILTER_PROTOCOL_TCP;
3803 else if (protocol_value == IPPROTO_UDP)
3804 return IXGBE_FILTER_PROTOCOL_UDP;
3805 else if (protocol_value == IPPROTO_SCTP)
3806 return IXGBE_FILTER_PROTOCOL_SCTP;
3808 return IXGBE_FILTER_PROTOCOL_NONE;
3811 static inline uint8_t
3812 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3814 if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3816 else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3818 else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3819 return IPPROTO_SCTP;
3825 * add a 5tuple filter
3828 * dev: Pointer to struct rte_eth_dev.
3829 * index: the index the filter allocates.
3830 * filter: ponter to the filter that will be added.
3831 * rx_queue: the queue id the filter assigned to.
3834 * - On success, zero.
3835 * - On failure, a negative value.
3838 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3839 struct rte_5tuple_filter *filter, uint16_t rx_queue)
3841 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3842 uint32_t ftqf, sdpqf = 0;
3843 uint32_t l34timir = 0;
3844 uint8_t mask = 0xff;
3846 if (hw->mac.type != ixgbe_mac_82599EB)
3849 if (index >= IXGBE_MAX_FTQF_FILTERS ||
3850 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3851 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3852 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3853 return -EINVAL; /* filter index is out of range. */
3855 if (filter->tcp_flags) {
3856 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3860 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3861 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3862 return -EINVAL; /* filter index is in use. */
3865 sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3866 sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3868 ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3869 IXGBE_FTQF_PROTOCOL_MASK);
3870 ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3871 IXGBE_FTQF_PRIORITY_SHIFT);
3872 if (filter->src_ip_mask == 0) /* 0 means compare. */
3873 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3874 if (filter->dst_ip_mask == 0)
3875 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3876 if (filter->src_port_mask == 0)
3877 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3878 if (filter->dst_port_mask == 0)
3879 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3880 if (filter->protocol_mask == 0)
3881 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3882 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3883 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3884 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3886 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3887 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3888 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3889 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3891 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3892 l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3893 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3898 * remove a 5tuple filter
3901 * dev: Pointer to struct rte_eth_dev.
3902 * index: the index the filter allocates.
3905 * - On success, zero.
3906 * - On failure, a negative value.
3909 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3912 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3914 if (hw->mac.type != ixgbe_mac_82599EB)
3917 if (index >= IXGBE_MAX_FTQF_FILTERS)
3918 return -EINVAL; /* filter index is out of range. */
3920 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3921 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3922 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3923 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3924 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3929 * get a 5tuple filter
3932 * dev: Pointer to struct rte_eth_dev.
3933 * index: the index the filter allocates
3934 * filter: ponter to the filter that returns.
3935 * *rx_queue: pointer of the queue id the filter assigned to.
3938 * - On success, zero.
3939 * - On failure, a negative value.
3942 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3943 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3945 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946 uint32_t sdpqf, ftqf, l34timir;
3948 enum ixgbe_5tuple_protocol proto;
3950 if (hw->mac.type != ixgbe_mac_82599EB)
3953 if (index >= IXGBE_MAX_FTQF_FILTERS)
3954 return -EINVAL; /* filter index is out of range. */
3956 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3957 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3958 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3959 filter->protocol = revert_protocol_type(proto);
3960 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3961 IXGBE_FTQF_PRIORITY_MASK;
3962 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3963 IXGBE_FTQF_5TUPLE_MASK_MASK);
3964 filter->src_ip_mask =
3965 (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3966 filter->dst_ip_mask =
3967 (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3968 filter->src_port_mask =
3969 (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3970 filter->dst_port_mask =
3971 (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3972 filter->protocol_mask =
3973 (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3975 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3976 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3977 IXGBE_SDPQF_DSTPORT_SHIFT;
3978 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3979 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3980 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3982 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3983 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3984 IXGBE_L34T_IMIR_QUEUE_SHIFT;
3991 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3993 struct ixgbe_hw *hw;
3994 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3996 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3998 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4001 /* refuse mtu that requires the support of scattered packets when this
4002 * feature has not been enabled before. */
4003 if (!dev->data->scattered_rx &&
4004 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4005 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4009 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4010 * request of the version 2.0 of the mailbox API.
4011 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4012 * of the mailbox API.
4013 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4014 * prior to 3.11.33 which contains the following change:
4015 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4017 ixgbevf_rlpml_set_vf(hw, max_frame);
4019 /* update max frame size */
4020 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4024 static struct rte_driver rte_ixgbe_driver = {
4026 .init = rte_ixgbe_pmd_init,
4029 static struct rte_driver rte_ixgbevf_driver = {
4031 .init = rte_ixgbevf_pmd_init,
4034 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4035 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);