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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_tailq.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
63 #include "ixgbe_logs.h"
64 #include "ixgbe/ixgbe_api.h"
65 #include "ixgbe/ixgbe_vf.h"
66 #include "ixgbe/ixgbe_common.h"
67 #include "ixgbe_ethdev.h"
68 #include "ixgbe_bypass.h"
71 * High threshold controlling when to start sending XOFF frames. Must be at
72 * least 8 bytes less than receive packet buffer size. This value is in units
75 #define IXGBE_FC_HI 0x80
78 * Low threshold controlling when to start sending XON frames. This value is
79 * in units of 1024 bytes.
81 #define IXGBE_FC_LO 0x40
83 /* Timer value included in XOFF frames. */
84 #define IXGBE_FC_PAUSE 0x680
86 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
87 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
88 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
91 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
93 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
95 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
96 struct rte_eth_dev *eth_dev);
97 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
98 static int ixgbe_dev_start(struct rte_eth_dev *dev);
99 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
100 static void ixgbe_dev_close(struct rte_eth_dev *dev);
101 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
102 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
103 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
104 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
105 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
106 int wait_to_complete);
107 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
108 struct rte_eth_stats *stats);
109 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
110 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
114 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
115 struct rte_eth_dev_info *dev_info);
116 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
117 uint16_t vlan_id, int on);
118 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
119 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
120 uint16_t queue, bool on);
121 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
123 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
124 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
125 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
126 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
127 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
129 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
130 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
131 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
132 struct rte_eth_fc_conf *fc_conf);
133 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
134 struct rte_eth_pfc_conf *pfc_conf);
135 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
136 struct rte_eth_rss_reta *reta_conf);
137 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
138 struct rte_eth_rss_reta *reta_conf);
139 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
140 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
141 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
142 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
143 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
145 static void ixgbe_dev_interrupt_delayed_handler(void *param);
146 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
147 uint32_t index, uint32_t pool);
148 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
149 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
151 /* For Virtual Function support */
152 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
153 struct rte_eth_dev *eth_dev);
154 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
155 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
156 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
157 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
158 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
159 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
160 struct rte_eth_stats *stats);
161 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
162 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
163 uint16_t vlan_id, int on);
164 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
165 uint16_t queue, int on);
166 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
167 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
169 /* For Eth VMDQ APIs support */
170 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
171 ether_addr* mac_addr,uint8_t on);
172 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
173 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
174 uint16_t rx_mask, uint8_t on);
175 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
176 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
177 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
178 uint64_t pool_mask,uint8_t vlan_on);
179 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
180 struct rte_eth_vmdq_mirror_conf *mirror_conf,
181 uint8_t rule_id, uint8_t on);
182 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
185 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
186 struct ether_addr *mac_addr,
187 uint32_t index, uint32_t pool);
188 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
191 * Define VF Stats MACRO for Non "cleared on read" register
193 #define UPDATE_VF_STAT(reg, last, cur) \
195 u32 latest = IXGBE_READ_REG(hw, reg); \
196 cur += latest - last; \
200 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
202 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
203 u64 new_msb = IXGBE_READ_REG(hw, msb); \
204 u64 latest = ((new_msb << 32) | new_lsb); \
205 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
209 #define IXGBE_SET_HWSTRIP(h, q) do{\
210 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
211 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
212 (h)->bitmap[idx] |= 1 << bit;\
215 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
216 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
217 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
218 (h)->bitmap[idx] &= ~(1 << bit);\
221 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
222 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
223 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
224 (r) = (h)->bitmap[idx] >> bit & 1;\
228 * The set of PCI devices this driver supports
230 static struct rte_pci_id pci_id_ixgbe_map[] = {
232 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
233 #include "rte_pci_dev_ids.h"
235 { .vendor_id = 0, /* sentinel */ },
240 * The set of PCI devices this driver supports (for 82599 VF)
242 static struct rte_pci_id pci_id_ixgbevf_map[] = {
244 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
245 #include "rte_pci_dev_ids.h"
246 { .vendor_id = 0, /* sentinel */ },
250 static struct eth_dev_ops ixgbe_eth_dev_ops = {
251 .dev_configure = ixgbe_dev_configure,
252 .dev_start = ixgbe_dev_start,
253 .dev_stop = ixgbe_dev_stop,
254 .dev_close = ixgbe_dev_close,
255 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
256 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
257 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
258 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
259 .link_update = ixgbe_dev_link_update,
260 .stats_get = ixgbe_dev_stats_get,
261 .stats_reset = ixgbe_dev_stats_reset,
262 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
263 .dev_infos_get = ixgbe_dev_info_get,
264 .vlan_filter_set = ixgbe_vlan_filter_set,
265 .vlan_tpid_set = ixgbe_vlan_tpid_set,
266 .vlan_offload_set = ixgbe_vlan_offload_set,
267 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
268 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
269 .rx_queue_release = ixgbe_dev_rx_queue_release,
270 .rx_queue_count = ixgbe_dev_rx_queue_count,
271 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
272 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
273 .tx_queue_release = ixgbe_dev_tx_queue_release,
274 .dev_led_on = ixgbe_dev_led_on,
275 .dev_led_off = ixgbe_dev_led_off,
276 .flow_ctrl_set = ixgbe_flow_ctrl_set,
277 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
278 .mac_addr_add = ixgbe_add_rar,
279 .mac_addr_remove = ixgbe_remove_rar,
280 .uc_hash_table_set = ixgbe_uc_hash_table_set,
281 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
282 .mirror_rule_set = ixgbe_mirror_rule_set,
283 .mirror_rule_reset = ixgbe_mirror_rule_reset,
284 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
285 .set_vf_rx = ixgbe_set_pool_rx,
286 .set_vf_tx = ixgbe_set_pool_tx,
287 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
288 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
289 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
290 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
291 .fdir_infos_get = ixgbe_fdir_info_get,
292 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
293 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
294 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
295 .fdir_set_masks = ixgbe_fdir_set_masks,
296 .reta_update = ixgbe_dev_rss_reta_update,
297 .reta_query = ixgbe_dev_rss_reta_query,
298 #ifdef RTE_NIC_BYPASS
299 .bypass_init = ixgbe_bypass_init,
300 .bypass_state_set = ixgbe_bypass_state_store,
301 .bypass_state_show = ixgbe_bypass_state_show,
302 .bypass_event_set = ixgbe_bypass_event_store,
303 .bypass_event_show = ixgbe_bypass_event_show,
304 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
305 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
306 .bypass_ver_show = ixgbe_bypass_ver_show,
307 .bypass_wd_reset = ixgbe_bypass_wd_reset,
308 #endif /* RTE_NIC_BYPASS */
312 * dev_ops for virtual function, bare necessities for basic vf
313 * operation have been implemented
315 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
317 .dev_configure = ixgbevf_dev_configure,
318 .dev_start = ixgbevf_dev_start,
319 .dev_stop = ixgbevf_dev_stop,
320 .link_update = ixgbe_dev_link_update,
321 .stats_get = ixgbevf_dev_stats_get,
322 .stats_reset = ixgbevf_dev_stats_reset,
323 .dev_close = ixgbevf_dev_close,
324 .dev_infos_get = ixgbe_dev_info_get,
325 .vlan_filter_set = ixgbevf_vlan_filter_set,
326 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
327 .vlan_offload_set = ixgbevf_vlan_offload_set,
328 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
329 .rx_queue_release = ixgbe_dev_rx_queue_release,
330 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
331 .tx_queue_release = ixgbe_dev_tx_queue_release,
332 .mac_addr_add = ixgbevf_add_mac_addr,
333 .mac_addr_remove = ixgbevf_remove_mac_addr,
337 * Atomically reads the link status information from global
338 * structure rte_eth_dev.
341 * - Pointer to the structure rte_eth_dev to read from.
342 * - Pointer to the buffer to be saved with the link status.
345 * - On success, zero.
346 * - On failure, negative value.
349 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
350 struct rte_eth_link *link)
352 struct rte_eth_link *dst = link;
353 struct rte_eth_link *src = &(dev->data->dev_link);
355 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
356 *(uint64_t *)src) == 0)
363 * Atomically writes the link status information into global
364 * structure rte_eth_dev.
367 * - Pointer to the structure rte_eth_dev to read from.
368 * - Pointer to the buffer to be saved with the link status.
371 * - On success, zero.
372 * - On failure, negative value.
375 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
376 struct rte_eth_link *link)
378 struct rte_eth_link *dst = &(dev->data->dev_link);
379 struct rte_eth_link *src = link;
381 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
382 *(uint64_t *)src) == 0)
389 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
392 ixgbe_is_sfp(struct ixgbe_hw *hw)
394 switch (hw->phy.type) {
395 case ixgbe_phy_sfp_avago:
396 case ixgbe_phy_sfp_ftl:
397 case ixgbe_phy_sfp_intel:
398 case ixgbe_phy_sfp_unknown:
399 case ixgbe_phy_sfp_passive_tyco:
400 case ixgbe_phy_sfp_passive_unknown:
407 static inline int32_t
408 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
413 status = ixgbe_reset_hw(hw);
415 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
416 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
417 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
418 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
419 IXGBE_WRITE_FLUSH(hw);
425 ixgbe_enable_intr(struct rte_eth_dev *dev)
427 struct ixgbe_interrupt *intr =
428 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
429 struct ixgbe_hw *hw =
430 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
432 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
433 IXGBE_WRITE_FLUSH(hw);
437 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
440 ixgbe_disable_intr(struct ixgbe_hw *hw)
442 PMD_INIT_FUNC_TRACE();
444 if (hw->mac.type == ixgbe_mac_82598EB) {
445 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
447 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
448 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
449 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
451 IXGBE_WRITE_FLUSH(hw);
455 * This function resets queue statistics mapping registers.
456 * From Niantic datasheet, Initialization of Statistics section:
457 * "...if software requires the queue counters, the RQSMR and TQSM registers
458 * must be re-programmed following a device reset.
461 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
465 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
466 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
467 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
473 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
478 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
479 #define NB_QMAP_FIELDS_PER_QSM_REG 4
480 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
482 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
483 struct ixgbe_stat_mapping_registers *stat_mappings =
484 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
485 uint32_t qsmr_mask = 0;
486 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
490 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
493 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
494 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
496 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
497 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
498 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
501 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
503 /* Now clear any previous stat_idx set */
504 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
506 stat_mappings->tqsm[n] &= ~clearing_mask;
508 stat_mappings->rqsmr[n] &= ~clearing_mask;
510 q_map = (uint32_t)stat_idx;
511 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
512 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
514 stat_mappings->tqsm[n] |= qsmr_mask;
516 stat_mappings->rqsmr[n] |= qsmr_mask;
518 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
520 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
521 is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
523 /* Now write the mapping in the appropriate register */
525 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
526 stat_mappings->rqsmr[n], n);
527 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
530 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
531 stat_mappings->tqsm[n], n);
532 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
538 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
540 struct ixgbe_stat_mapping_registers *stat_mappings =
541 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
542 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
545 /* write whatever was in stat mapping table to the NIC */
546 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
548 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
551 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
556 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
559 struct ixgbe_dcb_tc_config *tc;
560 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
562 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
563 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
564 for (i = 0; i < dcb_max_tc; i++) {
565 tc = &dcb_config->tc_config[i];
566 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
567 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
568 (uint8_t)(100/dcb_max_tc + (i & 1));
569 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
570 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
571 (uint8_t)(100/dcb_max_tc + (i & 1));
572 tc->pfc = ixgbe_dcb_pfc_disabled;
575 /* Initialize default user to priority mapping, UPx->TC0 */
576 tc = &dcb_config->tc_config[0];
577 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
578 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
579 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
580 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
581 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
583 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
584 dcb_config->pfc_mode_enable = false;
585 dcb_config->vt_mode = true;
586 dcb_config->round_robin_enable = false;
587 /* support all DCB capabilities in 82599 */
588 dcb_config->support.capabilities = 0xFF;
590 /*we only support 4 Tcs for X540*/
591 if (hw->mac.type == ixgbe_mac_X540) {
592 dcb_config->num_tcs.pg_tcs = 4;
593 dcb_config->num_tcs.pfc_tcs = 4;
598 * Ensure that all locks are released before first NVM or PHY access
601 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
606 * Phy lock should not fail in this early stage. If this is the case,
607 * it is due to an improper exit of the application.
608 * So force the release of the faulty lock. Release of common lock
609 * is done automatically by swfw_sync function.
611 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
612 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
613 DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
615 ixgbe_release_swfw_semaphore(hw, mask);
618 * These ones are more tricky since they are common to all ports; but
619 * swfw_sync retries last long enough (1s) to be almost sure that if
620 * lock can not be taken it is due to an improper lock of the
623 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
624 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
625 DEBUGOUT("SWFW common locks released");
627 ixgbe_release_swfw_semaphore(hw, mask);
631 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
632 * It returns 0 on success.
635 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
636 struct rte_eth_dev *eth_dev)
638 struct rte_pci_device *pci_dev;
639 struct ixgbe_hw *hw =
640 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
641 struct ixgbe_vfta * shadow_vfta =
642 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
643 struct ixgbe_hwstrip *hwstrip =
644 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
645 struct ixgbe_dcb_config *dcb_config =
646 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
651 PMD_INIT_FUNC_TRACE();
653 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
654 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
655 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
657 /* for secondary processes, we don't initialise any further as primary
658 * has already done this work. Only check we don't need a different
660 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
661 if (eth_dev->data->scattered_rx)
662 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
665 pci_dev = eth_dev->pci_dev;
667 /* Vendor and Device ID need to be set before init of shared code */
668 hw->device_id = pci_dev->id.device_id;
669 hw->vendor_id = pci_dev->id.vendor_id;
670 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
671 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
672 hw->allow_unsupported_sfp = 1;
675 /* Initialize the shared code */
676 #ifdef RTE_NIC_BYPASS
677 diag = ixgbe_bypass_init_shared_code(hw);
679 diag = ixgbe_init_shared_code(hw);
680 #endif /* RTE_NIC_BYPASS */
682 if (diag != IXGBE_SUCCESS) {
683 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
687 /* pick up the PCI bus settings for reporting later */
688 ixgbe_get_bus_info(hw);
690 /* Unlock any pending hardware semaphore */
691 ixgbe_swfw_lock_reset(hw);
693 /* Initialize DCB configuration*/
694 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
695 ixgbe_dcb_init(hw,dcb_config);
696 /* Get Hardware Flow Control setting */
697 hw->fc.requested_mode = ixgbe_fc_full;
698 hw->fc.current_mode = ixgbe_fc_full;
699 hw->fc.pause_time = IXGBE_FC_PAUSE;
700 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
701 hw->fc.low_water[i] = IXGBE_FC_LO;
702 hw->fc.high_water[i] = IXGBE_FC_HI;
706 /* Make sure we have a good EEPROM before we read from it */
707 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
708 if (diag != IXGBE_SUCCESS) {
709 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
713 #ifdef RTE_NIC_BYPASS
714 diag = ixgbe_bypass_init_hw(hw);
716 diag = ixgbe_init_hw(hw);
717 #endif /* RTE_NIC_BYPASS */
720 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
721 * is called too soon after the kernel driver unbinding/binding occurs.
722 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
723 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
724 * also called. See ixgbe_identify_phy_82599(). The reason for the
725 * failure is not known, and only occuts when virtualisation features
726 * are disabled in the bios. A delay of 100ms was found to be enough by
727 * trial-and-error, and is doubled to be safe.
729 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
731 diag = ixgbe_init_hw(hw);
734 if (diag == IXGBE_ERR_EEPROM_VERSION) {
735 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
736 "LOM. Please be aware there may be issues associated "
737 "with your hardware.\n If you are experiencing problems "
738 "please contact your Intel or hardware representative "
739 "who provided you with this hardware.\n");
740 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
741 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
743 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
747 /* disable interrupt */
748 ixgbe_disable_intr(hw);
750 /* reset mappings for queue statistics hw counters*/
751 ixgbe_reset_qstat_mappings(hw);
753 /* Allocate memory for storing MAC addresses */
754 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
755 hw->mac.num_rar_entries, 0);
756 if (eth_dev->data->mac_addrs == NULL) {
758 "Failed to allocate %u bytes needed to store "
760 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
763 /* Copy the permanent MAC address */
764 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
765 ð_dev->data->mac_addrs[0]);
767 /* Allocate memory for storing hash filter MAC addresses */
768 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
769 IXGBE_VMDQ_NUM_UC_MAC, 0);
770 if (eth_dev->data->hash_mac_addrs == NULL) {
772 "Failed to allocate %d bytes needed to store MAC addresses",
773 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
777 /* initialize the vfta */
778 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
780 /* initialize the hw strip bitmap*/
781 memset(hwstrip, 0, sizeof(*hwstrip));
783 /* initialize PF if max_vfs not zero */
784 ixgbe_pf_host_init(eth_dev);
786 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
787 /* let hardware know driver is loaded */
788 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
789 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
790 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
791 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
792 IXGBE_WRITE_FLUSH(hw);
794 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
796 "MAC: %d, PHY: %d, SFP+: %d<n",
797 (int) hw->mac.type, (int) hw->phy.type,
798 (int) hw->phy.sfp_type);
800 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
801 (int) hw->mac.type, (int) hw->phy.type);
803 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
804 eth_dev->data->port_id, pci_dev->id.vendor_id,
805 pci_dev->id.device_id);
807 rte_intr_callback_register(&(pci_dev->intr_handle),
808 ixgbe_dev_interrupt_handler, (void *)eth_dev);
810 /* enable uio intr after callback register */
811 rte_intr_enable(&(pci_dev->intr_handle));
813 /* enable support intr */
814 ixgbe_enable_intr(eth_dev);
821 * Negotiate mailbox API version with the PF.
822 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
823 * Then we try to negotiate starting with the most recent one.
824 * If all negotiation attempts fail, then we will proceed with
825 * the default one (ixgbe_mbox_api_10).
828 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
832 /* start with highest supported, proceed down */
833 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
839 i != RTE_DIM(sup_ver) &&
840 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
846 * Virtual Function device init
849 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
850 struct rte_eth_dev *eth_dev)
854 struct rte_pci_device *pci_dev;
855 struct ixgbe_hw *hw =
856 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
857 struct ixgbe_vfta * shadow_vfta =
858 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
859 struct ixgbe_hwstrip *hwstrip =
860 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
862 PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
864 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
865 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
866 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
868 /* for secondary processes, we don't initialise any further as primary
869 * has already done this work. Only check we don't need a different
871 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
872 if (eth_dev->data->scattered_rx)
873 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
877 pci_dev = eth_dev->pci_dev;
879 hw->device_id = pci_dev->id.device_id;
880 hw->vendor_id = pci_dev->id.vendor_id;
881 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
883 /* initialize the vfta */
884 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
886 /* initialize the hw strip bitmap*/
887 memset(hwstrip, 0, sizeof(*hwstrip));
889 /* Initialize the shared code */
890 diag = ixgbe_init_shared_code(hw);
891 if (diag != IXGBE_SUCCESS) {
892 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
896 /* init_mailbox_params */
897 hw->mbx.ops.init_params(hw);
899 /* Disable the interrupts for VF */
900 ixgbevf_intr_disable(hw);
902 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
903 diag = hw->mac.ops.reset_hw(hw);
905 if (diag != IXGBE_SUCCESS) {
906 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
907 RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
908 "\tThe most likely cause of this error is that the VM host\n"
909 "\thas not assigned a valid MAC address to this VF device.\n"
910 "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
911 "\ta possible solution to this problem.\n");
915 /* negotiate mailbox API version to use with the PF. */
916 ixgbevf_negotiate_api(hw);
918 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
919 ixgbevf_get_queues(hw, &tcs, &tc);
921 /* Allocate memory for storing MAC addresses */
922 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
923 hw->mac.num_rar_entries, 0);
924 if (eth_dev->data->mac_addrs == NULL) {
926 "Failed to allocate %u bytes needed to store "
928 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
932 /* Copy the permanent MAC address */
933 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
934 ð_dev->data->mac_addrs[0]);
936 /* reset the hardware with the new settings */
937 diag = hw->mac.ops.start_hw(hw);
943 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
947 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
948 eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
949 "ixgbe_mac_82599_vf");
954 static struct eth_driver rte_ixgbe_pmd = {
956 .name = "rte_ixgbe_pmd",
957 .id_table = pci_id_ixgbe_map,
958 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
960 .eth_dev_init = eth_ixgbe_dev_init,
961 .dev_private_size = sizeof(struct ixgbe_adapter),
965 * virtual function driver struct
967 static struct eth_driver rte_ixgbevf_pmd = {
969 .name = "rte_ixgbevf_pmd",
970 .id_table = pci_id_ixgbevf_map,
971 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
973 .eth_dev_init = eth_ixgbevf_dev_init,
974 .dev_private_size = sizeof(struct ixgbe_adapter),
978 * Driver initialization routine.
979 * Invoked once at EAL init time.
980 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
983 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
985 PMD_INIT_FUNC_TRACE();
987 rte_eth_driver_register(&rte_ixgbe_pmd);
992 * VF Driver initialization routine.
993 * Invoked one at EAL init time.
994 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
997 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
999 DEBUGFUNC("rte_ixgbevf_pmd_init");
1001 rte_eth_driver_register(&rte_ixgbevf_pmd);
1006 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1008 struct ixgbe_hw *hw =
1009 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1010 struct ixgbe_vfta * shadow_vfta =
1011 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1016 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1017 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1018 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1023 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1025 /* update local VFTA copy */
1026 shadow_vfta->vfta[vid_idx] = vfta;
1032 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1035 ixgbe_vlan_hw_strip_enable(dev, queue);
1037 ixgbe_vlan_hw_strip_disable(dev, queue);
1041 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1043 struct ixgbe_hw *hw =
1044 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1046 /* Only the high 16-bits is valid */
1047 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1051 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1053 struct ixgbe_hw *hw =
1054 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1057 PMD_INIT_FUNC_TRACE();
1059 /* Filter Table Disable */
1060 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1061 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1063 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1067 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1069 struct ixgbe_hw *hw =
1070 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1071 struct ixgbe_vfta * shadow_vfta =
1072 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1076 PMD_INIT_FUNC_TRACE();
1078 /* Filter Table Enable */
1079 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1080 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1081 vlnctrl |= IXGBE_VLNCTRL_VFE;
1083 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1085 /* write whatever is in local vfta copy */
1086 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1087 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1091 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1093 struct ixgbe_hwstrip *hwstrip =
1094 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1096 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1100 IXGBE_SET_HWSTRIP(hwstrip, queue);
1102 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1106 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1108 struct ixgbe_hw *hw =
1109 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112 PMD_INIT_FUNC_TRACE();
1114 if (hw->mac.type == ixgbe_mac_82598EB) {
1115 /* No queue level support */
1116 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1120 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1121 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1122 ctrl &= ~IXGBE_RXDCTL_VME;
1123 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1125 /* record those setting for HW strip per queue */
1126 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1130 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1132 struct ixgbe_hw *hw =
1133 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1136 PMD_INIT_FUNC_TRACE();
1138 if (hw->mac.type == ixgbe_mac_82598EB) {
1139 /* No queue level supported */
1140 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1144 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1145 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1146 ctrl |= IXGBE_RXDCTL_VME;
1147 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1149 /* record those setting for HW strip per queue */
1150 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1154 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1156 struct ixgbe_hw *hw =
1157 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1161 PMD_INIT_FUNC_TRACE();
1163 if (hw->mac.type == ixgbe_mac_82598EB) {
1164 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1165 ctrl &= ~IXGBE_VLNCTRL_VME;
1166 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1169 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1170 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1171 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1172 ctrl &= ~IXGBE_RXDCTL_VME;
1173 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1175 /* record those setting for HW strip per queue */
1176 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1182 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1184 struct ixgbe_hw *hw =
1185 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189 PMD_INIT_FUNC_TRACE();
1191 if (hw->mac.type == ixgbe_mac_82598EB) {
1192 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1193 ctrl |= IXGBE_VLNCTRL_VME;
1194 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1197 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1198 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1199 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1200 ctrl |= IXGBE_RXDCTL_VME;
1201 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1203 /* record those setting for HW strip per queue */
1204 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1210 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1212 struct ixgbe_hw *hw =
1213 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1216 PMD_INIT_FUNC_TRACE();
1218 /* DMATXCTRL: Geric Double VLAN Disable */
1219 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1220 ctrl &= ~IXGBE_DMATXCTL_GDV;
1221 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1223 /* CTRL_EXT: Global Double VLAN Disable */
1224 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1225 ctrl &= ~IXGBE_EXTENDED_VLAN;
1226 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1231 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1233 struct ixgbe_hw *hw =
1234 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1237 PMD_INIT_FUNC_TRACE();
1239 /* DMATXCTRL: Geric Double VLAN Enable */
1240 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1241 ctrl |= IXGBE_DMATXCTL_GDV;
1242 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1244 /* CTRL_EXT: Global Double VLAN Enable */
1245 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1246 ctrl |= IXGBE_EXTENDED_VLAN;
1247 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1250 * VET EXT field in the EXVET register = 0x8100 by default
1251 * So no need to change. Same to VT field of DMATXCTL register
1256 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1258 if(mask & ETH_VLAN_STRIP_MASK){
1259 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1260 ixgbe_vlan_hw_strip_enable_all(dev);
1262 ixgbe_vlan_hw_strip_disable_all(dev);
1265 if(mask & ETH_VLAN_FILTER_MASK){
1266 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1267 ixgbe_vlan_hw_filter_enable(dev);
1269 ixgbe_vlan_hw_filter_disable(dev);
1272 if(mask & ETH_VLAN_EXTEND_MASK){
1273 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1274 ixgbe_vlan_hw_extend_enable(dev);
1276 ixgbe_vlan_hw_extend_disable(dev);
1281 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1283 struct ixgbe_hw *hw =
1284 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1286 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1287 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1288 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1292 ixgbe_dev_configure(struct rte_eth_dev *dev)
1294 struct ixgbe_interrupt *intr =
1295 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1297 PMD_INIT_FUNC_TRACE();
1299 /* set flag to update link status after init */
1300 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1306 * Configure device link speed and setup link.
1307 * It returns 0 on success.
1310 ixgbe_dev_start(struct rte_eth_dev *dev)
1312 struct ixgbe_hw *hw =
1313 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1314 int err, link_up = 0, negotiate = 0;
1319 PMD_INIT_FUNC_TRACE();
1321 /* IXGBE devices don't support half duplex */
1322 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1323 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1324 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1325 dev->data->dev_conf.link_duplex,
1326 dev->data->port_id);
1331 hw->adapter_stopped = FALSE;
1332 ixgbe_stop_adapter(hw);
1334 /* reinitialize adapter
1335 * this calls reset and start */
1336 status = ixgbe_pf_reset_hw(hw);
1339 hw->mac.ops.start_hw(hw);
1341 /* configure PF module if SRIOV enabled */
1342 ixgbe_pf_host_configure(dev);
1344 /* initialize transmission unit */
1345 ixgbe_dev_tx_init(dev);
1347 /* This can fail when allocating mbufs for descriptor rings */
1348 err = ixgbe_dev_rx_init(dev);
1350 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1354 ixgbe_dev_rxtx_start(dev);
1356 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1357 err = hw->mac.ops.setup_sfp(hw);
1362 /* Turn on the laser */
1363 ixgbe_enable_tx_laser(hw);
1365 /* Skip link setup if loopback mode is enabled for 82599. */
1366 if (hw->mac.type == ixgbe_mac_82599EB &&
1367 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1368 goto skip_link_setup;
1370 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1373 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1377 switch(dev->data->dev_conf.link_speed) {
1378 case ETH_LINK_SPEED_AUTONEG:
1379 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1380 IXGBE_LINK_SPEED_82599_AUTONEG :
1381 IXGBE_LINK_SPEED_82598_AUTONEG;
1383 case ETH_LINK_SPEED_100:
1385 * Invalid for 82598 but error will be detected by
1386 * ixgbe_setup_link()
1388 speed = IXGBE_LINK_SPEED_100_FULL;
1390 case ETH_LINK_SPEED_1000:
1391 speed = IXGBE_LINK_SPEED_1GB_FULL;
1393 case ETH_LINK_SPEED_10000:
1394 speed = IXGBE_LINK_SPEED_10GB_FULL;
1397 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1398 dev->data->dev_conf.link_speed,
1399 dev->data->port_id);
1403 err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1409 /* check if lsc interrupt is enabled */
1410 if (dev->data->dev_conf.intr_conf.lsc != 0)
1411 ixgbe_dev_lsc_interrupt_setup(dev);
1413 /* resume enabled intr since hw reset */
1414 ixgbe_enable_intr(dev);
1416 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1417 ETH_VLAN_EXTEND_MASK;
1418 ixgbe_vlan_offload_set(dev, mask);
1420 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1421 /* Enable vlan filtering for VMDq */
1422 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1425 /* Configure DCB hw */
1426 ixgbe_configure_dcb(dev);
1428 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1429 err = ixgbe_fdir_configure(dev);
1434 ixgbe_restore_statistics_mapping(dev);
1439 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1440 ixgbe_dev_clear_queues(dev);
1445 * Stop device: disable rx and tx functions to allow for reconfiguring.
1448 ixgbe_dev_stop(struct rte_eth_dev *dev)
1450 struct rte_eth_link link;
1451 struct ixgbe_hw *hw =
1452 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453 struct ixgbe_vf_info *vfinfo =
1454 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1457 PMD_INIT_FUNC_TRACE();
1459 /* disable interrupts */
1460 ixgbe_disable_intr(hw);
1463 ixgbe_pf_reset_hw(hw);
1464 hw->adapter_stopped = FALSE;
1467 ixgbe_stop_adapter(hw);
1469 for (vf = 0; vfinfo != NULL &&
1470 vf < dev->pci_dev->max_vfs; vf++)
1471 vfinfo[vf].clear_to_send = false;
1473 /* Turn off the laser */
1474 ixgbe_disable_tx_laser(hw);
1476 ixgbe_dev_clear_queues(dev);
1478 /* Clear recorded link status */
1479 memset(&link, 0, sizeof(link));
1480 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1484 * Reest and stop device.
1487 ixgbe_dev_close(struct rte_eth_dev *dev)
1489 struct ixgbe_hw *hw =
1490 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1492 PMD_INIT_FUNC_TRACE();
1494 ixgbe_pf_reset_hw(hw);
1496 ixgbe_dev_stop(dev);
1497 hw->adapter_stopped = 1;
1499 ixgbe_disable_pcie_master(hw);
1501 /* reprogram the RAR[0] in case user changed it. */
1502 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1506 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1509 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1511 struct ixgbe_hw *hw =
1512 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1513 struct ixgbe_hw_stats *hw_stats =
1514 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1515 uint32_t bprc, lxon, lxoff, total;
1516 uint64_t total_missed_rx, total_qbrc, total_qprc;
1519 total_missed_rx = 0;
1523 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1524 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1525 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1526 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1528 for (i = 0; i < 8; i++) {
1530 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1531 /* global total per queue */
1532 hw_stats->mpc[i] += mp;
1533 /* Running comprehensive total for stats display */
1534 total_missed_rx += hw_stats->mpc[i];
1535 if (hw->mac.type == ixgbe_mac_82598EB)
1536 hw_stats->rnbc[i] +=
1537 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1538 hw_stats->pxontxc[i] +=
1539 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1540 hw_stats->pxonrxc[i] +=
1541 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1542 hw_stats->pxofftxc[i] +=
1543 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1544 hw_stats->pxoffrxc[i] +=
1545 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1546 hw_stats->pxon2offc[i] +=
1547 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1549 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1550 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1551 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1552 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1553 hw_stats->qbrc[i] +=
1554 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1555 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1556 hw_stats->qbtc[i] +=
1557 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1558 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1560 total_qprc += hw_stats->qprc[i];
1561 total_qbrc += hw_stats->qbrc[i];
1563 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1564 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1565 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1567 /* Note that gprc counts missed packets */
1568 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1570 if (hw->mac.type != ixgbe_mac_82598EB) {
1571 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1572 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1573 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1574 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1575 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1576 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1577 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1578 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1580 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1581 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1582 /* 82598 only has a counter in the high register */
1583 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1584 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1585 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1589 * Workaround: mprc hardware is incorrectly counting
1590 * broadcasts, so for now we subtract those.
1592 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1593 hw_stats->bprc += bprc;
1594 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1595 if (hw->mac.type == ixgbe_mac_82598EB)
1596 hw_stats->mprc -= bprc;
1598 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1599 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1600 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1601 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1602 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1603 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1605 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1606 hw_stats->lxontxc += lxon;
1607 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1608 hw_stats->lxofftxc += lxoff;
1609 total = lxon + lxoff;
1611 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1612 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1613 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1614 hw_stats->gptc -= total;
1615 hw_stats->mptc -= total;
1616 hw_stats->ptc64 -= total;
1617 hw_stats->gotc -= total * ETHER_MIN_LEN;
1619 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1620 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1621 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1622 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1623 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1624 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1625 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1626 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1627 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1628 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1629 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1630 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1631 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1632 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1633 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1634 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1635 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1636 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1637 /* Only read FCOE on 82599 */
1638 if (hw->mac.type != ixgbe_mac_82598EB) {
1639 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1640 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1641 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1642 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1643 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1649 /* Fill out the rte_eth_stats statistics structure */
1650 stats->ipackets = total_qprc;
1651 stats->ibytes = total_qbrc;
1652 stats->opackets = hw_stats->gptc;
1653 stats->obytes = hw_stats->gotc;
1654 stats->imcasts = hw_stats->mprc;
1656 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1657 stats->q_ipackets[i] = hw_stats->qprc[i];
1658 stats->q_opackets[i] = hw_stats->qptc[i];
1659 stats->q_ibytes[i] = hw_stats->qbrc[i];
1660 stats->q_obytes[i] = hw_stats->qbtc[i];
1661 stats->q_errors[i] = hw_stats->qprdc[i];
1665 stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1670 /* XON/XOFF pause frames */
1671 stats->tx_pause_xon = hw_stats->lxontxc;
1672 stats->rx_pause_xon = hw_stats->lxonrxc;
1673 stats->tx_pause_xoff = hw_stats->lxofftxc;
1674 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1676 /* Flow Director Stats registers */
1677 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1678 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1679 stats->fdirmatch = hw_stats->fdirmatch;
1680 stats->fdirmiss = hw_stats->fdirmiss;
1684 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1686 struct ixgbe_hw_stats *stats =
1687 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1689 /* HW registers are cleared on read */
1690 ixgbe_dev_stats_get(dev, NULL);
1692 /* Reset software totals */
1693 memset(stats, 0, sizeof(*stats));
1697 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1699 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1701 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1703 /* Good Rx packet, include VF loopback */
1704 UPDATE_VF_STAT(IXGBE_VFGPRC,
1705 hw_stats->last_vfgprc, hw_stats->vfgprc);
1707 /* Good Rx octets, include VF loopback */
1708 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1709 hw_stats->last_vfgorc, hw_stats->vfgorc);
1711 /* Good Tx packet, include VF loopback */
1712 UPDATE_VF_STAT(IXGBE_VFGPTC,
1713 hw_stats->last_vfgptc, hw_stats->vfgptc);
1715 /* Good Tx octets, include VF loopback */
1716 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1717 hw_stats->last_vfgotc, hw_stats->vfgotc);
1719 /* Rx Multicst Packet */
1720 UPDATE_VF_STAT(IXGBE_VFMPRC,
1721 hw_stats->last_vfmprc, hw_stats->vfmprc);
1726 memset(stats, 0, sizeof(*stats));
1727 stats->ipackets = hw_stats->vfgprc;
1728 stats->ibytes = hw_stats->vfgorc;
1729 stats->opackets = hw_stats->vfgptc;
1730 stats->obytes = hw_stats->vfgotc;
1731 stats->imcasts = hw_stats->vfmprc;
1735 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1737 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1738 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1740 /* Sync HW register to the last stats */
1741 ixgbevf_dev_stats_get(dev, NULL);
1743 /* reset HW current stats*/
1744 hw_stats->vfgprc = 0;
1745 hw_stats->vfgorc = 0;
1746 hw_stats->vfgptc = 0;
1747 hw_stats->vfgotc = 0;
1748 hw_stats->vfmprc = 0;
1753 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1755 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1758 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1759 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1760 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1761 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1762 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1763 dev_info->max_vfs = dev->pci_dev->max_vfs;
1764 if (hw->mac.type == ixgbe_mac_82598EB)
1765 dev_info->max_vmdq_pools = ETH_16_POOLS;
1767 dev_info->max_vmdq_pools = ETH_64_POOLS;
1768 dev_info->rx_offload_capa =
1769 DEV_RX_OFFLOAD_VLAN_STRIP |
1770 DEV_RX_OFFLOAD_IPV4_CKSUM |
1771 DEV_RX_OFFLOAD_UDP_CKSUM |
1772 DEV_RX_OFFLOAD_TCP_CKSUM;
1773 dev_info->tx_offload_capa =
1774 DEV_TX_OFFLOAD_VLAN_INSERT |
1775 DEV_TX_OFFLOAD_IPV4_CKSUM |
1776 DEV_TX_OFFLOAD_UDP_CKSUM |
1777 DEV_TX_OFFLOAD_TCP_CKSUM |
1778 DEV_TX_OFFLOAD_SCTP_CKSUM;
1781 /* return 0 means link status changed, -1 means not changed */
1783 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1785 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786 struct rte_eth_link link, old;
1787 ixgbe_link_speed link_speed;
1791 link.link_status = 0;
1792 link.link_speed = 0;
1793 link.link_duplex = 0;
1794 memset(&old, 0, sizeof(old));
1795 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1797 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1798 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1799 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1801 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1803 link.link_speed = ETH_LINK_SPEED_100;
1804 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1805 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1806 if (link.link_status == old.link_status)
1812 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1813 if (link.link_status == old.link_status)
1817 link.link_status = 1;
1818 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1820 switch (link_speed) {
1822 case IXGBE_LINK_SPEED_UNKNOWN:
1823 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1824 link.link_speed = ETH_LINK_SPEED_100;
1827 case IXGBE_LINK_SPEED_100_FULL:
1828 link.link_speed = ETH_LINK_SPEED_100;
1831 case IXGBE_LINK_SPEED_1GB_FULL:
1832 link.link_speed = ETH_LINK_SPEED_1000;
1835 case IXGBE_LINK_SPEED_10GB_FULL:
1836 link.link_speed = ETH_LINK_SPEED_10000;
1839 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1841 if (link.link_status == old.link_status)
1848 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1850 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1854 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1855 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1859 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1861 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1865 fctrl &= (~IXGBE_FCTRL_UPE);
1866 if (dev->data->all_multicast == 1)
1867 fctrl |= IXGBE_FCTRL_MPE;
1869 fctrl &= (~IXGBE_FCTRL_MPE);
1870 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1874 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1876 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1880 fctrl |= IXGBE_FCTRL_MPE;
1881 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1885 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1887 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890 if (dev->data->promiscuous == 1)
1891 return; /* must remain in all_multicast mode */
1893 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1894 fctrl &= (~IXGBE_FCTRL_MPE);
1895 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1899 * It clears the interrupt causes and enables the interrupt.
1900 * It will be called once only during nic initialized.
1903 * Pointer to struct rte_eth_dev.
1906 * - On success, zero.
1907 * - On failure, a negative value.
1910 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1912 struct ixgbe_interrupt *intr =
1913 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1915 ixgbe_dev_link_status_print(dev);
1916 intr->mask |= IXGBE_EICR_LSC;
1922 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1925 * Pointer to struct rte_eth_dev.
1928 * - On success, zero.
1929 * - On failure, a negative value.
1932 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1935 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936 struct ixgbe_interrupt *intr =
1937 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1939 /* clear all cause mask */
1940 ixgbe_disable_intr(hw);
1942 /* read-on-clear nic registers here */
1943 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1944 PMD_DRV_LOG(INFO, "eicr %x", eicr);
1947 if (eicr & IXGBE_EICR_LSC) {
1948 /* set flag for async link update */
1949 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1952 if (eicr & IXGBE_EICR_MAILBOX)
1953 intr->flags |= IXGBE_FLAG_MAILBOX;
1959 * It gets and then prints the link status.
1962 * Pointer to struct rte_eth_dev.
1965 * - On success, zero.
1966 * - On failure, a negative value.
1969 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1971 struct rte_eth_link link;
1973 memset(&link, 0, sizeof(link));
1974 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1975 if (link.link_status) {
1976 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1977 (int)(dev->data->port_id),
1978 (unsigned)link.link_speed,
1979 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1980 "full-duplex" : "half-duplex");
1982 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1983 (int)(dev->data->port_id));
1985 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1986 dev->pci_dev->addr.domain,
1987 dev->pci_dev->addr.bus,
1988 dev->pci_dev->addr.devid,
1989 dev->pci_dev->addr.function);
1993 * It executes link_update after knowing an interrupt occurred.
1996 * Pointer to struct rte_eth_dev.
1999 * - On success, zero.
2000 * - On failure, a negative value.
2003 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2005 struct ixgbe_interrupt *intr =
2006 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2008 struct rte_eth_link link;
2009 int intr_enable_delay = false;
2011 PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
2013 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2014 ixgbe_pf_mbx_process(dev);
2015 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2018 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2019 /* get the link status before link update, for predicting later */
2020 memset(&link, 0, sizeof(link));
2021 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2023 ixgbe_dev_link_update(dev, 0);
2026 if (!link.link_status)
2027 /* handle it 1 sec later, wait it being stable */
2028 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2029 /* likely to down */
2031 /* handle it 4 sec later, wait it being stable */
2032 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2034 ixgbe_dev_link_status_print(dev);
2036 intr_enable_delay = true;
2039 if (intr_enable_delay) {
2040 if (rte_eal_alarm_set(timeout * 1000,
2041 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2042 PMD_DRV_LOG(ERR, "Error setting alarm");
2044 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2045 ixgbe_enable_intr(dev);
2046 rte_intr_enable(&(dev->pci_dev->intr_handle));
2054 * Interrupt handler which shall be registered for alarm callback for delayed
2055 * handling specific interrupt to wait for the stable nic state. As the
2056 * NIC interrupt state is not stable for ixgbe after link is just down,
2057 * it needs to wait 4 seconds to get the stable status.
2060 * Pointer to interrupt handle.
2062 * The address of parameter (struct rte_eth_dev *) regsitered before.
2068 ixgbe_dev_interrupt_delayed_handler(void *param)
2070 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2071 struct ixgbe_interrupt *intr =
2072 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2073 struct ixgbe_hw *hw =
2074 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2078 if (eicr & IXGBE_EICR_MAILBOX)
2079 ixgbe_pf_mbx_process(dev);
2081 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2082 ixgbe_dev_link_update(dev, 0);
2083 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2084 ixgbe_dev_link_status_print(dev);
2085 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2088 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2089 ixgbe_enable_intr(dev);
2090 rte_intr_enable(&(dev->pci_dev->intr_handle));
2094 * Interrupt handler triggered by NIC for handling
2095 * specific interrupt.
2098 * Pointer to interrupt handle.
2100 * The address of parameter (struct rte_eth_dev *) regsitered before.
2106 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2109 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2110 ixgbe_dev_interrupt_get_status(dev);
2111 ixgbe_dev_interrupt_action(dev);
2115 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2117 struct ixgbe_hw *hw;
2119 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2124 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2126 struct ixgbe_hw *hw;
2128 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2129 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2133 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2135 struct ixgbe_hw *hw;
2137 uint32_t rx_buf_size;
2138 uint32_t max_high_water;
2140 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2147 PMD_INIT_FUNC_TRACE();
2149 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2151 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2154 * At least reserve one Ethernet frame for watermark
2155 * high_water/low_water in kilo bytes for ixgbe
2157 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2158 if ((fc_conf->high_water > max_high_water) ||
2159 (fc_conf->high_water < fc_conf->low_water)) {
2160 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2161 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2165 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2166 hw->fc.pause_time = fc_conf->pause_time;
2167 hw->fc.high_water[0] = fc_conf->high_water;
2168 hw->fc.low_water[0] = fc_conf->low_water;
2169 hw->fc.send_xon = fc_conf->send_xon;
2171 err = ixgbe_fc_enable(hw);
2173 /* Not negotiated is not an error case */
2174 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2176 /* check if we want to forward MAC frames - driver doesn't have native
2177 * capability to do that, so we'll write the registers ourselves */
2179 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2181 /* set or clear MFLCN.PMCF bit depending on configuration */
2182 if (fc_conf->mac_ctrl_frame_fwd != 0)
2183 mflcn |= IXGBE_MFLCN_PMCF;
2185 mflcn &= ~IXGBE_MFLCN_PMCF;
2187 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2188 IXGBE_WRITE_FLUSH(hw);
2193 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2198 * ixgbe_pfc_enable_generic - Enable flow control
2199 * @hw: pointer to hardware structure
2200 * @tc_num: traffic class number
2201 * Enable flow control according to the current settings.
2204 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2207 uint32_t mflcn_reg, fccfg_reg;
2209 uint32_t fcrtl, fcrth;
2213 /* Validate the water mark configuration */
2214 if (!hw->fc.pause_time) {
2215 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2219 /* Low water mark of zero causes XOFF floods */
2220 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2221 /* High/Low water can not be 0 */
2222 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2223 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2224 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2228 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2229 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2230 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2234 /* Negotiate the fc mode to use */
2235 ixgbe_fc_autoneg(hw);
2237 /* Disable any previous flow control settings */
2238 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2239 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2241 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2242 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2244 switch (hw->fc.current_mode) {
2247 * If the count of enabled RX Priority Flow control >1,
2248 * and the TX pause can not be disabled
2251 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2252 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2253 if (reg & IXGBE_FCRTH_FCEN)
2257 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2259 case ixgbe_fc_rx_pause:
2261 * Rx Flow control is enabled and Tx Flow control is
2262 * disabled by software override. Since there really
2263 * isn't a way to advertise that we are capable of RX
2264 * Pause ONLY, we will advertise that we support both
2265 * symmetric and asymmetric Rx PAUSE. Later, we will
2266 * disable the adapter's ability to send PAUSE frames.
2268 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2270 * If the count of enabled RX Priority Flow control >1,
2271 * and the TX pause can not be disabled
2274 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2275 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2276 if (reg & IXGBE_FCRTH_FCEN)
2280 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2282 case ixgbe_fc_tx_pause:
2284 * Tx Flow control is enabled, and Rx Flow control is
2285 * disabled by software override.
2287 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2290 /* Flow control (both Rx and Tx) is enabled by SW override. */
2291 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2292 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2295 DEBUGOUT("Flow control param set incorrectly\n");
2296 ret_val = IXGBE_ERR_CONFIG;
2301 /* Set 802.3x based flow control settings. */
2302 mflcn_reg |= IXGBE_MFLCN_DPF;
2303 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2304 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2306 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2307 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2308 hw->fc.high_water[tc_num]) {
2309 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2310 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2311 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2313 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2315 * In order to prevent Tx hangs when the internal Tx
2316 * switch is enabled we must set the high water mark
2317 * to the maximum FCRTH value. This allows the Tx
2318 * switch to function even under heavy Rx workloads.
2320 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2322 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2324 /* Configure pause time (2 TCs per register) */
2325 reg = hw->fc.pause_time * 0x00010001;
2326 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2327 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2329 /* Configure flow control refresh threshold value */
2330 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2337 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2339 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2342 if(hw->mac.type != ixgbe_mac_82598EB) {
2343 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2349 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2352 uint32_t rx_buf_size;
2353 uint32_t max_high_water;
2355 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2356 struct ixgbe_hw *hw =
2357 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358 struct ixgbe_dcb_config *dcb_config =
2359 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2361 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2368 PMD_INIT_FUNC_TRACE();
2370 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2371 tc_num = map[pfc_conf->priority];
2372 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2373 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2375 * At least reserve one Ethernet frame for watermark
2376 * high_water/low_water in kilo bytes for ixgbe
2378 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2379 if ((pfc_conf->fc.high_water > max_high_water) ||
2380 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2381 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2382 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2386 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2387 hw->fc.pause_time = pfc_conf->fc.pause_time;
2388 hw->fc.send_xon = pfc_conf->fc.send_xon;
2389 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2390 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2392 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2394 /* Not negotiated is not an error case */
2395 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2398 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2403 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2404 struct rte_eth_rss_reta *reta_conf)
2408 struct ixgbe_hw *hw =
2409 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411 PMD_INIT_FUNC_TRACE();
2413 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2414 * 128-entries in 32 registers
2416 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2417 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2418 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2420 mask = (uint8_t)((reta_conf->mask_hi >>
2421 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2425 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2427 for (j = 0; j < 4; j++) {
2428 if (mask & (0x1 << j)) {
2430 reta &= ~(0xFF << 8 * j);
2431 reta |= reta_conf->reta[i + j] << 8*j;
2434 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2442 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2443 struct rte_eth_rss_reta *reta_conf)
2447 struct ixgbe_hw *hw =
2448 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2450 PMD_INIT_FUNC_TRACE();
2452 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2453 * 128-entries in 32 registers
2455 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2456 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2457 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2459 mask = (uint8_t)((reta_conf->mask_hi >>
2460 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2463 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2464 for (j = 0; j < 4; j++) {
2465 if (mask & (0x1 << j))
2466 reta_conf->reta[i + j] =
2467 (uint8_t)((reta >> 8 * j) & 0xFF);
2476 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2477 uint32_t index, uint32_t pool)
2479 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2480 uint32_t enable_addr = 1;
2482 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2486 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2488 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490 ixgbe_clear_rar(hw, index);
2494 * Virtual Function operations
2497 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2499 PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2501 /* Clear interrupt mask to stop from interrupts being generated */
2502 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2504 IXGBE_WRITE_FLUSH(hw);
2508 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2510 struct rte_eth_conf* conf = &dev->data->dev_conf;
2512 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2513 dev->data->port_id);
2516 * VF has no ability to enable/disable HW CRC
2517 * Keep the persistent behavior the same as Host PF
2519 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2520 if (!conf->rxmode.hw_strip_crc) {
2521 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2522 conf->rxmode.hw_strip_crc = 1;
2525 if (conf->rxmode.hw_strip_crc) {
2526 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2527 conf->rxmode.hw_strip_crc = 0;
2535 ixgbevf_dev_start(struct rte_eth_dev *dev)
2537 struct ixgbe_hw *hw =
2538 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2543 hw->mac.ops.reset_hw(hw);
2545 /* negotiate mailbox API version to use with the PF. */
2546 ixgbevf_negotiate_api(hw);
2548 ixgbevf_dev_tx_init(dev);
2550 /* This can fail when allocating mbufs for descriptor rings */
2551 err = ixgbevf_dev_rx_init(dev);
2553 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2554 ixgbe_dev_clear_queues(dev);
2559 ixgbevf_set_vfta_all(dev,1);
2562 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2563 ETH_VLAN_EXTEND_MASK;
2564 ixgbevf_vlan_offload_set(dev, mask);
2566 ixgbevf_dev_rxtx_start(dev);
2572 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2574 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2578 hw->adapter_stopped = TRUE;
2579 ixgbe_stop_adapter(hw);
2582 * Clear what we set, but we still keep shadow_vfta to
2583 * restore after device starts
2585 ixgbevf_set_vfta_all(dev,0);
2587 ixgbe_dev_clear_queues(dev);
2591 ixgbevf_dev_close(struct rte_eth_dev *dev)
2593 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2595 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2599 ixgbevf_dev_stop(dev);
2601 /* reprogram the RAR[0] in case user changed it. */
2602 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2605 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2607 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2608 struct ixgbe_vfta * shadow_vfta =
2609 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2610 int i = 0, j = 0, vfta = 0, mask = 1;
2612 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2613 vfta = shadow_vfta->vfta[i];
2616 for (j = 0; j < 32; j++){
2618 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2627 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2629 struct ixgbe_hw *hw =
2630 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631 struct ixgbe_vfta * shadow_vfta =
2632 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2633 uint32_t vid_idx = 0;
2634 uint32_t vid_bit = 0;
2637 PMD_INIT_FUNC_TRACE();
2639 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2640 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2642 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2645 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2646 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2648 /* Save what we set and retore it after device reset */
2650 shadow_vfta->vfta[vid_idx] |= vid_bit;
2652 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2658 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2660 struct ixgbe_hw *hw =
2661 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2664 PMD_INIT_FUNC_TRACE();
2666 if(queue >= hw->mac.max_rx_queues)
2669 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2671 ctrl |= IXGBE_RXDCTL_VME;
2673 ctrl &= ~IXGBE_RXDCTL_VME;
2674 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2676 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2680 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2682 struct ixgbe_hw *hw =
2683 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2687 /* VF function only support hw strip feature, others are not support */
2688 if(mask & ETH_VLAN_STRIP_MASK){
2689 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2691 for(i=0; i < hw->mac.max_rx_queues; i++)
2692 ixgbevf_vlan_strip_queue_set(dev,i,on);
2697 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2701 /* we only need to do this if VMDq is enabled */
2702 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2703 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2704 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2712 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2714 uint32_t vector = 0;
2715 switch (hw->mac.mc_filter_type) {
2716 case 0: /* use bits [47:36] of the address */
2717 vector = ((uc_addr->addr_bytes[4] >> 4) |
2718 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2720 case 1: /* use bits [46:35] of the address */
2721 vector = ((uc_addr->addr_bytes[4] >> 3) |
2722 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2724 case 2: /* use bits [45:34] of the address */
2725 vector = ((uc_addr->addr_bytes[4] >> 2) |
2726 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2728 case 3: /* use bits [43:32] of the address */
2729 vector = ((uc_addr->addr_bytes[4]) |
2730 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2732 default: /* Invalid mc_filter_type */
2736 /* vector can only be 12-bits or boundary will be exceeded */
2742 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2750 const uint32_t ixgbe_uta_idx_mask = 0x7F;
2751 const uint32_t ixgbe_uta_bit_shift = 5;
2752 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2753 const uint32_t bit1 = 0x1;
2755 struct ixgbe_hw *hw =
2756 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757 struct ixgbe_uta_info *uta_info =
2758 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2760 /* The UTA table only exists on 82599 hardware and newer */
2761 if (hw->mac.type < ixgbe_mac_82599EB)
2764 vector = ixgbe_uta_vector(hw,mac_addr);
2765 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2766 uta_shift = vector & ixgbe_uta_bit_mask;
2768 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2772 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2774 uta_info->uta_in_use++;
2775 reg_val |= (bit1 << uta_shift);
2776 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2778 uta_info->uta_in_use--;
2779 reg_val &= ~(bit1 << uta_shift);
2780 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2783 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2785 if (uta_info->uta_in_use > 0)
2786 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2787 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2789 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2795 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2798 struct ixgbe_hw *hw =
2799 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2800 struct ixgbe_uta_info *uta_info =
2801 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2803 /* The UTA table only exists on 82599 hardware and newer */
2804 if (hw->mac.type < ixgbe_mac_82599EB)
2808 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2809 uta_info->uta_shadow[i] = ~0;
2810 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2813 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2814 uta_info->uta_shadow[i] = 0;
2815 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2822 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2823 uint16_t rx_mask, uint8_t on)
2827 struct ixgbe_hw *hw =
2828 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2829 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2831 if (hw->mac.type == ixgbe_mac_82598EB) {
2832 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2833 " on 82599 hardware and newer\n");
2836 if (ixgbe_vmdq_mode_check(hw) < 0)
2839 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2840 val |= IXGBE_VMOLR_AUPE;
2841 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2842 val |= IXGBE_VMOLR_ROMPE;
2843 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2844 val |= IXGBE_VMOLR_ROPE;
2845 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2846 val |= IXGBE_VMOLR_BAM;
2847 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2848 val |= IXGBE_VMOLR_MPE;
2855 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2861 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2865 const uint8_t bit1 = 0x1;
2867 struct ixgbe_hw *hw =
2868 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870 if (ixgbe_vmdq_mode_check(hw) < 0)
2873 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2874 reg = IXGBE_READ_REG(hw, addr);
2882 IXGBE_WRITE_REG(hw, addr,reg);
2888 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2892 const uint8_t bit1 = 0x1;
2894 struct ixgbe_hw *hw =
2895 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897 if (ixgbe_vmdq_mode_check(hw) < 0)
2900 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2901 reg = IXGBE_READ_REG(hw, addr);
2909 IXGBE_WRITE_REG(hw, addr,reg);
2915 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2916 uint64_t pool_mask, uint8_t vlan_on)
2920 struct ixgbe_hw *hw =
2921 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2923 if (ixgbe_vmdq_mode_check(hw) < 0)
2925 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2926 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2927 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2936 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2937 struct rte_eth_vmdq_mirror_conf *mirror_conf,
2938 uint8_t rule_id, uint8_t on)
2940 uint32_t mr_ctl,vlvf;
2941 uint32_t mp_lsb = 0;
2942 uint32_t mv_msb = 0;
2943 uint32_t mv_lsb = 0;
2944 uint32_t mp_msb = 0;
2947 uint64_t vlan_mask = 0;
2949 const uint8_t pool_mask_offset = 32;
2950 const uint8_t vlan_mask_offset = 32;
2951 const uint8_t dst_pool_offset = 8;
2952 const uint8_t rule_mr_offset = 4;
2953 const uint8_t mirror_rule_mask= 0x0F;
2955 struct ixgbe_mirror_info *mr_info =
2956 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2957 struct ixgbe_hw *hw =
2958 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960 if (ixgbe_vmdq_mode_check(hw) < 0)
2963 /* Check if vlan mask is valid */
2964 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2965 if (mirror_conf->vlan.vlan_mask == 0)
2969 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2970 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2971 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2972 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2973 /* search vlan id related pool vlan filter index */
2974 reg_index = ixgbe_find_vlvf_slot(hw,
2975 mirror_conf->vlan.vlan_id[i]);
2978 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2979 if ((vlvf & IXGBE_VLVF_VIEN) &&
2980 ((vlvf & IXGBE_VLVF_VLANID_MASK)
2981 == mirror_conf->vlan.vlan_id[i]))
2982 vlan_mask |= (1ULL << reg_index);
2989 mv_lsb = vlan_mask & 0xFFFFFFFF;
2990 mv_msb = vlan_mask >> vlan_mask_offset;
2992 mr_info->mr_conf[rule_id].vlan.vlan_mask =
2993 mirror_conf->vlan.vlan_mask;
2994 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2995 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2996 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2997 mirror_conf->vlan.vlan_id[i];
3002 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3003 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3004 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3009 * if enable pool mirror, write related pool mask register,if disable
3010 * pool mirror, clear PFMRVM register
3012 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3014 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3015 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3016 mr_info->mr_conf[rule_id].pool_mask =
3017 mirror_conf->pool_mask;
3022 mr_info->mr_conf[rule_id].pool_mask = 0;
3026 /* read mirror control register and recalculate it */
3027 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3030 mr_ctl |= mirror_conf->rule_type_mask;
3031 mr_ctl &= mirror_rule_mask;
3032 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3034 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3036 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3037 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3039 /* write mirrror control register */
3040 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3042 /* write pool mirrror control register */
3043 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3044 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3045 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3048 /* write VLAN mirrror control register */
3049 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3050 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3051 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3059 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3062 uint32_t lsb_val = 0;
3063 uint32_t msb_val = 0;
3064 const uint8_t rule_mr_offset = 4;
3066 struct ixgbe_hw *hw =
3067 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068 struct ixgbe_mirror_info *mr_info =
3069 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3071 if (ixgbe_vmdq_mode_check(hw) < 0)
3074 memset(&mr_info->mr_conf[rule_id], 0,
3075 sizeof(struct rte_eth_vmdq_mirror_conf));
3077 /* clear PFVMCTL register */
3078 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3080 /* clear pool mask register */
3081 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3082 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3084 /* clear vlan mask register */
3085 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3086 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3092 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3093 __attribute__((unused)) uint32_t index,
3094 __attribute__((unused)) uint32_t pool)
3096 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3099 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3102 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3106 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3108 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109 struct ether_addr *dev_mac_addrs;
3114 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3115 * not support the deletion of a given MAC address.
3116 * Instead, it imposes to delete all MAC addresses, then to add again
3117 * all MAC address with the exception of the one to be deleted.
3119 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3121 /* Add again all MAC addresses, excepted the deleted one. */
3122 dev_mac_addrs = dev->data->mac_addrs;
3123 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3124 /* Skip the deleted MAC address */
3127 diag = ixgbevf_set_uc_addr_vf(hw, 2,
3128 dev_mac_addrs[i].addr_bytes);
3130 PMD_DRV_LOG(ERR, "Adding MAC address failed diag=%d",
3135 static struct rte_driver rte_ixgbe_driver = {
3137 .init = rte_ixgbe_pmd_init,
3140 static struct rte_driver rte_ixgbevf_driver = {
3142 .init = rte_ixgbevf_pmd_init,
3145 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3146 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);