lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_tailq.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61
  62 #include "ixgbe_logs.h"
  63 #include "ixgbe/ixgbe_api.h"
  64 #include "ixgbe/ixgbe_vf.h"
  65 #include "ixgbe/ixgbe_common.h"
  66 #include "ixgbe_ethdev.h"
  67 #include "ixgbe_bypass.h"
  68
  69 /*
  70  * High threshold controlling when to start sending XOFF frames. Must be at
  71  * least 8 bytes less than receive packet buffer size. This value is in units
  72  * of 1024 bytes.
  73  */
  74 #define IXGBE_FC_HI    0x80
  75
  76 /*
  77  * Low threshold controlling when to start sending XON frames. This value is
  78  * in units of 1024 bytes.
  79  */
  80 #define IXGBE_FC_LO    0x40
  81
  82 /* Timer value included in XOFF frames. */
  83 #define IXGBE_FC_PAUSE 0x680
  84
  85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  86 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  87 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  88
  89
  90 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  91
  92 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  93
  94 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
  95                 struct rte_eth_dev *eth_dev);
  96 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
  97 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
  98 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
  99 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 100 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 101 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 102 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 104 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 105                                 int wait_to_complete);
 106 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_stats *stats);
 108 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 109 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 110                                              uint16_t queue_id,
 111                                              uint8_t stat_idx,
 112                                              uint8_t is_rx);
 113 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_dev_info *dev_info);
 115 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 116                 uint16_t vlan_id, int on);
 117 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 118 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 119                 uint16_t queue, bool on);
 120 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 121                 int on);
 122 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 123 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 124 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 125 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 126 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 127
 128 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 129 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 130 static int  ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 131                 struct rte_eth_fc_conf *fc_conf);
 132 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 133                 struct rte_eth_pfc_conf *pfc_conf);
 134 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 135                 struct rte_eth_rss_reta *reta_conf);
 136 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 137                 struct rte_eth_rss_reta *reta_conf);
 138 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 139 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 140 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 141 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 143                 void *param);
 144 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 145 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 146                 uint32_t index, uint32_t pool);
 147 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 148 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 149
 150 /* For Virtual Function support */
 151 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 152                 struct rte_eth_dev *eth_dev);
 153 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 154 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 155 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 156 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 157 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 158 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 159                 struct rte_eth_stats *stats);
 160 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 161 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 162                 uint16_t vlan_id, int on);
 163 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 164                 uint16_t queue, int on);
 165 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 166 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 167
 168 /* For Eth VMDQ APIs support */
 169 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 170                 ether_addr* mac_addr,uint8_t on);
 171 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 172 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 173                 uint16_t rx_mask, uint8_t on);
 174 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 175 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 176 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 177                 uint64_t pool_mask,uint8_t vlan_on);
 178 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 179                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 180                 uint8_t rule_id, uint8_t on);
 181 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 182                 uint8_t rule_id);
 183
 184 /*
 185  * Define VF Stats MACRO for Non "cleared on read" register
 186  */
 187 #define UPDATE_VF_STAT(reg, last, cur)                          \
 188 {                                                               \
 189         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 190         cur += latest - last;                                   \
 191         last = latest;                                          \
 192 }
 193
 194 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 195 {                                                                \
 196         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 197         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 198         u64 latest = ((new_msb << 32) | new_lsb);                \
 199         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 200         last = latest;                                           \
 201 }
 202
 203 #define IXGBE_SET_HWSTRIP(h, q) do{\
 204                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 205                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 206                 (h)->bitmap[idx] |= 1 << bit;\
 207         }while(0)
 208
 209 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 210                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 211                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 212                 (h)->bitmap[idx] &= ~(1 << bit);\
 213         }while(0)
 214
 215 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 216                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 217                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 218                 (r) = (h)->bitmap[idx] >> bit & 1;\
 219         }while(0)
 220
 221 /*
 222  * The set of PCI devices this driver supports
 223  */
 224 static struct rte_pci_id pci_id_ixgbe_map[] = {
 225
 226 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 227 #include "rte_pci_dev_ids.h"
 228
 229 { .vendor_id = 0, /* sentinel */ },
 230 };
 231
 232
 233 /*
 234  * The set of PCI devices this driver supports (for 82599 VF)
 235  */
 236 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 237
 238 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 239 #include "rte_pci_dev_ids.h"
 240 { .vendor_id = 0, /* sentinel */ },
 241
 242 };
 243
 244 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 245         .dev_configure        = ixgbe_dev_configure,
 246         .dev_start            = ixgbe_dev_start,
 247         .dev_stop             = ixgbe_dev_stop,
 248         .dev_close            = ixgbe_dev_close,
 249         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 250         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 251         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 252         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 253         .link_update          = ixgbe_dev_link_update,
 254         .stats_get            = ixgbe_dev_stats_get,
 255         .stats_reset          = ixgbe_dev_stats_reset,
 256         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 257         .dev_infos_get        = ixgbe_dev_info_get,
 258         .vlan_filter_set      = ixgbe_vlan_filter_set,
 259         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 260         .vlan_offload_set     = ixgbe_vlan_offload_set,
 261         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 262         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 263         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 264         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 265         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 266         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 267         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 268         .dev_led_on           = ixgbe_dev_led_on,
 269         .dev_led_off          = ixgbe_dev_led_off,
 270         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 271         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 272         .mac_addr_add         = ixgbe_add_rar,
 273         .mac_addr_remove      = ixgbe_remove_rar,
 274         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 275         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 276         .mirror_rule_set        = ixgbe_mirror_rule_set,
 277         .mirror_rule_reset      = ixgbe_mirror_rule_reset,
 278         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 279         .set_vf_rx            = ixgbe_set_pool_rx,
 280         .set_vf_tx            = ixgbe_set_pool_tx,
 281         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 282         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 283         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 284         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 285         .fdir_infos_get               = ixgbe_fdir_info_get,
 286         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 287         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 288         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 289         .fdir_set_masks               = ixgbe_fdir_set_masks,
 290         .reta_update          = ixgbe_dev_rss_reta_update,
 291         .reta_query           = ixgbe_dev_rss_reta_query,
 292 #ifdef RTE_NIC_BYPASS
 293         .bypass_init          = ixgbe_bypass_init,
 294         .bypass_state_set     = ixgbe_bypass_state_store,
 295         .bypass_state_show    = ixgbe_bypass_state_show,
 296         .bypass_event_set     = ixgbe_bypass_event_store,
 297         .bypass_event_show    = ixgbe_bypass_event_show,
 298         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 299         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 300         .bypass_ver_show      = ixgbe_bypass_ver_show,
 301         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 302 #endif /* RTE_NIC_BYPASS */
 303 };
 304
 305 /*
 306  * dev_ops for virtual function, bare necessities for basic vf
 307  * operation have been implemented
 308  */
 309 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 310
 311         .dev_configure        = ixgbevf_dev_configure,
 312         .dev_start            = ixgbevf_dev_start,
 313         .dev_stop             = ixgbevf_dev_stop,
 314         .link_update          = ixgbe_dev_link_update,
 315         .stats_get            = ixgbevf_dev_stats_get,
 316         .stats_reset          = ixgbevf_dev_stats_reset,
 317         .dev_close            = ixgbevf_dev_close,
 318         .dev_infos_get        = ixgbe_dev_info_get,
 319         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 320         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 321         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 322         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 323         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 324         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 325         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 326 };
 327
 328 /**
 329  * Atomically reads the link status information from global
 330  * structure rte_eth_dev.
 331  *
 332  * @param dev
 333  *   - Pointer to the structure rte_eth_dev to read from.
 334  *   - Pointer to the buffer to be saved with the link status.
 335  *
 336  * @return
 337  *   - On success, zero.
 338  *   - On failure, negative value.
 339  */
 340 static inline int
 341 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 342                                 struct rte_eth_link *link)
 343 {
 344         struct rte_eth_link *dst = link;
 345         struct rte_eth_link *src = &(dev->data->dev_link);
 346
 347         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 348                                         *(uint64_t *)src) == 0)
 349                 return -1;
 350
 351         return 0;
 352 }
 353
 354 /**
 355  * Atomically writes the link status information into global
 356  * structure rte_eth_dev.
 357  *
 358  * @param dev
 359  *   - Pointer to the structure rte_eth_dev to read from.
 360  *   - Pointer to the buffer to be saved with the link status.
 361  *
 362  * @return
 363  *   - On success, zero.
 364  *   - On failure, negative value.
 365  */
 366 static inline int
 367 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 368                                 struct rte_eth_link *link)
 369 {
 370         struct rte_eth_link *dst = &(dev->data->dev_link);
 371         struct rte_eth_link *src = link;
 372
 373         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 374                                         *(uint64_t *)src) == 0)
 375                 return -1;
 376
 377         return 0;
 378 }
 379
 380 /*
 381  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 382  */
 383 static inline int
 384 ixgbe_is_sfp(struct ixgbe_hw *hw)
 385 {
 386         switch (hw->phy.type) {
 387         case ixgbe_phy_sfp_avago:
 388         case ixgbe_phy_sfp_ftl:
 389         case ixgbe_phy_sfp_intel:
 390         case ixgbe_phy_sfp_unknown:
 391         case ixgbe_phy_sfp_passive_tyco:
 392         case ixgbe_phy_sfp_passive_unknown:
 393                 return 1;
 394         default:
 395                 return 0;
 396         }
 397 }
 398
 399 static inline int32_t
 400 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 401 {
 402         uint32_t ctrl_ext;
 403         int32_t status;
 404
 405         status = ixgbe_reset_hw(hw);
 406
 407         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 408         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 409         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 410         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 411         IXGBE_WRITE_FLUSH(hw);
 412
 413         return status;
 414 }
 415
 416 static inline void
 417 ixgbe_enable_intr(struct rte_eth_dev *dev)
 418 {
 419         struct ixgbe_interrupt *intr =
 420                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 421         struct ixgbe_hw *hw =
 422                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 423
 424         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 425         IXGBE_WRITE_FLUSH(hw);
 426 }
 427
 428 /*
 429  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 430  */
 431 static void
 432 ixgbe_disable_intr(struct ixgbe_hw *hw)
 433 {
 434         PMD_INIT_FUNC_TRACE();
 435
 436         if (hw->mac.type == ixgbe_mac_82598EB) {
 437                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 438         } else {
 439                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 440                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 441                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 442         }
 443         IXGBE_WRITE_FLUSH(hw);
 444 }
 445
 446 /*
 447  * This function resets queue statistics mapping registers.
 448  * From Niantic datasheet, Initialization of Statistics section:
 449  * "...if software requires the queue counters, the RQSMR and TQSM registers
 450  * must be re-programmed following a device reset.
 451  */
 452 static void
 453 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 454 {
 455         uint32_t i;
 456
 457         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 458                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 459                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 460         }
 461 }
 462
 463
 464 static int
 465 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 466                                   uint16_t queue_id,
 467                                   uint8_t stat_idx,
 468                                   uint8_t is_rx)
 469 {
 470 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 471 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 472 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 473
 474         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 475         struct ixgbe_stat_mapping_registers *stat_mappings =
 476                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 477         uint32_t qsmr_mask = 0;
 478         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 479         uint32_t q_map;
 480         uint8_t n, offset;
 481
 482         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 483                 return -ENOSYS;
 484
 485         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 486                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 487
 488         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 489         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 490                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 491                 return -EIO;
 492         }
 493         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 494
 495         /* Now clear any previous stat_idx set */
 496         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 497         if (!is_rx)
 498                 stat_mappings->tqsm[n] &= ~clearing_mask;
 499         else
 500                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 501
 502         q_map = (uint32_t)stat_idx;
 503         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 504         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 505         if (!is_rx)
 506                 stat_mappings->tqsm[n] |= qsmr_mask;
 507         else
 508                 stat_mappings->rqsmr[n] |= qsmr_mask;
 509
 510         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 511                      "%s[%d] = 0x%08x\n",
 512                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 513                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 514
 515         /* Now write the mapping in the appropriate register */
 516         if (is_rx) {
 517                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 518                              stat_mappings->rqsmr[n], n);
 519                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 520         }
 521         else {
 522                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 523                              stat_mappings->tqsm[n], n);
 524                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 525         }
 526         return 0;
 527 }
 528
 529 static void
 530 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 531 {
 532         struct ixgbe_stat_mapping_registers *stat_mappings =
 533                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 535         int i;
 536
 537         /* write whatever was in stat mapping table to the NIC */
 538         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 539                 /* rx */
 540                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 541
 542                 /* tx */
 543                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 544         }
 545 }
 546
 547 static void
 548 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 549 {
 550         uint8_t i;
 551         struct ixgbe_dcb_tc_config *tc;
 552         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 553
 554         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 555         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 556         for (i = 0; i < dcb_max_tc; i++) {
 557                 tc = &dcb_config->tc_config[i];
 558                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 559                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 560                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 561                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 562                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 563                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 564                 tc->pfc = ixgbe_dcb_pfc_disabled;
 565         }
 566
 567         /* Initialize default user to priority mapping, UPx->TC0 */
 568         tc = &dcb_config->tc_config[0];
 569         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 570         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 571         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 572                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 573                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 574         }
 575         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 576         dcb_config->pfc_mode_enable = false;
 577         dcb_config->vt_mode = true;
 578         dcb_config->round_robin_enable = false;
 579         /* support all DCB capabilities in 82599 */
 580         dcb_config->support.capabilities = 0xFF;
 581
 582         /*we only support 4 Tcs for X540*/
 583         if (hw->mac.type == ixgbe_mac_X540) {
 584                 dcb_config->num_tcs.pg_tcs = 4;
 585                 dcb_config->num_tcs.pfc_tcs = 4;
 586         }
 587 }
 588
 589 /*
 590  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 591  * It returns 0 on success.
 592  */
 593 static int
 594 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 595                      struct rte_eth_dev *eth_dev)
 596 {
 597         struct rte_pci_device *pci_dev;
 598         struct ixgbe_hw *hw =
 599                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 600         struct ixgbe_vfta * shadow_vfta =
 601                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 602         struct ixgbe_hwstrip *hwstrip =
 603                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 604         struct ixgbe_dcb_config *dcb_config =
 605                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 606         uint32_t ctrl_ext;
 607         uint16_t csum;
 608         int diag, i;
 609
 610         PMD_INIT_FUNC_TRACE();
 611
 612         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 613         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 614         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 615
 616         /* for secondary processes, we don't initialise any further as primary
 617          * has already done this work. Only check we don't need a different
 618          * RX function */
 619         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 620                 if (eth_dev->data->scattered_rx)
 621                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 622                 return 0;
 623         }
 624         pci_dev = eth_dev->pci_dev;
 625
 626         /* Vendor and Device ID need to be set before init of shared code */
 627         hw->device_id = pci_dev->id.device_id;
 628         hw->vendor_id = pci_dev->id.vendor_id;
 629         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 630 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 631         hw->allow_unsupported_sfp = 1;
 632 #endif
 633
 634         /* Initialize the shared code */
 635 #ifdef RTE_NIC_BYPASS
 636         diag = ixgbe_bypass_init_shared_code(hw);
 637 #else
 638         diag = ixgbe_init_shared_code(hw);
 639 #endif /* RTE_NIC_BYPASS */
 640
 641         if (diag != IXGBE_SUCCESS) {
 642                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 643                 return -EIO;
 644         }
 645
 646         /* Initialize DCB configuration*/
 647         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 648         ixgbe_dcb_init(hw,dcb_config);
 649         /* Get Hardware Flow Control setting */
 650         hw->fc.requested_mode = ixgbe_fc_full;
 651         hw->fc.current_mode = ixgbe_fc_full;
 652         hw->fc.pause_time = IXGBE_FC_PAUSE;
 653         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 654                 hw->fc.low_water[i] = IXGBE_FC_LO;
 655                 hw->fc.high_water[i] = IXGBE_FC_HI;
 656         }
 657         hw->fc.send_xon = 1;
 658
 659         /* Make sure we have a good EEPROM before we read from it */
 660         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 661         if (diag != IXGBE_SUCCESS) {
 662                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 663                 return -EIO;
 664         }
 665
 666 #ifdef RTE_NIC_BYPASS
 667         diag = ixgbe_bypass_init_hw(hw);
 668 #else
 669         diag = ixgbe_init_hw(hw);
 670 #endif /* RTE_NIC_BYPASS */
 671
 672         /*
 673          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 674          * is called too soon after the kernel driver unbinding/binding occurs.
 675          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 676          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 677          * also called. See ixgbe_identify_phy_82599(). The reason for the
 678          * failure is not known, and only occuts when virtualisation features
 679          * are disabled in the bios. A delay of 100ms  was found to be enough by
 680          * trial-and-error, and is doubled to be safe.
 681          */
 682         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 683                 rte_delay_ms(200);
 684                 diag = ixgbe_init_hw(hw);
 685         }
 686
 687         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 688                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 689                     "LOM.  Please be aware there may be issues associated "
 690                     "with your hardware.\n If you are experiencing problems "
 691                     "please contact your Intel or hardware representative "
 692                     "who provided you with this hardware.\n");
 693         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 694                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 695         if (diag) {
 696                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 697                 return -EIO;
 698         }
 699
 700         /* disable interrupt */
 701         ixgbe_disable_intr(hw);
 702
 703         /* pick up the PCI bus settings for reporting later */
 704         ixgbe_get_bus_info(hw);
 705
 706         /* reset mappings for queue statistics hw counters*/
 707         ixgbe_reset_qstat_mappings(hw);
 708
 709         /* Allocate memory for storing MAC addresses */
 710         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 711                         hw->mac.num_rar_entries, 0);
 712         if (eth_dev->data->mac_addrs == NULL) {
 713                 PMD_INIT_LOG(ERR,
 714                         "Failed to allocate %u bytes needed to store "
 715                         "MAC addresses",
 716                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 717                 return -ENOMEM;
 718         }
 719         /* Copy the permanent MAC address */
 720         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 721                         &eth_dev->data->mac_addrs[0]);
 722
 723         /* Allocate memory for storing hash filter MAC addresses */
 724         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 725                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 726         if (eth_dev->data->hash_mac_addrs == NULL) {
 727                 PMD_INIT_LOG(ERR,
 728                         "Failed to allocate %d bytes needed to store MAC addresses",
 729                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 730                 return -ENOMEM;
 731         }
 732
 733         /* initialize the vfta */
 734         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 735
 736         /* initialize the hw strip bitmap*/
 737         memset(hwstrip, 0, sizeof(*hwstrip));
 738
 739         /* initialize PF if max_vfs not zero */
 740         ixgbe_pf_host_init(eth_dev);
 741
 742         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 743         /* let hardware know driver is loaded */
 744         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 745         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 746         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 747         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 748         IXGBE_WRITE_FLUSH(hw);
 749
 750         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 751                 PMD_INIT_LOG(DEBUG,
 752                              "MAC: %d, PHY: %d, SFP+: %d<n",
 753                              (int) hw->mac.type, (int) hw->phy.type,
 754                              (int) hw->phy.sfp_type);
 755         else
 756                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 757                              (int) hw->mac.type, (int) hw->phy.type);
 758
 759         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 760                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 761                         pci_dev->id.device_id);
 762
 763         rte_intr_callback_register(&(pci_dev->intr_handle),
 764                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 765
 766         /* enable uio intr after callback register */
 767         rte_intr_enable(&(pci_dev->intr_handle));
 768
 769         /* enable support intr */
 770         ixgbe_enable_intr(eth_dev);
 771
 772         return 0;
 773 }
 774
 775 static void ixgbevf_get_queue_num(struct ixgbe_hw *hw)
 776 {
 777         /* Traffic classes are not supported by now */
 778         unsigned int tcs, tc;
 779
 780         /*
 781          * Must let PF know we are at mailbox API version 1.1.
 782          * Otherwise PF won't answer properly.
 783          * In case that PF fails to provide Rx/Tx queue number,
 784          * max_tx_queues and max_rx_queues remain to be 1.
 785          */
 786         if (!ixgbevf_negotiate_api_version(hw, ixgbe_mbox_api_11))
 787                 ixgbevf_get_queues(hw, &tcs, &tc);
 788 }
 789
 790 /*
 791  * Virtual Function device init
 792  */
 793 static int
 794 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 795                      struct rte_eth_dev *eth_dev)
 796 {
 797         struct rte_pci_device *pci_dev;
 798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 799         int diag;
 800         struct ixgbe_vfta * shadow_vfta =
 801                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 802         struct ixgbe_hwstrip *hwstrip =
 803                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 804
 805         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 806
 807         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 808         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 809         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 810
 811         /* for secondary processes, we don't initialise any further as primary
 812          * has already done this work. Only check we don't need a different
 813          * RX function */
 814         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 815                 if (eth_dev->data->scattered_rx)
 816                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 817                 return 0;
 818         }
 819
 820         pci_dev = eth_dev->pci_dev;
 821
 822         hw->device_id = pci_dev->id.device_id;
 823         hw->vendor_id = pci_dev->id.vendor_id;
 824         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 825
 826         /* initialize the vfta */
 827         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 828
 829         /* initialize the hw strip bitmap*/
 830         memset(hwstrip, 0, sizeof(*hwstrip));
 831
 832         /* Initialize the shared code */
 833         diag = ixgbe_init_shared_code(hw);
 834         if (diag != IXGBE_SUCCESS) {
 835                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 836                 return -EIO;
 837         }
 838
 839         /* init_mailbox_params */
 840         hw->mbx.ops.init_params(hw);
 841
 842         /* Disable the interrupts for VF */
 843         ixgbevf_intr_disable(hw);
 844
 845         hw->mac.num_rar_entries = hw->mac.max_rx_queues;
 846         diag = hw->mac.ops.reset_hw(hw);
 847
 848         if (diag != IXGBE_SUCCESS) {
 849                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 850                         RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
 851                                         "\tThe most likely cause of this error is that the VM host\n"
 852                                         "\thas not assigned a valid MAC address to this VF device.\n"
 853                                         "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
 854                                         "\ta possible solution to this problem.\n");
 855                 return (diag);
 856         }
 857
 858         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
 859         ixgbevf_get_queue_num(hw);
 860
 861         /* Allocate memory for storing MAC addresses */
 862         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 863                         hw->mac.num_rar_entries, 0);
 864         if (eth_dev->data->mac_addrs == NULL) {
 865                 PMD_INIT_LOG(ERR,
 866                         "Failed to allocate %u bytes needed to store "
 867                         "MAC addresses",
 868                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 869                 return -ENOMEM;
 870         }
 871
 872         /* Copy the permanent MAC address */
 873         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 874                         &eth_dev->data->mac_addrs[0]);
 875
 876         /* reset the hardware with the new settings */
 877         diag = hw->mac.ops.start_hw(hw);
 878         switch (diag) {
 879                 case  0:
 880                         break;
 881
 882                 default:
 883                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 884                         return (-EIO);
 885         }
 886
 887         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
 888                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
 889                          "ixgbe_mac_82599_vf");
 890
 891         return 0;
 892 }
 893
 894 static struct eth_driver rte_ixgbe_pmd = {
 895         {
 896                 .name = "rte_ixgbe_pmd",
 897                 .id_table = pci_id_ixgbe_map,
 898 #ifdef RTE_EAL_UNBIND_PORTS
 899                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 900 #endif
 901         },
 902         .eth_dev_init = eth_ixgbe_dev_init,
 903         .dev_private_size = sizeof(struct ixgbe_adapter),
 904 };
 905
 906 /*
 907  * virtual function driver struct
 908  */
 909 static struct eth_driver rte_ixgbevf_pmd = {
 910         {
 911                 .name = "rte_ixgbevf_pmd",
 912                 .id_table = pci_id_ixgbevf_map,
 913 #ifdef RTE_EAL_UNBIND_PORTS
 914                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 915 #endif
 916         },
 917         .eth_dev_init = eth_ixgbevf_dev_init,
 918         .dev_private_size = sizeof(struct ixgbe_adapter),
 919 };
 920
 921 /*
 922  * Driver initialization routine.
 923  * Invoked once at EAL init time.
 924  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 925  */
 926 int
 927 rte_ixgbe_pmd_init(void)
 928 {
 929         PMD_INIT_FUNC_TRACE();
 930
 931         rte_eth_driver_register(&rte_ixgbe_pmd);
 932         return 0;
 933 }
 934
 935 /*
 936  * VF Driver initialization routine.
 937  * Invoked one at EAL init time.
 938  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
 939  */
 940 int
 941 rte_ixgbevf_pmd_init(void)
 942 {
 943         DEBUGFUNC("rte_ixgbevf_pmd_init");
 944
 945         rte_eth_driver_register(&rte_ixgbevf_pmd);
 946         return (0);
 947 }
 948
 949 static int
 950 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 951 {
 952         struct ixgbe_hw *hw =
 953                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 954         struct ixgbe_vfta * shadow_vfta =
 955                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 956         uint32_t vfta;
 957         uint32_t vid_idx;
 958         uint32_t vid_bit;
 959
 960         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
 961         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
 962         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
 963         if (on)
 964                 vfta |= vid_bit;
 965         else
 966                 vfta &= ~vid_bit;
 967         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
 968
 969         /* update local VFTA copy */
 970         shadow_vfta->vfta[vid_idx] = vfta;
 971
 972         return 0;
 973 }
 974
 975 static void
 976 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 977 {
 978         if (on)
 979                 ixgbe_vlan_hw_strip_enable(dev, queue);
 980         else
 981                 ixgbe_vlan_hw_strip_disable(dev, queue);
 982 }
 983
 984 static void
 985 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
 986 {
 987         struct ixgbe_hw *hw =
 988                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 989
 990         /* Only the high 16-bits is valid */
 991         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
 992 }
 993
 994 void
 995 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
 996 {
 997         struct ixgbe_hw *hw =
 998                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 999         uint32_t vlnctrl;
1000
1001         PMD_INIT_FUNC_TRACE();
1002
1003         /* Filter Table Disable */
1004         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1005         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1006
1007         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1008 }
1009
1010 void
1011 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1012 {
1013         struct ixgbe_hw *hw =
1014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1015         struct ixgbe_vfta * shadow_vfta =
1016                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1017         uint32_t vlnctrl;
1018         uint16_t i;
1019
1020         PMD_INIT_FUNC_TRACE();
1021
1022         /* Filter Table Enable */
1023         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1024         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1025         vlnctrl |= IXGBE_VLNCTRL_VFE;
1026
1027         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1028
1029         /* write whatever is in local vfta copy */
1030         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1031                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1032 }
1033
1034 static void
1035 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1036 {
1037         struct ixgbe_hwstrip *hwstrip =
1038                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1039
1040         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1041                 return;
1042
1043         if (on)
1044                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1045         else
1046                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1047 }
1048
1049 static void
1050 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1051 {
1052         struct ixgbe_hw *hw =
1053                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1054         uint32_t ctrl;
1055
1056         PMD_INIT_FUNC_TRACE();
1057
1058         if (hw->mac.type == ixgbe_mac_82598EB) {
1059                 /* No queue level support */
1060                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1061                 return;
1062         }
1063         else {
1064                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1065                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1066                 ctrl &= ~IXGBE_RXDCTL_VME;
1067                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1068         }
1069         /* record those setting for HW strip per queue */
1070         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1071 }
1072
1073 static void
1074 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1075 {
1076         struct ixgbe_hw *hw =
1077                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1078         uint32_t ctrl;
1079
1080         PMD_INIT_FUNC_TRACE();
1081
1082         if (hw->mac.type == ixgbe_mac_82598EB) {
1083                 /* No queue level supported */
1084                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1085                 return;
1086         }
1087         else {
1088                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1089                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1090                 ctrl |= IXGBE_RXDCTL_VME;
1091                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1092         }
1093         /* record those setting for HW strip per queue */
1094         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1095 }
1096
1097 void
1098 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1099 {
1100         struct ixgbe_hw *hw =
1101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1102         uint32_t ctrl;
1103         uint16_t i;
1104
1105         PMD_INIT_FUNC_TRACE();
1106
1107         if (hw->mac.type == ixgbe_mac_82598EB) {
1108                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1109                 ctrl &= ~IXGBE_VLNCTRL_VME;
1110                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1111         }
1112         else {
1113                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1114                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1115                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1116                         ctrl &= ~IXGBE_RXDCTL_VME;
1117                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1118
1119                         /* record those setting for HW strip per queue */
1120                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1121                 }
1122         }
1123 }
1124
1125 void
1126 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1127 {
1128         struct ixgbe_hw *hw =
1129                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130         uint32_t ctrl;
1131         uint16_t i;
1132
1133         PMD_INIT_FUNC_TRACE();
1134
1135         if (hw->mac.type == ixgbe_mac_82598EB) {
1136                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1137                 ctrl |= IXGBE_VLNCTRL_VME;
1138                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1139         }
1140         else {
1141                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1142                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1143                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1144                         ctrl |= IXGBE_RXDCTL_VME;
1145                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1146
1147                         /* record those setting for HW strip per queue */
1148                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1149                 }
1150         }
1151 }
1152
1153 static void
1154 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1155 {
1156         struct ixgbe_hw *hw =
1157                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1158         uint32_t ctrl;
1159
1160         PMD_INIT_FUNC_TRACE();
1161
1162         /* DMATXCTRL: Geric Double VLAN Disable */
1163         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1164         ctrl &= ~IXGBE_DMATXCTL_GDV;
1165         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1166
1167         /* CTRL_EXT: Global Double VLAN Disable */
1168         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1169         ctrl &= ~IXGBE_EXTENDED_VLAN;
1170         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1171
1172 }
1173
1174 static void
1175 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1176 {
1177         struct ixgbe_hw *hw =
1178                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1179         uint32_t ctrl;
1180
1181         PMD_INIT_FUNC_TRACE();
1182
1183         /* DMATXCTRL: Geric Double VLAN Enable */
1184         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1185         ctrl |= IXGBE_DMATXCTL_GDV;
1186         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1187
1188         /* CTRL_EXT: Global Double VLAN Enable */
1189         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1190         ctrl |= IXGBE_EXTENDED_VLAN;
1191         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1192
1193         /*
1194          * VET EXT field in the EXVET register = 0x8100 by default
1195          * So no need to change. Same to VT field of DMATXCTL register
1196          */
1197 }
1198
1199 static void
1200 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1201 {
1202         if(mask & ETH_VLAN_STRIP_MASK){
1203                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1204                         ixgbe_vlan_hw_strip_enable_all(dev);
1205                 else
1206                         ixgbe_vlan_hw_strip_disable_all(dev);
1207         }
1208
1209         if(mask & ETH_VLAN_FILTER_MASK){
1210                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1211                         ixgbe_vlan_hw_filter_enable(dev);
1212                 else
1213                         ixgbe_vlan_hw_filter_disable(dev);
1214         }
1215
1216         if(mask & ETH_VLAN_EXTEND_MASK){
1217                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1218                         ixgbe_vlan_hw_extend_enable(dev);
1219                 else
1220                         ixgbe_vlan_hw_extend_disable(dev);
1221         }
1222 }
1223
1224 static void
1225 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1226 {
1227         struct ixgbe_hw *hw =
1228                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1229         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1230         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1231         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1232         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1233 }
1234
1235 static int
1236 ixgbe_dev_configure(struct rte_eth_dev *dev)
1237 {
1238         struct ixgbe_interrupt *intr =
1239                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1240
1241         PMD_INIT_FUNC_TRACE();
1242
1243         /* set flag to update link status after init */
1244         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1245
1246         return 0;
1247 }
1248
1249 /*
1250  * Configure device link speed and setup link.
1251  * It returns 0 on success.
1252  */
1253 static int
1254 ixgbe_dev_start(struct rte_eth_dev *dev)
1255 {
1256         struct ixgbe_hw *hw =
1257                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1258         int err, link_up = 0, negotiate = 0;
1259         uint32_t speed = 0;
1260         int mask = 0;
1261         int status;
1262
1263         PMD_INIT_FUNC_TRACE();
1264
1265         /* IXGBE devices don't support half duplex */
1266         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1267                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1268                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1269                                 dev->data->dev_conf.link_duplex,
1270                                 dev->data->port_id);
1271                 return -EINVAL;
1272         }
1273
1274         /* stop adapter */
1275         hw->adapter_stopped = FALSE;
1276         ixgbe_stop_adapter(hw);
1277
1278         /* reinitialize adapter
1279          * this calls reset and start */
1280         status = ixgbe_pf_reset_hw(hw);
1281         if (status != 0)
1282                 return -1;
1283         hw->mac.ops.start_hw(hw);
1284
1285         /* configure PF module if SRIOV enabled */
1286         ixgbe_pf_host_configure(dev);
1287
1288         /* initialize transmission unit */
1289         ixgbe_dev_tx_init(dev);
1290
1291         /* This can fail when allocating mbufs for descriptor rings */
1292         err = ixgbe_dev_rx_init(dev);
1293         if (err) {
1294                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1295                 goto error;
1296         }
1297
1298         ixgbe_dev_rxtx_start(dev);
1299
1300         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1301                 err = hw->mac.ops.setup_sfp(hw);
1302                 if (err)
1303                         goto error;
1304         }
1305
1306         /* Turn on the laser */
1307         ixgbe_enable_tx_laser(hw);
1308
1309         /* Skip link setup if loopback mode is enabled for 82599. */
1310         if (hw->mac.type == ixgbe_mac_82599EB &&
1311                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1312                 goto skip_link_setup;
1313
1314         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1315         if (err)
1316                 goto error;
1317         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1318         if (err)
1319                 goto error;
1320
1321         switch(dev->data->dev_conf.link_speed) {
1322         case ETH_LINK_SPEED_AUTONEG:
1323                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1324                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1325                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1326                 break;
1327         case ETH_LINK_SPEED_100:
1328                 /*
1329                  * Invalid for 82598 but error will be detected by
1330                  * ixgbe_setup_link()
1331                  */
1332                 speed = IXGBE_LINK_SPEED_100_FULL;
1333                 break;
1334         case ETH_LINK_SPEED_1000:
1335                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1336                 break;
1337         case ETH_LINK_SPEED_10000:
1338                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1339                 break;
1340         default:
1341                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1342                                 dev->data->dev_conf.link_speed,
1343                                 dev->data->port_id);
1344                 goto error;
1345         }
1346
1347         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1348         if (err)
1349                 goto error;
1350
1351 skip_link_setup:
1352
1353         /* check if lsc interrupt is enabled */
1354         if (dev->data->dev_conf.intr_conf.lsc != 0)
1355                 ixgbe_dev_lsc_interrupt_setup(dev);
1356
1357         /* resume enabled intr since hw reset */
1358         ixgbe_enable_intr(dev);
1359
1360         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1361                 ETH_VLAN_EXTEND_MASK;
1362         ixgbe_vlan_offload_set(dev, mask);
1363
1364         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1365                 /* Enable vlan filtering for VMDq */
1366                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1367         }
1368
1369         /* Configure DCB hw */
1370         ixgbe_configure_dcb(dev);
1371
1372         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1373                 err = ixgbe_fdir_configure(dev);
1374                 if (err)
1375                         goto error;
1376         }
1377
1378         ixgbe_restore_statistics_mapping(dev);
1379
1380         return (0);
1381
1382 error:
1383         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1384         ixgbe_dev_clear_queues(dev);
1385         return -EIO;
1386 }
1387
1388 /*
1389  * Stop device: disable rx and tx functions to allow for reconfiguring.
1390  */
1391 static void
1392 ixgbe_dev_stop(struct rte_eth_dev *dev)
1393 {
1394         struct rte_eth_link link;
1395         struct ixgbe_hw *hw =
1396                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397
1398         PMD_INIT_FUNC_TRACE();
1399
1400         /* disable interrupts */
1401         ixgbe_disable_intr(hw);
1402
1403         /* reset the NIC */
1404         ixgbe_pf_reset_hw(hw);
1405         hw->adapter_stopped = FALSE;
1406
1407         /* stop adapter */
1408         ixgbe_stop_adapter(hw);
1409
1410         /* Turn off the laser */
1411         ixgbe_disable_tx_laser(hw);
1412
1413         ixgbe_dev_clear_queues(dev);
1414
1415         /* Clear recorded link status */
1416         memset(&link, 0, sizeof(link));
1417         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1418 }
1419
1420 /*
1421  * Reest and stop device.
1422  */
1423 static void
1424 ixgbe_dev_close(struct rte_eth_dev *dev)
1425 {
1426         struct ixgbe_hw *hw =
1427                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428
1429         PMD_INIT_FUNC_TRACE();
1430
1431         ixgbe_pf_reset_hw(hw);
1432
1433         ixgbe_dev_stop(dev);
1434         hw->adapter_stopped = 1;
1435
1436         ixgbe_disable_pcie_master(hw);
1437
1438         /* reprogram the RAR[0] in case user changed it. */
1439         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1440 }
1441
1442 /*
1443  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1444  */
1445 static void
1446 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1447 {
1448         struct ixgbe_hw *hw =
1449                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1450         struct ixgbe_hw_stats *hw_stats =
1451                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1452         uint32_t bprc, lxon, lxoff, total;
1453         uint64_t total_missed_rx, total_qbrc, total_qprc;
1454         unsigned i;
1455
1456         total_missed_rx = 0;
1457         total_qbrc = 0;
1458         total_qprc = 0;
1459
1460         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1461         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1462         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1463         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1464
1465         for (i = 0; i < 8; i++) {
1466                 uint32_t mp;
1467                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1468                 /* global total per queue */
1469                 hw_stats->mpc[i] += mp;
1470                 /* Running comprehensive total for stats display */
1471                 total_missed_rx += hw_stats->mpc[i];
1472                 if (hw->mac.type == ixgbe_mac_82598EB)
1473                         hw_stats->rnbc[i] +=
1474                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1475                 hw_stats->pxontxc[i] +=
1476                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1477                 hw_stats->pxonrxc[i] +=
1478                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1479                 hw_stats->pxofftxc[i] +=
1480                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1481                 hw_stats->pxoffrxc[i] +=
1482                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1483                 hw_stats->pxon2offc[i] +=
1484                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1485         }
1486         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1487                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1488                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1489                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1490                 hw_stats->qbrc[i] +=
1491                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1492                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1493                 hw_stats->qbtc[i] +=
1494                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1495                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1496
1497                 total_qprc += hw_stats->qprc[i];
1498                 total_qbrc += hw_stats->qbrc[i];
1499         }
1500         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1501         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1502         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1503
1504         /* Note that gprc counts missed packets */
1505         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1506
1507         if (hw->mac.type != ixgbe_mac_82598EB) {
1508                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1509                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1510                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1511                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1512                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1513                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1514                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1515                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1516         } else {
1517                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1518                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1519                 /* 82598 only has a counter in the high register */
1520                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1521                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1522                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1523         }
1524
1525         /*
1526          * Workaround: mprc hardware is incorrectly counting
1527          * broadcasts, so for now we subtract those.
1528          */
1529         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1530         hw_stats->bprc += bprc;
1531         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1532         if (hw->mac.type == ixgbe_mac_82598EB)
1533                 hw_stats->mprc -= bprc;
1534
1535         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1536         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1537         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1538         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1539         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1540         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1541
1542         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1543         hw_stats->lxontxc += lxon;
1544         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1545         hw_stats->lxofftxc += lxoff;
1546         total = lxon + lxoff;
1547
1548         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1549         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1550         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1551         hw_stats->gptc -= total;
1552         hw_stats->mptc -= total;
1553         hw_stats->ptc64 -= total;
1554         hw_stats->gotc -= total * ETHER_MIN_LEN;
1555
1556         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1557         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1558         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1559         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1560         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1561         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1562         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1563         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1564         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1565         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1566         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1567         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1568         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1569         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1570         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1571         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1572         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1573         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1574         /* Only read FCOE on 82599 */
1575         if (hw->mac.type != ixgbe_mac_82598EB) {
1576                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1577                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1578                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1579                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1580                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1581         }
1582
1583         if (stats == NULL)
1584                 return;
1585
1586         /* Fill out the rte_eth_stats statistics structure */
1587         stats->ipackets = total_qprc;
1588         stats->ibytes = total_qbrc;
1589         stats->opackets = hw_stats->gptc;
1590         stats->obytes = hw_stats->gotc;
1591         stats->imcasts = hw_stats->mprc;
1592
1593         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1594                 stats->q_ipackets[i] = hw_stats->qprc[i];
1595                 stats->q_opackets[i] = hw_stats->qptc[i];
1596                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1597                 stats->q_obytes[i] = hw_stats->qbtc[i];
1598                 stats->q_errors[i] = hw_stats->qprdc[i];
1599         }
1600
1601         /* Rx Errors */
1602         stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1603                 hw_stats->rlec;
1604
1605         stats->oerrors  = 0;
1606
1607         /* Flow Director Stats registers */
1608         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1609         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1610         stats->fdirmatch = hw_stats->fdirmatch;
1611         stats->fdirmiss = hw_stats->fdirmiss;
1612 }
1613
1614 static void
1615 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1616 {
1617         struct ixgbe_hw_stats *stats =
1618                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1619
1620         /* HW registers are cleared on read */
1621         ixgbe_dev_stats_get(dev, NULL);
1622
1623         /* Reset software totals */
1624         memset(stats, 0, sizeof(*stats));
1625 }
1626
1627 static void
1628 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1629 {
1630         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1632                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1633
1634         /* Good Rx packet, include VF loopback */
1635         UPDATE_VF_STAT(IXGBE_VFGPRC,
1636             hw_stats->last_vfgprc, hw_stats->vfgprc);
1637
1638         /* Good Rx octets, include VF loopback */
1639         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1640             hw_stats->last_vfgorc, hw_stats->vfgorc);
1641
1642         /* Good Tx packet, include VF loopback */
1643         UPDATE_VF_STAT(IXGBE_VFGPTC,
1644             hw_stats->last_vfgptc, hw_stats->vfgptc);
1645
1646         /* Good Tx octets, include VF loopback */
1647         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1648             hw_stats->last_vfgotc, hw_stats->vfgotc);
1649
1650         /* Rx Multicst Packet */
1651         UPDATE_VF_STAT(IXGBE_VFMPRC,
1652             hw_stats->last_vfmprc, hw_stats->vfmprc);
1653
1654         if (stats == NULL)
1655                 return;
1656
1657         memset(stats, 0, sizeof(*stats));
1658         stats->ipackets = hw_stats->vfgprc;
1659         stats->ibytes = hw_stats->vfgorc;
1660         stats->opackets = hw_stats->vfgptc;
1661         stats->obytes = hw_stats->vfgotc;
1662         stats->imcasts = hw_stats->vfmprc;
1663 }
1664
1665 static void
1666 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1667 {
1668         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1669                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1670
1671         /* Sync HW register to the last stats */
1672         ixgbevf_dev_stats_get(dev, NULL);
1673
1674         /* reset HW current stats*/
1675         hw_stats->vfgprc = 0;
1676         hw_stats->vfgorc = 0;
1677         hw_stats->vfgptc = 0;
1678         hw_stats->vfgotc = 0;
1679         hw_stats->vfmprc = 0;
1680
1681 }
1682
1683 static void
1684 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1685 {
1686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687
1688         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1689         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1690         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1691         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1692         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1693         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1694         dev_info->max_vfs = dev->pci_dev->max_vfs;
1695         if (hw->mac.type == ixgbe_mac_82598EB)
1696                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1697         else
1698                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1699 }
1700
1701 /* return 0 means link status changed, -1 means not changed */
1702 static int
1703 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1704 {
1705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1706         struct rte_eth_link link, old;
1707         ixgbe_link_speed link_speed;
1708         int link_up;
1709         int diag;
1710
1711         link.link_status = 0;
1712         link.link_speed = 0;
1713         link.link_duplex = 0;
1714         memset(&old, 0, sizeof(old));
1715         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1716
1717         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1718         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1719                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1720         else
1721                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1722         if (diag != 0) {
1723                 link.link_speed = ETH_LINK_SPEED_100;
1724                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1725                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1726                 if (link.link_status == old.link_status)
1727                         return -1;
1728                 return 0;
1729         }
1730
1731         if (link_up == 0) {
1732                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1733                 if (link.link_status == old.link_status)
1734                         return -1;
1735                 return 0;
1736         }
1737         link.link_status = 1;
1738         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1739
1740         switch (link_speed) {
1741         default:
1742         case IXGBE_LINK_SPEED_UNKNOWN:
1743                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1744                 link.link_speed = ETH_LINK_SPEED_100;
1745                 break;
1746
1747         case IXGBE_LINK_SPEED_100_FULL:
1748                 link.link_speed = ETH_LINK_SPEED_100;
1749                 break;
1750
1751         case IXGBE_LINK_SPEED_1GB_FULL:
1752                 link.link_speed = ETH_LINK_SPEED_1000;
1753                 break;
1754
1755         case IXGBE_LINK_SPEED_10GB_FULL:
1756                 link.link_speed = ETH_LINK_SPEED_10000;
1757                 break;
1758         }
1759         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1760
1761         if (link.link_status == old.link_status)
1762                 return -1;
1763
1764         return 0;
1765 }
1766
1767 static void
1768 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1769 {
1770         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771         uint32_t fctrl;
1772
1773         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1774         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1775         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1776 }
1777
1778 static void
1779 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1780 {
1781         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782         uint32_t fctrl;
1783
1784         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1785         fctrl &= (~IXGBE_FCTRL_UPE);
1786         if (dev->data->all_multicast == 1)
1787                 fctrl |= IXGBE_FCTRL_MPE;
1788         else
1789                 fctrl &= (~IXGBE_FCTRL_MPE);
1790         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1791 }
1792
1793 static void
1794 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1795 {
1796         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1797         uint32_t fctrl;
1798
1799         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1800         fctrl |= IXGBE_FCTRL_MPE;
1801         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1802 }
1803
1804 static void
1805 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1806 {
1807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1808         uint32_t fctrl;
1809
1810         if (dev->data->promiscuous == 1)
1811                 return; /* must remain in all_multicast mode */
1812
1813         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1814         fctrl &= (~IXGBE_FCTRL_MPE);
1815         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1816 }
1817
1818 /**
1819  * It clears the interrupt causes and enables the interrupt.
1820  * It will be called once only during nic initialized.
1821  *
1822  * @param dev
1823  *  Pointer to struct rte_eth_dev.
1824  *
1825  * @return
1826  *  - On success, zero.
1827  *  - On failure, a negative value.
1828  */
1829 static int
1830 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1831 {
1832         struct ixgbe_interrupt *intr =
1833                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1834
1835         ixgbe_dev_link_status_print(dev);
1836         intr->mask |= IXGBE_EICR_LSC;
1837
1838         return 0;
1839 }
1840
1841 /*
1842  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1843  *
1844  * @param dev
1845  *  Pointer to struct rte_eth_dev.
1846  *
1847  * @return
1848  *  - On success, zero.
1849  *  - On failure, a negative value.
1850  */
1851 static int
1852 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1853 {
1854         uint32_t eicr;
1855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856         struct ixgbe_interrupt *intr =
1857                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1858
1859         /* clear all cause mask */
1860         ixgbe_disable_intr(hw);
1861
1862         /* read-on-clear nic registers here */
1863         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1864         PMD_DRV_LOG(INFO, "eicr %x", eicr);
1865
1866         intr->flags = 0;
1867         if (eicr & IXGBE_EICR_LSC) {
1868                 /* set flag for async link update */
1869                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1870         }
1871
1872         if (eicr & IXGBE_EICR_MAILBOX)
1873                 intr->flags |= IXGBE_FLAG_MAILBOX;
1874
1875         return 0;
1876 }
1877
1878 /**
1879  * It gets and then prints the link status.
1880  *
1881  * @param dev
1882  *  Pointer to struct rte_eth_dev.
1883  *
1884  * @return
1885  *  - On success, zero.
1886  *  - On failure, a negative value.
1887  */
1888 static void
1889 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1890 {
1891         struct rte_eth_link link;
1892
1893         memset(&link, 0, sizeof(link));
1894         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1895         if (link.link_status) {
1896                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1897                                         (int)(dev->data->port_id),
1898                                         (unsigned)link.link_speed,
1899                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1900                                         "full-duplex" : "half-duplex");
1901         } else {
1902                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1903                                 (int)(dev->data->port_id));
1904         }
1905         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1906                                 dev->pci_dev->addr.domain,
1907                                 dev->pci_dev->addr.bus,
1908                                 dev->pci_dev->addr.devid,
1909                                 dev->pci_dev->addr.function);
1910 }
1911
1912 /*
1913  * It executes link_update after knowing an interrupt occured.
1914  *
1915  * @param dev
1916  *  Pointer to struct rte_eth_dev.
1917  *
1918  * @return
1919  *  - On success, zero.
1920  *  - On failure, a negative value.
1921  */
1922 static int
1923 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1924 {
1925         struct ixgbe_interrupt *intr =
1926                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1927         int64_t timeout;
1928         struct rte_eth_link link;
1929         int intr_enable_delay = false;
1930
1931         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1932
1933         if (intr->flags & IXGBE_FLAG_MAILBOX) {
1934                 ixgbe_pf_mbx_process(dev);
1935                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1936         }
1937
1938         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1939                 /* get the link status before link update, for predicting later */
1940                 memset(&link, 0, sizeof(link));
1941                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1942
1943                 ixgbe_dev_link_update(dev, 0);
1944
1945                 /* likely to up */
1946                 if (!link.link_status)
1947                         /* handle it 1 sec later, wait it being stable */
1948                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1949                 /* likely to down */
1950                 else
1951                         /* handle it 4 sec later, wait it being stable */
1952                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1953
1954                 ixgbe_dev_link_status_print(dev);
1955
1956                 intr_enable_delay = true;
1957         }
1958
1959         if (intr_enable_delay) {
1960                 if (rte_eal_alarm_set(timeout * 1000,
1961                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
1962                         PMD_DRV_LOG(ERR, "Error setting alarm");
1963         } else {
1964                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
1965                 ixgbe_enable_intr(dev);
1966                 rte_intr_enable(&(dev->pci_dev->intr_handle));
1967         }
1968
1969
1970         return 0;
1971 }
1972
1973 /**
1974  * Interrupt handler which shall be registered for alarm callback for delayed
1975  * handling specific interrupt to wait for the stable nic state. As the
1976  * NIC interrupt state is not stable for ixgbe after link is just down,
1977  * it needs to wait 4 seconds to get the stable status.
1978  *
1979  * @param handle
1980  *  Pointer to interrupt handle.
1981  * @param param
1982  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1983  *
1984  * @return
1985  *  void
1986  */
1987 static void
1988 ixgbe_dev_interrupt_delayed_handler(void *param)
1989 {
1990         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1991         struct ixgbe_interrupt *intr =
1992                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1993         struct ixgbe_hw *hw =
1994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1995         uint32_t eicr;
1996
1997         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1998         if (eicr & IXGBE_EICR_MAILBOX)
1999                 ixgbe_pf_mbx_process(dev);
2000
2001         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2002                 ixgbe_dev_link_update(dev, 0);
2003                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2004                 ixgbe_dev_link_status_print(dev);
2005                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2006         }
2007
2008         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2009         ixgbe_enable_intr(dev);
2010         rte_intr_enable(&(dev->pci_dev->intr_handle));
2011 }
2012
2013 /**
2014  * Interrupt handler triggered by NIC  for handling
2015  * specific interrupt.
2016  *
2017  * @param handle
2018  *  Pointer to interrupt handle.
2019  * @param param
2020  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2021  *
2022  * @return
2023  *  void
2024  */
2025 static void
2026 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2027                                                         void *param)
2028 {
2029         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2030         ixgbe_dev_interrupt_get_status(dev);
2031         ixgbe_dev_interrupt_action(dev);
2032 }
2033
2034 static int
2035 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2036 {
2037         struct ixgbe_hw *hw;
2038
2039         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2040         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2041 }
2042
2043 static int
2044 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2045 {
2046         struct ixgbe_hw *hw;
2047
2048         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2050 }
2051
2052 static int
2053 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2054 {
2055         struct ixgbe_hw *hw;
2056         int err;
2057         uint32_t rx_buf_size;
2058         uint32_t max_high_water;
2059         uint32_t mflcn;
2060         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2061                 ixgbe_fc_none,
2062                 ixgbe_fc_rx_pause,
2063                 ixgbe_fc_tx_pause,
2064                 ixgbe_fc_full
2065         };
2066
2067         PMD_INIT_FUNC_TRACE();
2068
2069         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2071         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2072
2073         /*
2074          * At least reserve one Ethernet frame for watermark
2075          * high_water/low_water in kilo bytes for ixgbe
2076          */
2077         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2078         if ((fc_conf->high_water > max_high_water) ||
2079                 (fc_conf->high_water < fc_conf->low_water)) {
2080                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2081                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2082                 return (-EINVAL);
2083         }
2084
2085         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2086         hw->fc.pause_time     = fc_conf->pause_time;
2087         hw->fc.high_water[0]  = fc_conf->high_water;
2088         hw->fc.low_water[0]   = fc_conf->low_water;
2089         hw->fc.send_xon       = fc_conf->send_xon;
2090
2091         err = ixgbe_fc_enable(hw);
2092
2093         /* Not negotiated is not an error case */
2094         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2095
2096                 /* check if we want to forward MAC frames - driver doesn't have native
2097                  * capability to do that, so we'll write the registers ourselves */
2098
2099                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2100
2101                 /* set or clear MFLCN.PMCF bit depending on configuration */
2102                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2103                         mflcn |= IXGBE_MFLCN_PMCF;
2104                 else
2105                         mflcn &= ~IXGBE_MFLCN_PMCF;
2106
2107                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2108                 IXGBE_WRITE_FLUSH(hw);
2109
2110                 return 0;
2111         }
2112
2113         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2114         return -EIO;
2115 }
2116
2117 /**
2118  *  ixgbe_pfc_enable_generic - Enable flow control
2119  *  @hw: pointer to hardware structure
2120  *  @tc_num: traffic class number
2121  *  Enable flow control according to the current settings.
2122  */
2123 static int
2124 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2125 {
2126         int ret_val = 0;
2127         uint32_t mflcn_reg, fccfg_reg;
2128         uint32_t reg;
2129         uint32_t fcrtl, fcrth;
2130         uint8_t i;
2131         uint8_t nb_rx_en;
2132
2133         /* Validate the water mark configuration */
2134         if (!hw->fc.pause_time) {
2135                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2136                 goto out;
2137         }
2138
2139         /* Low water mark of zero causes XOFF floods */
2140         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2141                  /* High/Low water can not be 0 */
2142                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2143                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2144                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2145                         goto out;
2146                 }
2147
2148                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2149                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2150                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2151                         goto out;
2152                 }
2153         }
2154         /* Negotiate the fc mode to use */
2155         ixgbe_fc_autoneg(hw);
2156
2157         /* Disable any previous flow control settings */
2158         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2159         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2160
2161         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2162         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2163
2164         switch (hw->fc.current_mode) {
2165         case ixgbe_fc_none:
2166                 /*
2167                  * If the count of enabled RX Priority Flow control >1,
2168                  * and the TX pause can not be disabled
2169                  */
2170                 nb_rx_en = 0;
2171                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2172                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2173                         if (reg & IXGBE_FCRTH_FCEN)
2174                                 nb_rx_en++;
2175                 }
2176                 if (nb_rx_en > 1)
2177                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2178                 break;
2179         case ixgbe_fc_rx_pause:
2180                 /*
2181                  * Rx Flow control is enabled and Tx Flow control is
2182                  * disabled by software override. Since there really
2183                  * isn't a way to advertise that we are capable of RX
2184                  * Pause ONLY, we will advertise that we support both
2185                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2186                  * disable the adapter's ability to send PAUSE frames.
2187                  */
2188                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2189                 /*
2190                  * If the count of enabled RX Priority Flow control >1,
2191                  * and the TX pause can not be disabled
2192                  */
2193                 nb_rx_en = 0;
2194                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2195                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2196                         if (reg & IXGBE_FCRTH_FCEN)
2197                                 nb_rx_en++;
2198                 }
2199                 if (nb_rx_en > 1)
2200                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2201                 break;
2202         case ixgbe_fc_tx_pause:
2203                 /*
2204                  * Tx Flow control is enabled, and Rx Flow control is
2205                  * disabled by software override.
2206                  */
2207                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2208                 break;
2209         case ixgbe_fc_full:
2210                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2211                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2212                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2213                 break;
2214         default:
2215                 DEBUGOUT("Flow control param set incorrectly\n");
2216                 ret_val = IXGBE_ERR_CONFIG;
2217                 goto out;
2218                 break;
2219         }
2220
2221         /* Set 802.3x based flow control settings. */
2222         mflcn_reg |= IXGBE_MFLCN_DPF;
2223         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2224         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2225
2226         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2227         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2228                 hw->fc.high_water[tc_num]) {
2229                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2230                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2231                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2232         } else {
2233                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2234                 /*
2235                  * In order to prevent Tx hangs when the internal Tx
2236                  * switch is enabled we must set the high water mark
2237                  * to the maximum FCRTH value.  This allows the Tx
2238                  * switch to function even under heavy Rx workloads.
2239                  */
2240                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2241         }
2242         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2243
2244         /* Configure pause time (2 TCs per register) */
2245         reg = hw->fc.pause_time * 0x00010001;
2246         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2247                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2248
2249         /* Configure flow control refresh threshold value */
2250         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2251
2252 out:
2253         return ret_val;
2254 }
2255
2256 static int
2257 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2258 {
2259         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2260         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2261
2262         if(hw->mac.type != ixgbe_mac_82598EB) {
2263                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2264         }
2265         return ret_val;
2266 }
2267
2268 static int
2269 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2270 {
2271         int err;
2272         uint32_t rx_buf_size;
2273         uint32_t max_high_water;
2274         uint8_t tc_num;
2275         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2276         struct ixgbe_hw *hw =
2277                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278         struct ixgbe_dcb_config *dcb_config =
2279                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2280
2281         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2282                 ixgbe_fc_none,
2283                 ixgbe_fc_rx_pause,
2284                 ixgbe_fc_tx_pause,
2285                 ixgbe_fc_full
2286         };
2287
2288         PMD_INIT_FUNC_TRACE();
2289
2290         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2291         tc_num = map[pfc_conf->priority];
2292         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2293         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2294         /*
2295          * At least reserve one Ethernet frame for watermark
2296          * high_water/low_water in kilo bytes for ixgbe
2297          */
2298         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2299         if ((pfc_conf->fc.high_water > max_high_water) ||
2300                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2301                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2302                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2303                 return (-EINVAL);
2304         }
2305
2306         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2307         hw->fc.pause_time = pfc_conf->fc.pause_time;
2308         hw->fc.send_xon = pfc_conf->fc.send_xon;
2309         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2310         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2311
2312         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2313
2314         /* Not negotiated is not an error case */
2315         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2316                 return 0;
2317
2318         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2319         return -EIO;
2320 }
2321
2322 static int
2323 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2324                                 struct rte_eth_rss_reta *reta_conf)
2325 {
2326         uint8_t i,j,mask;
2327         uint32_t reta;
2328         struct ixgbe_hw *hw =
2329                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2330
2331         PMD_INIT_FUNC_TRACE();
2332         /*
2333         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2334         * 128-entries in 32 registers
2335          */
2336         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2337                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2338                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2339                 else
2340                         mask = (uint8_t)((reta_conf->mask_hi >>
2341                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2342                 if (mask != 0) {
2343                         reta = 0;
2344                         if (mask != 0xF)
2345                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2346
2347                         for (j = 0; j < 4; j++) {
2348                                 if (mask & (0x1 << j)) {
2349                                         if (mask != 0xF)
2350                                                 reta &= ~(0xFF << 8 * j);
2351                                         reta |= reta_conf->reta[i + j] << 8*j;
2352                                 }
2353                         }
2354                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2355                 }
2356         }
2357
2358         return 0;
2359 }
2360
2361 static int
2362 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2363                                 struct rte_eth_rss_reta *reta_conf)
2364 {
2365         uint8_t i,j,mask;
2366         uint32_t reta;
2367         struct ixgbe_hw *hw =
2368                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369
2370         PMD_INIT_FUNC_TRACE();
2371         /*
2372          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2373          * 128-entries in 32 registers
2374          */
2375         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2376                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2377                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2378                 else
2379                         mask = (uint8_t)((reta_conf->mask_hi >>
2380                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2381
2382                 if (mask != 0) {
2383                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2384                         for (j = 0; j < 4; j++) {
2385                                 if (mask & (0x1 << j))
2386                                         reta_conf->reta[i + j] =
2387                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2388                         }
2389                 }
2390         }
2391
2392         return 0;
2393 }
2394
2395 static void
2396 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2397                                 uint32_t index, uint32_t pool)
2398 {
2399         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400         uint32_t enable_addr = 1;
2401
2402         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2403 }
2404
2405 static void
2406 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2407 {
2408         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409
2410         ixgbe_clear_rar(hw, index);
2411 }
2412
2413 /*
2414  * Virtual Function operations
2415  */
2416 static void
2417 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2418 {
2419         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2420
2421         /* Clear interrupt mask to stop from interrupts being generated */
2422         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2423
2424         IXGBE_WRITE_FLUSH(hw);
2425 }
2426
2427 static int
2428 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2429 {
2430         struct rte_eth_conf* conf = &dev->data->dev_conf;
2431
2432         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2433                 dev->data->port_id);
2434
2435         /*
2436          * VF has no ability to enable/disable HW CRC
2437          * Keep the persistent behavior the same as Host PF
2438          */
2439 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2440         if (!conf->rxmode.hw_strip_crc) {
2441                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2442                 conf->rxmode.hw_strip_crc = 1;
2443         }
2444 #else
2445         if (conf->rxmode.hw_strip_crc) {
2446                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2447                 conf->rxmode.hw_strip_crc = 0;
2448         }
2449 #endif
2450
2451         return 0;
2452 }
2453
2454 static int
2455 ixgbevf_dev_start(struct rte_eth_dev *dev)
2456 {
2457         struct ixgbe_hw *hw =
2458                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459         int err, mask = 0;
2460
2461         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2462
2463         hw->mac.ops.reset_hw(hw);
2464
2465         ixgbevf_dev_tx_init(dev);
2466
2467         /* This can fail when allocating mbufs for descriptor rings */
2468         err = ixgbevf_dev_rx_init(dev);
2469         if (err) {
2470                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2471                 ixgbe_dev_clear_queues(dev);
2472                 return err;
2473         }
2474
2475         /* Set vfta */
2476         ixgbevf_set_vfta_all(dev,1);
2477
2478         /* Set HW strip */
2479         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2480                 ETH_VLAN_EXTEND_MASK;
2481         ixgbevf_vlan_offload_set(dev, mask);
2482
2483         ixgbevf_dev_rxtx_start(dev);
2484
2485         return 0;
2486 }
2487
2488 static void
2489 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2490 {
2491         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492
2493         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2494
2495         hw->adapter_stopped = TRUE;
2496         ixgbe_stop_adapter(hw);
2497
2498         /*
2499           * Clear what we set, but we still keep shadow_vfta to
2500           * restore after device starts
2501           */
2502         ixgbevf_set_vfta_all(dev,0);
2503
2504         ixgbe_dev_clear_queues(dev);
2505 }
2506
2507 static void
2508 ixgbevf_dev_close(struct rte_eth_dev *dev)
2509 {
2510         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511
2512         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2513
2514         ixgbe_reset_hw(hw);
2515
2516         ixgbevf_dev_stop(dev);
2517
2518         /* reprogram the RAR[0] in case user changed it. */
2519         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2520 }
2521
2522 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2523 {
2524         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2525         struct ixgbe_vfta * shadow_vfta =
2526                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2527         int i = 0, j = 0, vfta = 0, mask = 1;
2528
2529         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2530                 vfta = shadow_vfta->vfta[i];
2531                 if(vfta){
2532                         mask = 1;
2533                         for (j = 0; j < 32; j++){
2534                                 if(vfta & mask)
2535                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2536                                 mask<<=1;
2537                         }
2538                 }
2539         }
2540
2541 }
2542
2543 static int
2544 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2545 {
2546         struct ixgbe_hw *hw =
2547                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2548         struct ixgbe_vfta * shadow_vfta =
2549                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2550         uint32_t vid_idx = 0;
2551         uint32_t vid_bit = 0;
2552         int ret = 0;
2553
2554         PMD_INIT_FUNC_TRACE();
2555
2556         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2557         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2558         if(ret){
2559                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2560                 return ret;
2561         }
2562         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2563         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2564
2565         /* Save what we set and retore it after device reset */
2566         if (on)
2567                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2568         else
2569                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2570
2571         return 0;
2572 }
2573
2574 static void
2575 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2576 {
2577         struct ixgbe_hw *hw =
2578                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579         uint32_t ctrl;
2580
2581         PMD_INIT_FUNC_TRACE();
2582
2583         if(queue >= hw->mac.max_rx_queues)
2584                 return;
2585
2586         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2587         if(on)
2588                 ctrl |= IXGBE_RXDCTL_VME;
2589         else
2590                 ctrl &= ~IXGBE_RXDCTL_VME;
2591         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2592
2593         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2594 }
2595
2596 static void
2597 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2598 {
2599         struct ixgbe_hw *hw =
2600                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601         uint16_t i;
2602         int on = 0;
2603
2604         /* VF function only support hw strip feature, others are not support */
2605         if(mask & ETH_VLAN_STRIP_MASK){
2606                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2607
2608                 for(i=0; i < hw->mac.max_rx_queues; i++)
2609                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2610         }
2611 }
2612
2613 static int
2614 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2615 {
2616         uint32_t reg_val;
2617
2618         /* we only need to do this if VMDq is enabled */
2619         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2620         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2621                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2622                 return (-1);
2623         }
2624
2625         return 0;
2626 }
2627
2628 static uint32_t
2629 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2630 {
2631         uint32_t vector = 0;
2632         switch (hw->mac.mc_filter_type) {
2633         case 0:   /* use bits [47:36] of the address */
2634                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2635                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2636                 break;
2637         case 1:   /* use bits [46:35] of the address */
2638                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2639                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2640                 break;
2641         case 2:   /* use bits [45:34] of the address */
2642                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2643                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2644                 break;
2645         case 3:   /* use bits [43:32] of the address */
2646                 vector = ((uc_addr->addr_bytes[4]) |
2647                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2648                 break;
2649         default:  /* Invalid mc_filter_type */
2650                 break;
2651         }
2652
2653         /* vector can only be 12-bits or boundary will be exceeded */
2654         vector &= 0xFFF;
2655         return vector;
2656 }
2657
2658 static int
2659 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2660                                uint8_t on)
2661 {
2662         uint32_t vector;
2663         uint32_t uta_idx;
2664         uint32_t reg_val;
2665         uint32_t uta_shift;
2666         uint32_t rc;
2667         const uint32_t ixgbe_uta_idx_mask = 0x7F;
2668         const uint32_t ixgbe_uta_bit_shift = 5;
2669         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2670         const uint32_t bit1 = 0x1;
2671
2672         struct ixgbe_hw *hw =
2673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2674         struct ixgbe_uta_info *uta_info =
2675                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2676
2677         /* The UTA table only exists on 82599 hardware and newer */
2678         if (hw->mac.type < ixgbe_mac_82599EB)
2679                 return (-ENOTSUP);
2680
2681         vector = ixgbe_uta_vector(hw,mac_addr);
2682         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2683         uta_shift = vector & ixgbe_uta_bit_mask;
2684
2685         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2686         if(rc == on)
2687                 return 0;
2688
2689         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2690         if (on) {
2691                 uta_info->uta_in_use++;
2692                 reg_val |= (bit1 << uta_shift);
2693                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2694         } else {
2695                 uta_info->uta_in_use--;
2696                 reg_val &= ~(bit1 << uta_shift);
2697                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2698         }
2699
2700         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2701
2702         if (uta_info->uta_in_use > 0)
2703                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2704                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2705         else
2706                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2707
2708         return 0;
2709 }
2710
2711 static int
2712 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2713 {
2714         int i;
2715         struct ixgbe_hw *hw =
2716                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2717         struct ixgbe_uta_info *uta_info =
2718                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2719
2720         /* The UTA table only exists on 82599 hardware and newer */
2721         if (hw->mac.type < ixgbe_mac_82599EB)
2722                 return (-ENOTSUP);
2723
2724         if(on) {
2725                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2726                         uta_info->uta_shadow[i] = ~0;
2727                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2728                 }
2729         } else {
2730                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2731                         uta_info->uta_shadow[i] = 0;
2732                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2733                 }
2734         }
2735         return 0;
2736
2737 }
2738 static int
2739 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2740                                uint16_t rx_mask, uint8_t on)
2741 {
2742         int val = 0;
2743
2744         struct ixgbe_hw *hw =
2745                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2746         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2747
2748         if (hw->mac.type == ixgbe_mac_82598EB) {
2749                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2750                         " on 82599 hardware and newer\n");
2751                 return (-ENOTSUP);
2752         }
2753         if (ixgbe_vmdq_mode_check(hw) < 0)
2754                 return (-ENOTSUP);
2755
2756         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2757                 val |= IXGBE_VMOLR_AUPE;
2758         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2759                 val |= IXGBE_VMOLR_ROMPE;
2760         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2761                 val |= IXGBE_VMOLR_ROPE;
2762         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2763                 val |= IXGBE_VMOLR_BAM;
2764         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2765                 val |= IXGBE_VMOLR_MPE;
2766
2767         if (on)
2768                 vmolr |= val;
2769         else
2770                 vmolr &= ~val;
2771
2772         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2773
2774         return 0;
2775 }
2776
2777 static int
2778 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2779 {
2780         uint32_t reg,addr;
2781         uint32_t val;
2782         const uint8_t bit1 = 0x1;
2783
2784         struct ixgbe_hw *hw =
2785                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786
2787         if (ixgbe_vmdq_mode_check(hw) < 0)
2788                 return (-ENOTSUP);
2789
2790         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2791         reg = IXGBE_READ_REG(hw, addr);
2792         val = bit1 << pool;
2793
2794         if (on)
2795                 reg |= val;
2796         else
2797                 reg &= ~val;
2798
2799         IXGBE_WRITE_REG(hw, addr,reg);
2800
2801         return 0;
2802 }
2803
2804 static int
2805 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2806 {
2807         uint32_t reg,addr;
2808         uint32_t val;
2809         const uint8_t bit1 = 0x1;
2810
2811         struct ixgbe_hw *hw =
2812                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813
2814         if (ixgbe_vmdq_mode_check(hw) < 0)
2815                 return (-ENOTSUP);
2816
2817         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2818         reg = IXGBE_READ_REG(hw, addr);
2819         val = bit1 << pool;
2820
2821         if (on)
2822                 reg |= val;
2823         else
2824                 reg &= ~val;
2825
2826         IXGBE_WRITE_REG(hw, addr,reg);
2827
2828         return 0;
2829 }
2830
2831 static int
2832 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2833                         uint64_t pool_mask, uint8_t vlan_on)
2834 {
2835         int ret = 0;
2836         uint16_t pool_idx;
2837         struct ixgbe_hw *hw =
2838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839
2840         if (ixgbe_vmdq_mode_check(hw) < 0)
2841                 return (-ENOTSUP);
2842         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2843                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2844                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2845                         if (ret < 0)
2846                                 return ret;
2847         }
2848
2849         return ret;
2850 }
2851
2852 static int
2853 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2854                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
2855                         uint8_t rule_id, uint8_t on)
2856 {
2857         uint32_t mr_ctl,vlvf;
2858         uint32_t mp_lsb = 0;
2859         uint32_t mv_msb = 0;
2860         uint32_t mv_lsb = 0;
2861         uint32_t mp_msb = 0;
2862         uint8_t i = 0;
2863         int reg_index = 0;
2864         uint64_t vlan_mask = 0;
2865
2866         const uint8_t pool_mask_offset = 32;
2867         const uint8_t vlan_mask_offset = 32;
2868         const uint8_t dst_pool_offset = 8;
2869         const uint8_t rule_mr_offset  = 4;
2870         const uint8_t mirror_rule_mask= 0x0F;
2871
2872         struct ixgbe_mirror_info *mr_info =
2873                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2874         struct ixgbe_hw *hw =
2875                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876
2877         if (ixgbe_vmdq_mode_check(hw) < 0)
2878                 return (-ENOTSUP);
2879
2880         /* Check if vlan mask is valid */
2881         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2882                 if (mirror_conf->vlan.vlan_mask == 0)
2883                         return (-EINVAL);
2884         }
2885
2886         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2887         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2888                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2889                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2890                                 /* search vlan id related pool vlan filter index */
2891                                 reg_index = ixgbe_find_vlvf_slot(hw,
2892                                                 mirror_conf->vlan.vlan_id[i]);
2893                                 if(reg_index < 0)
2894                                         return (-EINVAL);
2895                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2896                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
2897                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
2898                                                 == mirror_conf->vlan.vlan_id[i]))
2899                                         vlan_mask |= (1ULL << reg_index);
2900                                 else
2901                                         return (-EINVAL);
2902                         }
2903                 }
2904
2905                 if (on) {
2906                         mv_lsb = vlan_mask & 0xFFFFFFFF;
2907                         mv_msb = vlan_mask >> vlan_mask_offset;
2908
2909                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
2910                                                 mirror_conf->vlan.vlan_mask;
2911                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2912                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2913                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2914                                                 mirror_conf->vlan.vlan_id[i];
2915                         }
2916                 } else {
2917                         mv_lsb = 0;
2918                         mv_msb = 0;
2919                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
2920                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
2921                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
2922                 }
2923         }
2924
2925         /*
2926          * if enable pool mirror, write related pool mask register,if disable
2927          * pool mirror, clear PFMRVM register
2928          */
2929         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2930                 if (on) {
2931                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
2932                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
2933                         mr_info->mr_conf[rule_id].pool_mask =
2934                                         mirror_conf->pool_mask;
2935
2936                 } else {
2937                         mp_lsb = 0;
2938                         mp_msb = 0;
2939                         mr_info->mr_conf[rule_id].pool_mask = 0;
2940                 }
2941         }
2942
2943         /* read  mirror control register and recalculate it */
2944         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
2945
2946         if (on) {
2947                 mr_ctl |= mirror_conf->rule_type_mask;
2948                 mr_ctl &= mirror_rule_mask;
2949                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
2950         } else
2951                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
2952
2953         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
2954         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
2955
2956         /* write mirrror control  register */
2957         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
2958
2959         /* write pool mirrror control  register */
2960         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2961                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
2962                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
2963                                 mp_msb);
2964         }
2965         /* write VLAN mirrror control  register */
2966         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2967                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
2968                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
2969                                 mv_msb);
2970         }
2971
2972         return 0;
2973 }
2974
2975 static int
2976 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
2977 {
2978         int mr_ctl = 0;
2979         uint32_t lsb_val = 0;
2980         uint32_t msb_val = 0;
2981         const uint8_t rule_mr_offset = 4;
2982
2983         struct ixgbe_hw *hw =
2984                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2985         struct ixgbe_mirror_info *mr_info =
2986                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2987
2988         if (ixgbe_vmdq_mode_check(hw) < 0)
2989                 return (-ENOTSUP);
2990
2991         memset(&mr_info->mr_conf[rule_id], 0,
2992                 sizeof(struct rte_eth_vmdq_mirror_conf));
2993
2994         /* clear PFVMCTL register */
2995         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
2996
2997         /* clear pool mask register */
2998         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
2999         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3000
3001         /* clear vlan mask register */
3002         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3003         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3004
3005         return 0;
3006 }