lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  96
  97 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  98
  99 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 100                 struct rte_eth_dev *eth_dev);
 101 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 102 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 104 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 105 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 106 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 107 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 108 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 109 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 110 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 111 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 112                                 int wait_to_complete);
 113 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_stats *stats);
 115 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 116 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 117                                              uint16_t queue_id,
 118                                              uint8_t stat_idx,
 119                                              uint8_t is_rx);
 120 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 121                                 struct rte_eth_dev_info *dev_info);
 122
 123 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 128 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 129                 uint16_t queue, bool on);
 130 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 131                 int on);
 132 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 133 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 134 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 135 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 136 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 137
 138 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 139 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 140 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 141                                struct rte_eth_fc_conf *fc_conf);
 142 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 143                                struct rte_eth_fc_conf *fc_conf);
 144 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 145                 struct rte_eth_pfc_conf *pfc_conf);
 146 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 147                 struct rte_eth_rss_reta *reta_conf);
 148 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 149                 struct rte_eth_rss_reta *reta_conf);
 150 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 154 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 155                 void *param);
 156 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 157 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 158                 uint32_t index, uint32_t pool);
 159 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 160 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 161
 162 /* For Virtual Function support */
 163 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 164                 struct rte_eth_dev *eth_dev);
 165 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 166 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 167 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 168 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 169 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 170 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 171                 struct rte_eth_stats *stats);
 172 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 173 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 174                 uint16_t vlan_id, int on);
 175 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 176                 uint16_t queue, int on);
 177 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 178 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 179
 180 /* For Eth VMDQ APIs support */
 181 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 182                 ether_addr* mac_addr,uint8_t on);
 183 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 184 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 185                 uint16_t rx_mask, uint8_t on);
 186 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 187 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 188 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 189                 uint64_t pool_mask,uint8_t vlan_on);
 190 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 191                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 192                 uint8_t rule_id, uint8_t on);
 193 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 194                 uint8_t rule_id);
 195
 196 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 197                 uint16_t queue_idx, uint16_t tx_rate);
 198 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 199                 uint16_t tx_rate, uint64_t q_msk);
 200
 201 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 202                                  struct ether_addr *mac_addr,
 203                                  uint32_t index, uint32_t pool);
 204 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 205 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 206                         struct rte_syn_filter *filter, uint16_t rx_queue);
 207 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 208 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 209                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 210 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 211                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 212 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 213                         uint16_t index);
 214 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 215                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 216 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 217                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 218 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 219                         uint16_t index);
 220 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 221                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 222
 223 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 224
 225 /*
 226  * Define VF Stats MACRO for Non "cleared on read" register
 227  */
 228 #define UPDATE_VF_STAT(reg, last, cur)                          \
 229 {                                                               \
 230         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 231         cur += latest - last;                                   \
 232         last = latest;                                          \
 233 }
 234
 235 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 236 {                                                                \
 237         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 238         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 239         u64 latest = ((new_msb << 32) | new_lsb);                \
 240         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 241         last = latest;                                           \
 242 }
 243
 244 #define IXGBE_SET_HWSTRIP(h, q) do{\
 245                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 246                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 247                 (h)->bitmap[idx] |= 1 << bit;\
 248         }while(0)
 249
 250 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 251                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 252                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 253                 (h)->bitmap[idx] &= ~(1 << bit);\
 254         }while(0)
 255
 256 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 257                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 258                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 259                 (r) = (h)->bitmap[idx] >> bit & 1;\
 260         }while(0)
 261
 262 /*
 263  * The set of PCI devices this driver supports
 264  */
 265 static struct rte_pci_id pci_id_ixgbe_map[] = {
 266
 267 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 268 #include "rte_pci_dev_ids.h"
 269
 270 { .vendor_id = 0, /* sentinel */ },
 271 };
 272
 273
 274 /*
 275  * The set of PCI devices this driver supports (for 82599 VF)
 276  */
 277 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 278
 279 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 280 #include "rte_pci_dev_ids.h"
 281 { .vendor_id = 0, /* sentinel */ },
 282
 283 };
 284
 285 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 286         .dev_configure        = ixgbe_dev_configure,
 287         .dev_start            = ixgbe_dev_start,
 288         .dev_stop             = ixgbe_dev_stop,
 289         .dev_set_link_up    = ixgbe_dev_set_link_up,
 290         .dev_set_link_down  = ixgbe_dev_set_link_down,
 291         .dev_close            = ixgbe_dev_close,
 292         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 293         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 294         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 295         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 296         .link_update          = ixgbe_dev_link_update,
 297         .stats_get            = ixgbe_dev_stats_get,
 298         .stats_reset          = ixgbe_dev_stats_reset,
 299         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 300         .dev_infos_get        = ixgbe_dev_info_get,
 301         .mtu_set              = ixgbe_dev_mtu_set,
 302         .vlan_filter_set      = ixgbe_vlan_filter_set,
 303         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 304         .vlan_offload_set     = ixgbe_vlan_offload_set,
 305         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 306         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 307         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 308         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 309         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 310         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 311         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 312         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 313         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 314         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 315         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 316         .dev_led_on           = ixgbe_dev_led_on,
 317         .dev_led_off          = ixgbe_dev_led_off,
 318         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 319         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 320         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 321         .mac_addr_add         = ixgbe_add_rar,
 322         .mac_addr_remove      = ixgbe_remove_rar,
 323         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 324         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 325         .mirror_rule_set      = ixgbe_mirror_rule_set,
 326         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 327         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 328         .set_vf_rx            = ixgbe_set_pool_rx,
 329         .set_vf_tx            = ixgbe_set_pool_tx,
 330         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 331         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 332         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 333         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 334         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 335         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 336         .fdir_infos_get               = ixgbe_fdir_info_get,
 337         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 338         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 339         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 340         .fdir_set_masks               = ixgbe_fdir_set_masks,
 341         .reta_update          = ixgbe_dev_rss_reta_update,
 342         .reta_query           = ixgbe_dev_rss_reta_query,
 343 #ifdef RTE_NIC_BYPASS
 344         .bypass_init          = ixgbe_bypass_init,
 345         .bypass_state_set     = ixgbe_bypass_state_store,
 346         .bypass_state_show    = ixgbe_bypass_state_show,
 347         .bypass_event_set     = ixgbe_bypass_event_store,
 348         .bypass_event_show    = ixgbe_bypass_event_show,
 349         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 350         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 351         .bypass_ver_show      = ixgbe_bypass_ver_show,
 352         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 353 #endif /* RTE_NIC_BYPASS */
 354         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 355         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 356         .add_syn_filter          = ixgbe_add_syn_filter,
 357         .remove_syn_filter       = ixgbe_remove_syn_filter,
 358         .get_syn_filter          = ixgbe_get_syn_filter,
 359         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 360         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 361         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 362         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 363         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 364         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 365 };
 366
 367 /*
 368  * dev_ops for virtual function, bare necessities for basic vf
 369  * operation have been implemented
 370  */
 371 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 372
 373         .dev_configure        = ixgbevf_dev_configure,
 374         .dev_start            = ixgbevf_dev_start,
 375         .dev_stop             = ixgbevf_dev_stop,
 376         .link_update          = ixgbe_dev_link_update,
 377         .stats_get            = ixgbevf_dev_stats_get,
 378         .stats_reset          = ixgbevf_dev_stats_reset,
 379         .dev_close            = ixgbevf_dev_close,
 380         .dev_infos_get        = ixgbe_dev_info_get,
 381         .mtu_set              = ixgbevf_dev_set_mtu,
 382         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 383         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 384         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 385         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 386         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 387         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 388         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 389         .mac_addr_add         = ixgbevf_add_mac_addr,
 390         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 391 };
 392
 393 /**
 394  * Atomically reads the link status information from global
 395  * structure rte_eth_dev.
 396  *
 397  * @param dev
 398  *   - Pointer to the structure rte_eth_dev to read from.
 399  *   - Pointer to the buffer to be saved with the link status.
 400  *
 401  * @return
 402  *   - On success, zero.
 403  *   - On failure, negative value.
 404  */
 405 static inline int
 406 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 407                                 struct rte_eth_link *link)
 408 {
 409         struct rte_eth_link *dst = link;
 410         struct rte_eth_link *src = &(dev->data->dev_link);
 411
 412         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 413                                         *(uint64_t *)src) == 0)
 414                 return -1;
 415
 416         return 0;
 417 }
 418
 419 /**
 420  * Atomically writes the link status information into global
 421  * structure rte_eth_dev.
 422  *
 423  * @param dev
 424  *   - Pointer to the structure rte_eth_dev to read from.
 425  *   - Pointer to the buffer to be saved with the link status.
 426  *
 427  * @return
 428  *   - On success, zero.
 429  *   - On failure, negative value.
 430  */
 431 static inline int
 432 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 433                                 struct rte_eth_link *link)
 434 {
 435         struct rte_eth_link *dst = &(dev->data->dev_link);
 436         struct rte_eth_link *src = link;
 437
 438         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 439                                         *(uint64_t *)src) == 0)
 440                 return -1;
 441
 442         return 0;
 443 }
 444
 445 /*
 446  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 447  */
 448 static inline int
 449 ixgbe_is_sfp(struct ixgbe_hw *hw)
 450 {
 451         switch (hw->phy.type) {
 452         case ixgbe_phy_sfp_avago:
 453         case ixgbe_phy_sfp_ftl:
 454         case ixgbe_phy_sfp_intel:
 455         case ixgbe_phy_sfp_unknown:
 456         case ixgbe_phy_sfp_passive_tyco:
 457         case ixgbe_phy_sfp_passive_unknown:
 458                 return 1;
 459         default:
 460                 return 0;
 461         }
 462 }
 463
 464 static inline int32_t
 465 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 466 {
 467         uint32_t ctrl_ext;
 468         int32_t status;
 469
 470         status = ixgbe_reset_hw(hw);
 471
 472         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 473         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 474         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 475         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 476         IXGBE_WRITE_FLUSH(hw);
 477
 478         return status;
 479 }
 480
 481 static inline void
 482 ixgbe_enable_intr(struct rte_eth_dev *dev)
 483 {
 484         struct ixgbe_interrupt *intr =
 485                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 486         struct ixgbe_hw *hw =
 487                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 488
 489         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 490         IXGBE_WRITE_FLUSH(hw);
 491 }
 492
 493 /*
 494  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 495  */
 496 static void
 497 ixgbe_disable_intr(struct ixgbe_hw *hw)
 498 {
 499         PMD_INIT_FUNC_TRACE();
 500
 501         if (hw->mac.type == ixgbe_mac_82598EB) {
 502                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 503         } else {
 504                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 505                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 506                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 507         }
 508         IXGBE_WRITE_FLUSH(hw);
 509 }
 510
 511 /*
 512  * This function resets queue statistics mapping registers.
 513  * From Niantic datasheet, Initialization of Statistics section:
 514  * "...if software requires the queue counters, the RQSMR and TQSM registers
 515  * must be re-programmed following a device reset.
 516  */
 517 static void
 518 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 519 {
 520         uint32_t i;
 521
 522         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 523                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 524                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 525         }
 526 }
 527
 528
 529 static int
 530 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 531                                   uint16_t queue_id,
 532                                   uint8_t stat_idx,
 533                                   uint8_t is_rx)
 534 {
 535 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 536 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 537 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 538
 539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 540         struct ixgbe_stat_mapping_registers *stat_mappings =
 541                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 542         uint32_t qsmr_mask = 0;
 543         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 544         uint32_t q_map;
 545         uint8_t n, offset;
 546
 547         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 548                 return -ENOSYS;
 549
 550         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 551                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 552
 553         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 554         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 555                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 556                 return -EIO;
 557         }
 558         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 559
 560         /* Now clear any previous stat_idx set */
 561         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 562         if (!is_rx)
 563                 stat_mappings->tqsm[n] &= ~clearing_mask;
 564         else
 565                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 566
 567         q_map = (uint32_t)stat_idx;
 568         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 569         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 570         if (!is_rx)
 571                 stat_mappings->tqsm[n] |= qsmr_mask;
 572         else
 573                 stat_mappings->rqsmr[n] |= qsmr_mask;
 574
 575         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 576                      "%s[%d] = 0x%08x\n",
 577                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 578                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 579
 580         /* Now write the mapping in the appropriate register */
 581         if (is_rx) {
 582                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 583                              stat_mappings->rqsmr[n], n);
 584                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 585         }
 586         else {
 587                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 588                              stat_mappings->tqsm[n], n);
 589                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 590         }
 591         return 0;
 592 }
 593
 594 static void
 595 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 596 {
 597         struct ixgbe_stat_mapping_registers *stat_mappings =
 598                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 600         int i;
 601
 602         /* write whatever was in stat mapping table to the NIC */
 603         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 604                 /* rx */
 605                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 606
 607                 /* tx */
 608                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 609         }
 610 }
 611
 612 static void
 613 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 614 {
 615         uint8_t i;
 616         struct ixgbe_dcb_tc_config *tc;
 617         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 618
 619         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 620         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 621         for (i = 0; i < dcb_max_tc; i++) {
 622                 tc = &dcb_config->tc_config[i];
 623                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 624                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 625                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 626                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 627                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 628                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 629                 tc->pfc = ixgbe_dcb_pfc_disabled;
 630         }
 631
 632         /* Initialize default user to priority mapping, UPx->TC0 */
 633         tc = &dcb_config->tc_config[0];
 634         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 635         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 636         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 637                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 638                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 639         }
 640         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 641         dcb_config->pfc_mode_enable = false;
 642         dcb_config->vt_mode = true;
 643         dcb_config->round_robin_enable = false;
 644         /* support all DCB capabilities in 82599 */
 645         dcb_config->support.capabilities = 0xFF;
 646
 647         /*we only support 4 Tcs for X540*/
 648         if (hw->mac.type == ixgbe_mac_X540) {
 649                 dcb_config->num_tcs.pg_tcs = 4;
 650                 dcb_config->num_tcs.pfc_tcs = 4;
 651         }
 652 }
 653
 654 /*
 655  * Ensure that all locks are released before first NVM or PHY access
 656  */
 657 static void
 658 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 659 {
 660         uint16_t mask;
 661
 662         /*
 663          * Phy lock should not fail in this early stage. If this is the case,
 664          * it is due to an improper exit of the application.
 665          * So force the release of the faulty lock. Release of common lock
 666          * is done automatically by swfw_sync function.
 667          */
 668         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 669         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 670                    DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
 671         }
 672         ixgbe_release_swfw_semaphore(hw, mask);
 673
 674         /*
 675          * These ones are more tricky since they are common to all ports; but
 676          * swfw_sync retries last long enough (1s) to be almost sure that if
 677          * lock can not be taken it is due to an improper lock of the
 678          * semaphore.
 679          */
 680         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 681         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 682                    DEBUGOUT("SWFW common locks released");
 683         }
 684         ixgbe_release_swfw_semaphore(hw, mask);
 685 }
 686
 687 /*
 688  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 689  * It returns 0 on success.
 690  */
 691 static int
 692 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 693                      struct rte_eth_dev *eth_dev)
 694 {
 695         struct rte_pci_device *pci_dev;
 696         struct ixgbe_hw *hw =
 697                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 698         struct ixgbe_vfta * shadow_vfta =
 699                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 700         struct ixgbe_hwstrip *hwstrip =
 701                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 702         struct ixgbe_dcb_config *dcb_config =
 703                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 704         uint32_t ctrl_ext;
 705         uint16_t csum;
 706         int diag, i;
 707
 708         PMD_INIT_FUNC_TRACE();
 709
 710         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 711         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 712         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 713
 714         /* for secondary processes, we don't initialise any further as primary
 715          * has already done this work. Only check we don't need a different
 716          * RX function */
 717         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 718                 if (eth_dev->data->scattered_rx)
 719                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 720                 return 0;
 721         }
 722         pci_dev = eth_dev->pci_dev;
 723
 724         /* Vendor and Device ID need to be set before init of shared code */
 725         hw->device_id = pci_dev->id.device_id;
 726         hw->vendor_id = pci_dev->id.vendor_id;
 727         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 728 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 729         hw->allow_unsupported_sfp = 1;
 730 #endif
 731
 732         /* Initialize the shared code (base driver) */
 733 #ifdef RTE_NIC_BYPASS
 734         diag = ixgbe_bypass_init_shared_code(hw);
 735 #else
 736         diag = ixgbe_init_shared_code(hw);
 737 #endif /* RTE_NIC_BYPASS */
 738
 739         if (diag != IXGBE_SUCCESS) {
 740                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 741                 return -EIO;
 742         }
 743
 744         /* pick up the PCI bus settings for reporting later */
 745         ixgbe_get_bus_info(hw);
 746
 747         /* Unlock any pending hardware semaphore */
 748         ixgbe_swfw_lock_reset(hw);
 749
 750         /* Initialize DCB configuration*/
 751         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 752         ixgbe_dcb_init(hw,dcb_config);
 753         /* Get Hardware Flow Control setting */
 754         hw->fc.requested_mode = ixgbe_fc_full;
 755         hw->fc.current_mode = ixgbe_fc_full;
 756         hw->fc.pause_time = IXGBE_FC_PAUSE;
 757         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 758                 hw->fc.low_water[i] = IXGBE_FC_LO;
 759                 hw->fc.high_water[i] = IXGBE_FC_HI;
 760         }
 761         hw->fc.send_xon = 1;
 762
 763         /* Make sure we have a good EEPROM before we read from it */
 764         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 765         if (diag != IXGBE_SUCCESS) {
 766                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 767                 return -EIO;
 768         }
 769
 770 #ifdef RTE_NIC_BYPASS
 771         diag = ixgbe_bypass_init_hw(hw);
 772 #else
 773         diag = ixgbe_init_hw(hw);
 774 #endif /* RTE_NIC_BYPASS */
 775
 776         /*
 777          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 778          * is called too soon after the kernel driver unbinding/binding occurs.
 779          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 780          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 781          * also called. See ixgbe_identify_phy_82599(). The reason for the
 782          * failure is not known, and only occuts when virtualisation features
 783          * are disabled in the bios. A delay of 100ms  was found to be enough by
 784          * trial-and-error, and is doubled to be safe.
 785          */
 786         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 787                 rte_delay_ms(200);
 788                 diag = ixgbe_init_hw(hw);
 789         }
 790
 791         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 792                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 793                     "LOM.  Please be aware there may be issues associated "
 794                     "with your hardware.\n If you are experiencing problems "
 795                     "please contact your Intel or hardware representative "
 796                     "who provided you with this hardware.\n");
 797         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 798                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 799         if (diag) {
 800                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 801                 return -EIO;
 802         }
 803
 804         /* disable interrupt */
 805         ixgbe_disable_intr(hw);
 806
 807         /* reset mappings for queue statistics hw counters*/
 808         ixgbe_reset_qstat_mappings(hw);
 809
 810         /* Allocate memory for storing MAC addresses */
 811         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 812                         hw->mac.num_rar_entries, 0);
 813         if (eth_dev->data->mac_addrs == NULL) {
 814                 PMD_INIT_LOG(ERR,
 815                         "Failed to allocate %u bytes needed to store "
 816                         "MAC addresses",
 817                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 818                 return -ENOMEM;
 819         }
 820         /* Copy the permanent MAC address */
 821         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 822                         &eth_dev->data->mac_addrs[0]);
 823
 824         /* Allocate memory for storing hash filter MAC addresses */
 825         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 826                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 827         if (eth_dev->data->hash_mac_addrs == NULL) {
 828                 PMD_INIT_LOG(ERR,
 829                         "Failed to allocate %d bytes needed to store MAC addresses",
 830                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 831                 return -ENOMEM;
 832         }
 833
 834         /* initialize the vfta */
 835         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 836
 837         /* initialize the hw strip bitmap*/
 838         memset(hwstrip, 0, sizeof(*hwstrip));
 839
 840         /* initialize PF if max_vfs not zero */
 841         ixgbe_pf_host_init(eth_dev);
 842
 843         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 844         /* let hardware know driver is loaded */
 845         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 846         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 847         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 848         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 849         IXGBE_WRITE_FLUSH(hw);
 850
 851         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 852                 PMD_INIT_LOG(DEBUG,
 853                              "MAC: %d, PHY: %d, SFP+: %d<n",
 854                              (int) hw->mac.type, (int) hw->phy.type,
 855                              (int) hw->phy.sfp_type);
 856         else
 857                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 858                              (int) hw->mac.type, (int) hw->phy.type);
 859
 860         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 861                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 862                         pci_dev->id.device_id);
 863
 864         rte_intr_callback_register(&(pci_dev->intr_handle),
 865                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 866
 867         /* enable uio intr after callback register */
 868         rte_intr_enable(&(pci_dev->intr_handle));
 869
 870         /* enable support intr */
 871         ixgbe_enable_intr(eth_dev);
 872
 873         return 0;
 874 }
 875
 876
 877 /*
 878  * Negotiate mailbox API version with the PF.
 879  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 880  * Then we try to negotiate starting with the most recent one.
 881  * If all negotiation attempts fail, then we will proceed with
 882  * the default one (ixgbe_mbox_api_10).
 883  */
 884 static void
 885 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 886 {
 887         int32_t i;
 888
 889         /* start with highest supported, proceed down */
 890         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 891                 ixgbe_mbox_api_11,
 892                 ixgbe_mbox_api_10,
 893         };
 894
 895         for (i = 0;
 896                         i != RTE_DIM(sup_ver) &&
 897                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 898                         i++)
 899                 ;
 900 }
 901
 902 static void
 903 generate_random_mac_addr(struct ether_addr *mac_addr)
 904 {
 905         uint64_t random;
 906
 907         /* Set Organizationally Unique Identifier (OUI) prefix. */
 908         mac_addr->addr_bytes[0] = 0x00;
 909         mac_addr->addr_bytes[1] = 0x09;
 910         mac_addr->addr_bytes[2] = 0xC0;
 911         /* Force indication of locally assigned MAC address. */
 912         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 913         /* Generate the last 3 bytes of the MAC address with a random number. */
 914         random = rte_rand();
 915         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 916 }
 917
 918 /*
 919  * Virtual Function device init
 920  */
 921 static int
 922 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 923                      struct rte_eth_dev *eth_dev)
 924 {
 925         int diag;
 926         uint32_t tc, tcs;
 927         struct rte_pci_device *pci_dev;
 928         struct ixgbe_hw *hw =
 929                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 930         struct ixgbe_vfta * shadow_vfta =
 931                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 932         struct ixgbe_hwstrip *hwstrip =
 933                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 934         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 935
 936         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 937
 938         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 939         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 940         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 941
 942         /* for secondary processes, we don't initialise any further as primary
 943          * has already done this work. Only check we don't need a different
 944          * RX function */
 945         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 946                 if (eth_dev->data->scattered_rx)
 947                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 948                 return 0;
 949         }
 950
 951         pci_dev = eth_dev->pci_dev;
 952
 953         hw->device_id = pci_dev->id.device_id;
 954         hw->vendor_id = pci_dev->id.vendor_id;
 955         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 956
 957         /* initialize the vfta */
 958         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 959
 960         /* initialize the hw strip bitmap*/
 961         memset(hwstrip, 0, sizeof(*hwstrip));
 962
 963         /* Initialize the shared code (base driver) */
 964         diag = ixgbe_init_shared_code(hw);
 965         if (diag != IXGBE_SUCCESS) {
 966                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 967                 return -EIO;
 968         }
 969
 970         /* init_mailbox_params */
 971         hw->mbx.ops.init_params(hw);
 972
 973         /* Disable the interrupts for VF */
 974         ixgbevf_intr_disable(hw);
 975
 976         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
 977         diag = hw->mac.ops.reset_hw(hw);
 978
 979         /*
 980          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
 981          * the underlying PF driver has not assigned a MAC address to the VF.
 982          * In this case, assign a random MAC address.
 983          */
 984         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
 985                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 986                 return (diag);
 987         }
 988
 989         /* negotiate mailbox API version to use with the PF. */
 990         ixgbevf_negotiate_api(hw);
 991
 992         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
 993         ixgbevf_get_queues(hw, &tcs, &tc);
 994
 995         /* Allocate memory for storing MAC addresses */
 996         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 997                         hw->mac.num_rar_entries, 0);
 998         if (eth_dev->data->mac_addrs == NULL) {
 999                 PMD_INIT_LOG(ERR,
1000                         "Failed to allocate %u bytes needed to store "
1001                         "MAC addresses",
1002                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1003                 return -ENOMEM;
1004         }
1005
1006         /* Generate a random MAC address, if none was assigned by PF. */
1007         if (is_zero_ether_addr(perm_addr)) {
1008                 generate_random_mac_addr(perm_addr);
1009                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1010                 if (diag) {
1011                         rte_free(eth_dev->data->mac_addrs);
1012                         eth_dev->data->mac_addrs = NULL;
1013                         return diag;
1014                 }
1015                 RTE_LOG(INFO, PMD,
1016                         "\tVF MAC address not assigned by Host PF\n"
1017                         "\tAssign randomly generated MAC address "
1018                         "%02x:%02x:%02x:%02x:%02x:%02x\n",
1019                         perm_addr->addr_bytes[0],
1020                         perm_addr->addr_bytes[1],
1021                         perm_addr->addr_bytes[2],
1022                         perm_addr->addr_bytes[3],
1023                         perm_addr->addr_bytes[4],
1024                         perm_addr->addr_bytes[5]);
1025         }
1026
1027         /* Copy the permanent MAC address */
1028         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1029
1030         /* reset the hardware with the new settings */
1031         diag = hw->mac.ops.start_hw(hw);
1032         switch (diag) {
1033                 case  0:
1034                         break;
1035
1036                 default:
1037                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1038                         return (-EIO);
1039         }
1040
1041         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
1042                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
1043                          "ixgbe_mac_82599_vf");
1044
1045         return 0;
1046 }
1047
1048 static struct eth_driver rte_ixgbe_pmd = {
1049         {
1050                 .name = "rte_ixgbe_pmd",
1051                 .id_table = pci_id_ixgbe_map,
1052                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1053         },
1054         .eth_dev_init = eth_ixgbe_dev_init,
1055         .dev_private_size = sizeof(struct ixgbe_adapter),
1056 };
1057
1058 /*
1059  * virtual function driver struct
1060  */
1061 static struct eth_driver rte_ixgbevf_pmd = {
1062         {
1063                 .name = "rte_ixgbevf_pmd",
1064                 .id_table = pci_id_ixgbevf_map,
1065                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1066         },
1067         .eth_dev_init = eth_ixgbevf_dev_init,
1068         .dev_private_size = sizeof(struct ixgbe_adapter),
1069 };
1070
1071 /*
1072  * Driver initialization routine.
1073  * Invoked once at EAL init time.
1074  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1075  */
1076 static int
1077 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1078 {
1079         PMD_INIT_FUNC_TRACE();
1080
1081         rte_eth_driver_register(&rte_ixgbe_pmd);
1082         return 0;
1083 }
1084
1085 /*
1086  * VF Driver initialization routine.
1087  * Invoked one at EAL init time.
1088  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1089  */
1090 static int
1091 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1092 {
1093         DEBUGFUNC("rte_ixgbevf_pmd_init");
1094
1095         rte_eth_driver_register(&rte_ixgbevf_pmd);
1096         return (0);
1097 }
1098
1099 static int
1100 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1101 {
1102         struct ixgbe_hw *hw =
1103                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1104         struct ixgbe_vfta * shadow_vfta =
1105                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1106         uint32_t vfta;
1107         uint32_t vid_idx;
1108         uint32_t vid_bit;
1109
1110         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1111         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1112         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1113         if (on)
1114                 vfta |= vid_bit;
1115         else
1116                 vfta &= ~vid_bit;
1117         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1118
1119         /* update local VFTA copy */
1120         shadow_vfta->vfta[vid_idx] = vfta;
1121
1122         return 0;
1123 }
1124
1125 static void
1126 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1127 {
1128         if (on)
1129                 ixgbe_vlan_hw_strip_enable(dev, queue);
1130         else
1131                 ixgbe_vlan_hw_strip_disable(dev, queue);
1132 }
1133
1134 static void
1135 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1136 {
1137         struct ixgbe_hw *hw =
1138                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1139
1140         /* Only the high 16-bits is valid */
1141         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1142 }
1143
1144 void
1145 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1146 {
1147         struct ixgbe_hw *hw =
1148                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1149         uint32_t vlnctrl;
1150
1151         PMD_INIT_FUNC_TRACE();
1152
1153         /* Filter Table Disable */
1154         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1155         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1156
1157         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1158 }
1159
1160 void
1161 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1162 {
1163         struct ixgbe_hw *hw =
1164                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1165         struct ixgbe_vfta * shadow_vfta =
1166                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1167         uint32_t vlnctrl;
1168         uint16_t i;
1169
1170         PMD_INIT_FUNC_TRACE();
1171
1172         /* Filter Table Enable */
1173         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1174         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1175         vlnctrl |= IXGBE_VLNCTRL_VFE;
1176
1177         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1178
1179         /* write whatever is in local vfta copy */
1180         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1181                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1182 }
1183
1184 static void
1185 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1186 {
1187         struct ixgbe_hwstrip *hwstrip =
1188                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1189
1190         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1191                 return;
1192
1193         if (on)
1194                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1195         else
1196                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1197 }
1198
1199 static void
1200 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1201 {
1202         struct ixgbe_hw *hw =
1203                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204         uint32_t ctrl;
1205
1206         PMD_INIT_FUNC_TRACE();
1207
1208         if (hw->mac.type == ixgbe_mac_82598EB) {
1209                 /* No queue level support */
1210                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1211                 return;
1212         }
1213         else {
1214                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1215                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1216                 ctrl &= ~IXGBE_RXDCTL_VME;
1217                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1218         }
1219         /* record those setting for HW strip per queue */
1220         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1221 }
1222
1223 static void
1224 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1225 {
1226         struct ixgbe_hw *hw =
1227                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1228         uint32_t ctrl;
1229
1230         PMD_INIT_FUNC_TRACE();
1231
1232         if (hw->mac.type == ixgbe_mac_82598EB) {
1233                 /* No queue level supported */
1234                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1235                 return;
1236         }
1237         else {
1238                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1239                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1240                 ctrl |= IXGBE_RXDCTL_VME;
1241                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1242         }
1243         /* record those setting for HW strip per queue */
1244         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1245 }
1246
1247 void
1248 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1249 {
1250         struct ixgbe_hw *hw =
1251                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1252         uint32_t ctrl;
1253         uint16_t i;
1254
1255         PMD_INIT_FUNC_TRACE();
1256
1257         if (hw->mac.type == ixgbe_mac_82598EB) {
1258                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1259                 ctrl &= ~IXGBE_VLNCTRL_VME;
1260                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1261         }
1262         else {
1263                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1264                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1265                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1266                         ctrl &= ~IXGBE_RXDCTL_VME;
1267                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1268
1269                         /* record those setting for HW strip per queue */
1270                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1271                 }
1272         }
1273 }
1274
1275 void
1276 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1277 {
1278         struct ixgbe_hw *hw =
1279                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1280         uint32_t ctrl;
1281         uint16_t i;
1282
1283         PMD_INIT_FUNC_TRACE();
1284
1285         if (hw->mac.type == ixgbe_mac_82598EB) {
1286                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1287                 ctrl |= IXGBE_VLNCTRL_VME;
1288                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1289         }
1290         else {
1291                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1292                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1293                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1294                         ctrl |= IXGBE_RXDCTL_VME;
1295                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1296
1297                         /* record those setting for HW strip per queue */
1298                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1299                 }
1300         }
1301 }
1302
1303 static void
1304 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1305 {
1306         struct ixgbe_hw *hw =
1307                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308         uint32_t ctrl;
1309
1310         PMD_INIT_FUNC_TRACE();
1311
1312         /* DMATXCTRL: Geric Double VLAN Disable */
1313         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1314         ctrl &= ~IXGBE_DMATXCTL_GDV;
1315         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1316
1317         /* CTRL_EXT: Global Double VLAN Disable */
1318         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1319         ctrl &= ~IXGBE_EXTENDED_VLAN;
1320         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1321
1322 }
1323
1324 static void
1325 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1326 {
1327         struct ixgbe_hw *hw =
1328                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1329         uint32_t ctrl;
1330
1331         PMD_INIT_FUNC_TRACE();
1332
1333         /* DMATXCTRL: Geric Double VLAN Enable */
1334         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1335         ctrl |= IXGBE_DMATXCTL_GDV;
1336         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1337
1338         /* CTRL_EXT: Global Double VLAN Enable */
1339         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1340         ctrl |= IXGBE_EXTENDED_VLAN;
1341         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1342
1343         /*
1344          * VET EXT field in the EXVET register = 0x8100 by default
1345          * So no need to change. Same to VT field of DMATXCTL register
1346          */
1347 }
1348
1349 static void
1350 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1351 {
1352         if(mask & ETH_VLAN_STRIP_MASK){
1353                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1354                         ixgbe_vlan_hw_strip_enable_all(dev);
1355                 else
1356                         ixgbe_vlan_hw_strip_disable_all(dev);
1357         }
1358
1359         if(mask & ETH_VLAN_FILTER_MASK){
1360                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1361                         ixgbe_vlan_hw_filter_enable(dev);
1362                 else
1363                         ixgbe_vlan_hw_filter_disable(dev);
1364         }
1365
1366         if(mask & ETH_VLAN_EXTEND_MASK){
1367                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1368                         ixgbe_vlan_hw_extend_enable(dev);
1369                 else
1370                         ixgbe_vlan_hw_extend_disable(dev);
1371         }
1372 }
1373
1374 static void
1375 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1376 {
1377         struct ixgbe_hw *hw =
1378                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1379         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1380         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1381         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1382         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1383 }
1384
1385 static int
1386 ixgbe_dev_configure(struct rte_eth_dev *dev)
1387 {
1388         struct ixgbe_interrupt *intr =
1389                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1390
1391         PMD_INIT_FUNC_TRACE();
1392
1393         /* set flag to update link status after init */
1394         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1395
1396         return 0;
1397 }
1398
1399 /*
1400  * Configure device link speed and setup link.
1401  * It returns 0 on success.
1402  */
1403 static int
1404 ixgbe_dev_start(struct rte_eth_dev *dev)
1405 {
1406         struct ixgbe_hw *hw =
1407                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1408         struct ixgbe_vf_info *vfinfo =
1409                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1410         int err, link_up = 0, negotiate = 0;
1411         uint32_t speed = 0;
1412         int mask = 0;
1413         int status;
1414         uint16_t vf, idx;
1415
1416         PMD_INIT_FUNC_TRACE();
1417
1418         /* IXGBE devices don't support half duplex */
1419         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1420                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1421                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1422                                 dev->data->dev_conf.link_duplex,
1423                                 dev->data->port_id);
1424                 return -EINVAL;
1425         }
1426
1427         /* stop adapter */
1428         hw->adapter_stopped = FALSE;
1429         ixgbe_stop_adapter(hw);
1430
1431         /* reinitialize adapter
1432          * this calls reset and start */
1433         status = ixgbe_pf_reset_hw(hw);
1434         if (status != 0)
1435                 return -1;
1436         hw->mac.ops.start_hw(hw);
1437
1438         /* configure PF module if SRIOV enabled */
1439         ixgbe_pf_host_configure(dev);
1440
1441         /* initialize transmission unit */
1442         ixgbe_dev_tx_init(dev);
1443
1444         /* This can fail when allocating mbufs for descriptor rings */
1445         err = ixgbe_dev_rx_init(dev);
1446         if (err) {
1447                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1448                 goto error;
1449         }
1450
1451         ixgbe_dev_rxtx_start(dev);
1452
1453         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1454                 err = hw->mac.ops.setup_sfp(hw);
1455                 if (err)
1456                         goto error;
1457         }
1458
1459         /* Turn on the laser */
1460         ixgbe_enable_tx_laser(hw);
1461
1462         /* Skip link setup if loopback mode is enabled for 82599. */
1463         if (hw->mac.type == ixgbe_mac_82599EB &&
1464                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1465                 goto skip_link_setup;
1466
1467         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1468         if (err)
1469                 goto error;
1470         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1471         if (err)
1472                 goto error;
1473
1474         switch(dev->data->dev_conf.link_speed) {
1475         case ETH_LINK_SPEED_AUTONEG:
1476                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1477                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1478                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1479                 break;
1480         case ETH_LINK_SPEED_100:
1481                 /*
1482                  * Invalid for 82598 but error will be detected by
1483                  * ixgbe_setup_link()
1484                  */
1485                 speed = IXGBE_LINK_SPEED_100_FULL;
1486                 break;
1487         case ETH_LINK_SPEED_1000:
1488                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1489                 break;
1490         case ETH_LINK_SPEED_10000:
1491                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1492                 break;
1493         default:
1494                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1495                                 dev->data->dev_conf.link_speed,
1496                                 dev->data->port_id);
1497                 goto error;
1498         }
1499
1500         err = ixgbe_setup_link(hw, speed, link_up);
1501         if (err)
1502                 goto error;
1503
1504 skip_link_setup:
1505
1506         /* check if lsc interrupt is enabled */
1507         if (dev->data->dev_conf.intr_conf.lsc != 0)
1508                 ixgbe_dev_lsc_interrupt_setup(dev);
1509
1510         /* resume enabled intr since hw reset */
1511         ixgbe_enable_intr(dev);
1512
1513         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1514                 ETH_VLAN_EXTEND_MASK;
1515         ixgbe_vlan_offload_set(dev, mask);
1516
1517         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1518                 /* Enable vlan filtering for VMDq */
1519                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1520         }
1521
1522         /* Configure DCB hw */
1523         ixgbe_configure_dcb(dev);
1524
1525         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1526                 err = ixgbe_fdir_configure(dev);
1527                 if (err)
1528                         goto error;
1529         }
1530
1531         /* Restore vf rate limit */
1532         if (vfinfo != NULL) {
1533                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1534                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1535                                 if (vfinfo[vf].tx_rate[idx] != 0)
1536                                         ixgbe_set_vf_rate_limit(dev, vf,
1537                                                 vfinfo[vf].tx_rate[idx],
1538                                                 1 << idx);
1539         }
1540
1541         ixgbe_restore_statistics_mapping(dev);
1542
1543         return (0);
1544
1545 error:
1546         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1547         ixgbe_dev_clear_queues(dev);
1548         return -EIO;
1549 }
1550
1551 /*
1552  * Stop device: disable rx and tx functions to allow for reconfiguring.
1553  */
1554 static void
1555 ixgbe_dev_stop(struct rte_eth_dev *dev)
1556 {
1557         struct rte_eth_link link;
1558         struct ixgbe_hw *hw =
1559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560         struct ixgbe_vf_info *vfinfo =
1561                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1562         int vf;
1563
1564         PMD_INIT_FUNC_TRACE();
1565
1566         /* disable interrupts */
1567         ixgbe_disable_intr(hw);
1568
1569         /* reset the NIC */
1570         ixgbe_pf_reset_hw(hw);
1571         hw->adapter_stopped = FALSE;
1572
1573         /* stop adapter */
1574         ixgbe_stop_adapter(hw);
1575
1576         for (vf = 0; vfinfo != NULL &&
1577                      vf < dev->pci_dev->max_vfs; vf++)
1578                 vfinfo[vf].clear_to_send = false;
1579
1580         /* Turn off the laser */
1581         ixgbe_disable_tx_laser(hw);
1582
1583         ixgbe_dev_clear_queues(dev);
1584
1585         /* Clear recorded link status */
1586         memset(&link, 0, sizeof(link));
1587         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1588 }
1589
1590 /*
1591  * Set device link up: enable tx laser.
1592  */
1593 static int
1594 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         if (hw->mac.type == ixgbe_mac_82599EB) {
1599 #ifdef RTE_NIC_BYPASS
1600                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1601                         /* Not suported in bypass mode */
1602                         PMD_INIT_LOG(ERR,
1603                                 "\nSet link up is not supported "
1604                                 "by device id 0x%x\n",
1605                                 hw->device_id);
1606                         return -ENOTSUP;
1607                 }
1608 #endif
1609                 /* Turn on the laser */
1610                 ixgbe_enable_tx_laser(hw);
1611                 return 0;
1612         }
1613
1614         PMD_INIT_LOG(ERR, "\nSet link up is not supported by device id 0x%x\n",
1615                 hw->device_id);
1616         return -ENOTSUP;
1617 }
1618
1619 /*
1620  * Set device link down: disable tx laser.
1621  */
1622 static int
1623 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1624 {
1625         struct ixgbe_hw *hw =
1626                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1627         if (hw->mac.type == ixgbe_mac_82599EB) {
1628 #ifdef RTE_NIC_BYPASS
1629                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1630                         /* Not suported in bypass mode */
1631                         PMD_INIT_LOG(ERR,
1632                                 "\nSet link down is not supported "
1633                                 "by device id 0x%x\n",
1634                                  hw->device_id);
1635                         return -ENOTSUP;
1636                 }
1637 #endif
1638                 /* Turn off the laser */
1639                 ixgbe_disable_tx_laser(hw);
1640                 return 0;
1641         }
1642
1643         PMD_INIT_LOG(ERR,
1644                 "\nSet link down is not supported by device id 0x%x\n",
1645                  hw->device_id);
1646         return -ENOTSUP;
1647 }
1648
1649 /*
1650  * Reest and stop device.
1651  */
1652 static void
1653 ixgbe_dev_close(struct rte_eth_dev *dev)
1654 {
1655         struct ixgbe_hw *hw =
1656                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657
1658         PMD_INIT_FUNC_TRACE();
1659
1660         ixgbe_pf_reset_hw(hw);
1661
1662         ixgbe_dev_stop(dev);
1663         hw->adapter_stopped = 1;
1664
1665         ixgbe_disable_pcie_master(hw);
1666
1667         /* reprogram the RAR[0] in case user changed it. */
1668         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1669 }
1670
1671 /*
1672  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1673  */
1674 static void
1675 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1676 {
1677         struct ixgbe_hw *hw =
1678                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679         struct ixgbe_hw_stats *hw_stats =
1680                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1681         uint32_t bprc, lxon, lxoff, total;
1682         uint64_t total_missed_rx, total_qbrc, total_qprc;
1683         unsigned i;
1684
1685         total_missed_rx = 0;
1686         total_qbrc = 0;
1687         total_qprc = 0;
1688
1689         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1690         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1691         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1692         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1693
1694         for (i = 0; i < 8; i++) {
1695                 uint32_t mp;
1696                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1697                 /* global total per queue */
1698                 hw_stats->mpc[i] += mp;
1699                 /* Running comprehensive total for stats display */
1700                 total_missed_rx += hw_stats->mpc[i];
1701                 if (hw->mac.type == ixgbe_mac_82598EB)
1702                         hw_stats->rnbc[i] +=
1703                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1704                 hw_stats->pxontxc[i] +=
1705                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1706                 hw_stats->pxonrxc[i] +=
1707                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1708                 hw_stats->pxofftxc[i] +=
1709                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1710                 hw_stats->pxoffrxc[i] +=
1711                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1712                 hw_stats->pxon2offc[i] +=
1713                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1714         }
1715         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1716                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1717                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1718                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1719                 hw_stats->qbrc[i] +=
1720                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1721                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1722                 hw_stats->qbtc[i] +=
1723                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1724                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1725
1726                 total_qprc += hw_stats->qprc[i];
1727                 total_qbrc += hw_stats->qbrc[i];
1728         }
1729         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1730         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1731         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1732
1733         /* Note that gprc counts missed packets */
1734         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1735
1736         if (hw->mac.type != ixgbe_mac_82598EB) {
1737                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1738                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1739                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1740                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1741                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1742                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1743                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1744                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1745         } else {
1746                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1747                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1748                 /* 82598 only has a counter in the high register */
1749                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1750                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1751                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1752         }
1753
1754         /*
1755          * Workaround: mprc hardware is incorrectly counting
1756          * broadcasts, so for now we subtract those.
1757          */
1758         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1759         hw_stats->bprc += bprc;
1760         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1761         if (hw->mac.type == ixgbe_mac_82598EB)
1762                 hw_stats->mprc -= bprc;
1763
1764         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1765         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1766         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1767         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1768         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1769         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1770
1771         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1772         hw_stats->lxontxc += lxon;
1773         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1774         hw_stats->lxofftxc += lxoff;
1775         total = lxon + lxoff;
1776
1777         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1778         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1779         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1780         hw_stats->gptc -= total;
1781         hw_stats->mptc -= total;
1782         hw_stats->ptc64 -= total;
1783         hw_stats->gotc -= total * ETHER_MIN_LEN;
1784
1785         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1786         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1787         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1788         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1789         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1790         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1791         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1792         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1793         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1794         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1795         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1796         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1797         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1798         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1799         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1800         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1801         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1802         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1803         /* Only read FCOE on 82599 */
1804         if (hw->mac.type != ixgbe_mac_82598EB) {
1805                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1806                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1807                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1808                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1809                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1810         }
1811
1812         if (stats == NULL)
1813                 return;
1814
1815         /* Fill out the rte_eth_stats statistics structure */
1816         stats->ipackets = total_qprc;
1817         stats->ibytes = total_qbrc;
1818         stats->opackets = hw_stats->gptc;
1819         stats->obytes = hw_stats->gotc;
1820         stats->imcasts = hw_stats->mprc;
1821
1822         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1823                 stats->q_ipackets[i] = hw_stats->qprc[i];
1824                 stats->q_opackets[i] = hw_stats->qptc[i];
1825                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1826                 stats->q_obytes[i] = hw_stats->qbtc[i];
1827                 stats->q_errors[i] = hw_stats->qprdc[i];
1828         }
1829
1830         /* Rx Errors */
1831         stats->ibadcrc  = hw_stats->crcerrs;
1832         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1833         stats->imissed  = total_missed_rx;
1834         stats->ierrors  = stats->ibadcrc +
1835                           stats->ibadlen +
1836                           stats->imissed +
1837                           hw_stats->illerrc + hw_stats->errbc;
1838
1839         /* Tx Errors */
1840         stats->oerrors  = 0;
1841
1842         /* XON/XOFF pause frames */
1843         stats->tx_pause_xon  = hw_stats->lxontxc;
1844         stats->rx_pause_xon  = hw_stats->lxonrxc;
1845         stats->tx_pause_xoff = hw_stats->lxofftxc;
1846         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1847
1848         /* Flow Director Stats registers */
1849         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1850         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1851         stats->fdirmatch = hw_stats->fdirmatch;
1852         stats->fdirmiss = hw_stats->fdirmiss;
1853 }
1854
1855 static void
1856 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1857 {
1858         struct ixgbe_hw_stats *stats =
1859                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1860
1861         /* HW registers are cleared on read */
1862         ixgbe_dev_stats_get(dev, NULL);
1863
1864         /* Reset software totals */
1865         memset(stats, 0, sizeof(*stats));
1866 }
1867
1868 static void
1869 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1870 {
1871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1873                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1874
1875         /* Good Rx packet, include VF loopback */
1876         UPDATE_VF_STAT(IXGBE_VFGPRC,
1877             hw_stats->last_vfgprc, hw_stats->vfgprc);
1878
1879         /* Good Rx octets, include VF loopback */
1880         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1881             hw_stats->last_vfgorc, hw_stats->vfgorc);
1882
1883         /* Good Tx packet, include VF loopback */
1884         UPDATE_VF_STAT(IXGBE_VFGPTC,
1885             hw_stats->last_vfgptc, hw_stats->vfgptc);
1886
1887         /* Good Tx octets, include VF loopback */
1888         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1889             hw_stats->last_vfgotc, hw_stats->vfgotc);
1890
1891         /* Rx Multicst Packet */
1892         UPDATE_VF_STAT(IXGBE_VFMPRC,
1893             hw_stats->last_vfmprc, hw_stats->vfmprc);
1894
1895         if (stats == NULL)
1896                 return;
1897
1898         memset(stats, 0, sizeof(*stats));
1899         stats->ipackets = hw_stats->vfgprc;
1900         stats->ibytes = hw_stats->vfgorc;
1901         stats->opackets = hw_stats->vfgptc;
1902         stats->obytes = hw_stats->vfgotc;
1903         stats->imcasts = hw_stats->vfmprc;
1904 }
1905
1906 static void
1907 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1908 {
1909         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1910                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1911
1912         /* Sync HW register to the last stats */
1913         ixgbevf_dev_stats_get(dev, NULL);
1914
1915         /* reset HW current stats*/
1916         hw_stats->vfgprc = 0;
1917         hw_stats->vfgorc = 0;
1918         hw_stats->vfgptc = 0;
1919         hw_stats->vfgotc = 0;
1920         hw_stats->vfmprc = 0;
1921
1922 }
1923
1924 static void
1925 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1926 {
1927         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928
1929         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1930         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1931         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1932         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1933         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1934         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1935         dev_info->max_vfs = dev->pci_dev->max_vfs;
1936         if (hw->mac.type == ixgbe_mac_82598EB)
1937                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1938         else
1939                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1940         dev_info->rx_offload_capa =
1941                 DEV_RX_OFFLOAD_VLAN_STRIP |
1942                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1943                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1944                 DEV_RX_OFFLOAD_TCP_CKSUM;
1945         dev_info->tx_offload_capa =
1946                 DEV_TX_OFFLOAD_VLAN_INSERT |
1947                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1948                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1949                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1950                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1951 }
1952
1953 /* return 0 means link status changed, -1 means not changed */
1954 static int
1955 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1956 {
1957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958         struct rte_eth_link link, old;
1959         ixgbe_link_speed link_speed;
1960         int link_up;
1961         int diag;
1962
1963         link.link_status = 0;
1964         link.link_speed = 0;
1965         link.link_duplex = 0;
1966         memset(&old, 0, sizeof(old));
1967         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1968
1969         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1970         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1971                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1972         else
1973                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1974         if (diag != 0) {
1975                 link.link_speed = ETH_LINK_SPEED_100;
1976                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1977                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1978                 if (link.link_status == old.link_status)
1979                         return -1;
1980                 return 0;
1981         }
1982
1983         if (link_up == 0) {
1984                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1985                 if (link.link_status == old.link_status)
1986                         return -1;
1987                 return 0;
1988         }
1989         link.link_status = 1;
1990         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1991
1992         switch (link_speed) {
1993         default:
1994         case IXGBE_LINK_SPEED_UNKNOWN:
1995                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1996                 link.link_speed = ETH_LINK_SPEED_100;
1997                 break;
1998
1999         case IXGBE_LINK_SPEED_100_FULL:
2000                 link.link_speed = ETH_LINK_SPEED_100;
2001                 break;
2002
2003         case IXGBE_LINK_SPEED_1GB_FULL:
2004                 link.link_speed = ETH_LINK_SPEED_1000;
2005                 break;
2006
2007         case IXGBE_LINK_SPEED_10GB_FULL:
2008                 link.link_speed = ETH_LINK_SPEED_10000;
2009                 break;
2010         }
2011         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2012
2013         if (link.link_status == old.link_status)
2014                 return -1;
2015
2016         return 0;
2017 }
2018
2019 static void
2020 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2021 {
2022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023         uint32_t fctrl;
2024
2025         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2026         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2027         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2028 }
2029
2030 static void
2031 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2032 {
2033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2034         uint32_t fctrl;
2035
2036         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2037         fctrl &= (~IXGBE_FCTRL_UPE);
2038         if (dev->data->all_multicast == 1)
2039                 fctrl |= IXGBE_FCTRL_MPE;
2040         else
2041                 fctrl &= (~IXGBE_FCTRL_MPE);
2042         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2043 }
2044
2045 static void
2046 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2047 {
2048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049         uint32_t fctrl;
2050
2051         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2052         fctrl |= IXGBE_FCTRL_MPE;
2053         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2054 }
2055
2056 static void
2057 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2058 {
2059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         uint32_t fctrl;
2061
2062         if (dev->data->promiscuous == 1)
2063                 return; /* must remain in all_multicast mode */
2064
2065         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2066         fctrl &= (~IXGBE_FCTRL_MPE);
2067         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2068 }
2069
2070 /**
2071  * It clears the interrupt causes and enables the interrupt.
2072  * It will be called once only during nic initialized.
2073  *
2074  * @param dev
2075  *  Pointer to struct rte_eth_dev.
2076  *
2077  * @return
2078  *  - On success, zero.
2079  *  - On failure, a negative value.
2080  */
2081 static int
2082 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2083 {
2084         struct ixgbe_interrupt *intr =
2085                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2086
2087         ixgbe_dev_link_status_print(dev);
2088         intr->mask |= IXGBE_EICR_LSC;
2089
2090         return 0;
2091 }
2092
2093 /*
2094  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2095  *
2096  * @param dev
2097  *  Pointer to struct rte_eth_dev.
2098  *
2099  * @return
2100  *  - On success, zero.
2101  *  - On failure, a negative value.
2102  */
2103 static int
2104 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2105 {
2106         uint32_t eicr;
2107         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2108         struct ixgbe_interrupt *intr =
2109                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2110
2111         /* clear all cause mask */
2112         ixgbe_disable_intr(hw);
2113
2114         /* read-on-clear nic registers here */
2115         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2116         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2117
2118         intr->flags = 0;
2119         if (eicr & IXGBE_EICR_LSC) {
2120                 /* set flag for async link update */
2121                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2122         }
2123
2124         if (eicr & IXGBE_EICR_MAILBOX)
2125                 intr->flags |= IXGBE_FLAG_MAILBOX;
2126
2127         return 0;
2128 }
2129
2130 /**
2131  * It gets and then prints the link status.
2132  *
2133  * @param dev
2134  *  Pointer to struct rte_eth_dev.
2135  *
2136  * @return
2137  *  - On success, zero.
2138  *  - On failure, a negative value.
2139  */
2140 static void
2141 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2142 {
2143         struct rte_eth_link link;
2144
2145         memset(&link, 0, sizeof(link));
2146         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2147         if (link.link_status) {
2148                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2149                                         (int)(dev->data->port_id),
2150                                         (unsigned)link.link_speed,
2151                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2152                                         "full-duplex" : "half-duplex");
2153         } else {
2154                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2155                                 (int)(dev->data->port_id));
2156         }
2157         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2158                                 dev->pci_dev->addr.domain,
2159                                 dev->pci_dev->addr.bus,
2160                                 dev->pci_dev->addr.devid,
2161                                 dev->pci_dev->addr.function);
2162 }
2163
2164 /*
2165  * It executes link_update after knowing an interrupt occurred.
2166  *
2167  * @param dev
2168  *  Pointer to struct rte_eth_dev.
2169  *
2170  * @return
2171  *  - On success, zero.
2172  *  - On failure, a negative value.
2173  */
2174 static int
2175 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2176 {
2177         struct ixgbe_interrupt *intr =
2178                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2179         int64_t timeout;
2180         struct rte_eth_link link;
2181         int intr_enable_delay = false;
2182
2183         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
2184
2185         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2186                 ixgbe_pf_mbx_process(dev);
2187                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2188         }
2189
2190         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2191                 /* get the link status before link update, for predicting later */
2192                 memset(&link, 0, sizeof(link));
2193                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2194
2195                 ixgbe_dev_link_update(dev, 0);
2196
2197                 /* likely to up */
2198                 if (!link.link_status)
2199                         /* handle it 1 sec later, wait it being stable */
2200                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2201                 /* likely to down */
2202                 else
2203                         /* handle it 4 sec later, wait it being stable */
2204                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2205
2206                 ixgbe_dev_link_status_print(dev);
2207
2208                 intr_enable_delay = true;
2209         }
2210
2211         if (intr_enable_delay) {
2212                 if (rte_eal_alarm_set(timeout * 1000,
2213                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2214                         PMD_DRV_LOG(ERR, "Error setting alarm");
2215         } else {
2216                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2217                 ixgbe_enable_intr(dev);
2218                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2219         }
2220
2221
2222         return 0;
2223 }
2224
2225 /**
2226  * Interrupt handler which shall be registered for alarm callback for delayed
2227  * handling specific interrupt to wait for the stable nic state. As the
2228  * NIC interrupt state is not stable for ixgbe after link is just down,
2229  * it needs to wait 4 seconds to get the stable status.
2230  *
2231  * @param handle
2232  *  Pointer to interrupt handle.
2233  * @param param
2234  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2235  *
2236  * @return
2237  *  void
2238  */
2239 static void
2240 ixgbe_dev_interrupt_delayed_handler(void *param)
2241 {
2242         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2243         struct ixgbe_interrupt *intr =
2244                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2245         struct ixgbe_hw *hw =
2246                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247         uint32_t eicr;
2248
2249         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2250         if (eicr & IXGBE_EICR_MAILBOX)
2251                 ixgbe_pf_mbx_process(dev);
2252
2253         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2254                 ixgbe_dev_link_update(dev, 0);
2255                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2256                 ixgbe_dev_link_status_print(dev);
2257                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2258         }
2259
2260         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2261         ixgbe_enable_intr(dev);
2262         rte_intr_enable(&(dev->pci_dev->intr_handle));
2263 }
2264
2265 /**
2266  * Interrupt handler triggered by NIC  for handling
2267  * specific interrupt.
2268  *
2269  * @param handle
2270  *  Pointer to interrupt handle.
2271  * @param param
2272  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2273  *
2274  * @return
2275  *  void
2276  */
2277 static void
2278 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2279                                                         void *param)
2280 {
2281         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2282         ixgbe_dev_interrupt_get_status(dev);
2283         ixgbe_dev_interrupt_action(dev);
2284 }
2285
2286 static int
2287 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2288 {
2289         struct ixgbe_hw *hw;
2290
2291         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2292         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2293 }
2294
2295 static int
2296 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2297 {
2298         struct ixgbe_hw *hw;
2299
2300         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2301         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2302 }
2303
2304 static int
2305 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2306 {
2307         struct ixgbe_hw *hw;
2308         uint32_t mflcn_reg;
2309         uint32_t fccfg_reg;
2310         int rx_pause;
2311         int tx_pause;
2312
2313         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314
2315         fc_conf->pause_time = hw->fc.pause_time;
2316         fc_conf->high_water = hw->fc.high_water[0];
2317         fc_conf->low_water = hw->fc.low_water[0];
2318         fc_conf->send_xon = hw->fc.send_xon;
2319         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2320
2321         /*
2322          * Return rx_pause status according to actual setting of
2323          * MFLCN register.
2324          */
2325         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2326         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2327                 rx_pause = 1;
2328         else
2329                 rx_pause = 0;
2330
2331         /*
2332          * Return tx_pause status according to actual setting of
2333          * FCCFG register.
2334          */
2335         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2336         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2337                 tx_pause = 1;
2338         else
2339                 tx_pause = 0;
2340
2341         if (rx_pause && tx_pause)
2342                 fc_conf->mode = RTE_FC_FULL;
2343         else if (rx_pause)
2344                 fc_conf->mode = RTE_FC_RX_PAUSE;
2345         else if (tx_pause)
2346                 fc_conf->mode = RTE_FC_TX_PAUSE;
2347         else
2348                 fc_conf->mode = RTE_FC_NONE;
2349
2350         return 0;
2351 }
2352
2353 static int
2354 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2355 {
2356         struct ixgbe_hw *hw;
2357         int err;
2358         uint32_t rx_buf_size;
2359         uint32_t max_high_water;
2360         uint32_t mflcn;
2361         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2362                 ixgbe_fc_none,
2363                 ixgbe_fc_rx_pause,
2364                 ixgbe_fc_tx_pause,
2365                 ixgbe_fc_full
2366         };
2367
2368         PMD_INIT_FUNC_TRACE();
2369
2370         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2371         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2372                 return -ENOTSUP;
2373         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2374         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2375
2376         /*
2377          * At least reserve one Ethernet frame for watermark
2378          * high_water/low_water in kilo bytes for ixgbe
2379          */
2380         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2381         if ((fc_conf->high_water > max_high_water) ||
2382                 (fc_conf->high_water < fc_conf->low_water)) {
2383                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2384                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2385                 return (-EINVAL);
2386         }
2387
2388         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2389         hw->fc.pause_time     = fc_conf->pause_time;
2390         hw->fc.high_water[0]  = fc_conf->high_water;
2391         hw->fc.low_water[0]   = fc_conf->low_water;
2392         hw->fc.send_xon       = fc_conf->send_xon;
2393
2394         err = ixgbe_fc_enable(hw);
2395
2396         /* Not negotiated is not an error case */
2397         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2398
2399                 /* check if we want to forward MAC frames - driver doesn't have native
2400                  * capability to do that, so we'll write the registers ourselves */
2401
2402                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2403
2404                 /* set or clear MFLCN.PMCF bit depending on configuration */
2405                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2406                         mflcn |= IXGBE_MFLCN_PMCF;
2407                 else
2408                         mflcn &= ~IXGBE_MFLCN_PMCF;
2409
2410                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2411                 IXGBE_WRITE_FLUSH(hw);
2412
2413                 return 0;
2414         }
2415
2416         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2417         return -EIO;
2418 }
2419
2420 /**
2421  *  ixgbe_pfc_enable_generic - Enable flow control
2422  *  @hw: pointer to hardware structure
2423  *  @tc_num: traffic class number
2424  *  Enable flow control according to the current settings.
2425  */
2426 static int
2427 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2428 {
2429         int ret_val = 0;
2430         uint32_t mflcn_reg, fccfg_reg;
2431         uint32_t reg;
2432         uint32_t fcrtl, fcrth;
2433         uint8_t i;
2434         uint8_t nb_rx_en;
2435
2436         /* Validate the water mark configuration */
2437         if (!hw->fc.pause_time) {
2438                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2439                 goto out;
2440         }
2441
2442         /* Low water mark of zero causes XOFF floods */
2443         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2444                  /* High/Low water can not be 0 */
2445                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2446                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2447                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2448                         goto out;
2449                 }
2450
2451                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2452                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2453                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2454                         goto out;
2455                 }
2456         }
2457         /* Negotiate the fc mode to use */
2458         ixgbe_fc_autoneg(hw);
2459
2460         /* Disable any previous flow control settings */
2461         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2462         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2463
2464         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2465         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2466
2467         switch (hw->fc.current_mode) {
2468         case ixgbe_fc_none:
2469                 /*
2470                  * If the count of enabled RX Priority Flow control >1,
2471                  * and the TX pause can not be disabled
2472                  */
2473                 nb_rx_en = 0;
2474                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2475                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2476                         if (reg & IXGBE_FCRTH_FCEN)
2477                                 nb_rx_en++;
2478                 }
2479                 if (nb_rx_en > 1)
2480                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2481                 break;
2482         case ixgbe_fc_rx_pause:
2483                 /*
2484                  * Rx Flow control is enabled and Tx Flow control is
2485                  * disabled by software override. Since there really
2486                  * isn't a way to advertise that we are capable of RX
2487                  * Pause ONLY, we will advertise that we support both
2488                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2489                  * disable the adapter's ability to send PAUSE frames.
2490                  */
2491                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2492                 /*
2493                  * If the count of enabled RX Priority Flow control >1,
2494                  * and the TX pause can not be disabled
2495                  */
2496                 nb_rx_en = 0;
2497                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2498                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2499                         if (reg & IXGBE_FCRTH_FCEN)
2500                                 nb_rx_en++;
2501                 }
2502                 if (nb_rx_en > 1)
2503                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2504                 break;
2505         case ixgbe_fc_tx_pause:
2506                 /*
2507                  * Tx Flow control is enabled, and Rx Flow control is
2508                  * disabled by software override.
2509                  */
2510                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2511                 break;
2512         case ixgbe_fc_full:
2513                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2514                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2515                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2516                 break;
2517         default:
2518                 DEBUGOUT("Flow control param set incorrectly\n");
2519                 ret_val = IXGBE_ERR_CONFIG;
2520                 goto out;
2521                 break;
2522         }
2523
2524         /* Set 802.3x based flow control settings. */
2525         mflcn_reg |= IXGBE_MFLCN_DPF;
2526         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2527         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2528
2529         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2530         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2531                 hw->fc.high_water[tc_num]) {
2532                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2533                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2534                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2535         } else {
2536                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2537                 /*
2538                  * In order to prevent Tx hangs when the internal Tx
2539                  * switch is enabled we must set the high water mark
2540                  * to the maximum FCRTH value.  This allows the Tx
2541                  * switch to function even under heavy Rx workloads.
2542                  */
2543                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2544         }
2545         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2546
2547         /* Configure pause time (2 TCs per register) */
2548         reg = hw->fc.pause_time * 0x00010001;
2549         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2550                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2551
2552         /* Configure flow control refresh threshold value */
2553         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2554
2555 out:
2556         return ret_val;
2557 }
2558
2559 static int
2560 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2561 {
2562         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2563         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2564
2565         if(hw->mac.type != ixgbe_mac_82598EB) {
2566                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2567         }
2568         return ret_val;
2569 }
2570
2571 static int
2572 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2573 {
2574         int err;
2575         uint32_t rx_buf_size;
2576         uint32_t max_high_water;
2577         uint8_t tc_num;
2578         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2579         struct ixgbe_hw *hw =
2580                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581         struct ixgbe_dcb_config *dcb_config =
2582                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2583
2584         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2585                 ixgbe_fc_none,
2586                 ixgbe_fc_rx_pause,
2587                 ixgbe_fc_tx_pause,
2588                 ixgbe_fc_full
2589         };
2590
2591         PMD_INIT_FUNC_TRACE();
2592
2593         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2594         tc_num = map[pfc_conf->priority];
2595         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2596         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2597         /*
2598          * At least reserve one Ethernet frame for watermark
2599          * high_water/low_water in kilo bytes for ixgbe
2600          */
2601         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2602         if ((pfc_conf->fc.high_water > max_high_water) ||
2603                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2604                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2605                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2606                 return (-EINVAL);
2607         }
2608
2609         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2610         hw->fc.pause_time = pfc_conf->fc.pause_time;
2611         hw->fc.send_xon = pfc_conf->fc.send_xon;
2612         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2613         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2614
2615         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2616
2617         /* Not negotiated is not an error case */
2618         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2619                 return 0;
2620
2621         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2622         return -EIO;
2623 }
2624
2625 static int
2626 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2627                                 struct rte_eth_rss_reta *reta_conf)
2628 {
2629         uint8_t i,j,mask;
2630         uint32_t reta;
2631         struct ixgbe_hw *hw =
2632                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2633
2634         PMD_INIT_FUNC_TRACE();
2635         /*
2636         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2637         * 128-entries in 32 registers
2638          */
2639         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2640                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2641                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2642                 else
2643                         mask = (uint8_t)((reta_conf->mask_hi >>
2644                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2645                 if (mask != 0) {
2646                         reta = 0;
2647                         if (mask != 0xF)
2648                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2649
2650                         for (j = 0; j < 4; j++) {
2651                                 if (mask & (0x1 << j)) {
2652                                         if (mask != 0xF)
2653                                                 reta &= ~(0xFF << 8 * j);
2654                                         reta |= reta_conf->reta[i + j] << 8*j;
2655                                 }
2656                         }
2657                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2658                 }
2659         }
2660
2661         return 0;
2662 }
2663
2664 static int
2665 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2666                                 struct rte_eth_rss_reta *reta_conf)
2667 {
2668         uint8_t i,j,mask;
2669         uint32_t reta;
2670         struct ixgbe_hw *hw =
2671                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2672
2673         PMD_INIT_FUNC_TRACE();
2674         /*
2675          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2676          * 128-entries in 32 registers
2677          */
2678         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2679                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2680                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2681                 else
2682                         mask = (uint8_t)((reta_conf->mask_hi >>
2683                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2684
2685                 if (mask != 0) {
2686                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2687                         for (j = 0; j < 4; j++) {
2688                                 if (mask & (0x1 << j))
2689                                         reta_conf->reta[i + j] =
2690                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2691                         }
2692                 }
2693         }
2694
2695         return 0;
2696 }
2697
2698 static void
2699 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2700                                 uint32_t index, uint32_t pool)
2701 {
2702         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2703         uint32_t enable_addr = 1;
2704
2705         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2706 }
2707
2708 static void
2709 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2710 {
2711         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712
2713         ixgbe_clear_rar(hw, index);
2714 }
2715
2716 static int
2717 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2718 {
2719         uint32_t hlreg0;
2720         uint32_t maxfrs;
2721         struct ixgbe_hw *hw;
2722         struct rte_eth_dev_info dev_info;
2723         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2724
2725         ixgbe_dev_info_get(dev, &dev_info);
2726
2727         /* check that mtu is within the allowed range */
2728         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2729                 return -EINVAL;
2730
2731         /* refuse mtu that requires the support of scattered packets when this
2732          * feature has not been enabled before. */
2733         if (!dev->data->scattered_rx &&
2734             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2735              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2736                 return -EINVAL;
2737
2738         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2739         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2740
2741         /* switch to jumbo mode if needed */
2742         if (frame_size > ETHER_MAX_LEN) {
2743                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2744                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2745         } else {
2746                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2747                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2748         }
2749         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2750
2751         /* update max frame size */
2752         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2753
2754         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2755         maxfrs &= 0x0000FFFF;
2756         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2757         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2758
2759         return 0;
2760 }
2761
2762 /*
2763  * Virtual Function operations
2764  */
2765 static void
2766 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2767 {
2768         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2769
2770         /* Clear interrupt mask to stop from interrupts being generated */
2771         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2772
2773         IXGBE_WRITE_FLUSH(hw);
2774 }
2775
2776 static int
2777 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2778 {
2779         struct rte_eth_conf* conf = &dev->data->dev_conf;
2780
2781         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2782                 dev->data->port_id);
2783
2784         /*
2785          * VF has no ability to enable/disable HW CRC
2786          * Keep the persistent behavior the same as Host PF
2787          */
2788 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2789         if (!conf->rxmode.hw_strip_crc) {
2790                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2791                 conf->rxmode.hw_strip_crc = 1;
2792         }
2793 #else
2794         if (conf->rxmode.hw_strip_crc) {
2795                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2796                 conf->rxmode.hw_strip_crc = 0;
2797         }
2798 #endif
2799
2800         return 0;
2801 }
2802
2803 static int
2804 ixgbevf_dev_start(struct rte_eth_dev *dev)
2805 {
2806         struct ixgbe_hw *hw =
2807                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         int err, mask = 0;
2809
2810         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2811
2812         hw->mac.ops.reset_hw(hw);
2813
2814         /* negotiate mailbox API version to use with the PF. */
2815         ixgbevf_negotiate_api(hw);
2816
2817         ixgbevf_dev_tx_init(dev);
2818
2819         /* This can fail when allocating mbufs for descriptor rings */
2820         err = ixgbevf_dev_rx_init(dev);
2821         if (err) {
2822                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2823                 ixgbe_dev_clear_queues(dev);
2824                 return err;
2825         }
2826
2827         /* Set vfta */
2828         ixgbevf_set_vfta_all(dev,1);
2829
2830         /* Set HW strip */
2831         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2832                 ETH_VLAN_EXTEND_MASK;
2833         ixgbevf_vlan_offload_set(dev, mask);
2834
2835         ixgbevf_dev_rxtx_start(dev);
2836
2837         return 0;
2838 }
2839
2840 static void
2841 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2842 {
2843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844
2845         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2846
2847         hw->adapter_stopped = TRUE;
2848         ixgbe_stop_adapter(hw);
2849
2850         /*
2851           * Clear what we set, but we still keep shadow_vfta to
2852           * restore after device starts
2853           */
2854         ixgbevf_set_vfta_all(dev,0);
2855
2856         ixgbe_dev_clear_queues(dev);
2857 }
2858
2859 static void
2860 ixgbevf_dev_close(struct rte_eth_dev *dev)
2861 {
2862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2863
2864         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2865
2866         ixgbe_reset_hw(hw);
2867
2868         ixgbevf_dev_stop(dev);
2869
2870         /* reprogram the RAR[0] in case user changed it. */
2871         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2872 }
2873
2874 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2875 {
2876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2877         struct ixgbe_vfta * shadow_vfta =
2878                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2879         int i = 0, j = 0, vfta = 0, mask = 1;
2880
2881         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2882                 vfta = shadow_vfta->vfta[i];
2883                 if(vfta){
2884                         mask = 1;
2885                         for (j = 0; j < 32; j++){
2886                                 if(vfta & mask)
2887                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2888                                 mask<<=1;
2889                         }
2890                 }
2891         }
2892
2893 }
2894
2895 static int
2896 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2897 {
2898         struct ixgbe_hw *hw =
2899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900         struct ixgbe_vfta * shadow_vfta =
2901                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2902         uint32_t vid_idx = 0;
2903         uint32_t vid_bit = 0;
2904         int ret = 0;
2905
2906         PMD_INIT_FUNC_TRACE();
2907
2908         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2909         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2910         if(ret){
2911                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2912                 return ret;
2913         }
2914         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2915         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2916
2917         /* Save what we set and retore it after device reset */
2918         if (on)
2919                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2920         else
2921                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2922
2923         return 0;
2924 }
2925
2926 static void
2927 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2928 {
2929         struct ixgbe_hw *hw =
2930                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931         uint32_t ctrl;
2932
2933         PMD_INIT_FUNC_TRACE();
2934
2935         if(queue >= hw->mac.max_rx_queues)
2936                 return;
2937
2938         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2939         if(on)
2940                 ctrl |= IXGBE_RXDCTL_VME;
2941         else
2942                 ctrl &= ~IXGBE_RXDCTL_VME;
2943         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2944
2945         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2946 }
2947
2948 static void
2949 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2950 {
2951         struct ixgbe_hw *hw =
2952                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953         uint16_t i;
2954         int on = 0;
2955
2956         /* VF function only support hw strip feature, others are not support */
2957         if(mask & ETH_VLAN_STRIP_MASK){
2958                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2959
2960                 for(i=0; i < hw->mac.max_rx_queues; i++)
2961                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2962         }
2963 }
2964
2965 static int
2966 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2967 {
2968         uint32_t reg_val;
2969
2970         /* we only need to do this if VMDq is enabled */
2971         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2972         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2973                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2974                 return (-1);
2975         }
2976
2977         return 0;
2978 }
2979
2980 static uint32_t
2981 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2982 {
2983         uint32_t vector = 0;
2984         switch (hw->mac.mc_filter_type) {
2985         case 0:   /* use bits [47:36] of the address */
2986                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2987                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2988                 break;
2989         case 1:   /* use bits [46:35] of the address */
2990                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2991                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2992                 break;
2993         case 2:   /* use bits [45:34] of the address */
2994                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2995                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2996                 break;
2997         case 3:   /* use bits [43:32] of the address */
2998                 vector = ((uc_addr->addr_bytes[4]) |
2999                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3000                 break;
3001         default:  /* Invalid mc_filter_type */
3002                 break;
3003         }
3004
3005         /* vector can only be 12-bits or boundary will be exceeded */
3006         vector &= 0xFFF;
3007         return vector;
3008 }
3009
3010 static int
3011 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3012                                uint8_t on)
3013 {
3014         uint32_t vector;
3015         uint32_t uta_idx;
3016         uint32_t reg_val;
3017         uint32_t uta_shift;
3018         uint32_t rc;
3019         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3020         const uint32_t ixgbe_uta_bit_shift = 5;
3021         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3022         const uint32_t bit1 = 0x1;
3023
3024         struct ixgbe_hw *hw =
3025                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3026         struct ixgbe_uta_info *uta_info =
3027                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3028
3029         /* The UTA table only exists on 82599 hardware and newer */
3030         if (hw->mac.type < ixgbe_mac_82599EB)
3031                 return (-ENOTSUP);
3032
3033         vector = ixgbe_uta_vector(hw,mac_addr);
3034         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3035         uta_shift = vector & ixgbe_uta_bit_mask;
3036
3037         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3038         if(rc == on)
3039                 return 0;
3040
3041         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3042         if (on) {
3043                 uta_info->uta_in_use++;
3044                 reg_val |= (bit1 << uta_shift);
3045                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3046         } else {
3047                 uta_info->uta_in_use--;
3048                 reg_val &= ~(bit1 << uta_shift);
3049                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3050         }
3051
3052         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3053
3054         if (uta_info->uta_in_use > 0)
3055                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3056                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3057         else
3058                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3059
3060         return 0;
3061 }
3062
3063 static int
3064 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3065 {
3066         int i;
3067         struct ixgbe_hw *hw =
3068                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069         struct ixgbe_uta_info *uta_info =
3070                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3071
3072         /* The UTA table only exists on 82599 hardware and newer */
3073         if (hw->mac.type < ixgbe_mac_82599EB)
3074                 return (-ENOTSUP);
3075
3076         if(on) {
3077                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3078                         uta_info->uta_shadow[i] = ~0;
3079                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3080                 }
3081         } else {
3082                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3083                         uta_info->uta_shadow[i] = 0;
3084                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3085                 }
3086         }
3087         return 0;
3088
3089 }
3090 static int
3091 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3092                                uint16_t rx_mask, uint8_t on)
3093 {
3094         int val = 0;
3095
3096         struct ixgbe_hw *hw =
3097                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3098         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3099
3100         if (hw->mac.type == ixgbe_mac_82598EB) {
3101                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3102                         " on 82599 hardware and newer\n");
3103                 return (-ENOTSUP);
3104         }
3105         if (ixgbe_vmdq_mode_check(hw) < 0)
3106                 return (-ENOTSUP);
3107
3108         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
3109                 val |= IXGBE_VMOLR_AUPE;
3110         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
3111                 val |= IXGBE_VMOLR_ROMPE;
3112         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3113                 val |= IXGBE_VMOLR_ROPE;
3114         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3115                 val |= IXGBE_VMOLR_BAM;
3116         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3117                 val |= IXGBE_VMOLR_MPE;
3118
3119         if (on)
3120                 vmolr |= val;
3121         else
3122                 vmolr &= ~val;
3123
3124         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3125
3126         return 0;
3127 }
3128
3129 static int
3130 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3131 {
3132         uint32_t reg,addr;
3133         uint32_t val;
3134         const uint8_t bit1 = 0x1;
3135
3136         struct ixgbe_hw *hw =
3137                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138
3139         if (ixgbe_vmdq_mode_check(hw) < 0)
3140                 return (-ENOTSUP);
3141
3142         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3143         reg = IXGBE_READ_REG(hw, addr);
3144         val = bit1 << pool;
3145
3146         if (on)
3147                 reg |= val;
3148         else
3149                 reg &= ~val;
3150
3151         IXGBE_WRITE_REG(hw, addr,reg);
3152
3153         return 0;
3154 }
3155
3156 static int
3157 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3158 {
3159         uint32_t reg,addr;
3160         uint32_t val;
3161         const uint8_t bit1 = 0x1;
3162
3163         struct ixgbe_hw *hw =
3164                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3165
3166         if (ixgbe_vmdq_mode_check(hw) < 0)
3167                 return (-ENOTSUP);
3168
3169         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3170         reg = IXGBE_READ_REG(hw, addr);
3171         val = bit1 << pool;
3172
3173         if (on)
3174                 reg |= val;
3175         else
3176                 reg &= ~val;
3177
3178         IXGBE_WRITE_REG(hw, addr,reg);
3179
3180         return 0;
3181 }
3182
3183 static int
3184 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3185                         uint64_t pool_mask, uint8_t vlan_on)
3186 {
3187         int ret = 0;
3188         uint16_t pool_idx;
3189         struct ixgbe_hw *hw =
3190                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3191
3192         if (ixgbe_vmdq_mode_check(hw) < 0)
3193                 return (-ENOTSUP);
3194         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3195                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3196                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3197                         if (ret < 0)
3198                                 return ret;
3199         }
3200
3201         return ret;
3202 }
3203
3204 static int
3205 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3206                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3207                         uint8_t rule_id, uint8_t on)
3208 {
3209         uint32_t mr_ctl,vlvf;
3210         uint32_t mp_lsb = 0;
3211         uint32_t mv_msb = 0;
3212         uint32_t mv_lsb = 0;
3213         uint32_t mp_msb = 0;
3214         uint8_t i = 0;
3215         int reg_index = 0;
3216         uint64_t vlan_mask = 0;
3217
3218         const uint8_t pool_mask_offset = 32;
3219         const uint8_t vlan_mask_offset = 32;
3220         const uint8_t dst_pool_offset = 8;
3221         const uint8_t rule_mr_offset  = 4;
3222         const uint8_t mirror_rule_mask= 0x0F;
3223
3224         struct ixgbe_mirror_info *mr_info =
3225                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3226         struct ixgbe_hw *hw =
3227                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3228
3229         if (ixgbe_vmdq_mode_check(hw) < 0)
3230                 return (-ENOTSUP);
3231
3232         /* Check if vlan mask is valid */
3233         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3234                 if (mirror_conf->vlan.vlan_mask == 0)
3235                         return (-EINVAL);
3236         }
3237
3238         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3239         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3240                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3241                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3242                                 /* search vlan id related pool vlan filter index */
3243                                 reg_index = ixgbe_find_vlvf_slot(hw,
3244                                                 mirror_conf->vlan.vlan_id[i]);
3245                                 if(reg_index < 0)
3246                                         return (-EINVAL);
3247                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3248                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3249                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3250                                                 == mirror_conf->vlan.vlan_id[i]))
3251                                         vlan_mask |= (1ULL << reg_index);
3252                                 else
3253                                         return (-EINVAL);
3254                         }
3255                 }
3256
3257                 if (on) {
3258                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3259                         mv_msb = vlan_mask >> vlan_mask_offset;
3260
3261                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3262                                                 mirror_conf->vlan.vlan_mask;
3263                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3264                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3265                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3266                                                 mirror_conf->vlan.vlan_id[i];
3267                         }
3268                 } else {
3269                         mv_lsb = 0;
3270                         mv_msb = 0;
3271                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3272                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3273                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3274                 }
3275         }
3276
3277         /*
3278          * if enable pool mirror, write related pool mask register,if disable
3279          * pool mirror, clear PFMRVM register
3280          */
3281         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3282                 if (on) {
3283                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3284                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3285                         mr_info->mr_conf[rule_id].pool_mask =
3286                                         mirror_conf->pool_mask;
3287
3288                 } else {
3289                         mp_lsb = 0;
3290                         mp_msb = 0;
3291                         mr_info->mr_conf[rule_id].pool_mask = 0;
3292                 }
3293         }
3294
3295         /* read  mirror control register and recalculate it */
3296         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3297
3298         if (on) {
3299                 mr_ctl |= mirror_conf->rule_type_mask;
3300                 mr_ctl &= mirror_rule_mask;
3301                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3302         } else
3303                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3304
3305         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3306         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3307
3308         /* write mirrror control  register */
3309         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3310
3311         /* write pool mirrror control  register */
3312         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3313                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3314                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3315                                 mp_msb);
3316         }
3317         /* write VLAN mirrror control  register */
3318         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3319                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3320                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3321                                 mv_msb);
3322         }
3323
3324         return 0;
3325 }
3326
3327 static int
3328 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3329 {
3330         int mr_ctl = 0;
3331         uint32_t lsb_val = 0;
3332         uint32_t msb_val = 0;
3333         const uint8_t rule_mr_offset = 4;
3334
3335         struct ixgbe_hw *hw =
3336                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337         struct ixgbe_mirror_info *mr_info =
3338                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3339
3340         if (ixgbe_vmdq_mode_check(hw) < 0)
3341                 return (-ENOTSUP);
3342
3343         memset(&mr_info->mr_conf[rule_id], 0,
3344                 sizeof(struct rte_eth_vmdq_mirror_conf));
3345
3346         /* clear PFVMCTL register */
3347         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3348
3349         /* clear pool mask register */
3350         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3351         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3352
3353         /* clear vlan mask register */
3354         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3355         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3356
3357         return 0;
3358 }
3359
3360 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3361         uint16_t queue_idx, uint16_t tx_rate)
3362 {
3363         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3364         uint32_t rf_dec, rf_int;
3365         uint32_t bcnrc_val;
3366         uint16_t link_speed = dev->data->dev_link.link_speed;
3367
3368         if (queue_idx >= hw->mac.max_tx_queues)
3369                 return -EINVAL;
3370
3371         if (tx_rate != 0) {
3372                 /* Calculate the rate factor values to set */
3373                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3374                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3375                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3376
3377                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3378                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3379                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3380                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3381         } else {
3382                 bcnrc_val = 0;
3383         }
3384
3385         /*
3386          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3387          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3388          * set as 0x4.
3389          */
3390         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3391                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3392                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3393                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3394                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3395         else
3396                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3397                         IXGBE_MMW_SIZE_DEFAULT);
3398
3399         /* Set RTTBCNRC of queue X */
3400         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3401         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3402         IXGBE_WRITE_FLUSH(hw);
3403
3404         return 0;
3405 }
3406
3407 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3408         uint16_t tx_rate, uint64_t q_msk)
3409 {
3410         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3411         struct ixgbe_vf_info *vfinfo =
3412                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3413         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3414         uint32_t queue_stride =
3415                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3416         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3417         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3418         uint16_t total_rate = 0;
3419
3420         if (queue_end >= hw->mac.max_tx_queues)
3421                 return -EINVAL;
3422
3423         if (vfinfo != NULL) {
3424                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3425                         if (vf_idx == vf)
3426                                 continue;
3427                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3428                                 idx++)
3429                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3430                 }
3431         } else
3432                 return -EINVAL;
3433
3434         /* Store tx_rate for this vf. */
3435         for (idx = 0; idx < nb_q_per_pool; idx++) {
3436                 if (((uint64_t)0x1 << idx) & q_msk) {
3437                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3438                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3439                         total_rate += tx_rate;
3440                 }
3441         }
3442
3443         if (total_rate > dev->data->dev_link.link_speed) {
3444                 /*
3445                  * Reset stored TX rate of the VF if it causes exceed
3446                  * link speed.
3447                  */
3448                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3449                 return -EINVAL;
3450         }
3451
3452         /* Set RTTBCNRC of each queue/pool for vf X  */
3453         for (; queue_idx <= queue_end; queue_idx++) {
3454                 if (0x1 & q_msk)
3455                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3456                 q_msk = q_msk >> 1;
3457         }
3458
3459         return 0;
3460 }
3461
3462 static void
3463 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3464                      __attribute__((unused)) uint32_t index,
3465                      __attribute__((unused)) uint32_t pool)
3466 {
3467         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3468         int diag;
3469
3470         /*
3471          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3472          * operation. Trap this case to avoid exhausting the [very limited]
3473          * set of PF resources used to store VF MAC addresses.
3474          */
3475         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3476                 return;
3477         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3478         if (diag == 0)
3479                 return;
3480         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3481 }
3482
3483 static void
3484 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3485 {
3486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3487         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3488         struct ether_addr *mac_addr;
3489         uint32_t i;
3490         int diag;
3491
3492         /*
3493          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3494          * not support the deletion of a given MAC address.
3495          * Instead, it imposes to delete all MAC addresses, then to add again
3496          * all MAC addresses with the exception of the one to be deleted.
3497          */
3498         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3499
3500         /*
3501          * Add again all MAC addresses, with the exception of the deleted one
3502          * and of the permanent MAC address.
3503          */
3504         for (i = 0, mac_addr = dev->data->mac_addrs;
3505              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3506                 /* Skip the deleted MAC address */
3507                 if (i == index)
3508                         continue;
3509                 /* Skip NULL MAC addresses */
3510                 if (is_zero_ether_addr(mac_addr))
3511                         continue;
3512                 /* Skip the permanent MAC address */
3513                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3514                         continue;
3515                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3516                 if (diag != 0)
3517                         PMD_DRV_LOG(ERR,
3518                                     "Adding again MAC address "
3519                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3520                                     "diag=%d",
3521                                     mac_addr->addr_bytes[0],
3522                                     mac_addr->addr_bytes[1],
3523                                     mac_addr->addr_bytes[2],
3524                                     mac_addr->addr_bytes[3],
3525                                     mac_addr->addr_bytes[4],
3526                                     mac_addr->addr_bytes[5],
3527                                     diag);
3528         }
3529 }
3530
3531 /*
3532  * add syn filter
3533  *
3534  * @param
3535  * dev: Pointer to struct rte_eth_dev.
3536  * filter: ponter to the filter that will be added.
3537  * rx_queue: the queue id the filter assigned to.
3538  *
3539  * @return
3540  *    - On success, zero.
3541  *    - On failure, a negative value.
3542  */
3543 static int
3544 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3545                         struct rte_syn_filter *filter, uint16_t rx_queue)
3546 {
3547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548         uint32_t synqf;
3549
3550         if (hw->mac.type != ixgbe_mac_82599EB)
3551                 return -ENOSYS;
3552
3553         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3554                 return -EINVAL;
3555
3556         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3557
3558         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3559                 return -EINVAL;
3560
3561         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3562                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3563
3564         if (filter->hig_pri)
3565                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3566         else
3567                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3568
3569         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3570         return 0;
3571 }
3572
3573 /*
3574  * remove syn filter
3575  *
3576  * @param
3577  * dev: Pointer to struct rte_eth_dev.
3578  *
3579  * @return
3580  *    - On success, zero.
3581  *    - On failure, a negative value.
3582  */
3583 static int
3584 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3585 {
3586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587         uint32_t synqf;
3588
3589         if (hw->mac.type != ixgbe_mac_82599EB)
3590                 return -ENOSYS;
3591
3592         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3593
3594         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3595
3596         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3597         return 0;
3598 }
3599
3600 /*
3601  * get the syn filter's info
3602  *
3603  * @param
3604  * dev: Pointer to struct rte_eth_dev.
3605  * filter: ponter to the filter that returns.
3606  * *rx_queue: pointer to the queue id the filter assigned to.
3607  *
3608  * @return
3609  *    - On success, zero.
3610  *    - On failure, a negative value.
3611  */
3612 static int
3613 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3614                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3615
3616 {
3617         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3618         uint32_t synqf;
3619
3620         if (hw->mac.type != ixgbe_mac_82599EB)
3621                 return -ENOSYS;
3622
3623         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3624         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3625                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3626                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3627                 return 0;
3628         }
3629         return -ENOENT;
3630 }
3631
3632 /*
3633  * add an ethertype filter
3634  *
3635  * @param
3636  * dev: Pointer to struct rte_eth_dev.
3637  * index: the index the filter allocates.
3638  * filter: ponter to the filter that will be added.
3639  * rx_queue: the queue id the filter assigned to.
3640  *
3641  * @return
3642  *    - On success, zero.
3643  *    - On failure, a negative value.
3644  */
3645 static int
3646 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3647                         uint16_t index, struct rte_ethertype_filter *filter,
3648                         uint16_t rx_queue)
3649 {
3650         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3651         uint32_t etqf, etqs = 0;
3652
3653         if (hw->mac.type != ixgbe_mac_82599EB)
3654                 return -ENOSYS;
3655
3656         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3657                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3658                 return -EINVAL;
3659
3660         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3661         if (etqf & IXGBE_ETQF_FILTER_EN)
3662                 return -EINVAL;  /* filter index is in use. */
3663
3664         etqf = 0;
3665         etqf |= IXGBE_ETQF_FILTER_EN;
3666         etqf |= (uint32_t)filter->ethertype;
3667
3668         if (filter->priority_en) {
3669                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3670                         return -EINVAL;
3671                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3672                 etqf |= IXGBE_ETQF_UP_EN;
3673         }
3674         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3675         etqs |= IXGBE_ETQS_QUEUE_EN;
3676
3677         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3678         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3679         return 0;
3680 }
3681
3682 /*
3683  * remove an ethertype filter
3684  *
3685  * @param
3686  * dev: Pointer to struct rte_eth_dev.
3687  * index: the index the filter allocates.
3688  *
3689  * @return
3690  *    - On success, zero.
3691  *    - On failure, a negative value.
3692  */
3693 static int
3694 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3695                         uint16_t index)
3696 {
3697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698
3699         if (hw->mac.type != ixgbe_mac_82599EB)
3700                 return -ENOSYS;
3701
3702         if (index >= IXGBE_MAX_ETQF_FILTERS)
3703                 return -EINVAL;
3704
3705         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3706         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3707
3708         return 0;
3709 }
3710
3711 /*
3712  * get an ethertype filter
3713  *
3714  * @param
3715  * dev: Pointer to struct rte_eth_dev.
3716  * index: the index the filter allocates.
3717  * filter: ponter to the filter that will be gotten.
3718  * *rx_queue: the ponited of the queue id the filter assigned to.
3719  *
3720  * @return
3721  *    - On success, zero.
3722  *    - On failure, a negative value.
3723  */
3724 static int
3725 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3726                         uint16_t index, struct rte_ethertype_filter *filter,
3727                         uint16_t *rx_queue)
3728 {
3729         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3730         uint32_t etqf, etqs;
3731
3732         if (hw->mac.type != ixgbe_mac_82599EB)
3733                 return -ENOSYS;
3734
3735         if (index >= IXGBE_MAX_ETQF_FILTERS)
3736                 return -EINVAL;
3737
3738         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3739         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3740         if (etqf & IXGBE_ETQF_FILTER_EN) {
3741                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3742                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3743                 if (filter->priority_en)
3744                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3745                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3746                 return 0;
3747         }
3748         return -ENOENT;
3749 }
3750
3751 static inline enum ixgbe_5tuple_protocol
3752 convert_protocol_type(uint8_t protocol_value)
3753 {
3754         if (protocol_value == IPPROTO_TCP)
3755                 return IXGBE_FILTER_PROTOCOL_TCP;
3756         else if (protocol_value == IPPROTO_UDP)
3757                 return IXGBE_FILTER_PROTOCOL_UDP;
3758         else if (protocol_value == IPPROTO_SCTP)
3759                 return IXGBE_FILTER_PROTOCOL_SCTP;
3760         else
3761                 return IXGBE_FILTER_PROTOCOL_NONE;
3762 }
3763
3764 static inline uint8_t
3765 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3766 {
3767         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3768                 return IPPROTO_TCP;
3769         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3770                 return IPPROTO_UDP;
3771         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3772                 return IPPROTO_SCTP;
3773         else
3774                 return 0;
3775 }
3776
3777 /*
3778  * add a 5tuple filter
3779  *
3780  * @param
3781  * dev: Pointer to struct rte_eth_dev.
3782  * index: the index the filter allocates.
3783  * filter: ponter to the filter that will be added.
3784  * rx_queue: the queue id the filter assigned to.
3785  *
3786  * @return
3787  *    - On success, zero.
3788  *    - On failure, a negative value.
3789  */
3790 static int
3791 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3792                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3793 {
3794         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3795         uint32_t ftqf, sdpqf = 0;
3796         uint32_t l34timir = 0;
3797         uint8_t mask = 0xff;
3798
3799         if (hw->mac.type != ixgbe_mac_82599EB)
3800                 return -ENOSYS;
3801
3802         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3803                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3804                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3805                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3806                 return -EINVAL;  /* filter index is out of range. */
3807
3808         if (filter->tcp_flags) {
3809                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3810                 return -EINVAL;
3811         }
3812
3813         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3814         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3815                 return -EINVAL;  /* filter index is in use. */
3816
3817         ftqf = 0;
3818         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3819         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3820
3821         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3822                 IXGBE_FTQF_PROTOCOL_MASK);
3823         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3824                 IXGBE_FTQF_PRIORITY_SHIFT);
3825         if (filter->src_ip_mask == 0) /* 0 means compare. */
3826                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3827         if (filter->dst_ip_mask == 0)
3828                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3829         if (filter->src_port_mask == 0)
3830                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3831         if (filter->dst_port_mask == 0)
3832                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3833         if (filter->protocol_mask == 0)
3834                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3835         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3836         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3837         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3838
3839         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3840         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3841         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3842         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3843
3844         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3845         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3846         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3847         return 0;
3848 }
3849
3850 /*
3851  * remove a 5tuple filter
3852  *
3853  * @param
3854  * dev: Pointer to struct rte_eth_dev.
3855  * index: the index the filter allocates.
3856  *
3857  * @return
3858  *    - On success, zero.
3859  *    - On failure, a negative value.
3860  */
3861 static int
3862 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3863                         uint16_t index)
3864 {
3865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866
3867         if (hw->mac.type != ixgbe_mac_82599EB)
3868                 return -ENOSYS;
3869
3870         if (index >= IXGBE_MAX_FTQF_FILTERS)
3871                 return -EINVAL;  /* filter index is out of range. */
3872
3873         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3874         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3875         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3876         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3877         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3878         return 0;
3879 }
3880
3881 /*
3882  * get a 5tuple filter
3883  *
3884  * @param
3885  * dev: Pointer to struct rte_eth_dev.
3886  * index: the index the filter allocates
3887  * filter: ponter to the filter that returns.
3888  * *rx_queue: pointer of the queue id the filter assigned to.
3889  *
3890  * @return
3891  *    - On success, zero.
3892  *    - On failure, a negative value.
3893  */
3894 static int
3895 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3896                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3897 {
3898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3899         uint32_t sdpqf, ftqf, l34timir;
3900         uint8_t mask;
3901         enum ixgbe_5tuple_protocol proto;
3902
3903         if (hw->mac.type != ixgbe_mac_82599EB)
3904                 return -ENOSYS;
3905
3906         if (index >= IXGBE_MAX_FTQF_FILTERS)
3907                 return -EINVAL;  /* filter index is out of range. */
3908
3909         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3910         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3911                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3912                 filter->protocol = revert_protocol_type(proto);
3913                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3914                                         IXGBE_FTQF_PRIORITY_MASK;
3915                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3916                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3917                 filter->src_ip_mask =
3918                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3919                 filter->dst_ip_mask =
3920                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3921                 filter->src_port_mask =
3922                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3923                 filter->dst_port_mask =
3924                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3925                 filter->protocol_mask =
3926                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3927
3928                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3929                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3930                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3931                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3932                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3933                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3934
3935                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3936                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3937                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3938                 return 0;
3939         }
3940         return -ENOENT;
3941 }
3942
3943 static int
3944 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3945 {
3946         struct ixgbe_hw *hw;
3947         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3948
3949         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3950
3951         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3952                 return -EINVAL;
3953
3954         /* refuse mtu that requires the support of scattered packets when this
3955          * feature has not been enabled before. */
3956         if (!dev->data->scattered_rx &&
3957             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3958              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3959                 return -EINVAL;
3960
3961         /*
3962          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3963          * request of the version 2.0 of the mailbox API.
3964          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3965          * of the mailbox API.
3966          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3967          * prior to 3.11.33 which contains the following change:
3968          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3969          */
3970         ixgbevf_rlpml_set_vf(hw, max_frame);
3971
3972         /* update max frame size */
3973         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3974         return 0;
3975 }
3976
3977 static struct rte_driver rte_ixgbe_driver = {
3978         .type = PMD_PDEV,
3979         .init = rte_ixgbe_pmd_init,
3980 };
3981
3982 static struct rte_driver rte_ixgbevf_driver = {
3983         .type = PMD_PDEV,
3984         .init = rte_ixgbevf_pmd_init,
3985 };
3986
3987 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3988 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);