lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72
  73 /*
  74  * High threshold controlling when to start sending XOFF frames. Must be at
  75  * least 8 bytes less than receive packet buffer size. This value is in units
  76  * of 1024 bytes.
  77  */
  78 #define IXGBE_FC_HI    0x80
  79
  80 /*
  81  * Low threshold controlling when to start sending XON frames. This value is
  82  * in units of 1024 bytes.
  83  */
  84 #define IXGBE_FC_LO    0x40
  85
  86 /* Timer value included in XOFF frames. */
  87 #define IXGBE_FC_PAUSE 0x680
  88
  89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  90 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  91 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  92
  93 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  94 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  95
  96 /*
  97  *  Default values for RX/TX configuration
  98  */
  99 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 100 #define IXGBE_DEFAULT_RX_PTHRESH      8
 101 #define IXGBE_DEFAULT_RX_HTHRESH      8
 102 #define IXGBE_DEFAULT_RX_WTHRESH      0
 103
 104 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 105 #define IXGBE_DEFAULT_TX_PTHRESH      32
 106 #define IXGBE_DEFAULT_TX_HTHRESH      0
 107 #define IXGBE_DEFAULT_TX_WTHRESH      0
 108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 109
 110 /* Bit shift and mask */
 111 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 112 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 113 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 114 #define IXGBE_8_BIT_MASK   UINT8_MAX
 115
 116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 117
 118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 119
 120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 121                 struct rte_eth_dev *eth_dev);
 122 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 125 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 126 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 133                                 int wait_to_complete);
 134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 135                                 struct rte_eth_stats *stats);
 136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 138                                              uint16_t queue_id,
 139                                              uint8_t stat_idx,
 140                                              uint8_t is_rx);
 141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 142                                struct rte_eth_dev_info *dev_info);
 143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 144                                  struct rte_eth_dev_info *dev_info);
 145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 151                 uint16_t queue, bool on);
 152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 153                 int on);
 154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 165                                struct rte_eth_fc_conf *fc_conf);
 166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 167                 struct rte_eth_pfc_conf *pfc_conf);
 168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 169                         struct rte_eth_rss_reta_entry64 *reta_conf,
 170                         uint16_t reta_size);
 171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 172                         struct rte_eth_rss_reta_entry64 *reta_conf,
 173                         uint16_t reta_size);
 174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 179                 void *param);
 180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 182                 uint32_t index, uint32_t pool);
 183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 185
 186 /* For Virtual Function support */
 187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 188                 struct rte_eth_dev *eth_dev);
 189 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 190 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 195                 struct rte_eth_stats *stats);
 196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 198                 uint16_t vlan_id, int on);
 199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 200                 uint16_t queue, int on);
 201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203
 204 /* For Eth VMDQ APIs support */
 205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 206                 ether_addr* mac_addr,uint8_t on);
 207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 208 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 209                 uint16_t rx_mask, uint8_t on);
 210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 213                 uint64_t pool_mask,uint8_t vlan_on);
 214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 216                 uint8_t rule_id, uint8_t on);
 217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 218                 uint8_t rule_id);
 219
 220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 221                 uint16_t queue_idx, uint16_t tx_rate);
 222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 223                 uint16_t tx_rate, uint64_t q_msk);
 224
 225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 226                                  struct ether_addr *mac_addr,
 227                                  uint32_t index, uint32_t pool);
 228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 229 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 230                         struct rte_syn_filter *filter, uint16_t rx_queue);
 231 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 232 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 233                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 235                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 236 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 237                         uint16_t index);
 238 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 239                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 240
 241 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 242 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter,
 244                         bool add);
 245 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter);
 250 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 251                      enum rte_filter_type filter_type,
 252                      enum rte_filter_op filter_op,
 253                      void *arg);
 254
 255 /*
 256  * Define VF Stats MACRO for Non "cleared on read" register
 257  */
 258 #define UPDATE_VF_STAT(reg, last, cur)                          \
 259 {                                                               \
 260         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 261         cur += latest - last;                                   \
 262         last = latest;                                          \
 263 }
 264
 265 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 266 {                                                                \
 267         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 268         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 269         u64 latest = ((new_msb << 32) | new_lsb);                \
 270         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 271         last = latest;                                           \
 272 }
 273
 274 #define IXGBE_SET_HWSTRIP(h, q) do{\
 275                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 276                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 277                 (h)->bitmap[idx] |= 1 << bit;\
 278         }while(0)
 279
 280 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 281                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 283                 (h)->bitmap[idx] &= ~(1 << bit);\
 284         }while(0)
 285
 286 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 287                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 288                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 289                 (r) = (h)->bitmap[idx] >> bit & 1;\
 290         }while(0)
 291
 292 /*
 293  * The set of PCI devices this driver supports
 294  */
 295 static struct rte_pci_id pci_id_ixgbe_map[] = {
 296
 297 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 298 #include "rte_pci_dev_ids.h"
 299
 300 { .vendor_id = 0, /* sentinel */ },
 301 };
 302
 303
 304 /*
 305  * The set of PCI devices this driver supports (for 82599 VF)
 306  */
 307 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 308
 309 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 310 #include "rte_pci_dev_ids.h"
 311 { .vendor_id = 0, /* sentinel */ },
 312
 313 };
 314
 315 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 316         .dev_configure        = ixgbe_dev_configure,
 317         .dev_start            = ixgbe_dev_start,
 318         .dev_stop             = ixgbe_dev_stop,
 319         .dev_set_link_up    = ixgbe_dev_set_link_up,
 320         .dev_set_link_down  = ixgbe_dev_set_link_down,
 321         .dev_close            = ixgbe_dev_close,
 322         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 323         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 324         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 325         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 326         .link_update          = ixgbe_dev_link_update,
 327         .stats_get            = ixgbe_dev_stats_get,
 328         .stats_reset          = ixgbe_dev_stats_reset,
 329         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 330         .dev_infos_get        = ixgbe_dev_info_get,
 331         .mtu_set              = ixgbe_dev_mtu_set,
 332         .vlan_filter_set      = ixgbe_vlan_filter_set,
 333         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 334         .vlan_offload_set     = ixgbe_vlan_offload_set,
 335         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 336         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 337         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 338         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 339         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 340         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 341         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 342         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 343         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 344         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 345         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 346         .dev_led_on           = ixgbe_dev_led_on,
 347         .dev_led_off          = ixgbe_dev_led_off,
 348         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 349         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 350         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 351         .mac_addr_add         = ixgbe_add_rar,
 352         .mac_addr_remove      = ixgbe_remove_rar,
 353         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 354         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 355         .mirror_rule_set      = ixgbe_mirror_rule_set,
 356         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 357         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 358         .set_vf_rx            = ixgbe_set_pool_rx,
 359         .set_vf_tx            = ixgbe_set_pool_tx,
 360         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 361         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 362         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 363         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 364         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 365         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 366         .fdir_infos_get               = ixgbe_fdir_info_get,
 367         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 368         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 369         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 370         .fdir_set_masks               = ixgbe_fdir_set_masks,
 371         .reta_update          = ixgbe_dev_rss_reta_update,
 372         .reta_query           = ixgbe_dev_rss_reta_query,
 373 #ifdef RTE_NIC_BYPASS
 374         .bypass_init          = ixgbe_bypass_init,
 375         .bypass_state_set     = ixgbe_bypass_state_store,
 376         .bypass_state_show    = ixgbe_bypass_state_show,
 377         .bypass_event_set     = ixgbe_bypass_event_store,
 378         .bypass_event_show    = ixgbe_bypass_event_show,
 379         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 380         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 381         .bypass_ver_show      = ixgbe_bypass_ver_show,
 382         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 383 #endif /* RTE_NIC_BYPASS */
 384         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 385         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 386         .add_syn_filter          = ixgbe_add_syn_filter,
 387         .remove_syn_filter       = ixgbe_remove_syn_filter,
 388         .get_syn_filter          = ixgbe_get_syn_filter,
 389         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 390         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 391         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 392         .filter_ctrl             = ixgbe_dev_filter_ctrl,
 393 };
 394
 395 /*
 396  * dev_ops for virtual function, bare necessities for basic vf
 397  * operation have been implemented
 398  */
 399 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 400
 401         .dev_configure        = ixgbevf_dev_configure,
 402         .dev_start            = ixgbevf_dev_start,
 403         .dev_stop             = ixgbevf_dev_stop,
 404         .link_update          = ixgbe_dev_link_update,
 405         .stats_get            = ixgbevf_dev_stats_get,
 406         .stats_reset          = ixgbevf_dev_stats_reset,
 407         .dev_close            = ixgbevf_dev_close,
 408         .dev_infos_get        = ixgbevf_dev_info_get,
 409         .mtu_set              = ixgbevf_dev_set_mtu,
 410         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 411         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 412         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 413         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 414         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 415         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 416         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 417         .mac_addr_add         = ixgbevf_add_mac_addr,
 418         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 419 };
 420
 421 /**
 422  * Atomically reads the link status information from global
 423  * structure rte_eth_dev.
 424  *
 425  * @param dev
 426  *   - Pointer to the structure rte_eth_dev to read from.
 427  *   - Pointer to the buffer to be saved with the link status.
 428  *
 429  * @return
 430  *   - On success, zero.
 431  *   - On failure, negative value.
 432  */
 433 static inline int
 434 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 435                                 struct rte_eth_link *link)
 436 {
 437         struct rte_eth_link *dst = link;
 438         struct rte_eth_link *src = &(dev->data->dev_link);
 439
 440         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 441                                         *(uint64_t *)src) == 0)
 442                 return -1;
 443
 444         return 0;
 445 }
 446
 447 /**
 448  * Atomically writes the link status information into global
 449  * structure rte_eth_dev.
 450  *
 451  * @param dev
 452  *   - Pointer to the structure rte_eth_dev to read from.
 453  *   - Pointer to the buffer to be saved with the link status.
 454  *
 455  * @return
 456  *   - On success, zero.
 457  *   - On failure, negative value.
 458  */
 459 static inline int
 460 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 461                                 struct rte_eth_link *link)
 462 {
 463         struct rte_eth_link *dst = &(dev->data->dev_link);
 464         struct rte_eth_link *src = link;
 465
 466         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 467                                         *(uint64_t *)src) == 0)
 468                 return -1;
 469
 470         return 0;
 471 }
 472
 473 /*
 474  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 475  */
 476 static inline int
 477 ixgbe_is_sfp(struct ixgbe_hw *hw)
 478 {
 479         switch (hw->phy.type) {
 480         case ixgbe_phy_sfp_avago:
 481         case ixgbe_phy_sfp_ftl:
 482         case ixgbe_phy_sfp_intel:
 483         case ixgbe_phy_sfp_unknown:
 484         case ixgbe_phy_sfp_passive_tyco:
 485         case ixgbe_phy_sfp_passive_unknown:
 486                 return 1;
 487         default:
 488                 return 0;
 489         }
 490 }
 491
 492 static inline int32_t
 493 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 494 {
 495         uint32_t ctrl_ext;
 496         int32_t status;
 497
 498         status = ixgbe_reset_hw(hw);
 499
 500         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 501         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 502         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 503         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 504         IXGBE_WRITE_FLUSH(hw);
 505
 506         return status;
 507 }
 508
 509 static inline void
 510 ixgbe_enable_intr(struct rte_eth_dev *dev)
 511 {
 512         struct ixgbe_interrupt *intr =
 513                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 514         struct ixgbe_hw *hw =
 515                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 516
 517         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 518         IXGBE_WRITE_FLUSH(hw);
 519 }
 520
 521 /*
 522  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 523  */
 524 static void
 525 ixgbe_disable_intr(struct ixgbe_hw *hw)
 526 {
 527         PMD_INIT_FUNC_TRACE();
 528
 529         if (hw->mac.type == ixgbe_mac_82598EB) {
 530                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 531         } else {
 532                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 533                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 534                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 535         }
 536         IXGBE_WRITE_FLUSH(hw);
 537 }
 538
 539 /*
 540  * This function resets queue statistics mapping registers.
 541  * From Niantic datasheet, Initialization of Statistics section:
 542  * "...if software requires the queue counters, the RQSMR and TQSM registers
 543  * must be re-programmed following a device reset.
 544  */
 545 static void
 546 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 547 {
 548         uint32_t i;
 549
 550         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 551                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 552                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 553         }
 554 }
 555
 556
 557 static int
 558 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 559                                   uint16_t queue_id,
 560                                   uint8_t stat_idx,
 561                                   uint8_t is_rx)
 562 {
 563 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 564 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 565 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 566
 567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 568         struct ixgbe_stat_mapping_registers *stat_mappings =
 569                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 570         uint32_t qsmr_mask = 0;
 571         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 572         uint32_t q_map;
 573         uint8_t n, offset;
 574
 575         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 576                 (hw->mac.type != ixgbe_mac_X540) &&
 577                 (hw->mac.type != ixgbe_mac_X550) &&
 578                 (hw->mac.type != ixgbe_mac_X550EM_x))
 579                 return -ENOSYS;
 580
 581         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 582                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 583                      queue_id, stat_idx);
 584
 585         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 586         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 587                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 588                 return -EIO;
 589         }
 590         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 591
 592         /* Now clear any previous stat_idx set */
 593         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 594         if (!is_rx)
 595                 stat_mappings->tqsm[n] &= ~clearing_mask;
 596         else
 597                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 598
 599         q_map = (uint32_t)stat_idx;
 600         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 601         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 602         if (!is_rx)
 603                 stat_mappings->tqsm[n] |= qsmr_mask;
 604         else
 605                 stat_mappings->rqsmr[n] |= qsmr_mask;
 606
 607         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 608                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 609                      queue_id, stat_idx);
 610         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 611                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 612
 613         /* Now write the mapping in the appropriate register */
 614         if (is_rx) {
 615                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 616                              stat_mappings->rqsmr[n], n);
 617                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 618         }
 619         else {
 620                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 621                              stat_mappings->tqsm[n], n);
 622                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 623         }
 624         return 0;
 625 }
 626
 627 static void
 628 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 629 {
 630         struct ixgbe_stat_mapping_registers *stat_mappings =
 631                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 632         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 633         int i;
 634
 635         /* write whatever was in stat mapping table to the NIC */
 636         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 637                 /* rx */
 638                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 639
 640                 /* tx */
 641                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 642         }
 643 }
 644
 645 static void
 646 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 647 {
 648         uint8_t i;
 649         struct ixgbe_dcb_tc_config *tc;
 650         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 651
 652         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 653         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 654         for (i = 0; i < dcb_max_tc; i++) {
 655                 tc = &dcb_config->tc_config[i];
 656                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 657                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 658                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 659                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 660                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 661                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 662                 tc->pfc = ixgbe_dcb_pfc_disabled;
 663         }
 664
 665         /* Initialize default user to priority mapping, UPx->TC0 */
 666         tc = &dcb_config->tc_config[0];
 667         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 668         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 669         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 670                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 671                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 672         }
 673         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 674         dcb_config->pfc_mode_enable = false;
 675         dcb_config->vt_mode = true;
 676         dcb_config->round_robin_enable = false;
 677         /* support all DCB capabilities in 82599 */
 678         dcb_config->support.capabilities = 0xFF;
 679
 680         /*we only support 4 Tcs for X540, X550 */
 681         if (hw->mac.type == ixgbe_mac_X540 ||
 682                 hw->mac.type == ixgbe_mac_X550 ||
 683                 hw->mac.type == ixgbe_mac_X550EM_x) {
 684                 dcb_config->num_tcs.pg_tcs = 4;
 685                 dcb_config->num_tcs.pfc_tcs = 4;
 686         }
 687 }
 688
 689 /*
 690  * Ensure that all locks are released before first NVM or PHY access
 691  */
 692 static void
 693 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 694 {
 695         uint16_t mask;
 696
 697         /*
 698          * Phy lock should not fail in this early stage. If this is the case,
 699          * it is due to an improper exit of the application.
 700          * So force the release of the faulty lock. Release of common lock
 701          * is done automatically by swfw_sync function.
 702          */
 703         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 704         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 705                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 706         }
 707         ixgbe_release_swfw_semaphore(hw, mask);
 708
 709         /*
 710          * These ones are more tricky since they are common to all ports; but
 711          * swfw_sync retries last long enough (1s) to be almost sure that if
 712          * lock can not be taken it is due to an improper lock of the
 713          * semaphore.
 714          */
 715         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 716         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 717                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 718         }
 719         ixgbe_release_swfw_semaphore(hw, mask);
 720 }
 721
 722 /*
 723  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 724  * It returns 0 on success.
 725  */
 726 static int
 727 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 728                      struct rte_eth_dev *eth_dev)
 729 {
 730         struct rte_pci_device *pci_dev;
 731         struct ixgbe_hw *hw =
 732                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 733         struct ixgbe_vfta * shadow_vfta =
 734                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 735         struct ixgbe_hwstrip *hwstrip =
 736                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 737         struct ixgbe_dcb_config *dcb_config =
 738                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 739         uint32_t ctrl_ext;
 740         uint16_t csum;
 741         int diag, i;
 742
 743         PMD_INIT_FUNC_TRACE();
 744
 745         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 746         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 747         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 748
 749         /*
 750          * For secondary processes, we don't initialise any further as primary
 751          * has already done this work. Only check we don't need a different
 752          * RX and TX function.
 753          */
 754         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 755                 struct igb_tx_queue *txq;
 756                 /* TX queue function in primary, set by last queue initialized
 757                  * Tx queue may not initialized by primary process */
 758                 if (eth_dev->data->tx_queues) {
 759                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 760                         set_tx_function(eth_dev, txq);
 761                 } else {
 762                         /* Use default TX function if we get here */
 763                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 764                                            "Using default TX function.");
 765                 }
 766
 767                 if (eth_dev->data->scattered_rx)
 768                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 769                 return 0;
 770         }
 771         pci_dev = eth_dev->pci_dev;
 772
 773         /* Vendor and Device ID need to be set before init of shared code */
 774         hw->device_id = pci_dev->id.device_id;
 775         hw->vendor_id = pci_dev->id.vendor_id;
 776         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 777         hw->allow_unsupported_sfp = 1;
 778
 779         /* Initialize the shared code (base driver) */
 780 #ifdef RTE_NIC_BYPASS
 781         diag = ixgbe_bypass_init_shared_code(hw);
 782 #else
 783         diag = ixgbe_init_shared_code(hw);
 784 #endif /* RTE_NIC_BYPASS */
 785
 786         if (diag != IXGBE_SUCCESS) {
 787                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 788                 return -EIO;
 789         }
 790
 791         /* pick up the PCI bus settings for reporting later */
 792         ixgbe_get_bus_info(hw);
 793
 794         /* Unlock any pending hardware semaphore */
 795         ixgbe_swfw_lock_reset(hw);
 796
 797         /* Initialize DCB configuration*/
 798         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 799         ixgbe_dcb_init(hw,dcb_config);
 800         /* Get Hardware Flow Control setting */
 801         hw->fc.requested_mode = ixgbe_fc_full;
 802         hw->fc.current_mode = ixgbe_fc_full;
 803         hw->fc.pause_time = IXGBE_FC_PAUSE;
 804         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 805                 hw->fc.low_water[i] = IXGBE_FC_LO;
 806                 hw->fc.high_water[i] = IXGBE_FC_HI;
 807         }
 808         hw->fc.send_xon = 1;
 809
 810         /* Make sure we have a good EEPROM before we read from it */
 811         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 812         if (diag != IXGBE_SUCCESS) {
 813                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 814                 return -EIO;
 815         }
 816
 817 #ifdef RTE_NIC_BYPASS
 818         diag = ixgbe_bypass_init_hw(hw);
 819 #else
 820         diag = ixgbe_init_hw(hw);
 821 #endif /* RTE_NIC_BYPASS */
 822
 823         /*
 824          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 825          * is called too soon after the kernel driver unbinding/binding occurs.
 826          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 827          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 828          * also called. See ixgbe_identify_phy_82599(). The reason for the
 829          * failure is not known, and only occuts when virtualisation features
 830          * are disabled in the bios. A delay of 100ms  was found to be enough by
 831          * trial-and-error, and is doubled to be safe.
 832          */
 833         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 834                 rte_delay_ms(200);
 835                 diag = ixgbe_init_hw(hw);
 836         }
 837
 838         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 839                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 840                     "LOM.  Please be aware there may be issues associated "
 841                     "with your hardware.");
 842                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 843                     "please contact your Intel or hardware representative "
 844                     "who provided you with this hardware.");
 845         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 846                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 847         if (diag) {
 848                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 849                 return -EIO;
 850         }
 851
 852         /* disable interrupt */
 853         ixgbe_disable_intr(hw);
 854
 855         /* reset mappings for queue statistics hw counters*/
 856         ixgbe_reset_qstat_mappings(hw);
 857
 858         /* Allocate memory for storing MAC addresses */
 859         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 860                         hw->mac.num_rar_entries, 0);
 861         if (eth_dev->data->mac_addrs == NULL) {
 862                 PMD_INIT_LOG(ERR,
 863                         "Failed to allocate %u bytes needed to store "
 864                         "MAC addresses",
 865                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 866                 return -ENOMEM;
 867         }
 868         /* Copy the permanent MAC address */
 869         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 870                         &eth_dev->data->mac_addrs[0]);
 871
 872         /* Allocate memory for storing hash filter MAC addresses */
 873         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 874                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 875         if (eth_dev->data->hash_mac_addrs == NULL) {
 876                 PMD_INIT_LOG(ERR,
 877                         "Failed to allocate %d bytes needed to store MAC addresses",
 878                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 879                 return -ENOMEM;
 880         }
 881
 882         /* initialize the vfta */
 883         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 884
 885         /* initialize the hw strip bitmap*/
 886         memset(hwstrip, 0, sizeof(*hwstrip));
 887
 888         /* initialize PF if max_vfs not zero */
 889         ixgbe_pf_host_init(eth_dev);
 890
 891         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 892         /* let hardware know driver is loaded */
 893         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 894         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 895         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 896         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 897         IXGBE_WRITE_FLUSH(hw);
 898
 899         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 900                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 901                              (int) hw->mac.type, (int) hw->phy.type,
 902                              (int) hw->phy.sfp_type);
 903         else
 904                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 905                              (int) hw->mac.type, (int) hw->phy.type);
 906
 907         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 908                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 909                         pci_dev->id.device_id);
 910
 911         rte_intr_callback_register(&(pci_dev->intr_handle),
 912                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 913
 914         /* enable uio intr after callback register */
 915         rte_intr_enable(&(pci_dev->intr_handle));
 916
 917         /* enable support intr */
 918         ixgbe_enable_intr(eth_dev);
 919
 920         return 0;
 921 }
 922
 923
 924 /*
 925  * Negotiate mailbox API version with the PF.
 926  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 927  * Then we try to negotiate starting with the most recent one.
 928  * If all negotiation attempts fail, then we will proceed with
 929  * the default one (ixgbe_mbox_api_10).
 930  */
 931 static void
 932 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 933 {
 934         int32_t i;
 935
 936         /* start with highest supported, proceed down */
 937         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 938                 ixgbe_mbox_api_11,
 939                 ixgbe_mbox_api_10,
 940         };
 941
 942         for (i = 0;
 943                         i != RTE_DIM(sup_ver) &&
 944                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 945                         i++)
 946                 ;
 947 }
 948
 949 static void
 950 generate_random_mac_addr(struct ether_addr *mac_addr)
 951 {
 952         uint64_t random;
 953
 954         /* Set Organizationally Unique Identifier (OUI) prefix. */
 955         mac_addr->addr_bytes[0] = 0x00;
 956         mac_addr->addr_bytes[1] = 0x09;
 957         mac_addr->addr_bytes[2] = 0xC0;
 958         /* Force indication of locally assigned MAC address. */
 959         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 960         /* Generate the last 3 bytes of the MAC address with a random number. */
 961         random = rte_rand();
 962         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 963 }
 964
 965 /*
 966  * Virtual Function device init
 967  */
 968 static int
 969 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 970                      struct rte_eth_dev *eth_dev)
 971 {
 972         int diag;
 973         uint32_t tc, tcs;
 974         struct rte_pci_device *pci_dev;
 975         struct ixgbe_hw *hw =
 976                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 977         struct ixgbe_vfta * shadow_vfta =
 978                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 979         struct ixgbe_hwstrip *hwstrip =
 980                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 981         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 982
 983         PMD_INIT_FUNC_TRACE();
 984
 985         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 986         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 987         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 988
 989         /* for secondary processes, we don't initialise any further as primary
 990          * has already done this work. Only check we don't need a different
 991          * RX function */
 992         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 993                 if (eth_dev->data->scattered_rx)
 994                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 995                 return 0;
 996         }
 997
 998         pci_dev = eth_dev->pci_dev;
 999
1000         hw->device_id = pci_dev->id.device_id;
1001         hw->vendor_id = pci_dev->id.vendor_id;
1002         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1003
1004         /* initialize the vfta */
1005         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1006
1007         /* initialize the hw strip bitmap*/
1008         memset(hwstrip, 0, sizeof(*hwstrip));
1009
1010         /* Initialize the shared code (base driver) */
1011         diag = ixgbe_init_shared_code(hw);
1012         if (diag != IXGBE_SUCCESS) {
1013                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1014                 return -EIO;
1015         }
1016
1017         /* init_mailbox_params */
1018         hw->mbx.ops.init_params(hw);
1019
1020         /* Disable the interrupts for VF */
1021         ixgbevf_intr_disable(hw);
1022
1023         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1024         diag = hw->mac.ops.reset_hw(hw);
1025
1026         /*
1027          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1028          * the underlying PF driver has not assigned a MAC address to the VF.
1029          * In this case, assign a random MAC address.
1030          */
1031         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1032                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1033                 return (diag);
1034         }
1035
1036         /* negotiate mailbox API version to use with the PF. */
1037         ixgbevf_negotiate_api(hw);
1038
1039         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1040         ixgbevf_get_queues(hw, &tcs, &tc);
1041
1042         /* Allocate memory for storing MAC addresses */
1043         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1044                         hw->mac.num_rar_entries, 0);
1045         if (eth_dev->data->mac_addrs == NULL) {
1046                 PMD_INIT_LOG(ERR,
1047                         "Failed to allocate %u bytes needed to store "
1048                         "MAC addresses",
1049                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1050                 return -ENOMEM;
1051         }
1052
1053         /* Generate a random MAC address, if none was assigned by PF. */
1054         if (is_zero_ether_addr(perm_addr)) {
1055                 generate_random_mac_addr(perm_addr);
1056                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1057                 if (diag) {
1058                         rte_free(eth_dev->data->mac_addrs);
1059                         eth_dev->data->mac_addrs = NULL;
1060                         return diag;
1061                 }
1062                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1063                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1064                              "%02x:%02x:%02x:%02x:%02x:%02x",
1065                              perm_addr->addr_bytes[0],
1066                              perm_addr->addr_bytes[1],
1067                              perm_addr->addr_bytes[2],
1068                              perm_addr->addr_bytes[3],
1069                              perm_addr->addr_bytes[4],
1070                              perm_addr->addr_bytes[5]);
1071         }
1072
1073         /* Copy the permanent MAC address */
1074         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1075
1076         /* reset the hardware with the new settings */
1077         diag = hw->mac.ops.start_hw(hw);
1078         switch (diag) {
1079                 case  0:
1080                         break;
1081
1082                 default:
1083                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1084                         return (-EIO);
1085         }
1086
1087         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1088                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1089                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1090
1091         return 0;
1092 }
1093
1094 static struct eth_driver rte_ixgbe_pmd = {
1095         {
1096                 .name = "rte_ixgbe_pmd",
1097                 .id_table = pci_id_ixgbe_map,
1098                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1099         },
1100         .eth_dev_init = eth_ixgbe_dev_init,
1101         .dev_private_size = sizeof(struct ixgbe_adapter),
1102 };
1103
1104 /*
1105  * virtual function driver struct
1106  */
1107 static struct eth_driver rte_ixgbevf_pmd = {
1108         {
1109                 .name = "rte_ixgbevf_pmd",
1110                 .id_table = pci_id_ixgbevf_map,
1111                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1112         },
1113         .eth_dev_init = eth_ixgbevf_dev_init,
1114         .dev_private_size = sizeof(struct ixgbe_adapter),
1115 };
1116
1117 /*
1118  * Driver initialization routine.
1119  * Invoked once at EAL init time.
1120  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1121  */
1122 static int
1123 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1124 {
1125         PMD_INIT_FUNC_TRACE();
1126
1127         rte_eth_driver_register(&rte_ixgbe_pmd);
1128         return 0;
1129 }
1130
1131 /*
1132  * VF Driver initialization routine.
1133  * Invoked one at EAL init time.
1134  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1135  */
1136 static int
1137 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1138 {
1139         PMD_INIT_FUNC_TRACE();
1140
1141         rte_eth_driver_register(&rte_ixgbevf_pmd);
1142         return (0);
1143 }
1144
1145 static int
1146 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1147 {
1148         struct ixgbe_hw *hw =
1149                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1150         struct ixgbe_vfta * shadow_vfta =
1151                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1152         uint32_t vfta;
1153         uint32_t vid_idx;
1154         uint32_t vid_bit;
1155
1156         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1157         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1158         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1159         if (on)
1160                 vfta |= vid_bit;
1161         else
1162                 vfta &= ~vid_bit;
1163         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1164
1165         /* update local VFTA copy */
1166         shadow_vfta->vfta[vid_idx] = vfta;
1167
1168         return 0;
1169 }
1170
1171 static void
1172 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1173 {
1174         if (on)
1175                 ixgbe_vlan_hw_strip_enable(dev, queue);
1176         else
1177                 ixgbe_vlan_hw_strip_disable(dev, queue);
1178 }
1179
1180 static void
1181 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1182 {
1183         struct ixgbe_hw *hw =
1184                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1185
1186         /* Only the high 16-bits is valid */
1187         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1188 }
1189
1190 void
1191 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1192 {
1193         struct ixgbe_hw *hw =
1194                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1195         uint32_t vlnctrl;
1196
1197         PMD_INIT_FUNC_TRACE();
1198
1199         /* Filter Table Disable */
1200         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1201         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1202
1203         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1204 }
1205
1206 void
1207 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1208 {
1209         struct ixgbe_hw *hw =
1210                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211         struct ixgbe_vfta * shadow_vfta =
1212                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1213         uint32_t vlnctrl;
1214         uint16_t i;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         /* Filter Table Enable */
1219         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1220         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1221         vlnctrl |= IXGBE_VLNCTRL_VFE;
1222
1223         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1224
1225         /* write whatever is in local vfta copy */
1226         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1227                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1228 }
1229
1230 static void
1231 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1232 {
1233         struct ixgbe_hwstrip *hwstrip =
1234                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1235
1236         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1237                 return;
1238
1239         if (on)
1240                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1241         else
1242                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1243 }
1244
1245 static void
1246 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1247 {
1248         struct ixgbe_hw *hw =
1249                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1250         uint32_t ctrl;
1251
1252         PMD_INIT_FUNC_TRACE();
1253
1254         if (hw->mac.type == ixgbe_mac_82598EB) {
1255                 /* No queue level support */
1256                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1257                 return;
1258         }
1259         else {
1260                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1261                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1262                 ctrl &= ~IXGBE_RXDCTL_VME;
1263                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1264         }
1265         /* record those setting for HW strip per queue */
1266         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1267 }
1268
1269 static void
1270 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1271 {
1272         struct ixgbe_hw *hw =
1273                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         uint32_t ctrl;
1275
1276         PMD_INIT_FUNC_TRACE();
1277
1278         if (hw->mac.type == ixgbe_mac_82598EB) {
1279                 /* No queue level supported */
1280                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1281                 return;
1282         }
1283         else {
1284                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1285                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1286                 ctrl |= IXGBE_RXDCTL_VME;
1287                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1288         }
1289         /* record those setting for HW strip per queue */
1290         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1291 }
1292
1293 void
1294 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1295 {
1296         struct ixgbe_hw *hw =
1297                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1298         uint32_t ctrl;
1299         uint16_t i;
1300
1301         PMD_INIT_FUNC_TRACE();
1302
1303         if (hw->mac.type == ixgbe_mac_82598EB) {
1304                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1305                 ctrl &= ~IXGBE_VLNCTRL_VME;
1306                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1307         }
1308         else {
1309                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1310                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1311                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1312                         ctrl &= ~IXGBE_RXDCTL_VME;
1313                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1314
1315                         /* record those setting for HW strip per queue */
1316                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1317                 }
1318         }
1319 }
1320
1321 void
1322 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1323 {
1324         struct ixgbe_hw *hw =
1325                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         uint32_t ctrl;
1327         uint16_t i;
1328
1329         PMD_INIT_FUNC_TRACE();
1330
1331         if (hw->mac.type == ixgbe_mac_82598EB) {
1332                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1333                 ctrl |= IXGBE_VLNCTRL_VME;
1334                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1335         }
1336         else {
1337                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1338                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1339                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1340                         ctrl |= IXGBE_RXDCTL_VME;
1341                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1342
1343                         /* record those setting for HW strip per queue */
1344                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1345                 }
1346         }
1347 }
1348
1349 static void
1350 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1351 {
1352         struct ixgbe_hw *hw =
1353                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354         uint32_t ctrl;
1355
1356         PMD_INIT_FUNC_TRACE();
1357
1358         /* DMATXCTRL: Geric Double VLAN Disable */
1359         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1360         ctrl &= ~IXGBE_DMATXCTL_GDV;
1361         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1362
1363         /* CTRL_EXT: Global Double VLAN Disable */
1364         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1365         ctrl &= ~IXGBE_EXTENDED_VLAN;
1366         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1367
1368 }
1369
1370 static void
1371 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1372 {
1373         struct ixgbe_hw *hw =
1374                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375         uint32_t ctrl;
1376
1377         PMD_INIT_FUNC_TRACE();
1378
1379         /* DMATXCTRL: Geric Double VLAN Enable */
1380         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1381         ctrl |= IXGBE_DMATXCTL_GDV;
1382         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1383
1384         /* CTRL_EXT: Global Double VLAN Enable */
1385         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1386         ctrl |= IXGBE_EXTENDED_VLAN;
1387         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1388
1389         /*
1390          * VET EXT field in the EXVET register = 0x8100 by default
1391          * So no need to change. Same to VT field of DMATXCTL register
1392          */
1393 }
1394
1395 static void
1396 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1397 {
1398         if(mask & ETH_VLAN_STRIP_MASK){
1399                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1400                         ixgbe_vlan_hw_strip_enable_all(dev);
1401                 else
1402                         ixgbe_vlan_hw_strip_disable_all(dev);
1403         }
1404
1405         if(mask & ETH_VLAN_FILTER_MASK){
1406                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1407                         ixgbe_vlan_hw_filter_enable(dev);
1408                 else
1409                         ixgbe_vlan_hw_filter_disable(dev);
1410         }
1411
1412         if(mask & ETH_VLAN_EXTEND_MASK){
1413                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1414                         ixgbe_vlan_hw_extend_enable(dev);
1415                 else
1416                         ixgbe_vlan_hw_extend_disable(dev);
1417         }
1418 }
1419
1420 static void
1421 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1422 {
1423         struct ixgbe_hw *hw =
1424                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1425         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1426         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1427         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1428         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1429 }
1430
1431 static int
1432 ixgbe_dev_configure(struct rte_eth_dev *dev)
1433 {
1434         struct ixgbe_interrupt *intr =
1435                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1436
1437         PMD_INIT_FUNC_TRACE();
1438
1439         /* set flag to update link status after init */
1440         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1441
1442         return 0;
1443 }
1444
1445 /*
1446  * Configure device link speed and setup link.
1447  * It returns 0 on success.
1448  */
1449 static int
1450 ixgbe_dev_start(struct rte_eth_dev *dev)
1451 {
1452         struct ixgbe_hw *hw =
1453                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454         struct ixgbe_vf_info *vfinfo =
1455                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1456         int err, link_up = 0, negotiate = 0;
1457         uint32_t speed = 0;
1458         int mask = 0;
1459         int status;
1460         uint16_t vf, idx;
1461
1462         PMD_INIT_FUNC_TRACE();
1463
1464         /* IXGBE devices don't support half duplex */
1465         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1466                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1467                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1468                              dev->data->dev_conf.link_duplex,
1469                              dev->data->port_id);
1470                 return -EINVAL;
1471         }
1472
1473         /* stop adapter */
1474         hw->adapter_stopped = FALSE;
1475         ixgbe_stop_adapter(hw);
1476
1477         /* reinitialize adapter
1478          * this calls reset and start */
1479         status = ixgbe_pf_reset_hw(hw);
1480         if (status != 0)
1481                 return -1;
1482         hw->mac.ops.start_hw(hw);
1483         hw->mac.get_link_status = true;
1484
1485         /* configure PF module if SRIOV enabled */
1486         ixgbe_pf_host_configure(dev);
1487
1488         /* initialize transmission unit */
1489         ixgbe_dev_tx_init(dev);
1490
1491         /* This can fail when allocating mbufs for descriptor rings */
1492         err = ixgbe_dev_rx_init(dev);
1493         if (err) {
1494                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1495                 goto error;
1496         }
1497
1498         ixgbe_dev_rxtx_start(dev);
1499
1500         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1501                 err = hw->mac.ops.setup_sfp(hw);
1502                 if (err)
1503                         goto error;
1504         }
1505
1506         /* Turn on the laser */
1507         ixgbe_enable_tx_laser(hw);
1508
1509         /* Skip link setup if loopback mode is enabled for 82599. */
1510         if (hw->mac.type == ixgbe_mac_82599EB &&
1511                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1512                 goto skip_link_setup;
1513
1514         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1515         if (err)
1516                 goto error;
1517         dev->data->dev_link.link_status = link_up;
1518
1519         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1520         if (err)
1521                 goto error;
1522
1523         switch(dev->data->dev_conf.link_speed) {
1524         case ETH_LINK_SPEED_AUTONEG:
1525                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1526                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1527                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1528                 break;
1529         case ETH_LINK_SPEED_100:
1530                 /*
1531                  * Invalid for 82598 but error will be detected by
1532                  * ixgbe_setup_link()
1533                  */
1534                 speed = IXGBE_LINK_SPEED_100_FULL;
1535                 break;
1536         case ETH_LINK_SPEED_1000:
1537                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1538                 break;
1539         case ETH_LINK_SPEED_10000:
1540                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1541                 break;
1542         default:
1543                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1544                              dev->data->dev_conf.link_speed,
1545                              dev->data->port_id);
1546                 goto error;
1547         }
1548
1549         err = ixgbe_setup_link(hw, speed, link_up);
1550         if (err)
1551                 goto error;
1552
1553 skip_link_setup:
1554
1555         /* check if lsc interrupt is enabled */
1556         if (dev->data->dev_conf.intr_conf.lsc != 0)
1557                 ixgbe_dev_lsc_interrupt_setup(dev);
1558
1559         /* resume enabled intr since hw reset */
1560         ixgbe_enable_intr(dev);
1561
1562         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1563                 ETH_VLAN_EXTEND_MASK;
1564         ixgbe_vlan_offload_set(dev, mask);
1565
1566         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1567                 /* Enable vlan filtering for VMDq */
1568                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1569         }
1570
1571         /* Configure DCB hw */
1572         ixgbe_configure_dcb(dev);
1573
1574         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1575                 err = ixgbe_fdir_configure(dev);
1576                 if (err)
1577                         goto error;
1578         }
1579
1580         /* Restore vf rate limit */
1581         if (vfinfo != NULL) {
1582                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1583                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1584                                 if (vfinfo[vf].tx_rate[idx] != 0)
1585                                         ixgbe_set_vf_rate_limit(dev, vf,
1586                                                 vfinfo[vf].tx_rate[idx],
1587                                                 1 << idx);
1588         }
1589
1590         ixgbe_restore_statistics_mapping(dev);
1591
1592         return (0);
1593
1594 error:
1595         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1596         ixgbe_dev_clear_queues(dev);
1597         return -EIO;
1598 }
1599
1600 /*
1601  * Stop device: disable rx and tx functions to allow for reconfiguring.
1602  */
1603 static void
1604 ixgbe_dev_stop(struct rte_eth_dev *dev)
1605 {
1606         struct rte_eth_link link;
1607         struct ixgbe_hw *hw =
1608                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1609         struct ixgbe_vf_info *vfinfo =
1610                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1611         int vf;
1612
1613         PMD_INIT_FUNC_TRACE();
1614
1615         /* disable interrupts */
1616         ixgbe_disable_intr(hw);
1617
1618         /* reset the NIC */
1619         ixgbe_pf_reset_hw(hw);
1620         hw->adapter_stopped = FALSE;
1621
1622         /* stop adapter */
1623         ixgbe_stop_adapter(hw);
1624
1625         for (vf = 0; vfinfo != NULL &&
1626                      vf < dev->pci_dev->max_vfs; vf++)
1627                 vfinfo[vf].clear_to_send = false;
1628
1629         /* Turn off the laser */
1630         ixgbe_disable_tx_laser(hw);
1631
1632         ixgbe_dev_clear_queues(dev);
1633
1634         /* Clear stored conf */
1635         dev->data->scattered_rx = 0;
1636
1637         /* Clear recorded link status */
1638         memset(&link, 0, sizeof(link));
1639         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1640 }
1641
1642 /*
1643  * Set device link up: enable tx laser.
1644  */
1645 static int
1646 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1647 {
1648         struct ixgbe_hw *hw =
1649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         if (hw->mac.type == ixgbe_mac_82599EB) {
1651 #ifdef RTE_NIC_BYPASS
1652                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1653                         /* Not suported in bypass mode */
1654                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1655                                      "by device id 0x%x", hw->device_id);
1656                         return -ENOTSUP;
1657                 }
1658 #endif
1659                 /* Turn on the laser */
1660                 ixgbe_enable_tx_laser(hw);
1661                 return 0;
1662         }
1663
1664         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1665                      hw->device_id);
1666         return -ENOTSUP;
1667 }
1668
1669 /*
1670  * Set device link down: disable tx laser.
1671  */
1672 static int
1673 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1674 {
1675         struct ixgbe_hw *hw =
1676                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         if (hw->mac.type == ixgbe_mac_82599EB) {
1678 #ifdef RTE_NIC_BYPASS
1679                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1680                         /* Not suported in bypass mode */
1681                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1682                                      "by device id 0x%x", hw->device_id);
1683                         return -ENOTSUP;
1684                 }
1685 #endif
1686                 /* Turn off the laser */
1687                 ixgbe_disable_tx_laser(hw);
1688                 return 0;
1689         }
1690
1691         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1692                      hw->device_id);
1693         return -ENOTSUP;
1694 }
1695
1696 /*
1697  * Reest and stop device.
1698  */
1699 static void
1700 ixgbe_dev_close(struct rte_eth_dev *dev)
1701 {
1702         struct ixgbe_hw *hw =
1703                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704
1705         PMD_INIT_FUNC_TRACE();
1706
1707         ixgbe_pf_reset_hw(hw);
1708
1709         ixgbe_dev_stop(dev);
1710         hw->adapter_stopped = 1;
1711
1712         ixgbe_disable_pcie_master(hw);
1713
1714         /* reprogram the RAR[0] in case user changed it. */
1715         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1716 }
1717
1718 /*
1719  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1720  */
1721 static void
1722 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1723 {
1724         struct ixgbe_hw *hw =
1725                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         struct ixgbe_hw_stats *hw_stats =
1727                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1728         uint32_t bprc, lxon, lxoff, total;
1729         uint64_t total_missed_rx, total_qbrc, total_qprc;
1730         unsigned i;
1731
1732         total_missed_rx = 0;
1733         total_qbrc = 0;
1734         total_qprc = 0;
1735
1736         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1737         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1738         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1739         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1740
1741         for (i = 0; i < 8; i++) {
1742                 uint32_t mp;
1743                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1744                 /* global total per queue */
1745                 hw_stats->mpc[i] += mp;
1746                 /* Running comprehensive total for stats display */
1747                 total_missed_rx += hw_stats->mpc[i];
1748                 if (hw->mac.type == ixgbe_mac_82598EB)
1749                         hw_stats->rnbc[i] +=
1750                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1751                 hw_stats->pxontxc[i] +=
1752                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1753                 hw_stats->pxonrxc[i] +=
1754                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1755                 hw_stats->pxofftxc[i] +=
1756                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1757                 hw_stats->pxoffrxc[i] +=
1758                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1759                 hw_stats->pxon2offc[i] +=
1760                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1761         }
1762         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1763                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1764                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1765                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1766                 hw_stats->qbrc[i] +=
1767                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1768                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1769                 hw_stats->qbtc[i] +=
1770                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1771                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1772
1773                 total_qprc += hw_stats->qprc[i];
1774                 total_qbrc += hw_stats->qbrc[i];
1775         }
1776         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1777         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1778         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1779
1780         /* Note that gprc counts missed packets */
1781         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1782
1783         if (hw->mac.type != ixgbe_mac_82598EB) {
1784                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1785                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1786                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1787                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1788                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1789                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1790                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1791                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1792         } else {
1793                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1794                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1795                 /* 82598 only has a counter in the high register */
1796                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1797                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1798                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1799         }
1800
1801         /*
1802          * Workaround: mprc hardware is incorrectly counting
1803          * broadcasts, so for now we subtract those.
1804          */
1805         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1806         hw_stats->bprc += bprc;
1807         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1808         if (hw->mac.type == ixgbe_mac_82598EB)
1809                 hw_stats->mprc -= bprc;
1810
1811         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1812         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1813         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1814         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1815         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1816         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1817
1818         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1819         hw_stats->lxontxc += lxon;
1820         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1821         hw_stats->lxofftxc += lxoff;
1822         total = lxon + lxoff;
1823
1824         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1825         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1826         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1827         hw_stats->gptc -= total;
1828         hw_stats->mptc -= total;
1829         hw_stats->ptc64 -= total;
1830         hw_stats->gotc -= total * ETHER_MIN_LEN;
1831
1832         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1833         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1834         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1835         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1836         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1837         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1838         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1839         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1840         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1841         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1842         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1843         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1844         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1845         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1846         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1847         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1848         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1849         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1850         /* Only read FCOE on 82599 */
1851         if (hw->mac.type != ixgbe_mac_82598EB) {
1852                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1853                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1854                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1855                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1856                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1857         }
1858
1859         if (stats == NULL)
1860                 return;
1861
1862         /* Fill out the rte_eth_stats statistics structure */
1863         stats->ipackets = total_qprc;
1864         stats->ibytes = total_qbrc;
1865         stats->opackets = hw_stats->gptc;
1866         stats->obytes = hw_stats->gotc;
1867         stats->imcasts = hw_stats->mprc;
1868
1869         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1870                 stats->q_ipackets[i] = hw_stats->qprc[i];
1871                 stats->q_opackets[i] = hw_stats->qptc[i];
1872                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1873                 stats->q_obytes[i] = hw_stats->qbtc[i];
1874                 stats->q_errors[i] = hw_stats->qprdc[i];
1875         }
1876
1877         /* Rx Errors */
1878         stats->ibadcrc  = hw_stats->crcerrs;
1879         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1880         stats->imissed  = total_missed_rx;
1881         stats->ierrors  = stats->ibadcrc +
1882                           stats->ibadlen +
1883                           stats->imissed +
1884                           hw_stats->illerrc + hw_stats->errbc;
1885
1886         /* Tx Errors */
1887         stats->oerrors  = 0;
1888
1889         /* XON/XOFF pause frames */
1890         stats->tx_pause_xon  = hw_stats->lxontxc;
1891         stats->rx_pause_xon  = hw_stats->lxonrxc;
1892         stats->tx_pause_xoff = hw_stats->lxofftxc;
1893         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1894
1895         /* Flow Director Stats registers */
1896         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1897         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1898         stats->fdirmatch = hw_stats->fdirmatch;
1899         stats->fdirmiss = hw_stats->fdirmiss;
1900 }
1901
1902 static void
1903 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1904 {
1905         struct ixgbe_hw_stats *stats =
1906                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1907
1908         /* HW registers are cleared on read */
1909         ixgbe_dev_stats_get(dev, NULL);
1910
1911         /* Reset software totals */
1912         memset(stats, 0, sizeof(*stats));
1913 }
1914
1915 static void
1916 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1917 {
1918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1919         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1920                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1921
1922         /* Good Rx packet, include VF loopback */
1923         UPDATE_VF_STAT(IXGBE_VFGPRC,
1924             hw_stats->last_vfgprc, hw_stats->vfgprc);
1925
1926         /* Good Rx octets, include VF loopback */
1927         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1928             hw_stats->last_vfgorc, hw_stats->vfgorc);
1929
1930         /* Good Tx packet, include VF loopback */
1931         UPDATE_VF_STAT(IXGBE_VFGPTC,
1932             hw_stats->last_vfgptc, hw_stats->vfgptc);
1933
1934         /* Good Tx octets, include VF loopback */
1935         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1936             hw_stats->last_vfgotc, hw_stats->vfgotc);
1937
1938         /* Rx Multicst Packet */
1939         UPDATE_VF_STAT(IXGBE_VFMPRC,
1940             hw_stats->last_vfmprc, hw_stats->vfmprc);
1941
1942         if (stats == NULL)
1943                 return;
1944
1945         stats->ipackets = hw_stats->vfgprc;
1946         stats->ibytes = hw_stats->vfgorc;
1947         stats->opackets = hw_stats->vfgptc;
1948         stats->obytes = hw_stats->vfgotc;
1949         stats->imcasts = hw_stats->vfmprc;
1950 }
1951
1952 static void
1953 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1954 {
1955         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1956                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1957
1958         /* Sync HW register to the last stats */
1959         ixgbevf_dev_stats_get(dev, NULL);
1960
1961         /* reset HW current stats*/
1962         hw_stats->vfgprc = 0;
1963         hw_stats->vfgorc = 0;
1964         hw_stats->vfgptc = 0;
1965         hw_stats->vfgotc = 0;
1966         hw_stats->vfmprc = 0;
1967
1968 }
1969
1970 static void
1971 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1972 {
1973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974
1975         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1976         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1977         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1978         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1979         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1980         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1981         dev_info->max_vfs = dev->pci_dev->max_vfs;
1982         if (hw->mac.type == ixgbe_mac_82598EB)
1983                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1984         else
1985                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1986         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1987         dev_info->rx_offload_capa =
1988                 DEV_RX_OFFLOAD_VLAN_STRIP |
1989                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1990                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1991                 DEV_RX_OFFLOAD_TCP_CKSUM;
1992         dev_info->tx_offload_capa =
1993                 DEV_TX_OFFLOAD_VLAN_INSERT |
1994                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1995                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1996                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1997                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1998                 DEV_TX_OFFLOAD_TCP_TSO;
1999
2000         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2001                 .rx_thresh = {
2002                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2003                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2004                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2005                 },
2006                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2007                 .rx_drop_en = 0,
2008         };
2009
2010         dev_info->default_txconf = (struct rte_eth_txconf) {
2011                 .tx_thresh = {
2012                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2013                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2014                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2015                 },
2016                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2017                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2018                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2019                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2020         };
2021         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2022 }
2023
2024 static void
2025 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2026                      struct rte_eth_dev_info *dev_info)
2027 {
2028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029
2030         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2031         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2032         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2033         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2034         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2035         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2036         dev_info->max_vfs = dev->pci_dev->max_vfs;
2037         if (hw->mac.type == ixgbe_mac_82598EB)
2038                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2039         else
2040                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2041         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2042                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2043                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2044                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2045         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2046                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2047                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2048                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2049                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2050
2051         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2052                 .rx_thresh = {
2053                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2054                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2055                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2056                 },
2057                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2058                 .rx_drop_en = 0,
2059         };
2060
2061         dev_info->default_txconf = (struct rte_eth_txconf) {
2062                 .tx_thresh = {
2063                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2064                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2065                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2066                 },
2067                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2068                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2069                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2070                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2071         };
2072 }
2073
2074 /* return 0 means link status changed, -1 means not changed */
2075 static int
2076 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2077 {
2078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         struct rte_eth_link link, old;
2080         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2081         int link_up;
2082         int diag;
2083
2084         link.link_status = 0;
2085         link.link_speed = 0;
2086         link.link_duplex = 0;
2087         memset(&old, 0, sizeof(old));
2088         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2089
2090         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2091         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2092                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2093         else
2094                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2095         if (diag != 0) {
2096                 link.link_speed = ETH_LINK_SPEED_100;
2097                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2098                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2099                 if (link.link_status == old.link_status)
2100                         return -1;
2101                 return 0;
2102         }
2103
2104         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2105             !hw->mac.get_link_status) {
2106                 memcpy(&link, &old, sizeof(link));
2107                 return -1;
2108         }
2109
2110         if (link_up == 0) {
2111                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2112                 if (link.link_status == old.link_status)
2113                         return -1;
2114                 return 0;
2115         }
2116         link.link_status = 1;
2117         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2118
2119         switch (link_speed) {
2120         default:
2121         case IXGBE_LINK_SPEED_UNKNOWN:
2122                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2123                 link.link_speed = ETH_LINK_SPEED_100;
2124                 break;
2125
2126         case IXGBE_LINK_SPEED_100_FULL:
2127                 link.link_speed = ETH_LINK_SPEED_100;
2128                 break;
2129
2130         case IXGBE_LINK_SPEED_1GB_FULL:
2131                 link.link_speed = ETH_LINK_SPEED_1000;
2132                 break;
2133
2134         case IXGBE_LINK_SPEED_10GB_FULL:
2135                 link.link_speed = ETH_LINK_SPEED_10000;
2136                 break;
2137         }
2138         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2139
2140         if (link.link_status == old.link_status)
2141                 return -1;
2142
2143         return 0;
2144 }
2145
2146 static void
2147 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2148 {
2149         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         uint32_t fctrl;
2151
2152         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2153         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2154         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2155 }
2156
2157 static void
2158 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2159 {
2160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2161         uint32_t fctrl;
2162
2163         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2164         fctrl &= (~IXGBE_FCTRL_UPE);
2165         if (dev->data->all_multicast == 1)
2166                 fctrl |= IXGBE_FCTRL_MPE;
2167         else
2168                 fctrl &= (~IXGBE_FCTRL_MPE);
2169         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2170 }
2171
2172 static void
2173 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2174 {
2175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2176         uint32_t fctrl;
2177
2178         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2179         fctrl |= IXGBE_FCTRL_MPE;
2180         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2181 }
2182
2183 static void
2184 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2185 {
2186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187         uint32_t fctrl;
2188
2189         if (dev->data->promiscuous == 1)
2190                 return; /* must remain in all_multicast mode */
2191
2192         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2193         fctrl &= (~IXGBE_FCTRL_MPE);
2194         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2195 }
2196
2197 /**
2198  * It clears the interrupt causes and enables the interrupt.
2199  * It will be called once only during nic initialized.
2200  *
2201  * @param dev
2202  *  Pointer to struct rte_eth_dev.
2203  *
2204  * @return
2205  *  - On success, zero.
2206  *  - On failure, a negative value.
2207  */
2208 static int
2209 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2210 {
2211         struct ixgbe_interrupt *intr =
2212                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2213
2214         ixgbe_dev_link_status_print(dev);
2215         intr->mask |= IXGBE_EICR_LSC;
2216
2217         return 0;
2218 }
2219
2220 /*
2221  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2222  *
2223  * @param dev
2224  *  Pointer to struct rte_eth_dev.
2225  *
2226  * @return
2227  *  - On success, zero.
2228  *  - On failure, a negative value.
2229  */
2230 static int
2231 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2232 {
2233         uint32_t eicr;
2234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2235         struct ixgbe_interrupt *intr =
2236                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2237
2238         /* clear all cause mask */
2239         ixgbe_disable_intr(hw);
2240
2241         /* read-on-clear nic registers here */
2242         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2243         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2244
2245         intr->flags = 0;
2246         if (eicr & IXGBE_EICR_LSC) {
2247                 /* set flag for async link update */
2248                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2249         }
2250
2251         if (eicr & IXGBE_EICR_MAILBOX)
2252                 intr->flags |= IXGBE_FLAG_MAILBOX;
2253
2254         return 0;
2255 }
2256
2257 /**
2258  * It gets and then prints the link status.
2259  *
2260  * @param dev
2261  *  Pointer to struct rte_eth_dev.
2262  *
2263  * @return
2264  *  - On success, zero.
2265  *  - On failure, a negative value.
2266  */
2267 static void
2268 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2269 {
2270         struct rte_eth_link link;
2271
2272         memset(&link, 0, sizeof(link));
2273         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2274         if (link.link_status) {
2275                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2276                                         (int)(dev->data->port_id),
2277                                         (unsigned)link.link_speed,
2278                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2279                                         "full-duplex" : "half-duplex");
2280         } else {
2281                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2282                                 (int)(dev->data->port_id));
2283         }
2284         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2285                                 dev->pci_dev->addr.domain,
2286                                 dev->pci_dev->addr.bus,
2287                                 dev->pci_dev->addr.devid,
2288                                 dev->pci_dev->addr.function);
2289 }
2290
2291 /*
2292  * It executes link_update after knowing an interrupt occurred.
2293  *
2294  * @param dev
2295  *  Pointer to struct rte_eth_dev.
2296  *
2297  * @return
2298  *  - On success, zero.
2299  *  - On failure, a negative value.
2300  */
2301 static int
2302 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2303 {
2304         struct ixgbe_interrupt *intr =
2305                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2306         int64_t timeout;
2307         struct rte_eth_link link;
2308         int intr_enable_delay = false;
2309
2310         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2311
2312         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2313                 ixgbe_pf_mbx_process(dev);
2314                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2315         }
2316
2317         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2318                 /* get the link status before link update, for predicting later */
2319                 memset(&link, 0, sizeof(link));
2320                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2321
2322                 ixgbe_dev_link_update(dev, 0);
2323
2324                 /* likely to up */
2325                 if (!link.link_status)
2326                         /* handle it 1 sec later, wait it being stable */
2327                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2328                 /* likely to down */
2329                 else
2330                         /* handle it 4 sec later, wait it being stable */
2331                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2332
2333                 ixgbe_dev_link_status_print(dev);
2334
2335                 intr_enable_delay = true;
2336         }
2337
2338         if (intr_enable_delay) {
2339                 if (rte_eal_alarm_set(timeout * 1000,
2340                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2341                         PMD_DRV_LOG(ERR, "Error setting alarm");
2342         } else {
2343                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2344                 ixgbe_enable_intr(dev);
2345                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2346         }
2347
2348
2349         return 0;
2350 }
2351
2352 /**
2353  * Interrupt handler which shall be registered for alarm callback for delayed
2354  * handling specific interrupt to wait for the stable nic state. As the
2355  * NIC interrupt state is not stable for ixgbe after link is just down,
2356  * it needs to wait 4 seconds to get the stable status.
2357  *
2358  * @param handle
2359  *  Pointer to interrupt handle.
2360  * @param param
2361  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2362  *
2363  * @return
2364  *  void
2365  */
2366 static void
2367 ixgbe_dev_interrupt_delayed_handler(void *param)
2368 {
2369         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2370         struct ixgbe_interrupt *intr =
2371                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2372         struct ixgbe_hw *hw =
2373                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374         uint32_t eicr;
2375
2376         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2377         if (eicr & IXGBE_EICR_MAILBOX)
2378                 ixgbe_pf_mbx_process(dev);
2379
2380         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2381                 ixgbe_dev_link_update(dev, 0);
2382                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2383                 ixgbe_dev_link_status_print(dev);
2384                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2385         }
2386
2387         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2388         ixgbe_enable_intr(dev);
2389         rte_intr_enable(&(dev->pci_dev->intr_handle));
2390 }
2391
2392 /**
2393  * Interrupt handler triggered by NIC  for handling
2394  * specific interrupt.
2395  *
2396  * @param handle
2397  *  Pointer to interrupt handle.
2398  * @param param
2399  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2400  *
2401  * @return
2402  *  void
2403  */
2404 static void
2405 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2406                                                         void *param)
2407 {
2408         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2409         ixgbe_dev_interrupt_get_status(dev);
2410         ixgbe_dev_interrupt_action(dev);
2411 }
2412
2413 static int
2414 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2415 {
2416         struct ixgbe_hw *hw;
2417
2418         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2420 }
2421
2422 static int
2423 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2424 {
2425         struct ixgbe_hw *hw;
2426
2427         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2428         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2429 }
2430
2431 static int
2432 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2433 {
2434         struct ixgbe_hw *hw;
2435         uint32_t mflcn_reg;
2436         uint32_t fccfg_reg;
2437         int rx_pause;
2438         int tx_pause;
2439
2440         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441
2442         fc_conf->pause_time = hw->fc.pause_time;
2443         fc_conf->high_water = hw->fc.high_water[0];
2444         fc_conf->low_water = hw->fc.low_water[0];
2445         fc_conf->send_xon = hw->fc.send_xon;
2446         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2447
2448         /*
2449          * Return rx_pause status according to actual setting of
2450          * MFLCN register.
2451          */
2452         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2453         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2454                 rx_pause = 1;
2455         else
2456                 rx_pause = 0;
2457
2458         /*
2459          * Return tx_pause status according to actual setting of
2460          * FCCFG register.
2461          */
2462         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2463         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2464                 tx_pause = 1;
2465         else
2466                 tx_pause = 0;
2467
2468         if (rx_pause && tx_pause)
2469                 fc_conf->mode = RTE_FC_FULL;
2470         else if (rx_pause)
2471                 fc_conf->mode = RTE_FC_RX_PAUSE;
2472         else if (tx_pause)
2473                 fc_conf->mode = RTE_FC_TX_PAUSE;
2474         else
2475                 fc_conf->mode = RTE_FC_NONE;
2476
2477         return 0;
2478 }
2479
2480 static int
2481 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2482 {
2483         struct ixgbe_hw *hw;
2484         int err;
2485         uint32_t rx_buf_size;
2486         uint32_t max_high_water;
2487         uint32_t mflcn;
2488         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2489                 ixgbe_fc_none,
2490                 ixgbe_fc_rx_pause,
2491                 ixgbe_fc_tx_pause,
2492                 ixgbe_fc_full
2493         };
2494
2495         PMD_INIT_FUNC_TRACE();
2496
2497         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2499                 return -ENOTSUP;
2500         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2501         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2502
2503         /*
2504          * At least reserve one Ethernet frame for watermark
2505          * high_water/low_water in kilo bytes for ixgbe
2506          */
2507         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2508         if ((fc_conf->high_water > max_high_water) ||
2509                 (fc_conf->high_water < fc_conf->low_water)) {
2510                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2511                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2512                 return (-EINVAL);
2513         }
2514
2515         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2516         hw->fc.pause_time     = fc_conf->pause_time;
2517         hw->fc.high_water[0]  = fc_conf->high_water;
2518         hw->fc.low_water[0]   = fc_conf->low_water;
2519         hw->fc.send_xon       = fc_conf->send_xon;
2520
2521         err = ixgbe_fc_enable(hw);
2522
2523         /* Not negotiated is not an error case */
2524         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2525
2526                 /* check if we want to forward MAC frames - driver doesn't have native
2527                  * capability to do that, so we'll write the registers ourselves */
2528
2529                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2530
2531                 /* set or clear MFLCN.PMCF bit depending on configuration */
2532                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2533                         mflcn |= IXGBE_MFLCN_PMCF;
2534                 else
2535                         mflcn &= ~IXGBE_MFLCN_PMCF;
2536
2537                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2538                 IXGBE_WRITE_FLUSH(hw);
2539
2540                 return 0;
2541         }
2542
2543         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2544         return -EIO;
2545 }
2546
2547 /**
2548  *  ixgbe_pfc_enable_generic - Enable flow control
2549  *  @hw: pointer to hardware structure
2550  *  @tc_num: traffic class number
2551  *  Enable flow control according to the current settings.
2552  */
2553 static int
2554 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2555 {
2556         int ret_val = 0;
2557         uint32_t mflcn_reg, fccfg_reg;
2558         uint32_t reg;
2559         uint32_t fcrtl, fcrth;
2560         uint8_t i;
2561         uint8_t nb_rx_en;
2562
2563         /* Validate the water mark configuration */
2564         if (!hw->fc.pause_time) {
2565                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2566                 goto out;
2567         }
2568
2569         /* Low water mark of zero causes XOFF floods */
2570         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2571                  /* High/Low water can not be 0 */
2572                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2573                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2574                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2575                         goto out;
2576                 }
2577
2578                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2579                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2580                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2581                         goto out;
2582                 }
2583         }
2584         /* Negotiate the fc mode to use */
2585         ixgbe_fc_autoneg(hw);
2586
2587         /* Disable any previous flow control settings */
2588         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2589         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2590
2591         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2592         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2593
2594         switch (hw->fc.current_mode) {
2595         case ixgbe_fc_none:
2596                 /*
2597                  * If the count of enabled RX Priority Flow control >1,
2598                  * and the TX pause can not be disabled
2599                  */
2600                 nb_rx_en = 0;
2601                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2602                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2603                         if (reg & IXGBE_FCRTH_FCEN)
2604                                 nb_rx_en++;
2605                 }
2606                 if (nb_rx_en > 1)
2607                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2608                 break;
2609         case ixgbe_fc_rx_pause:
2610                 /*
2611                  * Rx Flow control is enabled and Tx Flow control is
2612                  * disabled by software override. Since there really
2613                  * isn't a way to advertise that we are capable of RX
2614                  * Pause ONLY, we will advertise that we support both
2615                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2616                  * disable the adapter's ability to send PAUSE frames.
2617                  */
2618                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2619                 /*
2620                  * If the count of enabled RX Priority Flow control >1,
2621                  * and the TX pause can not be disabled
2622                  */
2623                 nb_rx_en = 0;
2624                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2625                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2626                         if (reg & IXGBE_FCRTH_FCEN)
2627                                 nb_rx_en++;
2628                 }
2629                 if (nb_rx_en > 1)
2630                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2631                 break;
2632         case ixgbe_fc_tx_pause:
2633                 /*
2634                  * Tx Flow control is enabled, and Rx Flow control is
2635                  * disabled by software override.
2636                  */
2637                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2638                 break;
2639         case ixgbe_fc_full:
2640                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2641                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2642                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2643                 break;
2644         default:
2645                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2646                 ret_val = IXGBE_ERR_CONFIG;
2647                 goto out;
2648                 break;
2649         }
2650
2651         /* Set 802.3x based flow control settings. */
2652         mflcn_reg |= IXGBE_MFLCN_DPF;
2653         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2654         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2655
2656         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2657         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2658                 hw->fc.high_water[tc_num]) {
2659                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2660                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2661                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2662         } else {
2663                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2664                 /*
2665                  * In order to prevent Tx hangs when the internal Tx
2666                  * switch is enabled we must set the high water mark
2667                  * to the maximum FCRTH value.  This allows the Tx
2668                  * switch to function even under heavy Rx workloads.
2669                  */
2670                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2671         }
2672         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2673
2674         /* Configure pause time (2 TCs per register) */
2675         reg = hw->fc.pause_time * 0x00010001;
2676         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2677                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2678
2679         /* Configure flow control refresh threshold value */
2680         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2681
2682 out:
2683         return ret_val;
2684 }
2685
2686 static int
2687 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2688 {
2689         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2691
2692         if(hw->mac.type != ixgbe_mac_82598EB) {
2693                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2694         }
2695         return ret_val;
2696 }
2697
2698 static int
2699 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2700 {
2701         int err;
2702         uint32_t rx_buf_size;
2703         uint32_t max_high_water;
2704         uint8_t tc_num;
2705         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2706         struct ixgbe_hw *hw =
2707                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708         struct ixgbe_dcb_config *dcb_config =
2709                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2710
2711         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2712                 ixgbe_fc_none,
2713                 ixgbe_fc_rx_pause,
2714                 ixgbe_fc_tx_pause,
2715                 ixgbe_fc_full
2716         };
2717
2718         PMD_INIT_FUNC_TRACE();
2719
2720         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2721         tc_num = map[pfc_conf->priority];
2722         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2723         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2724         /*
2725          * At least reserve one Ethernet frame for watermark
2726          * high_water/low_water in kilo bytes for ixgbe
2727          */
2728         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2729         if ((pfc_conf->fc.high_water > max_high_water) ||
2730             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2731                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2732                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2733                 return (-EINVAL);
2734         }
2735
2736         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2737         hw->fc.pause_time = pfc_conf->fc.pause_time;
2738         hw->fc.send_xon = pfc_conf->fc.send_xon;
2739         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2740         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2741
2742         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2743
2744         /* Not negotiated is not an error case */
2745         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2746                 return 0;
2747
2748         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2749         return -EIO;
2750 }
2751
2752 static int
2753 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2754                           struct rte_eth_rss_reta_entry64 *reta_conf,
2755                           uint16_t reta_size)
2756 {
2757         uint8_t i, j, mask;
2758         uint32_t reta, r;
2759         uint16_t idx, shift;
2760         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2761
2762         PMD_INIT_FUNC_TRACE();
2763         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2764                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2765                         "(%d) doesn't match the number hardware can supported "
2766                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2767                 return -EINVAL;
2768         }
2769
2770         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2771                 idx = i / RTE_RETA_GROUP_SIZE;
2772                 shift = i % RTE_RETA_GROUP_SIZE;
2773                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2774                                                 IXGBE_4_BIT_MASK);
2775                 if (!mask)
2776                         continue;
2777                 if (mask == IXGBE_4_BIT_MASK)
2778                         r = 0;
2779                 else
2780                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2781                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2782                         if (mask & (0x1 << j))
2783                                 reta |= reta_conf[idx].reta[shift + j] <<
2784                                                         (CHAR_BIT * j);
2785                         else
2786                                 reta |= r & (IXGBE_8_BIT_MASK <<
2787                                                 (CHAR_BIT * j));
2788                 }
2789                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2790         }
2791
2792         return 0;
2793 }
2794
2795 static int
2796 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2797                          struct rte_eth_rss_reta_entry64 *reta_conf,
2798                          uint16_t reta_size)
2799 {
2800         uint8_t i, j, mask;
2801         uint32_t reta;
2802         uint16_t idx, shift;
2803         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2804
2805         PMD_INIT_FUNC_TRACE();
2806         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2807                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2808                         "(%d) doesn't match the number hardware can supported "
2809                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2810                 return -EINVAL;
2811         }
2812
2813         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2814                 idx = i / RTE_RETA_GROUP_SIZE;
2815                 shift = i % RTE_RETA_GROUP_SIZE;
2816                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2817                                                 IXGBE_4_BIT_MASK);
2818                 if (!mask)
2819                         continue;
2820
2821                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2822                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2823                         if (mask & (0x1 << j))
2824                                 reta_conf[idx].reta[shift + j] =
2825                                         ((reta >> (CHAR_BIT * j)) &
2826                                                 IXGBE_8_BIT_MASK);
2827                 }
2828         }
2829
2830         return 0;
2831 }
2832
2833 static void
2834 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2835                                 uint32_t index, uint32_t pool)
2836 {
2837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838         uint32_t enable_addr = 1;
2839
2840         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2841 }
2842
2843 static void
2844 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2845 {
2846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847
2848         ixgbe_clear_rar(hw, index);
2849 }
2850
2851 static int
2852 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2853 {
2854         uint32_t hlreg0;
2855         uint32_t maxfrs;
2856         struct ixgbe_hw *hw;
2857         struct rte_eth_dev_info dev_info;
2858         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2859
2860         ixgbe_dev_info_get(dev, &dev_info);
2861
2862         /* check that mtu is within the allowed range */
2863         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2864                 return -EINVAL;
2865
2866         /* refuse mtu that requires the support of scattered packets when this
2867          * feature has not been enabled before. */
2868         if (!dev->data->scattered_rx &&
2869             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2870              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2871                 return -EINVAL;
2872
2873         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2874         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2875
2876         /* switch to jumbo mode if needed */
2877         if (frame_size > ETHER_MAX_LEN) {
2878                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2879                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2880         } else {
2881                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2882                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2883         }
2884         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2885
2886         /* update max frame size */
2887         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2888
2889         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2890         maxfrs &= 0x0000FFFF;
2891         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2892         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2893
2894         return 0;
2895 }
2896
2897 /*
2898  * Virtual Function operations
2899  */
2900 static void
2901 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2902 {
2903         PMD_INIT_FUNC_TRACE();
2904
2905         /* Clear interrupt mask to stop from interrupts being generated */
2906         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2907
2908         IXGBE_WRITE_FLUSH(hw);
2909 }
2910
2911 static int
2912 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2913 {
2914         struct rte_eth_conf* conf = &dev->data->dev_conf;
2915
2916         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2917                      dev->data->port_id);
2918
2919         /*
2920          * VF has no ability to enable/disable HW CRC
2921          * Keep the persistent behavior the same as Host PF
2922          */
2923 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2924         if (!conf->rxmode.hw_strip_crc) {
2925                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2926                 conf->rxmode.hw_strip_crc = 1;
2927         }
2928 #else
2929         if (conf->rxmode.hw_strip_crc) {
2930                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2931                 conf->rxmode.hw_strip_crc = 0;
2932         }
2933 #endif
2934
2935         return 0;
2936 }
2937
2938 static int
2939 ixgbevf_dev_start(struct rte_eth_dev *dev)
2940 {
2941         struct ixgbe_hw *hw =
2942                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943         int err, mask = 0;
2944
2945         PMD_INIT_FUNC_TRACE();
2946
2947         hw->mac.ops.reset_hw(hw);
2948         hw->mac.get_link_status = true;
2949
2950         /* negotiate mailbox API version to use with the PF. */
2951         ixgbevf_negotiate_api(hw);
2952
2953         ixgbevf_dev_tx_init(dev);
2954
2955         /* This can fail when allocating mbufs for descriptor rings */
2956         err = ixgbevf_dev_rx_init(dev);
2957         if (err) {
2958                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2959                 ixgbe_dev_clear_queues(dev);
2960                 return err;
2961         }
2962
2963         /* Set vfta */
2964         ixgbevf_set_vfta_all(dev,1);
2965
2966         /* Set HW strip */
2967         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2968                 ETH_VLAN_EXTEND_MASK;
2969         ixgbevf_vlan_offload_set(dev, mask);
2970
2971         ixgbevf_dev_rxtx_start(dev);
2972
2973         return 0;
2974 }
2975
2976 static void
2977 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2978 {
2979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2980
2981         PMD_INIT_FUNC_TRACE();
2982
2983         hw->adapter_stopped = TRUE;
2984         ixgbe_stop_adapter(hw);
2985
2986         /*
2987           * Clear what we set, but we still keep shadow_vfta to
2988           * restore after device starts
2989           */
2990         ixgbevf_set_vfta_all(dev,0);
2991
2992         /* Clear stored conf */
2993         dev->data->scattered_rx = 0;
2994
2995         ixgbe_dev_clear_queues(dev);
2996 }
2997
2998 static void
2999 ixgbevf_dev_close(struct rte_eth_dev *dev)
3000 {
3001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3002
3003         PMD_INIT_FUNC_TRACE();
3004
3005         ixgbe_reset_hw(hw);
3006
3007         ixgbevf_dev_stop(dev);
3008
3009         /* reprogram the RAR[0] in case user changed it. */
3010         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3011 }
3012
3013 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3014 {
3015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3016         struct ixgbe_vfta * shadow_vfta =
3017                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3018         int i = 0, j = 0, vfta = 0, mask = 1;
3019
3020         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3021                 vfta = shadow_vfta->vfta[i];
3022                 if(vfta){
3023                         mask = 1;
3024                         for (j = 0; j < 32; j++){
3025                                 if(vfta & mask)
3026                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3027                                 mask<<=1;
3028                         }
3029                 }
3030         }
3031
3032 }
3033
3034 static int
3035 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3036 {
3037         struct ixgbe_hw *hw =
3038                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039         struct ixgbe_vfta * shadow_vfta =
3040                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3041         uint32_t vid_idx = 0;
3042         uint32_t vid_bit = 0;
3043         int ret = 0;
3044
3045         PMD_INIT_FUNC_TRACE();
3046
3047         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3048         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3049         if(ret){
3050                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3051                 return ret;
3052         }
3053         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3054         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3055
3056         /* Save what we set and retore it after device reset */
3057         if (on)
3058                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3059         else
3060                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3061
3062         return 0;
3063 }
3064
3065 static void
3066 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3067 {
3068         struct ixgbe_hw *hw =
3069                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3070         uint32_t ctrl;
3071
3072         PMD_INIT_FUNC_TRACE();
3073
3074         if(queue >= hw->mac.max_rx_queues)
3075                 return;
3076
3077         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3078         if(on)
3079                 ctrl |= IXGBE_RXDCTL_VME;
3080         else
3081                 ctrl &= ~IXGBE_RXDCTL_VME;
3082         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3083
3084         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3085 }
3086
3087 static void
3088 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3089 {
3090         struct ixgbe_hw *hw =
3091                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3092         uint16_t i;
3093         int on = 0;
3094
3095         /* VF function only support hw strip feature, others are not support */
3096         if(mask & ETH_VLAN_STRIP_MASK){
3097                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3098
3099                 for(i=0; i < hw->mac.max_rx_queues; i++)
3100                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3101         }
3102 }
3103
3104 static int
3105 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3106 {
3107         uint32_t reg_val;
3108
3109         /* we only need to do this if VMDq is enabled */
3110         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3111         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3112                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3113                 return (-1);
3114         }
3115
3116         return 0;
3117 }
3118
3119 static uint32_t
3120 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3121 {
3122         uint32_t vector = 0;
3123         switch (hw->mac.mc_filter_type) {
3124         case 0:   /* use bits [47:36] of the address */
3125                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3126                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3127                 break;
3128         case 1:   /* use bits [46:35] of the address */
3129                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3130                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3131                 break;
3132         case 2:   /* use bits [45:34] of the address */
3133                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3134                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3135                 break;
3136         case 3:   /* use bits [43:32] of the address */
3137                 vector = ((uc_addr->addr_bytes[4]) |
3138                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3139                 break;
3140         default:  /* Invalid mc_filter_type */
3141                 break;
3142         }
3143
3144         /* vector can only be 12-bits or boundary will be exceeded */
3145         vector &= 0xFFF;
3146         return vector;
3147 }
3148
3149 static int
3150 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3151                                uint8_t on)
3152 {
3153         uint32_t vector;
3154         uint32_t uta_idx;
3155         uint32_t reg_val;
3156         uint32_t uta_shift;
3157         uint32_t rc;
3158         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3159         const uint32_t ixgbe_uta_bit_shift = 5;
3160         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3161         const uint32_t bit1 = 0x1;
3162
3163         struct ixgbe_hw *hw =
3164                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3165         struct ixgbe_uta_info *uta_info =
3166                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3167
3168         /* The UTA table only exists on 82599 hardware and newer */
3169         if (hw->mac.type < ixgbe_mac_82599EB)
3170                 return (-ENOTSUP);
3171
3172         vector = ixgbe_uta_vector(hw,mac_addr);
3173         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3174         uta_shift = vector & ixgbe_uta_bit_mask;
3175
3176         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3177         if(rc == on)
3178                 return 0;
3179
3180         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3181         if (on) {
3182                 uta_info->uta_in_use++;
3183                 reg_val |= (bit1 << uta_shift);
3184                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3185         } else {
3186                 uta_info->uta_in_use--;
3187                 reg_val &= ~(bit1 << uta_shift);
3188                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3189         }
3190
3191         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3192
3193         if (uta_info->uta_in_use > 0)
3194                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3195                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3196         else
3197                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3198
3199         return 0;
3200 }
3201
3202 static int
3203 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3204 {
3205         int i;
3206         struct ixgbe_hw *hw =
3207                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3208         struct ixgbe_uta_info *uta_info =
3209                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3210
3211         /* The UTA table only exists on 82599 hardware and newer */
3212         if (hw->mac.type < ixgbe_mac_82599EB)
3213                 return (-ENOTSUP);
3214
3215         if(on) {
3216                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3217                         uta_info->uta_shadow[i] = ~0;
3218                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3219                 }
3220         } else {
3221                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3222                         uta_info->uta_shadow[i] = 0;
3223                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3224                 }
3225         }
3226         return 0;
3227
3228 }
3229
3230 uint32_t
3231 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3232 {
3233         uint32_t new_val = orig_val;
3234
3235         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3236                 new_val |= IXGBE_VMOLR_AUPE;
3237         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3238                 new_val |= IXGBE_VMOLR_ROMPE;
3239         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3240                 new_val |= IXGBE_VMOLR_ROPE;
3241         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3242                 new_val |= IXGBE_VMOLR_BAM;
3243         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3244                 new_val |= IXGBE_VMOLR_MPE;
3245
3246         return new_val;
3247 }
3248
3249 static int
3250 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3251                                uint16_t rx_mask, uint8_t on)
3252 {
3253         int val = 0;
3254
3255         struct ixgbe_hw *hw =
3256                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3257         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3258
3259         if (hw->mac.type == ixgbe_mac_82598EB) {
3260                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3261                              " on 82599 hardware and newer");
3262                 return (-ENOTSUP);
3263         }
3264         if (ixgbe_vmdq_mode_check(hw) < 0)
3265                 return (-ENOTSUP);
3266
3267         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3268
3269         if (on)
3270                 vmolr |= val;
3271         else
3272                 vmolr &= ~val;
3273
3274         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3275
3276         return 0;
3277 }
3278
3279 static int
3280 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3281 {
3282         uint32_t reg,addr;
3283         uint32_t val;
3284         const uint8_t bit1 = 0x1;
3285
3286         struct ixgbe_hw *hw =
3287                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288
3289         if (ixgbe_vmdq_mode_check(hw) < 0)
3290                 return (-ENOTSUP);
3291
3292         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3293         reg = IXGBE_READ_REG(hw, addr);
3294         val = bit1 << pool;
3295
3296         if (on)
3297                 reg |= val;
3298         else
3299                 reg &= ~val;
3300
3301         IXGBE_WRITE_REG(hw, addr,reg);
3302
3303         return 0;
3304 }
3305
3306 static int
3307 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3308 {
3309         uint32_t reg,addr;
3310         uint32_t val;
3311         const uint8_t bit1 = 0x1;
3312
3313         struct ixgbe_hw *hw =
3314                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3315
3316         if (ixgbe_vmdq_mode_check(hw) < 0)
3317                 return (-ENOTSUP);
3318
3319         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3320         reg = IXGBE_READ_REG(hw, addr);
3321         val = bit1 << pool;
3322
3323         if (on)
3324                 reg |= val;
3325         else
3326                 reg &= ~val;
3327
3328         IXGBE_WRITE_REG(hw, addr,reg);
3329
3330         return 0;
3331 }
3332
3333 static int
3334 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3335                         uint64_t pool_mask, uint8_t vlan_on)
3336 {
3337         int ret = 0;
3338         uint16_t pool_idx;
3339         struct ixgbe_hw *hw =
3340                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3341
3342         if (ixgbe_vmdq_mode_check(hw) < 0)
3343                 return (-ENOTSUP);
3344         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3345                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3346                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3347                         if (ret < 0)
3348                                 return ret;
3349         }
3350
3351         return ret;
3352 }
3353
3354 static int
3355 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3356                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3357                         uint8_t rule_id, uint8_t on)
3358 {
3359         uint32_t mr_ctl,vlvf;
3360         uint32_t mp_lsb = 0;
3361         uint32_t mv_msb = 0;
3362         uint32_t mv_lsb = 0;
3363         uint32_t mp_msb = 0;
3364         uint8_t i = 0;
3365         int reg_index = 0;
3366         uint64_t vlan_mask = 0;
3367
3368         const uint8_t pool_mask_offset = 32;
3369         const uint8_t vlan_mask_offset = 32;
3370         const uint8_t dst_pool_offset = 8;
3371         const uint8_t rule_mr_offset  = 4;
3372         const uint8_t mirror_rule_mask= 0x0F;
3373
3374         struct ixgbe_mirror_info *mr_info =
3375                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3376         struct ixgbe_hw *hw =
3377                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378
3379         if (ixgbe_vmdq_mode_check(hw) < 0)
3380                 return (-ENOTSUP);
3381
3382         /* Check if vlan mask is valid */
3383         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3384                 if (mirror_conf->vlan.vlan_mask == 0)
3385                         return (-EINVAL);
3386         }
3387
3388         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3389         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3390                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3391                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3392                                 /* search vlan id related pool vlan filter index */
3393                                 reg_index = ixgbe_find_vlvf_slot(hw,
3394                                                 mirror_conf->vlan.vlan_id[i]);
3395                                 if(reg_index < 0)
3396                                         return (-EINVAL);
3397                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3398                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3399                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3400                                                 == mirror_conf->vlan.vlan_id[i]))
3401                                         vlan_mask |= (1ULL << reg_index);
3402                                 else
3403                                         return (-EINVAL);
3404                         }
3405                 }
3406
3407                 if (on) {
3408                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3409                         mv_msb = vlan_mask >> vlan_mask_offset;
3410
3411                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3412                                                 mirror_conf->vlan.vlan_mask;
3413                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3414                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3415                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3416                                                 mirror_conf->vlan.vlan_id[i];
3417                         }
3418                 } else {
3419                         mv_lsb = 0;
3420                         mv_msb = 0;
3421                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3422                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3423                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3424                 }
3425         }
3426
3427         /*
3428          * if enable pool mirror, write related pool mask register,if disable
3429          * pool mirror, clear PFMRVM register
3430          */
3431         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3432                 if (on) {
3433                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3434                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3435                         mr_info->mr_conf[rule_id].pool_mask =
3436                                         mirror_conf->pool_mask;
3437
3438                 } else {
3439                         mp_lsb = 0;
3440                         mp_msb = 0;
3441                         mr_info->mr_conf[rule_id].pool_mask = 0;
3442                 }
3443         }
3444
3445         /* read  mirror control register and recalculate it */
3446         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3447
3448         if (on) {
3449                 mr_ctl |= mirror_conf->rule_type_mask;
3450                 mr_ctl &= mirror_rule_mask;
3451                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3452         } else
3453                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3454
3455         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3456         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3457
3458         /* write mirrror control  register */
3459         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3460
3461         /* write pool mirrror control  register */
3462         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3463                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3464                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3465                                 mp_msb);
3466         }
3467         /* write VLAN mirrror control  register */
3468         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3469                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3470                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3471                                 mv_msb);
3472         }
3473
3474         return 0;
3475 }
3476
3477 static int
3478 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3479 {
3480         int mr_ctl = 0;
3481         uint32_t lsb_val = 0;
3482         uint32_t msb_val = 0;
3483         const uint8_t rule_mr_offset = 4;
3484
3485         struct ixgbe_hw *hw =
3486                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3487         struct ixgbe_mirror_info *mr_info =
3488                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3489
3490         if (ixgbe_vmdq_mode_check(hw) < 0)
3491                 return (-ENOTSUP);
3492
3493         memset(&mr_info->mr_conf[rule_id], 0,
3494                 sizeof(struct rte_eth_vmdq_mirror_conf));
3495
3496         /* clear PFVMCTL register */
3497         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3498
3499         /* clear pool mask register */
3500         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3501         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3502
3503         /* clear vlan mask register */
3504         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3505         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3506
3507         return 0;
3508 }
3509
3510 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3511         uint16_t queue_idx, uint16_t tx_rate)
3512 {
3513         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514         uint32_t rf_dec, rf_int;
3515         uint32_t bcnrc_val;
3516         uint16_t link_speed = dev->data->dev_link.link_speed;
3517
3518         if (queue_idx >= hw->mac.max_tx_queues)
3519                 return -EINVAL;
3520
3521         if (tx_rate != 0) {
3522                 /* Calculate the rate factor values to set */
3523                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3524                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3525                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3526
3527                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3528                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3529                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3530                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3531         } else {
3532                 bcnrc_val = 0;
3533         }
3534
3535         /*
3536          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3537          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3538          * set as 0x4.
3539          */
3540         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3541                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3542                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3543                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3544                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3545         else
3546                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3547                         IXGBE_MMW_SIZE_DEFAULT);
3548
3549         /* Set RTTBCNRC of queue X */
3550         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3551         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3552         IXGBE_WRITE_FLUSH(hw);
3553
3554         return 0;
3555 }
3556
3557 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3558         uint16_t tx_rate, uint64_t q_msk)
3559 {
3560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561         struct ixgbe_vf_info *vfinfo =
3562                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3563         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3564         uint32_t queue_stride =
3565                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3566         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3567         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3568         uint16_t total_rate = 0;
3569
3570         if (queue_end >= hw->mac.max_tx_queues)
3571                 return -EINVAL;
3572
3573         if (vfinfo != NULL) {
3574                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3575                         if (vf_idx == vf)
3576                                 continue;
3577                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3578                                 idx++)
3579                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3580                 }
3581         } else
3582                 return -EINVAL;
3583
3584         /* Store tx_rate for this vf. */
3585         for (idx = 0; idx < nb_q_per_pool; idx++) {
3586                 if (((uint64_t)0x1 << idx) & q_msk) {
3587                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3588                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3589                         total_rate += tx_rate;
3590                 }
3591         }
3592
3593         if (total_rate > dev->data->dev_link.link_speed) {
3594                 /*
3595                  * Reset stored TX rate of the VF if it causes exceed
3596                  * link speed.
3597                  */
3598                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3599                 return -EINVAL;
3600         }
3601
3602         /* Set RTTBCNRC of each queue/pool for vf X  */
3603         for (; queue_idx <= queue_end; queue_idx++) {
3604                 if (0x1 & q_msk)
3605                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3606                 q_msk = q_msk >> 1;
3607         }
3608
3609         return 0;
3610 }
3611
3612 static void
3613 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3614                      __attribute__((unused)) uint32_t index,
3615                      __attribute__((unused)) uint32_t pool)
3616 {
3617         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3618         int diag;
3619
3620         /*
3621          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3622          * operation. Trap this case to avoid exhausting the [very limited]
3623          * set of PF resources used to store VF MAC addresses.
3624          */
3625         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3626                 return;
3627         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3628         if (diag == 0)
3629                 return;
3630         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3631 }
3632
3633 static void
3634 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3635 {
3636         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3637         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3638         struct ether_addr *mac_addr;
3639         uint32_t i;
3640         int diag;
3641
3642         /*
3643          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3644          * not support the deletion of a given MAC address.
3645          * Instead, it imposes to delete all MAC addresses, then to add again
3646          * all MAC addresses with the exception of the one to be deleted.
3647          */
3648         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3649
3650         /*
3651          * Add again all MAC addresses, with the exception of the deleted one
3652          * and of the permanent MAC address.
3653          */
3654         for (i = 0, mac_addr = dev->data->mac_addrs;
3655              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3656                 /* Skip the deleted MAC address */
3657                 if (i == index)
3658                         continue;
3659                 /* Skip NULL MAC addresses */
3660                 if (is_zero_ether_addr(mac_addr))
3661                         continue;
3662                 /* Skip the permanent MAC address */
3663                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3664                         continue;
3665                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3666                 if (diag != 0)
3667                         PMD_DRV_LOG(ERR,
3668                                     "Adding again MAC address "
3669                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3670                                     "diag=%d",
3671                                     mac_addr->addr_bytes[0],
3672                                     mac_addr->addr_bytes[1],
3673                                     mac_addr->addr_bytes[2],
3674                                     mac_addr->addr_bytes[3],
3675                                     mac_addr->addr_bytes[4],
3676                                     mac_addr->addr_bytes[5],
3677                                     diag);
3678         }
3679 }
3680
3681 /*
3682  * add syn filter
3683  *
3684  * @param
3685  * dev: Pointer to struct rte_eth_dev.
3686  * filter: ponter to the filter that will be added.
3687  * rx_queue: the queue id the filter assigned to.
3688  *
3689  * @return
3690  *    - On success, zero.
3691  *    - On failure, a negative value.
3692  */
3693 static int
3694 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3695                         struct rte_syn_filter *filter, uint16_t rx_queue)
3696 {
3697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698         uint32_t synqf;
3699
3700         if (hw->mac.type != ixgbe_mac_82599EB)
3701                 return -ENOSYS;
3702
3703         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3704                 return -EINVAL;
3705
3706         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3707
3708         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3709                 return -EINVAL;
3710
3711         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3712                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3713
3714         if (filter->hig_pri)
3715                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3716         else
3717                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3718
3719         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3720         return 0;
3721 }
3722
3723 /*
3724  * remove syn filter
3725  *
3726  * @param
3727  * dev: Pointer to struct rte_eth_dev.
3728  *
3729  * @return
3730  *    - On success, zero.
3731  *    - On failure, a negative value.
3732  */
3733 static int
3734 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3735 {
3736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737         uint32_t synqf;
3738
3739         if (hw->mac.type != ixgbe_mac_82599EB)
3740                 return -ENOSYS;
3741
3742         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3743
3744         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3745
3746         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3747         return 0;
3748 }
3749
3750 /*
3751  * get the syn filter's info
3752  *
3753  * @param
3754  * dev: Pointer to struct rte_eth_dev.
3755  * filter: ponter to the filter that returns.
3756  * *rx_queue: pointer to the queue id the filter assigned to.
3757  *
3758  * @return
3759  *    - On success, zero.
3760  *    - On failure, a negative value.
3761  */
3762 static int
3763 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3764                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3765
3766 {
3767         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3768         uint32_t synqf;
3769
3770         if (hw->mac.type != ixgbe_mac_82599EB)
3771                 return -ENOSYS;
3772
3773         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3774         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3775                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3776                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3777                 return 0;
3778         }
3779         return -ENOENT;
3780 }
3781
3782 static inline enum ixgbe_5tuple_protocol
3783 convert_protocol_type(uint8_t protocol_value)
3784 {
3785         if (protocol_value == IPPROTO_TCP)
3786                 return IXGBE_FILTER_PROTOCOL_TCP;
3787         else if (protocol_value == IPPROTO_UDP)
3788                 return IXGBE_FILTER_PROTOCOL_UDP;
3789         else if (protocol_value == IPPROTO_SCTP)
3790                 return IXGBE_FILTER_PROTOCOL_SCTP;
3791         else
3792                 return IXGBE_FILTER_PROTOCOL_NONE;
3793 }
3794
3795 static inline uint8_t
3796 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3797 {
3798         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3799                 return IPPROTO_TCP;
3800         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3801                 return IPPROTO_UDP;
3802         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3803                 return IPPROTO_SCTP;
3804         else
3805                 return 0;
3806 }
3807
3808 /*
3809  * add a 5tuple filter
3810  *
3811  * @param
3812  * dev: Pointer to struct rte_eth_dev.
3813  * index: the index the filter allocates.
3814  * filter: ponter to the filter that will be added.
3815  * rx_queue: the queue id the filter assigned to.
3816  *
3817  * @return
3818  *    - On success, zero.
3819  *    - On failure, a negative value.
3820  */
3821 static int
3822 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3823                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3824 {
3825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3826         uint32_t ftqf, sdpqf = 0;
3827         uint32_t l34timir = 0;
3828         uint8_t mask = 0xff;
3829
3830         if (hw->mac.type != ixgbe_mac_82599EB)
3831                 return -ENOSYS;
3832
3833         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3834                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3835                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3836                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3837                 return -EINVAL;  /* filter index is out of range. */
3838
3839         if (filter->tcp_flags) {
3840                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3841                 return -EINVAL;
3842         }
3843
3844         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3845         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3846                 return -EINVAL;  /* filter index is in use. */
3847
3848         ftqf = 0;
3849         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3850         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3851
3852         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3853                 IXGBE_FTQF_PROTOCOL_MASK);
3854         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3855                 IXGBE_FTQF_PRIORITY_SHIFT);
3856         if (filter->src_ip_mask == 0) /* 0 means compare. */
3857                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3858         if (filter->dst_ip_mask == 0)
3859                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3860         if (filter->src_port_mask == 0)
3861                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3862         if (filter->dst_port_mask == 0)
3863                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3864         if (filter->protocol_mask == 0)
3865                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3866         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3867         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3868         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3869
3870         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3871         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3872         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3873         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3874
3875         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3876         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3877         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3878         return 0;
3879 }
3880
3881 /*
3882  * remove a 5tuple filter
3883  *
3884  * @param
3885  * dev: Pointer to struct rte_eth_dev.
3886  * index: the index the filter allocates.
3887  *
3888  * @return
3889  *    - On success, zero.
3890  *    - On failure, a negative value.
3891  */
3892 static int
3893 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3894                         uint16_t index)
3895 {
3896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3897
3898         if (hw->mac.type != ixgbe_mac_82599EB)
3899                 return -ENOSYS;
3900
3901         if (index >= IXGBE_MAX_FTQF_FILTERS)
3902                 return -EINVAL;  /* filter index is out of range. */
3903
3904         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3905         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3906         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3907         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3908         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3909         return 0;
3910 }
3911
3912 /*
3913  * get a 5tuple filter
3914  *
3915  * @param
3916  * dev: Pointer to struct rte_eth_dev.
3917  * index: the index the filter allocates
3918  * filter: ponter to the filter that returns.
3919  * *rx_queue: pointer of the queue id the filter assigned to.
3920  *
3921  * @return
3922  *    - On success, zero.
3923  *    - On failure, a negative value.
3924  */
3925 static int
3926 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3927                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3928 {
3929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3930         uint32_t sdpqf, ftqf, l34timir;
3931         uint8_t mask;
3932         enum ixgbe_5tuple_protocol proto;
3933
3934         if (hw->mac.type != ixgbe_mac_82599EB)
3935                 return -ENOSYS;
3936
3937         if (index >= IXGBE_MAX_FTQF_FILTERS)
3938                 return -EINVAL;  /* filter index is out of range. */
3939
3940         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3941         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3942                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3943                 filter->protocol = revert_protocol_type(proto);
3944                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3945                                         IXGBE_FTQF_PRIORITY_MASK;
3946                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3947                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3948                 filter->src_ip_mask =
3949                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3950                 filter->dst_ip_mask =
3951                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3952                 filter->src_port_mask =
3953                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3954                 filter->dst_port_mask =
3955                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3956                 filter->protocol_mask =
3957                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3958
3959                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3960                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3961                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3962                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3963                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3964                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3965
3966                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3967                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3968                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3969                 return 0;
3970         }
3971         return -ENOENT;
3972 }
3973
3974 static int
3975 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3976 {
3977         struct ixgbe_hw *hw;
3978         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3979
3980         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3981
3982         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3983                 return -EINVAL;
3984
3985         /* refuse mtu that requires the support of scattered packets when this
3986          * feature has not been enabled before. */
3987         if (!dev->data->scattered_rx &&
3988             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3989              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3990                 return -EINVAL;
3991
3992         /*
3993          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3994          * request of the version 2.0 of the mailbox API.
3995          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3996          * of the mailbox API.
3997          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3998          * prior to 3.11.33 which contains the following change:
3999          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4000          */
4001         ixgbevf_rlpml_set_vf(hw, max_frame);
4002
4003         /* update max frame size */
4004         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4005         return 0;
4006 }
4007
4008 #define MAC_TYPE_FILTER_SUP(type)    do {\
4009         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4010                 (type) != ixgbe_mac_X550)\
4011                 return -ENOTSUP;\
4012 } while (0)
4013
4014 static inline int
4015 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4016                         uint16_t ethertype)
4017 {
4018         int i;
4019
4020         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4021                 if (filter_info->ethertype_filters[i] == ethertype &&
4022                     (filter_info->ethertype_mask & (1 << i)))
4023                         return i;
4024         }
4025         return -1;
4026 }
4027
4028 static inline int
4029 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4030                         uint16_t ethertype)
4031 {
4032         int i;
4033
4034         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4035                 if (!(filter_info->ethertype_mask & (1 << i))) {
4036                         filter_info->ethertype_mask |= 1 << i;
4037                         filter_info->ethertype_filters[i] = ethertype;
4038                         return i;
4039                 }
4040         }
4041         return -1;
4042 }
4043
4044 static inline int
4045 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4046                         uint8_t idx)
4047 {
4048         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4049                 return -1;
4050         filter_info->ethertype_mask &= ~(1 << idx);
4051         filter_info->ethertype_filters[idx] = 0;
4052         return idx;
4053 }
4054
4055 static int
4056 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4057                         struct rte_eth_ethertype_filter *filter,
4058                         bool add)
4059 {
4060         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4061         struct ixgbe_filter_info *filter_info =
4062                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4063         uint32_t etqf = 0;
4064         uint32_t etqs = 0;
4065         int ret;
4066
4067         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4068                 return -EINVAL;
4069
4070         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4071                 filter->ether_type == ETHER_TYPE_IPv6) {
4072                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4073                         " ethertype filter.", filter->ether_type);
4074                 return -EINVAL;
4075         }
4076
4077         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4078                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4079                 return -EINVAL;
4080         }
4081         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4082                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4083                 return -EINVAL;
4084         }
4085
4086         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4087         if (ret >= 0 && add) {
4088                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4089                             filter->ether_type);
4090                 return -EEXIST;
4091         }
4092         if (ret < 0 && !add) {
4093                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4094                             filter->ether_type);
4095                 return -ENOENT;
4096         }
4097
4098         if (add) {
4099                 ret = ixgbe_ethertype_filter_insert(filter_info,
4100                         filter->ether_type);
4101                 if (ret < 0) {
4102                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4103                         return -ENOSYS;
4104                 }
4105                 etqf = IXGBE_ETQF_FILTER_EN;
4106                 etqf |= (uint32_t)filter->ether_type;
4107                 etqs |= (uint32_t)((filter->queue <<
4108                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4109                                     IXGBE_ETQS_RX_QUEUE);
4110                 etqs |= IXGBE_ETQS_QUEUE_EN;
4111         } else {
4112                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4113                 if (ret < 0)
4114                         return -ENOSYS;
4115         }
4116         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4117         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4118         IXGBE_WRITE_FLUSH(hw);
4119
4120         return 0;
4121 }
4122
4123 static int
4124 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4125                         struct rte_eth_ethertype_filter *filter)
4126 {
4127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4128         struct ixgbe_filter_info *filter_info =
4129                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4130         uint32_t etqf, etqs;
4131         int ret;
4132
4133         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4134         if (ret < 0) {
4135                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4136                             filter->ether_type);
4137                 return -ENOENT;
4138         }
4139
4140         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4141         if (etqf & IXGBE_ETQF_FILTER_EN) {
4142                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4143                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4144                 filter->flags = 0;
4145                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4146                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4147                 return 0;
4148         }
4149         return -ENOENT;
4150 }
4151
4152 /*
4153  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4154  * @dev: pointer to rte_eth_dev structure
4155  * @filter_op:operation will be taken.
4156  * @arg: a pointer to specific structure corresponding to the filter_op
4157  */
4158 static int
4159 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4160                                 enum rte_filter_op filter_op,
4161                                 void *arg)
4162 {
4163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4164         int ret;
4165
4166         MAC_TYPE_FILTER_SUP(hw->mac.type);
4167
4168         if (filter_op == RTE_ETH_FILTER_NOP)
4169                 return 0;
4170
4171         if (arg == NULL) {
4172                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4173                             filter_op);
4174                 return -EINVAL;
4175         }
4176
4177         switch (filter_op) {
4178         case RTE_ETH_FILTER_ADD:
4179                 ret = ixgbe_add_del_ethertype_filter(dev,
4180                         (struct rte_eth_ethertype_filter *)arg,
4181                         TRUE);
4182                 break;
4183         case RTE_ETH_FILTER_DELETE:
4184                 ret = ixgbe_add_del_ethertype_filter(dev,
4185                         (struct rte_eth_ethertype_filter *)arg,
4186                         FALSE);
4187                 break;
4188         case RTE_ETH_FILTER_GET:
4189                 ret = ixgbe_get_ethertype_filter(dev,
4190                         (struct rte_eth_ethertype_filter *)arg);
4191                 break;
4192         default:
4193                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4194                 ret = -EINVAL;
4195                 break;
4196         }
4197         return ret;
4198 }
4199
4200 static int
4201 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4202                      enum rte_filter_type filter_type,
4203                      enum rte_filter_op filter_op,
4204                      void *arg)
4205 {
4206         int ret = -EINVAL;
4207
4208         switch (filter_type) {
4209         case RTE_ETH_FILTER_ETHERTYPE:
4210                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4211                 break;
4212         default:
4213                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4214                                                         filter_type);
4215                 break;
4216         }
4217
4218         return ret;
4219 }
4220
4221 static struct rte_driver rte_ixgbe_driver = {
4222         .type = PMD_PDEV,
4223         .init = rte_ixgbe_pmd_init,
4224 };
4225
4226 static struct rte_driver rte_ixgbevf_driver = {
4227         .type = PMD_PDEV,
4228         .init = rte_ixgbevf_pmd_init,
4229 };
4230
4231 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4232 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);