lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72
  73 /*
  74  * High threshold controlling when to start sending XOFF frames. Must be at
  75  * least 8 bytes less than receive packet buffer size. This value is in units
  76  * of 1024 bytes.
  77  */
  78 #define IXGBE_FC_HI    0x80
  79
  80 /*
  81  * Low threshold controlling when to start sending XON frames. This value is
  82  * in units of 1024 bytes.
  83  */
  84 #define IXGBE_FC_LO    0x40
  85
  86 /* Timer value included in XOFF frames. */
  87 #define IXGBE_FC_PAUSE 0x680
  88
  89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  90 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  91 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  92
  93 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  94 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  95
  96 /*
  97  *  Default values for RX/TX configuration
  98  */
  99 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 100 #define IXGBE_DEFAULT_RX_PTHRESH      8
 101 #define IXGBE_DEFAULT_RX_HTHRESH      8
 102 #define IXGBE_DEFAULT_RX_WTHRESH      0
 103
 104 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 105 #define IXGBE_DEFAULT_TX_PTHRESH      32
 106 #define IXGBE_DEFAULT_TX_HTHRESH      0
 107 #define IXGBE_DEFAULT_TX_WTHRESH      0
 108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 109
 110 /* Bit shift and mask */
 111 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 112 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 113 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 114 #define IXGBE_8_BIT_MASK   UINT8_MAX
 115
 116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 117
 118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 119
 120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 121                 struct rte_eth_dev *eth_dev);
 122 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 125 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 126 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 133                                 int wait_to_complete);
 134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 135                                 struct rte_eth_stats *stats);
 136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 138                                              uint16_t queue_id,
 139                                              uint8_t stat_idx,
 140                                              uint8_t is_rx);
 141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 142                                struct rte_eth_dev_info *dev_info);
 143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 144                                  struct rte_eth_dev_info *dev_info);
 145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 151                 uint16_t queue, bool on);
 152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 153                 int on);
 154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 165                                struct rte_eth_fc_conf *fc_conf);
 166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 167                 struct rte_eth_pfc_conf *pfc_conf);
 168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 169                         struct rte_eth_rss_reta_entry64 *reta_conf,
 170                         uint16_t reta_size);
 171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 172                         struct rte_eth_rss_reta_entry64 *reta_conf,
 173                         uint16_t reta_size);
 174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 179                 void *param);
 180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 182                 uint32_t index, uint32_t pool);
 183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 185
 186 /* For Virtual Function support */
 187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 188                 struct rte_eth_dev *eth_dev);
 189 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 190 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 195                 struct rte_eth_stats *stats);
 196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 198                 uint16_t vlan_id, int on);
 199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 200                 uint16_t queue, int on);
 201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203
 204 /* For Eth VMDQ APIs support */
 205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 206                 ether_addr* mac_addr,uint8_t on);
 207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 208 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 209                 uint16_t rx_mask, uint8_t on);
 210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 213                 uint64_t pool_mask,uint8_t vlan_on);
 214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 216                 uint8_t rule_id, uint8_t on);
 217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 218                 uint8_t rule_id);
 219
 220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 221                 uint16_t queue_idx, uint16_t tx_rate);
 222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 223                 uint16_t tx_rate, uint64_t q_msk);
 224
 225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 226                                  struct ether_addr *mac_addr,
 227                                  uint32_t index, uint32_t pool);
 228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 229 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 230                         struct rte_syn_filter *filter, uint16_t rx_queue);
 231 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 232 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 233                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 234 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 235                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 236 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 237                         uint16_t index);
 238 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 239                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 240 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 241                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 242 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 243                         uint16_t index);
 244 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 245                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 246
 247 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 248
 249 /*
 250  * Define VF Stats MACRO for Non "cleared on read" register
 251  */
 252 #define UPDATE_VF_STAT(reg, last, cur)                          \
 253 {                                                               \
 254         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 255         cur += latest - last;                                   \
 256         last = latest;                                          \
 257 }
 258
 259 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 260 {                                                                \
 261         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 262         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 263         u64 latest = ((new_msb << 32) | new_lsb);                \
 264         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 265         last = latest;                                           \
 266 }
 267
 268 #define IXGBE_SET_HWSTRIP(h, q) do{\
 269                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 270                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 271                 (h)->bitmap[idx] |= 1 << bit;\
 272         }while(0)
 273
 274 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 275                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 276                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 277                 (h)->bitmap[idx] &= ~(1 << bit);\
 278         }while(0)
 279
 280 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 281                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 283                 (r) = (h)->bitmap[idx] >> bit & 1;\
 284         }while(0)
 285
 286 /*
 287  * The set of PCI devices this driver supports
 288  */
 289 static struct rte_pci_id pci_id_ixgbe_map[] = {
 290
 291 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 292 #include "rte_pci_dev_ids.h"
 293
 294 { .vendor_id = 0, /* sentinel */ },
 295 };
 296
 297
 298 /*
 299  * The set of PCI devices this driver supports (for 82599 VF)
 300  */
 301 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 302
 303 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 304 #include "rte_pci_dev_ids.h"
 305 { .vendor_id = 0, /* sentinel */ },
 306
 307 };
 308
 309 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 310         .dev_configure        = ixgbe_dev_configure,
 311         .dev_start            = ixgbe_dev_start,
 312         .dev_stop             = ixgbe_dev_stop,
 313         .dev_set_link_up    = ixgbe_dev_set_link_up,
 314         .dev_set_link_down  = ixgbe_dev_set_link_down,
 315         .dev_close            = ixgbe_dev_close,
 316         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 317         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 318         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 319         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 320         .link_update          = ixgbe_dev_link_update,
 321         .stats_get            = ixgbe_dev_stats_get,
 322         .stats_reset          = ixgbe_dev_stats_reset,
 323         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 324         .dev_infos_get        = ixgbe_dev_info_get,
 325         .mtu_set              = ixgbe_dev_mtu_set,
 326         .vlan_filter_set      = ixgbe_vlan_filter_set,
 327         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 328         .vlan_offload_set     = ixgbe_vlan_offload_set,
 329         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 330         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 331         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 332         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 333         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 334         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 335         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 336         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 337         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 338         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 339         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 340         .dev_led_on           = ixgbe_dev_led_on,
 341         .dev_led_off          = ixgbe_dev_led_off,
 342         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 343         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 344         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 345         .mac_addr_add         = ixgbe_add_rar,
 346         .mac_addr_remove      = ixgbe_remove_rar,
 347         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 348         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 349         .mirror_rule_set      = ixgbe_mirror_rule_set,
 350         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 351         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 352         .set_vf_rx            = ixgbe_set_pool_rx,
 353         .set_vf_tx            = ixgbe_set_pool_tx,
 354         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 355         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 356         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 357         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 358         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 359         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 360         .fdir_infos_get               = ixgbe_fdir_info_get,
 361         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 362         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 363         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 364         .fdir_set_masks               = ixgbe_fdir_set_masks,
 365         .reta_update          = ixgbe_dev_rss_reta_update,
 366         .reta_query           = ixgbe_dev_rss_reta_query,
 367 #ifdef RTE_NIC_BYPASS
 368         .bypass_init          = ixgbe_bypass_init,
 369         .bypass_state_set     = ixgbe_bypass_state_store,
 370         .bypass_state_show    = ixgbe_bypass_state_show,
 371         .bypass_event_set     = ixgbe_bypass_event_store,
 372         .bypass_event_show    = ixgbe_bypass_event_show,
 373         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 374         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 375         .bypass_ver_show      = ixgbe_bypass_ver_show,
 376         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 377 #endif /* RTE_NIC_BYPASS */
 378         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 379         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 380         .add_syn_filter          = ixgbe_add_syn_filter,
 381         .remove_syn_filter       = ixgbe_remove_syn_filter,
 382         .get_syn_filter          = ixgbe_get_syn_filter,
 383         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 384         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 385         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 386         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 387         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 388         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 389 };
 390
 391 /*
 392  * dev_ops for virtual function, bare necessities for basic vf
 393  * operation have been implemented
 394  */
 395 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 396
 397         .dev_configure        = ixgbevf_dev_configure,
 398         .dev_start            = ixgbevf_dev_start,
 399         .dev_stop             = ixgbevf_dev_stop,
 400         .link_update          = ixgbe_dev_link_update,
 401         .stats_get            = ixgbevf_dev_stats_get,
 402         .stats_reset          = ixgbevf_dev_stats_reset,
 403         .dev_close            = ixgbevf_dev_close,
 404         .dev_infos_get        = ixgbevf_dev_info_get,
 405         .mtu_set              = ixgbevf_dev_set_mtu,
 406         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 407         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 408         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 409         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 410         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 411         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 412         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 413         .mac_addr_add         = ixgbevf_add_mac_addr,
 414         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 415 };
 416
 417 /**
 418  * Atomically reads the link status information from global
 419  * structure rte_eth_dev.
 420  *
 421  * @param dev
 422  *   - Pointer to the structure rte_eth_dev to read from.
 423  *   - Pointer to the buffer to be saved with the link status.
 424  *
 425  * @return
 426  *   - On success, zero.
 427  *   - On failure, negative value.
 428  */
 429 static inline int
 430 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 431                                 struct rte_eth_link *link)
 432 {
 433         struct rte_eth_link *dst = link;
 434         struct rte_eth_link *src = &(dev->data->dev_link);
 435
 436         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 437                                         *(uint64_t *)src) == 0)
 438                 return -1;
 439
 440         return 0;
 441 }
 442
 443 /**
 444  * Atomically writes the link status information into global
 445  * structure rte_eth_dev.
 446  *
 447  * @param dev
 448  *   - Pointer to the structure rte_eth_dev to read from.
 449  *   - Pointer to the buffer to be saved with the link status.
 450  *
 451  * @return
 452  *   - On success, zero.
 453  *   - On failure, negative value.
 454  */
 455 static inline int
 456 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 457                                 struct rte_eth_link *link)
 458 {
 459         struct rte_eth_link *dst = &(dev->data->dev_link);
 460         struct rte_eth_link *src = link;
 461
 462         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 463                                         *(uint64_t *)src) == 0)
 464                 return -1;
 465
 466         return 0;
 467 }
 468
 469 /*
 470  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 471  */
 472 static inline int
 473 ixgbe_is_sfp(struct ixgbe_hw *hw)
 474 {
 475         switch (hw->phy.type) {
 476         case ixgbe_phy_sfp_avago:
 477         case ixgbe_phy_sfp_ftl:
 478         case ixgbe_phy_sfp_intel:
 479         case ixgbe_phy_sfp_unknown:
 480         case ixgbe_phy_sfp_passive_tyco:
 481         case ixgbe_phy_sfp_passive_unknown:
 482                 return 1;
 483         default:
 484                 return 0;
 485         }
 486 }
 487
 488 static inline int32_t
 489 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 490 {
 491         uint32_t ctrl_ext;
 492         int32_t status;
 493
 494         status = ixgbe_reset_hw(hw);
 495
 496         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 497         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 498         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 499         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 500         IXGBE_WRITE_FLUSH(hw);
 501
 502         return status;
 503 }
 504
 505 static inline void
 506 ixgbe_enable_intr(struct rte_eth_dev *dev)
 507 {
 508         struct ixgbe_interrupt *intr =
 509                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 510         struct ixgbe_hw *hw =
 511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 512
 513         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 514         IXGBE_WRITE_FLUSH(hw);
 515 }
 516
 517 /*
 518  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 519  */
 520 static void
 521 ixgbe_disable_intr(struct ixgbe_hw *hw)
 522 {
 523         PMD_INIT_FUNC_TRACE();
 524
 525         if (hw->mac.type == ixgbe_mac_82598EB) {
 526                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 527         } else {
 528                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 529                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 530                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 531         }
 532         IXGBE_WRITE_FLUSH(hw);
 533 }
 534
 535 /*
 536  * This function resets queue statistics mapping registers.
 537  * From Niantic datasheet, Initialization of Statistics section:
 538  * "...if software requires the queue counters, the RQSMR and TQSM registers
 539  * must be re-programmed following a device reset.
 540  */
 541 static void
 542 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 543 {
 544         uint32_t i;
 545
 546         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 547                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 548                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 549         }
 550 }
 551
 552
 553 static int
 554 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 555                                   uint16_t queue_id,
 556                                   uint8_t stat_idx,
 557                                   uint8_t is_rx)
 558 {
 559 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 560 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 561 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 562
 563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 564         struct ixgbe_stat_mapping_registers *stat_mappings =
 565                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 566         uint32_t qsmr_mask = 0;
 567         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 568         uint32_t q_map;
 569         uint8_t n, offset;
 570
 571         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 572                 (hw->mac.type != ixgbe_mac_X540) &&
 573                 (hw->mac.type != ixgbe_mac_X550) &&
 574                 (hw->mac.type != ixgbe_mac_X550EM_x))
 575                 return -ENOSYS;
 576
 577         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 578                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 579                      queue_id, stat_idx);
 580
 581         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 582         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 583                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 584                 return -EIO;
 585         }
 586         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 587
 588         /* Now clear any previous stat_idx set */
 589         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 590         if (!is_rx)
 591                 stat_mappings->tqsm[n] &= ~clearing_mask;
 592         else
 593                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 594
 595         q_map = (uint32_t)stat_idx;
 596         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 597         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 598         if (!is_rx)
 599                 stat_mappings->tqsm[n] |= qsmr_mask;
 600         else
 601                 stat_mappings->rqsmr[n] |= qsmr_mask;
 602
 603         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 604                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 605                      queue_id, stat_idx);
 606         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 607                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 608
 609         /* Now write the mapping in the appropriate register */
 610         if (is_rx) {
 611                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 612                              stat_mappings->rqsmr[n], n);
 613                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 614         }
 615         else {
 616                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 617                              stat_mappings->tqsm[n], n);
 618                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 619         }
 620         return 0;
 621 }
 622
 623 static void
 624 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 625 {
 626         struct ixgbe_stat_mapping_registers *stat_mappings =
 627                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 629         int i;
 630
 631         /* write whatever was in stat mapping table to the NIC */
 632         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 633                 /* rx */
 634                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 635
 636                 /* tx */
 637                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 638         }
 639 }
 640
 641 static void
 642 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 643 {
 644         uint8_t i;
 645         struct ixgbe_dcb_tc_config *tc;
 646         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 647
 648         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 649         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 650         for (i = 0; i < dcb_max_tc; i++) {
 651                 tc = &dcb_config->tc_config[i];
 652                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 653                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 654                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 655                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 656                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 657                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 658                 tc->pfc = ixgbe_dcb_pfc_disabled;
 659         }
 660
 661         /* Initialize default user to priority mapping, UPx->TC0 */
 662         tc = &dcb_config->tc_config[0];
 663         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 664         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 665         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 666                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 667                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 668         }
 669         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 670         dcb_config->pfc_mode_enable = false;
 671         dcb_config->vt_mode = true;
 672         dcb_config->round_robin_enable = false;
 673         /* support all DCB capabilities in 82599 */
 674         dcb_config->support.capabilities = 0xFF;
 675
 676         /*we only support 4 Tcs for X540, X550 */
 677         if (hw->mac.type == ixgbe_mac_X540 ||
 678                 hw->mac.type == ixgbe_mac_X550 ||
 679                 hw->mac.type == ixgbe_mac_X550EM_x) {
 680                 dcb_config->num_tcs.pg_tcs = 4;
 681                 dcb_config->num_tcs.pfc_tcs = 4;
 682         }
 683 }
 684
 685 /*
 686  * Ensure that all locks are released before first NVM or PHY access
 687  */
 688 static void
 689 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 690 {
 691         uint16_t mask;
 692
 693         /*
 694          * Phy lock should not fail in this early stage. If this is the case,
 695          * it is due to an improper exit of the application.
 696          * So force the release of the faulty lock. Release of common lock
 697          * is done automatically by swfw_sync function.
 698          */
 699         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 700         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 701                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 702         }
 703         ixgbe_release_swfw_semaphore(hw, mask);
 704
 705         /*
 706          * These ones are more tricky since they are common to all ports; but
 707          * swfw_sync retries last long enough (1s) to be almost sure that if
 708          * lock can not be taken it is due to an improper lock of the
 709          * semaphore.
 710          */
 711         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 712         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 713                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 714         }
 715         ixgbe_release_swfw_semaphore(hw, mask);
 716 }
 717
 718 /*
 719  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 720  * It returns 0 on success.
 721  */
 722 static int
 723 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 724                      struct rte_eth_dev *eth_dev)
 725 {
 726         struct rte_pci_device *pci_dev;
 727         struct ixgbe_hw *hw =
 728                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 729         struct ixgbe_vfta * shadow_vfta =
 730                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 731         struct ixgbe_hwstrip *hwstrip =
 732                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 733         struct ixgbe_dcb_config *dcb_config =
 734                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 735         uint32_t ctrl_ext;
 736         uint16_t csum;
 737         int diag, i;
 738
 739         PMD_INIT_FUNC_TRACE();
 740
 741         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 742         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 743         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 744
 745         /*
 746          * For secondary processes, we don't initialise any further as primary
 747          * has already done this work. Only check we don't need a different
 748          * RX and TX function.
 749          */
 750         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 751                 struct igb_tx_queue *txq;
 752                 /* TX queue function in primary, set by last queue initialized */
 753                 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 754                 set_tx_function(eth_dev, txq);
 755
 756                 if (eth_dev->data->scattered_rx)
 757                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 758                 return 0;
 759         }
 760         pci_dev = eth_dev->pci_dev;
 761
 762         /* Vendor and Device ID need to be set before init of shared code */
 763         hw->device_id = pci_dev->id.device_id;
 764         hw->vendor_id = pci_dev->id.vendor_id;
 765         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 766         hw->allow_unsupported_sfp = 1;
 767
 768         /* Initialize the shared code (base driver) */
 769 #ifdef RTE_NIC_BYPASS
 770         diag = ixgbe_bypass_init_shared_code(hw);
 771 #else
 772         diag = ixgbe_init_shared_code(hw);
 773 #endif /* RTE_NIC_BYPASS */
 774
 775         if (diag != IXGBE_SUCCESS) {
 776                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 777                 return -EIO;
 778         }
 779
 780         /* pick up the PCI bus settings for reporting later */
 781         ixgbe_get_bus_info(hw);
 782
 783         /* Unlock any pending hardware semaphore */
 784         ixgbe_swfw_lock_reset(hw);
 785
 786         /* Initialize DCB configuration*/
 787         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 788         ixgbe_dcb_init(hw,dcb_config);
 789         /* Get Hardware Flow Control setting */
 790         hw->fc.requested_mode = ixgbe_fc_full;
 791         hw->fc.current_mode = ixgbe_fc_full;
 792         hw->fc.pause_time = IXGBE_FC_PAUSE;
 793         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 794                 hw->fc.low_water[i] = IXGBE_FC_LO;
 795                 hw->fc.high_water[i] = IXGBE_FC_HI;
 796         }
 797         hw->fc.send_xon = 1;
 798
 799         /* Make sure we have a good EEPROM before we read from it */
 800         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 801         if (diag != IXGBE_SUCCESS) {
 802                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 803                 return -EIO;
 804         }
 805
 806 #ifdef RTE_NIC_BYPASS
 807         diag = ixgbe_bypass_init_hw(hw);
 808 #else
 809         diag = ixgbe_init_hw(hw);
 810 #endif /* RTE_NIC_BYPASS */
 811
 812         /*
 813          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 814          * is called too soon after the kernel driver unbinding/binding occurs.
 815          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 816          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 817          * also called. See ixgbe_identify_phy_82599(). The reason for the
 818          * failure is not known, and only occuts when virtualisation features
 819          * are disabled in the bios. A delay of 100ms  was found to be enough by
 820          * trial-and-error, and is doubled to be safe.
 821          */
 822         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 823                 rte_delay_ms(200);
 824                 diag = ixgbe_init_hw(hw);
 825         }
 826
 827         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 828                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 829                     "LOM.  Please be aware there may be issues associated "
 830                     "with your hardware.");
 831                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 832                     "please contact your Intel or hardware representative "
 833                     "who provided you with this hardware.");
 834         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 835                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 836         if (diag) {
 837                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 838                 return -EIO;
 839         }
 840
 841         /* disable interrupt */
 842         ixgbe_disable_intr(hw);
 843
 844         /* reset mappings for queue statistics hw counters*/
 845         ixgbe_reset_qstat_mappings(hw);
 846
 847         /* Allocate memory for storing MAC addresses */
 848         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 849                         hw->mac.num_rar_entries, 0);
 850         if (eth_dev->data->mac_addrs == NULL) {
 851                 PMD_INIT_LOG(ERR,
 852                         "Failed to allocate %u bytes needed to store "
 853                         "MAC addresses",
 854                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 855                 return -ENOMEM;
 856         }
 857         /* Copy the permanent MAC address */
 858         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 859                         &eth_dev->data->mac_addrs[0]);
 860
 861         /* Allocate memory for storing hash filter MAC addresses */
 862         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 863                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 864         if (eth_dev->data->hash_mac_addrs == NULL) {
 865                 PMD_INIT_LOG(ERR,
 866                         "Failed to allocate %d bytes needed to store MAC addresses",
 867                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 868                 return -ENOMEM;
 869         }
 870
 871         /* initialize the vfta */
 872         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 873
 874         /* initialize the hw strip bitmap*/
 875         memset(hwstrip, 0, sizeof(*hwstrip));
 876
 877         /* initialize PF if max_vfs not zero */
 878         ixgbe_pf_host_init(eth_dev);
 879
 880         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 881         /* let hardware know driver is loaded */
 882         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 883         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 884         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 885         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 886         IXGBE_WRITE_FLUSH(hw);
 887
 888         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 889                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 890                              (int) hw->mac.type, (int) hw->phy.type,
 891                              (int) hw->phy.sfp_type);
 892         else
 893                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 894                              (int) hw->mac.type, (int) hw->phy.type);
 895
 896         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 897                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 898                         pci_dev->id.device_id);
 899
 900         rte_intr_callback_register(&(pci_dev->intr_handle),
 901                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 902
 903         /* enable uio intr after callback register */
 904         rte_intr_enable(&(pci_dev->intr_handle));
 905
 906         /* enable support intr */
 907         ixgbe_enable_intr(eth_dev);
 908
 909         return 0;
 910 }
 911
 912
 913 /*
 914  * Negotiate mailbox API version with the PF.
 915  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 916  * Then we try to negotiate starting with the most recent one.
 917  * If all negotiation attempts fail, then we will proceed with
 918  * the default one (ixgbe_mbox_api_10).
 919  */
 920 static void
 921 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 922 {
 923         int32_t i;
 924
 925         /* start with highest supported, proceed down */
 926         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 927                 ixgbe_mbox_api_11,
 928                 ixgbe_mbox_api_10,
 929         };
 930
 931         for (i = 0;
 932                         i != RTE_DIM(sup_ver) &&
 933                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 934                         i++)
 935                 ;
 936 }
 937
 938 static void
 939 generate_random_mac_addr(struct ether_addr *mac_addr)
 940 {
 941         uint64_t random;
 942
 943         /* Set Organizationally Unique Identifier (OUI) prefix. */
 944         mac_addr->addr_bytes[0] = 0x00;
 945         mac_addr->addr_bytes[1] = 0x09;
 946         mac_addr->addr_bytes[2] = 0xC0;
 947         /* Force indication of locally assigned MAC address. */
 948         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 949         /* Generate the last 3 bytes of the MAC address with a random number. */
 950         random = rte_rand();
 951         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 952 }
 953
 954 /*
 955  * Virtual Function device init
 956  */
 957 static int
 958 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 959                      struct rte_eth_dev *eth_dev)
 960 {
 961         int diag;
 962         uint32_t tc, tcs;
 963         struct rte_pci_device *pci_dev;
 964         struct ixgbe_hw *hw =
 965                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 966         struct ixgbe_vfta * shadow_vfta =
 967                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 968         struct ixgbe_hwstrip *hwstrip =
 969                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 970         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 971
 972         PMD_INIT_FUNC_TRACE();
 973
 974         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 975         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 976         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 977
 978         /* for secondary processes, we don't initialise any further as primary
 979          * has already done this work. Only check we don't need a different
 980          * RX function */
 981         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 982                 if (eth_dev->data->scattered_rx)
 983                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 984                 return 0;
 985         }
 986
 987         pci_dev = eth_dev->pci_dev;
 988
 989         hw->device_id = pci_dev->id.device_id;
 990         hw->vendor_id = pci_dev->id.vendor_id;
 991         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 992
 993         /* initialize the vfta */
 994         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 995
 996         /* initialize the hw strip bitmap*/
 997         memset(hwstrip, 0, sizeof(*hwstrip));
 998
 999         /* Initialize the shared code (base driver) */
1000         diag = ixgbe_init_shared_code(hw);
1001         if (diag != IXGBE_SUCCESS) {
1002                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1003                 return -EIO;
1004         }
1005
1006         /* init_mailbox_params */
1007         hw->mbx.ops.init_params(hw);
1008
1009         /* Disable the interrupts for VF */
1010         ixgbevf_intr_disable(hw);
1011
1012         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1013         diag = hw->mac.ops.reset_hw(hw);
1014
1015         /*
1016          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1017          * the underlying PF driver has not assigned a MAC address to the VF.
1018          * In this case, assign a random MAC address.
1019          */
1020         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1021                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1022                 return (diag);
1023         }
1024
1025         /* negotiate mailbox API version to use with the PF. */
1026         ixgbevf_negotiate_api(hw);
1027
1028         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1029         ixgbevf_get_queues(hw, &tcs, &tc);
1030
1031         /* Allocate memory for storing MAC addresses */
1032         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1033                         hw->mac.num_rar_entries, 0);
1034         if (eth_dev->data->mac_addrs == NULL) {
1035                 PMD_INIT_LOG(ERR,
1036                         "Failed to allocate %u bytes needed to store "
1037                         "MAC addresses",
1038                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1039                 return -ENOMEM;
1040         }
1041
1042         /* Generate a random MAC address, if none was assigned by PF. */
1043         if (is_zero_ether_addr(perm_addr)) {
1044                 generate_random_mac_addr(perm_addr);
1045                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1046                 if (diag) {
1047                         rte_free(eth_dev->data->mac_addrs);
1048                         eth_dev->data->mac_addrs = NULL;
1049                         return diag;
1050                 }
1051                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1052                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1053                              "%02x:%02x:%02x:%02x:%02x:%02x",
1054                              perm_addr->addr_bytes[0],
1055                              perm_addr->addr_bytes[1],
1056                              perm_addr->addr_bytes[2],
1057                              perm_addr->addr_bytes[3],
1058                              perm_addr->addr_bytes[4],
1059                              perm_addr->addr_bytes[5]);
1060         }
1061
1062         /* Copy the permanent MAC address */
1063         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1064
1065         /* reset the hardware with the new settings */
1066         diag = hw->mac.ops.start_hw(hw);
1067         switch (diag) {
1068                 case  0:
1069                         break;
1070
1071                 default:
1072                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1073                         return (-EIO);
1074         }
1075
1076         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1077                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1078                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1079
1080         return 0;
1081 }
1082
1083 static struct eth_driver rte_ixgbe_pmd = {
1084         {
1085                 .name = "rte_ixgbe_pmd",
1086                 .id_table = pci_id_ixgbe_map,
1087                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1088         },
1089         .eth_dev_init = eth_ixgbe_dev_init,
1090         .dev_private_size = sizeof(struct ixgbe_adapter),
1091 };
1092
1093 /*
1094  * virtual function driver struct
1095  */
1096 static struct eth_driver rte_ixgbevf_pmd = {
1097         {
1098                 .name = "rte_ixgbevf_pmd",
1099                 .id_table = pci_id_ixgbevf_map,
1100                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1101         },
1102         .eth_dev_init = eth_ixgbevf_dev_init,
1103         .dev_private_size = sizeof(struct ixgbe_adapter),
1104 };
1105
1106 /*
1107  * Driver initialization routine.
1108  * Invoked once at EAL init time.
1109  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1110  */
1111 static int
1112 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1113 {
1114         PMD_INIT_FUNC_TRACE();
1115
1116         rte_eth_driver_register(&rte_ixgbe_pmd);
1117         return 0;
1118 }
1119
1120 /*
1121  * VF Driver initialization routine.
1122  * Invoked one at EAL init time.
1123  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1124  */
1125 static int
1126 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1127 {
1128         PMD_INIT_FUNC_TRACE();
1129
1130         rte_eth_driver_register(&rte_ixgbevf_pmd);
1131         return (0);
1132 }
1133
1134 static int
1135 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1136 {
1137         struct ixgbe_hw *hw =
1138                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1139         struct ixgbe_vfta * shadow_vfta =
1140                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1141         uint32_t vfta;
1142         uint32_t vid_idx;
1143         uint32_t vid_bit;
1144
1145         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1146         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1147         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1148         if (on)
1149                 vfta |= vid_bit;
1150         else
1151                 vfta &= ~vid_bit;
1152         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1153
1154         /* update local VFTA copy */
1155         shadow_vfta->vfta[vid_idx] = vfta;
1156
1157         return 0;
1158 }
1159
1160 static void
1161 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1162 {
1163         if (on)
1164                 ixgbe_vlan_hw_strip_enable(dev, queue);
1165         else
1166                 ixgbe_vlan_hw_strip_disable(dev, queue);
1167 }
1168
1169 static void
1170 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1171 {
1172         struct ixgbe_hw *hw =
1173                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1174
1175         /* Only the high 16-bits is valid */
1176         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1177 }
1178
1179 void
1180 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1181 {
1182         struct ixgbe_hw *hw =
1183                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1184         uint32_t vlnctrl;
1185
1186         PMD_INIT_FUNC_TRACE();
1187
1188         /* Filter Table Disable */
1189         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1190         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1191
1192         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1193 }
1194
1195 void
1196 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1197 {
1198         struct ixgbe_hw *hw =
1199                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200         struct ixgbe_vfta * shadow_vfta =
1201                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1202         uint32_t vlnctrl;
1203         uint16_t i;
1204
1205         PMD_INIT_FUNC_TRACE();
1206
1207         /* Filter Table Enable */
1208         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1209         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1210         vlnctrl |= IXGBE_VLNCTRL_VFE;
1211
1212         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1213
1214         /* write whatever is in local vfta copy */
1215         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1216                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1217 }
1218
1219 static void
1220 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1221 {
1222         struct ixgbe_hwstrip *hwstrip =
1223                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1224
1225         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1226                 return;
1227
1228         if (on)
1229                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1230         else
1231                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1232 }
1233
1234 static void
1235 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1236 {
1237         struct ixgbe_hw *hw =
1238                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1239         uint32_t ctrl;
1240
1241         PMD_INIT_FUNC_TRACE();
1242
1243         if (hw->mac.type == ixgbe_mac_82598EB) {
1244                 /* No queue level support */
1245                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1246                 return;
1247         }
1248         else {
1249                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1250                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1251                 ctrl &= ~IXGBE_RXDCTL_VME;
1252                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1253         }
1254         /* record those setting for HW strip per queue */
1255         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1256 }
1257
1258 static void
1259 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1260 {
1261         struct ixgbe_hw *hw =
1262                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1263         uint32_t ctrl;
1264
1265         PMD_INIT_FUNC_TRACE();
1266
1267         if (hw->mac.type == ixgbe_mac_82598EB) {
1268                 /* No queue level supported */
1269                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1270                 return;
1271         }
1272         else {
1273                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1274                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1275                 ctrl |= IXGBE_RXDCTL_VME;
1276                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1277         }
1278         /* record those setting for HW strip per queue */
1279         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1280 }
1281
1282 void
1283 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1284 {
1285         struct ixgbe_hw *hw =
1286                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1287         uint32_t ctrl;
1288         uint16_t i;
1289
1290         PMD_INIT_FUNC_TRACE();
1291
1292         if (hw->mac.type == ixgbe_mac_82598EB) {
1293                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1294                 ctrl &= ~IXGBE_VLNCTRL_VME;
1295                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1296         }
1297         else {
1298                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1299                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1300                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1301                         ctrl &= ~IXGBE_RXDCTL_VME;
1302                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1303
1304                         /* record those setting for HW strip per queue */
1305                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1306                 }
1307         }
1308 }
1309
1310 void
1311 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1312 {
1313         struct ixgbe_hw *hw =
1314                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315         uint32_t ctrl;
1316         uint16_t i;
1317
1318         PMD_INIT_FUNC_TRACE();
1319
1320         if (hw->mac.type == ixgbe_mac_82598EB) {
1321                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1322                 ctrl |= IXGBE_VLNCTRL_VME;
1323                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1324         }
1325         else {
1326                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1327                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1328                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1329                         ctrl |= IXGBE_RXDCTL_VME;
1330                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1331
1332                         /* record those setting for HW strip per queue */
1333                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1334                 }
1335         }
1336 }
1337
1338 static void
1339 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1340 {
1341         struct ixgbe_hw *hw =
1342                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343         uint32_t ctrl;
1344
1345         PMD_INIT_FUNC_TRACE();
1346
1347         /* DMATXCTRL: Geric Double VLAN Disable */
1348         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1349         ctrl &= ~IXGBE_DMATXCTL_GDV;
1350         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1351
1352         /* CTRL_EXT: Global Double VLAN Disable */
1353         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1354         ctrl &= ~IXGBE_EXTENDED_VLAN;
1355         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1356
1357 }
1358
1359 static void
1360 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1361 {
1362         struct ixgbe_hw *hw =
1363                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364         uint32_t ctrl;
1365
1366         PMD_INIT_FUNC_TRACE();
1367
1368         /* DMATXCTRL: Geric Double VLAN Enable */
1369         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1370         ctrl |= IXGBE_DMATXCTL_GDV;
1371         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1372
1373         /* CTRL_EXT: Global Double VLAN Enable */
1374         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1375         ctrl |= IXGBE_EXTENDED_VLAN;
1376         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1377
1378         /*
1379          * VET EXT field in the EXVET register = 0x8100 by default
1380          * So no need to change. Same to VT field of DMATXCTL register
1381          */
1382 }
1383
1384 static void
1385 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1386 {
1387         if(mask & ETH_VLAN_STRIP_MASK){
1388                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1389                         ixgbe_vlan_hw_strip_enable_all(dev);
1390                 else
1391                         ixgbe_vlan_hw_strip_disable_all(dev);
1392         }
1393
1394         if(mask & ETH_VLAN_FILTER_MASK){
1395                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1396                         ixgbe_vlan_hw_filter_enable(dev);
1397                 else
1398                         ixgbe_vlan_hw_filter_disable(dev);
1399         }
1400
1401         if(mask & ETH_VLAN_EXTEND_MASK){
1402                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1403                         ixgbe_vlan_hw_extend_enable(dev);
1404                 else
1405                         ixgbe_vlan_hw_extend_disable(dev);
1406         }
1407 }
1408
1409 static void
1410 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1411 {
1412         struct ixgbe_hw *hw =
1413                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1415         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1416         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1417         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1418 }
1419
1420 static int
1421 ixgbe_dev_configure(struct rte_eth_dev *dev)
1422 {
1423         struct ixgbe_interrupt *intr =
1424                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1425
1426         PMD_INIT_FUNC_TRACE();
1427
1428         /* set flag to update link status after init */
1429         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1430
1431         return 0;
1432 }
1433
1434 /*
1435  * Configure device link speed and setup link.
1436  * It returns 0 on success.
1437  */
1438 static int
1439 ixgbe_dev_start(struct rte_eth_dev *dev)
1440 {
1441         struct ixgbe_hw *hw =
1442                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1443         struct ixgbe_vf_info *vfinfo =
1444                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1445         int err, link_up = 0, negotiate = 0;
1446         uint32_t speed = 0;
1447         int mask = 0;
1448         int status;
1449         uint16_t vf, idx;
1450
1451         PMD_INIT_FUNC_TRACE();
1452
1453         /* IXGBE devices don't support half duplex */
1454         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1455                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1456                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1457                              dev->data->dev_conf.link_duplex,
1458                              dev->data->port_id);
1459                 return -EINVAL;
1460         }
1461
1462         /* stop adapter */
1463         hw->adapter_stopped = FALSE;
1464         ixgbe_stop_adapter(hw);
1465
1466         /* reinitialize adapter
1467          * this calls reset and start */
1468         status = ixgbe_pf_reset_hw(hw);
1469         if (status != 0)
1470                 return -1;
1471         hw->mac.ops.start_hw(hw);
1472
1473         /* configure PF module if SRIOV enabled */
1474         ixgbe_pf_host_configure(dev);
1475
1476         /* initialize transmission unit */
1477         ixgbe_dev_tx_init(dev);
1478
1479         /* This can fail when allocating mbufs for descriptor rings */
1480         err = ixgbe_dev_rx_init(dev);
1481         if (err) {
1482                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1483                 goto error;
1484         }
1485
1486         ixgbe_dev_rxtx_start(dev);
1487
1488         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1489                 err = hw->mac.ops.setup_sfp(hw);
1490                 if (err)
1491                         goto error;
1492         }
1493
1494         /* Turn on the laser */
1495         ixgbe_enable_tx_laser(hw);
1496
1497         /* Skip link setup if loopback mode is enabled for 82599. */
1498         if (hw->mac.type == ixgbe_mac_82599EB &&
1499                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1500                 goto skip_link_setup;
1501
1502         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1503         if (err)
1504                 goto error;
1505         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1506         if (err)
1507                 goto error;
1508
1509         switch(dev->data->dev_conf.link_speed) {
1510         case ETH_LINK_SPEED_AUTONEG:
1511                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1512                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1513                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1514                 break;
1515         case ETH_LINK_SPEED_100:
1516                 /*
1517                  * Invalid for 82598 but error will be detected by
1518                  * ixgbe_setup_link()
1519                  */
1520                 speed = IXGBE_LINK_SPEED_100_FULL;
1521                 break;
1522         case ETH_LINK_SPEED_1000:
1523                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1524                 break;
1525         case ETH_LINK_SPEED_10000:
1526                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1527                 break;
1528         default:
1529                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1530                              dev->data->dev_conf.link_speed,
1531                              dev->data->port_id);
1532                 goto error;
1533         }
1534
1535         err = ixgbe_setup_link(hw, speed, link_up);
1536         if (err)
1537                 goto error;
1538
1539 skip_link_setup:
1540
1541         /* check if lsc interrupt is enabled */
1542         if (dev->data->dev_conf.intr_conf.lsc != 0)
1543                 ixgbe_dev_lsc_interrupt_setup(dev);
1544
1545         /* resume enabled intr since hw reset */
1546         ixgbe_enable_intr(dev);
1547
1548         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1549                 ETH_VLAN_EXTEND_MASK;
1550         ixgbe_vlan_offload_set(dev, mask);
1551
1552         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1553                 /* Enable vlan filtering for VMDq */
1554                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1555         }
1556
1557         /* Configure DCB hw */
1558         ixgbe_configure_dcb(dev);
1559
1560         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1561                 err = ixgbe_fdir_configure(dev);
1562                 if (err)
1563                         goto error;
1564         }
1565
1566         /* Restore vf rate limit */
1567         if (vfinfo != NULL) {
1568                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1569                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1570                                 if (vfinfo[vf].tx_rate[idx] != 0)
1571                                         ixgbe_set_vf_rate_limit(dev, vf,
1572                                                 vfinfo[vf].tx_rate[idx],
1573                                                 1 << idx);
1574         }
1575
1576         ixgbe_restore_statistics_mapping(dev);
1577
1578         return (0);
1579
1580 error:
1581         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1582         ixgbe_dev_clear_queues(dev);
1583         return -EIO;
1584 }
1585
1586 /*
1587  * Stop device: disable rx and tx functions to allow for reconfiguring.
1588  */
1589 static void
1590 ixgbe_dev_stop(struct rte_eth_dev *dev)
1591 {
1592         struct rte_eth_link link;
1593         struct ixgbe_hw *hw =
1594                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         struct ixgbe_vf_info *vfinfo =
1596                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1597         int vf;
1598
1599         PMD_INIT_FUNC_TRACE();
1600
1601         /* disable interrupts */
1602         ixgbe_disable_intr(hw);
1603
1604         /* reset the NIC */
1605         ixgbe_pf_reset_hw(hw);
1606         hw->adapter_stopped = FALSE;
1607
1608         /* stop adapter */
1609         ixgbe_stop_adapter(hw);
1610
1611         for (vf = 0; vfinfo != NULL &&
1612                      vf < dev->pci_dev->max_vfs; vf++)
1613                 vfinfo[vf].clear_to_send = false;
1614
1615         /* Turn off the laser */
1616         ixgbe_disable_tx_laser(hw);
1617
1618         ixgbe_dev_clear_queues(dev);
1619
1620         /* Clear stored conf */
1621         dev->data->scattered_rx = 0;
1622
1623         /* Clear recorded link status */
1624         memset(&link, 0, sizeof(link));
1625         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1626 }
1627
1628 /*
1629  * Set device link up: enable tx laser.
1630  */
1631 static int
1632 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1633 {
1634         struct ixgbe_hw *hw =
1635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636         if (hw->mac.type == ixgbe_mac_82599EB) {
1637 #ifdef RTE_NIC_BYPASS
1638                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1639                         /* Not suported in bypass mode */
1640                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1641                                      "by device id 0x%x", hw->device_id);
1642                         return -ENOTSUP;
1643                 }
1644 #endif
1645                 /* Turn on the laser */
1646                 ixgbe_enable_tx_laser(hw);
1647                 return 0;
1648         }
1649
1650         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1651                      hw->device_id);
1652         return -ENOTSUP;
1653 }
1654
1655 /*
1656  * Set device link down: disable tx laser.
1657  */
1658 static int
1659 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1660 {
1661         struct ixgbe_hw *hw =
1662                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663         if (hw->mac.type == ixgbe_mac_82599EB) {
1664 #ifdef RTE_NIC_BYPASS
1665                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1666                         /* Not suported in bypass mode */
1667                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1668                                      "by device id 0x%x", hw->device_id);
1669                         return -ENOTSUP;
1670                 }
1671 #endif
1672                 /* Turn off the laser */
1673                 ixgbe_disable_tx_laser(hw);
1674                 return 0;
1675         }
1676
1677         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1678                      hw->device_id);
1679         return -ENOTSUP;
1680 }
1681
1682 /*
1683  * Reest and stop device.
1684  */
1685 static void
1686 ixgbe_dev_close(struct rte_eth_dev *dev)
1687 {
1688         struct ixgbe_hw *hw =
1689                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1690
1691         PMD_INIT_FUNC_TRACE();
1692
1693         ixgbe_pf_reset_hw(hw);
1694
1695         ixgbe_dev_stop(dev);
1696         hw->adapter_stopped = 1;
1697
1698         ixgbe_disable_pcie_master(hw);
1699
1700         /* reprogram the RAR[0] in case user changed it. */
1701         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1702 }
1703
1704 /*
1705  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1706  */
1707 static void
1708 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1709 {
1710         struct ixgbe_hw *hw =
1711                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712         struct ixgbe_hw_stats *hw_stats =
1713                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1714         uint32_t bprc, lxon, lxoff, total;
1715         uint64_t total_missed_rx, total_qbrc, total_qprc;
1716         unsigned i;
1717
1718         total_missed_rx = 0;
1719         total_qbrc = 0;
1720         total_qprc = 0;
1721
1722         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1723         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1724         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1725         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1726
1727         for (i = 0; i < 8; i++) {
1728                 uint32_t mp;
1729                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1730                 /* global total per queue */
1731                 hw_stats->mpc[i] += mp;
1732                 /* Running comprehensive total for stats display */
1733                 total_missed_rx += hw_stats->mpc[i];
1734                 if (hw->mac.type == ixgbe_mac_82598EB)
1735                         hw_stats->rnbc[i] +=
1736                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1737                 hw_stats->pxontxc[i] +=
1738                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1739                 hw_stats->pxonrxc[i] +=
1740                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1741                 hw_stats->pxofftxc[i] +=
1742                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1743                 hw_stats->pxoffrxc[i] +=
1744                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1745                 hw_stats->pxon2offc[i] +=
1746                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1747         }
1748         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1749                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1750                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1751                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1752                 hw_stats->qbrc[i] +=
1753                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1754                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1755                 hw_stats->qbtc[i] +=
1756                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1757                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1758
1759                 total_qprc += hw_stats->qprc[i];
1760                 total_qbrc += hw_stats->qbrc[i];
1761         }
1762         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1763         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1764         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1765
1766         /* Note that gprc counts missed packets */
1767         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1768
1769         if (hw->mac.type != ixgbe_mac_82598EB) {
1770                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1771                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1772                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1773                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1774                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1775                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1776                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1777                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1778         } else {
1779                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1780                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1781                 /* 82598 only has a counter in the high register */
1782                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1783                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1784                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1785         }
1786
1787         /*
1788          * Workaround: mprc hardware is incorrectly counting
1789          * broadcasts, so for now we subtract those.
1790          */
1791         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1792         hw_stats->bprc += bprc;
1793         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1794         if (hw->mac.type == ixgbe_mac_82598EB)
1795                 hw_stats->mprc -= bprc;
1796
1797         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1798         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1799         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1800         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1801         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1802         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1803
1804         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1805         hw_stats->lxontxc += lxon;
1806         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1807         hw_stats->lxofftxc += lxoff;
1808         total = lxon + lxoff;
1809
1810         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1811         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1812         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1813         hw_stats->gptc -= total;
1814         hw_stats->mptc -= total;
1815         hw_stats->ptc64 -= total;
1816         hw_stats->gotc -= total * ETHER_MIN_LEN;
1817
1818         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1819         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1820         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1821         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1822         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1823         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1824         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1825         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1826         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1827         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1828         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1829         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1830         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1831         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1832         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1833         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1834         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1835         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1836         /* Only read FCOE on 82599 */
1837         if (hw->mac.type != ixgbe_mac_82598EB) {
1838                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1839                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1840                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1841                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1842                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1843         }
1844
1845         if (stats == NULL)
1846                 return;
1847
1848         /* Fill out the rte_eth_stats statistics structure */
1849         stats->ipackets = total_qprc;
1850         stats->ibytes = total_qbrc;
1851         stats->opackets = hw_stats->gptc;
1852         stats->obytes = hw_stats->gotc;
1853         stats->imcasts = hw_stats->mprc;
1854
1855         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1856                 stats->q_ipackets[i] = hw_stats->qprc[i];
1857                 stats->q_opackets[i] = hw_stats->qptc[i];
1858                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1859                 stats->q_obytes[i] = hw_stats->qbtc[i];
1860                 stats->q_errors[i] = hw_stats->qprdc[i];
1861         }
1862
1863         /* Rx Errors */
1864         stats->ibadcrc  = hw_stats->crcerrs;
1865         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1866         stats->imissed  = total_missed_rx;
1867         stats->ierrors  = stats->ibadcrc +
1868                           stats->ibadlen +
1869                           stats->imissed +
1870                           hw_stats->illerrc + hw_stats->errbc;
1871
1872         /* Tx Errors */
1873         stats->oerrors  = 0;
1874
1875         /* XON/XOFF pause frames */
1876         stats->tx_pause_xon  = hw_stats->lxontxc;
1877         stats->rx_pause_xon  = hw_stats->lxonrxc;
1878         stats->tx_pause_xoff = hw_stats->lxofftxc;
1879         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1880
1881         /* Flow Director Stats registers */
1882         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1883         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1884         stats->fdirmatch = hw_stats->fdirmatch;
1885         stats->fdirmiss = hw_stats->fdirmiss;
1886 }
1887
1888 static void
1889 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1890 {
1891         struct ixgbe_hw_stats *stats =
1892                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1893
1894         /* HW registers are cleared on read */
1895         ixgbe_dev_stats_get(dev, NULL);
1896
1897         /* Reset software totals */
1898         memset(stats, 0, sizeof(*stats));
1899 }
1900
1901 static void
1902 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1903 {
1904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1906                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1907
1908         /* Good Rx packet, include VF loopback */
1909         UPDATE_VF_STAT(IXGBE_VFGPRC,
1910             hw_stats->last_vfgprc, hw_stats->vfgprc);
1911
1912         /* Good Rx octets, include VF loopback */
1913         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1914             hw_stats->last_vfgorc, hw_stats->vfgorc);
1915
1916         /* Good Tx packet, include VF loopback */
1917         UPDATE_VF_STAT(IXGBE_VFGPTC,
1918             hw_stats->last_vfgptc, hw_stats->vfgptc);
1919
1920         /* Good Tx octets, include VF loopback */
1921         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1922             hw_stats->last_vfgotc, hw_stats->vfgotc);
1923
1924         /* Rx Multicst Packet */
1925         UPDATE_VF_STAT(IXGBE_VFMPRC,
1926             hw_stats->last_vfmprc, hw_stats->vfmprc);
1927
1928         if (stats == NULL)
1929                 return;
1930
1931         memset(stats, 0, sizeof(*stats));
1932         stats->ipackets = hw_stats->vfgprc;
1933         stats->ibytes = hw_stats->vfgorc;
1934         stats->opackets = hw_stats->vfgptc;
1935         stats->obytes = hw_stats->vfgotc;
1936         stats->imcasts = hw_stats->vfmprc;
1937 }
1938
1939 static void
1940 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1941 {
1942         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1943                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1944
1945         /* Sync HW register to the last stats */
1946         ixgbevf_dev_stats_get(dev, NULL);
1947
1948         /* reset HW current stats*/
1949         hw_stats->vfgprc = 0;
1950         hw_stats->vfgorc = 0;
1951         hw_stats->vfgptc = 0;
1952         hw_stats->vfgotc = 0;
1953         hw_stats->vfmprc = 0;
1954
1955 }
1956
1957 static void
1958 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1959 {
1960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961
1962         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1963         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1964         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1965         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1966         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1967         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1968         dev_info->max_vfs = dev->pci_dev->max_vfs;
1969         if (hw->mac.type == ixgbe_mac_82598EB)
1970                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1971         else
1972                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1973         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1974         dev_info->rx_offload_capa =
1975                 DEV_RX_OFFLOAD_VLAN_STRIP |
1976                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1977                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1978                 DEV_RX_OFFLOAD_TCP_CKSUM;
1979         dev_info->tx_offload_capa =
1980                 DEV_TX_OFFLOAD_VLAN_INSERT |
1981                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1982                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1983                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1984                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1985                 DEV_TX_OFFLOAD_TCP_TSO;
1986
1987         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1988                 .rx_thresh = {
1989                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
1990                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
1991                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
1992                 },
1993                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
1994                 .rx_drop_en = 0,
1995         };
1996
1997         dev_info->default_txconf = (struct rte_eth_txconf) {
1998                 .tx_thresh = {
1999                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2000                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2001                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2002                 },
2003                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2004                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2005                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2006                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2007         };
2008         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2009 }
2010
2011 static void
2012 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2013                      struct rte_eth_dev_info *dev_info)
2014 {
2015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2016
2017         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2018         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2019         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2020         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2021         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2022         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2023         dev_info->max_vfs = dev->pci_dev->max_vfs;
2024         if (hw->mac.type == ixgbe_mac_82598EB)
2025                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2026         else
2027                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2028         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2029                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2030                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2031                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2032         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2033                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2034                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2035                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2036                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2037
2038         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2039                 .rx_thresh = {
2040                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2041                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2042                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2043                 },
2044                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2045                 .rx_drop_en = 0,
2046         };
2047
2048         dev_info->default_txconf = (struct rte_eth_txconf) {
2049                 .tx_thresh = {
2050                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2051                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2052                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2053                 },
2054                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2055                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2056                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2057                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2058         };
2059 }
2060
2061 /* return 0 means link status changed, -1 means not changed */
2062 static int
2063 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2064 {
2065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2066         struct rte_eth_link link, old;
2067         ixgbe_link_speed link_speed;
2068         int link_up;
2069         int diag;
2070
2071         link.link_status = 0;
2072         link.link_speed = 0;
2073         link.link_duplex = 0;
2074         memset(&old, 0, sizeof(old));
2075         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2076
2077         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2078         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2079                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2080         else
2081                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2082         if (diag != 0) {
2083                 link.link_speed = ETH_LINK_SPEED_100;
2084                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2085                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2086                 if (link.link_status == old.link_status)
2087                         return -1;
2088                 return 0;
2089         }
2090
2091         if (link_up == 0) {
2092                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2093                 if (link.link_status == old.link_status)
2094                         return -1;
2095                 return 0;
2096         }
2097         link.link_status = 1;
2098         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2099
2100         switch (link_speed) {
2101         default:
2102         case IXGBE_LINK_SPEED_UNKNOWN:
2103                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2104                 link.link_speed = ETH_LINK_SPEED_100;
2105                 break;
2106
2107         case IXGBE_LINK_SPEED_100_FULL:
2108                 link.link_speed = ETH_LINK_SPEED_100;
2109                 break;
2110
2111         case IXGBE_LINK_SPEED_1GB_FULL:
2112                 link.link_speed = ETH_LINK_SPEED_1000;
2113                 break;
2114
2115         case IXGBE_LINK_SPEED_10GB_FULL:
2116                 link.link_speed = ETH_LINK_SPEED_10000;
2117                 break;
2118         }
2119         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2120
2121         if (link.link_status == old.link_status)
2122                 return -1;
2123
2124         return 0;
2125 }
2126
2127 static void
2128 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2129 {
2130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2131         uint32_t fctrl;
2132
2133         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2134         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2135         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2136 }
2137
2138 static void
2139 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2140 {
2141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142         uint32_t fctrl;
2143
2144         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2145         fctrl &= (~IXGBE_FCTRL_UPE);
2146         if (dev->data->all_multicast == 1)
2147                 fctrl |= IXGBE_FCTRL_MPE;
2148         else
2149                 fctrl &= (~IXGBE_FCTRL_MPE);
2150         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2151 }
2152
2153 static void
2154 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2155 {
2156         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2157         uint32_t fctrl;
2158
2159         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2160         fctrl |= IXGBE_FCTRL_MPE;
2161         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2162 }
2163
2164 static void
2165 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2166 {
2167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168         uint32_t fctrl;
2169
2170         if (dev->data->promiscuous == 1)
2171                 return; /* must remain in all_multicast mode */
2172
2173         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2174         fctrl &= (~IXGBE_FCTRL_MPE);
2175         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2176 }
2177
2178 /**
2179  * It clears the interrupt causes and enables the interrupt.
2180  * It will be called once only during nic initialized.
2181  *
2182  * @param dev
2183  *  Pointer to struct rte_eth_dev.
2184  *
2185  * @return
2186  *  - On success, zero.
2187  *  - On failure, a negative value.
2188  */
2189 static int
2190 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2191 {
2192         struct ixgbe_interrupt *intr =
2193                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2194
2195         ixgbe_dev_link_status_print(dev);
2196         intr->mask |= IXGBE_EICR_LSC;
2197
2198         return 0;
2199 }
2200
2201 /*
2202  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2203  *
2204  * @param dev
2205  *  Pointer to struct rte_eth_dev.
2206  *
2207  * @return
2208  *  - On success, zero.
2209  *  - On failure, a negative value.
2210  */
2211 static int
2212 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2213 {
2214         uint32_t eicr;
2215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216         struct ixgbe_interrupt *intr =
2217                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2218
2219         /* clear all cause mask */
2220         ixgbe_disable_intr(hw);
2221
2222         /* read-on-clear nic registers here */
2223         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2224         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2225
2226         intr->flags = 0;
2227         if (eicr & IXGBE_EICR_LSC) {
2228                 /* set flag for async link update */
2229                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2230         }
2231
2232         if (eicr & IXGBE_EICR_MAILBOX)
2233                 intr->flags |= IXGBE_FLAG_MAILBOX;
2234
2235         return 0;
2236 }
2237
2238 /**
2239  * It gets and then prints the link status.
2240  *
2241  * @param dev
2242  *  Pointer to struct rte_eth_dev.
2243  *
2244  * @return
2245  *  - On success, zero.
2246  *  - On failure, a negative value.
2247  */
2248 static void
2249 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2250 {
2251         struct rte_eth_link link;
2252
2253         memset(&link, 0, sizeof(link));
2254         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2255         if (link.link_status) {
2256                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2257                                         (int)(dev->data->port_id),
2258                                         (unsigned)link.link_speed,
2259                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2260                                         "full-duplex" : "half-duplex");
2261         } else {
2262                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2263                                 (int)(dev->data->port_id));
2264         }
2265         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2266                                 dev->pci_dev->addr.domain,
2267                                 dev->pci_dev->addr.bus,
2268                                 dev->pci_dev->addr.devid,
2269                                 dev->pci_dev->addr.function);
2270 }
2271
2272 /*
2273  * It executes link_update after knowing an interrupt occurred.
2274  *
2275  * @param dev
2276  *  Pointer to struct rte_eth_dev.
2277  *
2278  * @return
2279  *  - On success, zero.
2280  *  - On failure, a negative value.
2281  */
2282 static int
2283 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2284 {
2285         struct ixgbe_interrupt *intr =
2286                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2287         int64_t timeout;
2288         struct rte_eth_link link;
2289         int intr_enable_delay = false;
2290
2291         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2292
2293         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2294                 ixgbe_pf_mbx_process(dev);
2295                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2296         }
2297
2298         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2299                 /* get the link status before link update, for predicting later */
2300                 memset(&link, 0, sizeof(link));
2301                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2302
2303                 ixgbe_dev_link_update(dev, 0);
2304
2305                 /* likely to up */
2306                 if (!link.link_status)
2307                         /* handle it 1 sec later, wait it being stable */
2308                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2309                 /* likely to down */
2310                 else
2311                         /* handle it 4 sec later, wait it being stable */
2312                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2313
2314                 ixgbe_dev_link_status_print(dev);
2315
2316                 intr_enable_delay = true;
2317         }
2318
2319         if (intr_enable_delay) {
2320                 if (rte_eal_alarm_set(timeout * 1000,
2321                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2322                         PMD_DRV_LOG(ERR, "Error setting alarm");
2323         } else {
2324                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2325                 ixgbe_enable_intr(dev);
2326                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2327         }
2328
2329
2330         return 0;
2331 }
2332
2333 /**
2334  * Interrupt handler which shall be registered for alarm callback for delayed
2335  * handling specific interrupt to wait for the stable nic state. As the
2336  * NIC interrupt state is not stable for ixgbe after link is just down,
2337  * it needs to wait 4 seconds to get the stable status.
2338  *
2339  * @param handle
2340  *  Pointer to interrupt handle.
2341  * @param param
2342  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2343  *
2344  * @return
2345  *  void
2346  */
2347 static void
2348 ixgbe_dev_interrupt_delayed_handler(void *param)
2349 {
2350         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2351         struct ixgbe_interrupt *intr =
2352                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2353         struct ixgbe_hw *hw =
2354                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2355         uint32_t eicr;
2356
2357         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2358         if (eicr & IXGBE_EICR_MAILBOX)
2359                 ixgbe_pf_mbx_process(dev);
2360
2361         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2362                 ixgbe_dev_link_update(dev, 0);
2363                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2364                 ixgbe_dev_link_status_print(dev);
2365                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2366         }
2367
2368         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2369         ixgbe_enable_intr(dev);
2370         rte_intr_enable(&(dev->pci_dev->intr_handle));
2371 }
2372
2373 /**
2374  * Interrupt handler triggered by NIC  for handling
2375  * specific interrupt.
2376  *
2377  * @param handle
2378  *  Pointer to interrupt handle.
2379  * @param param
2380  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2381  *
2382  * @return
2383  *  void
2384  */
2385 static void
2386 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2387                                                         void *param)
2388 {
2389         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2390         ixgbe_dev_interrupt_get_status(dev);
2391         ixgbe_dev_interrupt_action(dev);
2392 }
2393
2394 static int
2395 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2396 {
2397         struct ixgbe_hw *hw;
2398
2399         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2401 }
2402
2403 static int
2404 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2405 {
2406         struct ixgbe_hw *hw;
2407
2408         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2410 }
2411
2412 static int
2413 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2414 {
2415         struct ixgbe_hw *hw;
2416         uint32_t mflcn_reg;
2417         uint32_t fccfg_reg;
2418         int rx_pause;
2419         int tx_pause;
2420
2421         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2422
2423         fc_conf->pause_time = hw->fc.pause_time;
2424         fc_conf->high_water = hw->fc.high_water[0];
2425         fc_conf->low_water = hw->fc.low_water[0];
2426         fc_conf->send_xon = hw->fc.send_xon;
2427         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2428
2429         /*
2430          * Return rx_pause status according to actual setting of
2431          * MFLCN register.
2432          */
2433         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2434         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2435                 rx_pause = 1;
2436         else
2437                 rx_pause = 0;
2438
2439         /*
2440          * Return tx_pause status according to actual setting of
2441          * FCCFG register.
2442          */
2443         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2444         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2445                 tx_pause = 1;
2446         else
2447                 tx_pause = 0;
2448
2449         if (rx_pause && tx_pause)
2450                 fc_conf->mode = RTE_FC_FULL;
2451         else if (rx_pause)
2452                 fc_conf->mode = RTE_FC_RX_PAUSE;
2453         else if (tx_pause)
2454                 fc_conf->mode = RTE_FC_TX_PAUSE;
2455         else
2456                 fc_conf->mode = RTE_FC_NONE;
2457
2458         return 0;
2459 }
2460
2461 static int
2462 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2463 {
2464         struct ixgbe_hw *hw;
2465         int err;
2466         uint32_t rx_buf_size;
2467         uint32_t max_high_water;
2468         uint32_t mflcn;
2469         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2470                 ixgbe_fc_none,
2471                 ixgbe_fc_rx_pause,
2472                 ixgbe_fc_tx_pause,
2473                 ixgbe_fc_full
2474         };
2475
2476         PMD_INIT_FUNC_TRACE();
2477
2478         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2479         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2480                 return -ENOTSUP;
2481         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2482         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2483
2484         /*
2485          * At least reserve one Ethernet frame for watermark
2486          * high_water/low_water in kilo bytes for ixgbe
2487          */
2488         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2489         if ((fc_conf->high_water > max_high_water) ||
2490                 (fc_conf->high_water < fc_conf->low_water)) {
2491                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2492                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2493                 return (-EINVAL);
2494         }
2495
2496         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2497         hw->fc.pause_time     = fc_conf->pause_time;
2498         hw->fc.high_water[0]  = fc_conf->high_water;
2499         hw->fc.low_water[0]   = fc_conf->low_water;
2500         hw->fc.send_xon       = fc_conf->send_xon;
2501
2502         err = ixgbe_fc_enable(hw);
2503
2504         /* Not negotiated is not an error case */
2505         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2506
2507                 /* check if we want to forward MAC frames - driver doesn't have native
2508                  * capability to do that, so we'll write the registers ourselves */
2509
2510                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2511
2512                 /* set or clear MFLCN.PMCF bit depending on configuration */
2513                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2514                         mflcn |= IXGBE_MFLCN_PMCF;
2515                 else
2516                         mflcn &= ~IXGBE_MFLCN_PMCF;
2517
2518                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2519                 IXGBE_WRITE_FLUSH(hw);
2520
2521                 return 0;
2522         }
2523
2524         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2525         return -EIO;
2526 }
2527
2528 /**
2529  *  ixgbe_pfc_enable_generic - Enable flow control
2530  *  @hw: pointer to hardware structure
2531  *  @tc_num: traffic class number
2532  *  Enable flow control according to the current settings.
2533  */
2534 static int
2535 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2536 {
2537         int ret_val = 0;
2538         uint32_t mflcn_reg, fccfg_reg;
2539         uint32_t reg;
2540         uint32_t fcrtl, fcrth;
2541         uint8_t i;
2542         uint8_t nb_rx_en;
2543
2544         /* Validate the water mark configuration */
2545         if (!hw->fc.pause_time) {
2546                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2547                 goto out;
2548         }
2549
2550         /* Low water mark of zero causes XOFF floods */
2551         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2552                  /* High/Low water can not be 0 */
2553                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2554                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2555                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2556                         goto out;
2557                 }
2558
2559                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2560                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2561                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2562                         goto out;
2563                 }
2564         }
2565         /* Negotiate the fc mode to use */
2566         ixgbe_fc_autoneg(hw);
2567
2568         /* Disable any previous flow control settings */
2569         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2570         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2571
2572         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2573         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2574
2575         switch (hw->fc.current_mode) {
2576         case ixgbe_fc_none:
2577                 /*
2578                  * If the count of enabled RX Priority Flow control >1,
2579                  * and the TX pause can not be disabled
2580                  */
2581                 nb_rx_en = 0;
2582                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2583                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2584                         if (reg & IXGBE_FCRTH_FCEN)
2585                                 nb_rx_en++;
2586                 }
2587                 if (nb_rx_en > 1)
2588                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2589                 break;
2590         case ixgbe_fc_rx_pause:
2591                 /*
2592                  * Rx Flow control is enabled and Tx Flow control is
2593                  * disabled by software override. Since there really
2594                  * isn't a way to advertise that we are capable of RX
2595                  * Pause ONLY, we will advertise that we support both
2596                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2597                  * disable the adapter's ability to send PAUSE frames.
2598                  */
2599                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2600                 /*
2601                  * If the count of enabled RX Priority Flow control >1,
2602                  * and the TX pause can not be disabled
2603                  */
2604                 nb_rx_en = 0;
2605                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2606                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2607                         if (reg & IXGBE_FCRTH_FCEN)
2608                                 nb_rx_en++;
2609                 }
2610                 if (nb_rx_en > 1)
2611                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2612                 break;
2613         case ixgbe_fc_tx_pause:
2614                 /*
2615                  * Tx Flow control is enabled, and Rx Flow control is
2616                  * disabled by software override.
2617                  */
2618                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2619                 break;
2620         case ixgbe_fc_full:
2621                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2622                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2623                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2624                 break;
2625         default:
2626                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2627                 ret_val = IXGBE_ERR_CONFIG;
2628                 goto out;
2629                 break;
2630         }
2631
2632         /* Set 802.3x based flow control settings. */
2633         mflcn_reg |= IXGBE_MFLCN_DPF;
2634         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2635         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2636
2637         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2638         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2639                 hw->fc.high_water[tc_num]) {
2640                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2641                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2642                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2643         } else {
2644                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2645                 /*
2646                  * In order to prevent Tx hangs when the internal Tx
2647                  * switch is enabled we must set the high water mark
2648                  * to the maximum FCRTH value.  This allows the Tx
2649                  * switch to function even under heavy Rx workloads.
2650                  */
2651                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2652         }
2653         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2654
2655         /* Configure pause time (2 TCs per register) */
2656         reg = hw->fc.pause_time * 0x00010001;
2657         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2658                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2659
2660         /* Configure flow control refresh threshold value */
2661         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2662
2663 out:
2664         return ret_val;
2665 }
2666
2667 static int
2668 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2669 {
2670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2672
2673         if(hw->mac.type != ixgbe_mac_82598EB) {
2674                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2675         }
2676         return ret_val;
2677 }
2678
2679 static int
2680 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2681 {
2682         int err;
2683         uint32_t rx_buf_size;
2684         uint32_t max_high_water;
2685         uint8_t tc_num;
2686         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2687         struct ixgbe_hw *hw =
2688                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689         struct ixgbe_dcb_config *dcb_config =
2690                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2691
2692         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2693                 ixgbe_fc_none,
2694                 ixgbe_fc_rx_pause,
2695                 ixgbe_fc_tx_pause,
2696                 ixgbe_fc_full
2697         };
2698
2699         PMD_INIT_FUNC_TRACE();
2700
2701         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2702         tc_num = map[pfc_conf->priority];
2703         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2704         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2705         /*
2706          * At least reserve one Ethernet frame for watermark
2707          * high_water/low_water in kilo bytes for ixgbe
2708          */
2709         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2710         if ((pfc_conf->fc.high_water > max_high_water) ||
2711             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2712                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2713                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2714                 return (-EINVAL);
2715         }
2716
2717         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2718         hw->fc.pause_time = pfc_conf->fc.pause_time;
2719         hw->fc.send_xon = pfc_conf->fc.send_xon;
2720         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2721         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2722
2723         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2724
2725         /* Not negotiated is not an error case */
2726         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2727                 return 0;
2728
2729         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2730         return -EIO;
2731 }
2732
2733 static int
2734 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2735                           struct rte_eth_rss_reta_entry64 *reta_conf,
2736                           uint16_t reta_size)
2737 {
2738         uint8_t i, j, mask;
2739         uint32_t reta, r;
2740         uint16_t idx, shift;
2741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2742
2743         PMD_INIT_FUNC_TRACE();
2744         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2745                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2746                         "(%d) doesn't match the number hardware can supported "
2747                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2748                 return -EINVAL;
2749         }
2750
2751         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2752                 idx = i / RTE_RETA_GROUP_SIZE;
2753                 shift = i % RTE_RETA_GROUP_SIZE;
2754                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2755                                                 IXGBE_4_BIT_MASK);
2756                 if (!mask)
2757                         continue;
2758                 if (mask == IXGBE_4_BIT_MASK)
2759                         r = 0;
2760                 else
2761                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2762                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2763                         if (mask & (0x1 << j))
2764                                 reta |= reta_conf[idx].reta[shift + j] <<
2765                                                         (CHAR_BIT * j);
2766                         else
2767                                 reta |= r & (IXGBE_8_BIT_MASK <<
2768                                                 (CHAR_BIT * j));
2769                 }
2770                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2771         }
2772
2773         return 0;
2774 }
2775
2776 static int
2777 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2778                          struct rte_eth_rss_reta_entry64 *reta_conf,
2779                          uint16_t reta_size)
2780 {
2781         uint8_t i, j, mask;
2782         uint32_t reta;
2783         uint16_t idx, shift;
2784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785
2786         PMD_INIT_FUNC_TRACE();
2787         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2788                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2789                         "(%d) doesn't match the number hardware can supported "
2790                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2791                 return -EINVAL;
2792         }
2793
2794         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2795                 idx = i / RTE_RETA_GROUP_SIZE;
2796                 shift = i % RTE_RETA_GROUP_SIZE;
2797                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2798                                                 IXGBE_4_BIT_MASK);
2799                 if (!mask)
2800                         continue;
2801
2802                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2803                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2804                         if (mask & (0x1 << j))
2805                                 reta_conf[idx].reta[shift + j] =
2806                                         ((reta >> (CHAR_BIT * j)) &
2807                                                 IXGBE_8_BIT_MASK);
2808                 }
2809         }
2810
2811         return 0;
2812 }
2813
2814 static void
2815 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2816                                 uint32_t index, uint32_t pool)
2817 {
2818         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819         uint32_t enable_addr = 1;
2820
2821         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2822 }
2823
2824 static void
2825 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2826 {
2827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2828
2829         ixgbe_clear_rar(hw, index);
2830 }
2831
2832 static int
2833 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2834 {
2835         uint32_t hlreg0;
2836         uint32_t maxfrs;
2837         struct ixgbe_hw *hw;
2838         struct rte_eth_dev_info dev_info;
2839         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2840
2841         ixgbe_dev_info_get(dev, &dev_info);
2842
2843         /* check that mtu is within the allowed range */
2844         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2845                 return -EINVAL;
2846
2847         /* refuse mtu that requires the support of scattered packets when this
2848          * feature has not been enabled before. */
2849         if (!dev->data->scattered_rx &&
2850             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2851              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2852                 return -EINVAL;
2853
2854         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2856
2857         /* switch to jumbo mode if needed */
2858         if (frame_size > ETHER_MAX_LEN) {
2859                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2860                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2861         } else {
2862                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2863                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2864         }
2865         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2866
2867         /* update max frame size */
2868         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2869
2870         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2871         maxfrs &= 0x0000FFFF;
2872         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2873         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2874
2875         return 0;
2876 }
2877
2878 /*
2879  * Virtual Function operations
2880  */
2881 static void
2882 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2883 {
2884         PMD_INIT_FUNC_TRACE();
2885
2886         /* Clear interrupt mask to stop from interrupts being generated */
2887         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2888
2889         IXGBE_WRITE_FLUSH(hw);
2890 }
2891
2892 static int
2893 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2894 {
2895         struct rte_eth_conf* conf = &dev->data->dev_conf;
2896
2897         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2898                      dev->data->port_id);
2899
2900         /*
2901          * VF has no ability to enable/disable HW CRC
2902          * Keep the persistent behavior the same as Host PF
2903          */
2904 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2905         if (!conf->rxmode.hw_strip_crc) {
2906                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2907                 conf->rxmode.hw_strip_crc = 1;
2908         }
2909 #else
2910         if (conf->rxmode.hw_strip_crc) {
2911                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2912                 conf->rxmode.hw_strip_crc = 0;
2913         }
2914 #endif
2915
2916         return 0;
2917 }
2918
2919 static int
2920 ixgbevf_dev_start(struct rte_eth_dev *dev)
2921 {
2922         struct ixgbe_hw *hw =
2923                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2924         int err, mask = 0;
2925
2926         PMD_INIT_FUNC_TRACE();
2927
2928         hw->mac.ops.reset_hw(hw);
2929
2930         /* negotiate mailbox API version to use with the PF. */
2931         ixgbevf_negotiate_api(hw);
2932
2933         ixgbevf_dev_tx_init(dev);
2934
2935         /* This can fail when allocating mbufs for descriptor rings */
2936         err = ixgbevf_dev_rx_init(dev);
2937         if (err) {
2938                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2939                 ixgbe_dev_clear_queues(dev);
2940                 return err;
2941         }
2942
2943         /* Set vfta */
2944         ixgbevf_set_vfta_all(dev,1);
2945
2946         /* Set HW strip */
2947         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2948                 ETH_VLAN_EXTEND_MASK;
2949         ixgbevf_vlan_offload_set(dev, mask);
2950
2951         ixgbevf_dev_rxtx_start(dev);
2952
2953         return 0;
2954 }
2955
2956 static void
2957 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2958 {
2959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960
2961         PMD_INIT_FUNC_TRACE();
2962
2963         hw->adapter_stopped = TRUE;
2964         ixgbe_stop_adapter(hw);
2965
2966         /*
2967           * Clear what we set, but we still keep shadow_vfta to
2968           * restore after device starts
2969           */
2970         ixgbevf_set_vfta_all(dev,0);
2971
2972         /* Clear stored conf */
2973         dev->data->scattered_rx = 0;
2974
2975         ixgbe_dev_clear_queues(dev);
2976 }
2977
2978 static void
2979 ixgbevf_dev_close(struct rte_eth_dev *dev)
2980 {
2981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2982
2983         PMD_INIT_FUNC_TRACE();
2984
2985         ixgbe_reset_hw(hw);
2986
2987         ixgbevf_dev_stop(dev);
2988
2989         /* reprogram the RAR[0] in case user changed it. */
2990         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2991 }
2992
2993 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2994 {
2995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2996         struct ixgbe_vfta * shadow_vfta =
2997                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2998         int i = 0, j = 0, vfta = 0, mask = 1;
2999
3000         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3001                 vfta = shadow_vfta->vfta[i];
3002                 if(vfta){
3003                         mask = 1;
3004                         for (j = 0; j < 32; j++){
3005                                 if(vfta & mask)
3006                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3007                                 mask<<=1;
3008                         }
3009                 }
3010         }
3011
3012 }
3013
3014 static int
3015 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3016 {
3017         struct ixgbe_hw *hw =
3018                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019         struct ixgbe_vfta * shadow_vfta =
3020                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3021         uint32_t vid_idx = 0;
3022         uint32_t vid_bit = 0;
3023         int ret = 0;
3024
3025         PMD_INIT_FUNC_TRACE();
3026
3027         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3028         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3029         if(ret){
3030                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3031                 return ret;
3032         }
3033         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3034         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3035
3036         /* Save what we set and retore it after device reset */
3037         if (on)
3038                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3039         else
3040                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3041
3042         return 0;
3043 }
3044
3045 static void
3046 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3047 {
3048         struct ixgbe_hw *hw =
3049                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3050         uint32_t ctrl;
3051
3052         PMD_INIT_FUNC_TRACE();
3053
3054         if(queue >= hw->mac.max_rx_queues)
3055                 return;
3056
3057         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3058         if(on)
3059                 ctrl |= IXGBE_RXDCTL_VME;
3060         else
3061                 ctrl &= ~IXGBE_RXDCTL_VME;
3062         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3063
3064         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3065 }
3066
3067 static void
3068 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3069 {
3070         struct ixgbe_hw *hw =
3071                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072         uint16_t i;
3073         int on = 0;
3074
3075         /* VF function only support hw strip feature, others are not support */
3076         if(mask & ETH_VLAN_STRIP_MASK){
3077                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3078
3079                 for(i=0; i < hw->mac.max_rx_queues; i++)
3080                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3081         }
3082 }
3083
3084 static int
3085 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3086 {
3087         uint32_t reg_val;
3088
3089         /* we only need to do this if VMDq is enabled */
3090         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3091         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3092                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3093                 return (-1);
3094         }
3095
3096         return 0;
3097 }
3098
3099 static uint32_t
3100 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3101 {
3102         uint32_t vector = 0;
3103         switch (hw->mac.mc_filter_type) {
3104         case 0:   /* use bits [47:36] of the address */
3105                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3106                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3107                 break;
3108         case 1:   /* use bits [46:35] of the address */
3109                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3110                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3111                 break;
3112         case 2:   /* use bits [45:34] of the address */
3113                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3114                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3115                 break;
3116         case 3:   /* use bits [43:32] of the address */
3117                 vector = ((uc_addr->addr_bytes[4]) |
3118                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3119                 break;
3120         default:  /* Invalid mc_filter_type */
3121                 break;
3122         }
3123
3124         /* vector can only be 12-bits or boundary will be exceeded */
3125         vector &= 0xFFF;
3126         return vector;
3127 }
3128
3129 static int
3130 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3131                                uint8_t on)
3132 {
3133         uint32_t vector;
3134         uint32_t uta_idx;
3135         uint32_t reg_val;
3136         uint32_t uta_shift;
3137         uint32_t rc;
3138         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3139         const uint32_t ixgbe_uta_bit_shift = 5;
3140         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3141         const uint32_t bit1 = 0x1;
3142
3143         struct ixgbe_hw *hw =
3144                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3145         struct ixgbe_uta_info *uta_info =
3146                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3147
3148         /* The UTA table only exists on 82599 hardware and newer */
3149         if (hw->mac.type < ixgbe_mac_82599EB)
3150                 return (-ENOTSUP);
3151
3152         vector = ixgbe_uta_vector(hw,mac_addr);
3153         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3154         uta_shift = vector & ixgbe_uta_bit_mask;
3155
3156         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3157         if(rc == on)
3158                 return 0;
3159
3160         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3161         if (on) {
3162                 uta_info->uta_in_use++;
3163                 reg_val |= (bit1 << uta_shift);
3164                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3165         } else {
3166                 uta_info->uta_in_use--;
3167                 reg_val &= ~(bit1 << uta_shift);
3168                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3169         }
3170
3171         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3172
3173         if (uta_info->uta_in_use > 0)
3174                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3175                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3176         else
3177                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3178
3179         return 0;
3180 }
3181
3182 static int
3183 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3184 {
3185         int i;
3186         struct ixgbe_hw *hw =
3187                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3188         struct ixgbe_uta_info *uta_info =
3189                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3190
3191         /* The UTA table only exists on 82599 hardware and newer */
3192         if (hw->mac.type < ixgbe_mac_82599EB)
3193                 return (-ENOTSUP);
3194
3195         if(on) {
3196                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3197                         uta_info->uta_shadow[i] = ~0;
3198                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3199                 }
3200         } else {
3201                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3202                         uta_info->uta_shadow[i] = 0;
3203                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3204                 }
3205         }
3206         return 0;
3207
3208 }
3209
3210 uint32_t
3211 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3212 {
3213         uint32_t new_val = orig_val;
3214
3215         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3216                 new_val |= IXGBE_VMOLR_AUPE;
3217         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3218                 new_val |= IXGBE_VMOLR_ROMPE;
3219         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3220                 new_val |= IXGBE_VMOLR_ROPE;
3221         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3222                 new_val |= IXGBE_VMOLR_BAM;
3223         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3224                 new_val |= IXGBE_VMOLR_MPE;
3225
3226         return new_val;
3227 }
3228
3229 static int
3230 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3231                                uint16_t rx_mask, uint8_t on)
3232 {
3233         int val = 0;
3234
3235         struct ixgbe_hw *hw =
3236                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3237         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3238
3239         if (hw->mac.type == ixgbe_mac_82598EB) {
3240                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3241                              " on 82599 hardware and newer");
3242                 return (-ENOTSUP);
3243         }
3244         if (ixgbe_vmdq_mode_check(hw) < 0)
3245                 return (-ENOTSUP);
3246
3247         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3248
3249         if (on)
3250                 vmolr |= val;
3251         else
3252                 vmolr &= ~val;
3253
3254         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3255
3256         return 0;
3257 }
3258
3259 static int
3260 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3261 {
3262         uint32_t reg,addr;
3263         uint32_t val;
3264         const uint8_t bit1 = 0x1;
3265
3266         struct ixgbe_hw *hw =
3267                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3268
3269         if (ixgbe_vmdq_mode_check(hw) < 0)
3270                 return (-ENOTSUP);
3271
3272         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3273         reg = IXGBE_READ_REG(hw, addr);
3274         val = bit1 << pool;
3275
3276         if (on)
3277                 reg |= val;
3278         else
3279                 reg &= ~val;
3280
3281         IXGBE_WRITE_REG(hw, addr,reg);
3282
3283         return 0;
3284 }
3285
3286 static int
3287 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3288 {
3289         uint32_t reg,addr;
3290         uint32_t val;
3291         const uint8_t bit1 = 0x1;
3292
3293         struct ixgbe_hw *hw =
3294                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295
3296         if (ixgbe_vmdq_mode_check(hw) < 0)
3297                 return (-ENOTSUP);
3298
3299         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3300         reg = IXGBE_READ_REG(hw, addr);
3301         val = bit1 << pool;
3302
3303         if (on)
3304                 reg |= val;
3305         else
3306                 reg &= ~val;
3307
3308         IXGBE_WRITE_REG(hw, addr,reg);
3309
3310         return 0;
3311 }
3312
3313 static int
3314 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3315                         uint64_t pool_mask, uint8_t vlan_on)
3316 {
3317         int ret = 0;
3318         uint16_t pool_idx;
3319         struct ixgbe_hw *hw =
3320                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3321
3322         if (ixgbe_vmdq_mode_check(hw) < 0)
3323                 return (-ENOTSUP);
3324         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3325                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3326                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3327                         if (ret < 0)
3328                                 return ret;
3329         }
3330
3331         return ret;
3332 }
3333
3334 static int
3335 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3336                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3337                         uint8_t rule_id, uint8_t on)
3338 {
3339         uint32_t mr_ctl,vlvf;
3340         uint32_t mp_lsb = 0;
3341         uint32_t mv_msb = 0;
3342         uint32_t mv_lsb = 0;
3343         uint32_t mp_msb = 0;
3344         uint8_t i = 0;
3345         int reg_index = 0;
3346         uint64_t vlan_mask = 0;
3347
3348         const uint8_t pool_mask_offset = 32;
3349         const uint8_t vlan_mask_offset = 32;
3350         const uint8_t dst_pool_offset = 8;
3351         const uint8_t rule_mr_offset  = 4;
3352         const uint8_t mirror_rule_mask= 0x0F;
3353
3354         struct ixgbe_mirror_info *mr_info =
3355                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3356         struct ixgbe_hw *hw =
3357                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358
3359         if (ixgbe_vmdq_mode_check(hw) < 0)
3360                 return (-ENOTSUP);
3361
3362         /* Check if vlan mask is valid */
3363         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3364                 if (mirror_conf->vlan.vlan_mask == 0)
3365                         return (-EINVAL);
3366         }
3367
3368         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3369         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3370                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3371                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3372                                 /* search vlan id related pool vlan filter index */
3373                                 reg_index = ixgbe_find_vlvf_slot(hw,
3374                                                 mirror_conf->vlan.vlan_id[i]);
3375                                 if(reg_index < 0)
3376                                         return (-EINVAL);
3377                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3378                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3379                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3380                                                 == mirror_conf->vlan.vlan_id[i]))
3381                                         vlan_mask |= (1ULL << reg_index);
3382                                 else
3383                                         return (-EINVAL);
3384                         }
3385                 }
3386
3387                 if (on) {
3388                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3389                         mv_msb = vlan_mask >> vlan_mask_offset;
3390
3391                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3392                                                 mirror_conf->vlan.vlan_mask;
3393                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3394                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3395                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3396                                                 mirror_conf->vlan.vlan_id[i];
3397                         }
3398                 } else {
3399                         mv_lsb = 0;
3400                         mv_msb = 0;
3401                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3402                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3403                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3404                 }
3405         }
3406
3407         /*
3408          * if enable pool mirror, write related pool mask register,if disable
3409          * pool mirror, clear PFMRVM register
3410          */
3411         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3412                 if (on) {
3413                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3414                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3415                         mr_info->mr_conf[rule_id].pool_mask =
3416                                         mirror_conf->pool_mask;
3417
3418                 } else {
3419                         mp_lsb = 0;
3420                         mp_msb = 0;
3421                         mr_info->mr_conf[rule_id].pool_mask = 0;
3422                 }
3423         }
3424
3425         /* read  mirror control register and recalculate it */
3426         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3427
3428         if (on) {
3429                 mr_ctl |= mirror_conf->rule_type_mask;
3430                 mr_ctl &= mirror_rule_mask;
3431                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3432         } else
3433                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3434
3435         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3436         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3437
3438         /* write mirrror control  register */
3439         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3440
3441         /* write pool mirrror control  register */
3442         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3443                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3444                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3445                                 mp_msb);
3446         }
3447         /* write VLAN mirrror control  register */
3448         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3449                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3450                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3451                                 mv_msb);
3452         }
3453
3454         return 0;
3455 }
3456
3457 static int
3458 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3459 {
3460         int mr_ctl = 0;
3461         uint32_t lsb_val = 0;
3462         uint32_t msb_val = 0;
3463         const uint8_t rule_mr_offset = 4;
3464
3465         struct ixgbe_hw *hw =
3466                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467         struct ixgbe_mirror_info *mr_info =
3468                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3469
3470         if (ixgbe_vmdq_mode_check(hw) < 0)
3471                 return (-ENOTSUP);
3472
3473         memset(&mr_info->mr_conf[rule_id], 0,
3474                 sizeof(struct rte_eth_vmdq_mirror_conf));
3475
3476         /* clear PFVMCTL register */
3477         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3478
3479         /* clear pool mask register */
3480         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3481         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3482
3483         /* clear vlan mask register */
3484         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3485         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3486
3487         return 0;
3488 }
3489
3490 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3491         uint16_t queue_idx, uint16_t tx_rate)
3492 {
3493         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3494         uint32_t rf_dec, rf_int;
3495         uint32_t bcnrc_val;
3496         uint16_t link_speed = dev->data->dev_link.link_speed;
3497
3498         if (queue_idx >= hw->mac.max_tx_queues)
3499                 return -EINVAL;
3500
3501         if (tx_rate != 0) {
3502                 /* Calculate the rate factor values to set */
3503                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3504                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3505                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3506
3507                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3508                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3509                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3510                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3511         } else {
3512                 bcnrc_val = 0;
3513         }
3514
3515         /*
3516          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3517          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3518          * set as 0x4.
3519          */
3520         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3521                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3522                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3523                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3524                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3525         else
3526                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3527                         IXGBE_MMW_SIZE_DEFAULT);
3528
3529         /* Set RTTBCNRC of queue X */
3530         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3531         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3532         IXGBE_WRITE_FLUSH(hw);
3533
3534         return 0;
3535 }
3536
3537 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3538         uint16_t tx_rate, uint64_t q_msk)
3539 {
3540         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3541         struct ixgbe_vf_info *vfinfo =
3542                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3543         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3544         uint32_t queue_stride =
3545                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3546         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3547         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3548         uint16_t total_rate = 0;
3549
3550         if (queue_end >= hw->mac.max_tx_queues)
3551                 return -EINVAL;
3552
3553         if (vfinfo != NULL) {
3554                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3555                         if (vf_idx == vf)
3556                                 continue;
3557                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3558                                 idx++)
3559                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3560                 }
3561         } else
3562                 return -EINVAL;
3563
3564         /* Store tx_rate for this vf. */
3565         for (idx = 0; idx < nb_q_per_pool; idx++) {
3566                 if (((uint64_t)0x1 << idx) & q_msk) {
3567                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3568                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3569                         total_rate += tx_rate;
3570                 }
3571         }
3572
3573         if (total_rate > dev->data->dev_link.link_speed) {
3574                 /*
3575                  * Reset stored TX rate of the VF if it causes exceed
3576                  * link speed.
3577                  */
3578                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3579                 return -EINVAL;
3580         }
3581
3582         /* Set RTTBCNRC of each queue/pool for vf X  */
3583         for (; queue_idx <= queue_end; queue_idx++) {
3584                 if (0x1 & q_msk)
3585                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3586                 q_msk = q_msk >> 1;
3587         }
3588
3589         return 0;
3590 }
3591
3592 static void
3593 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3594                      __attribute__((unused)) uint32_t index,
3595                      __attribute__((unused)) uint32_t pool)
3596 {
3597         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3598         int diag;
3599
3600         /*
3601          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3602          * operation. Trap this case to avoid exhausting the [very limited]
3603          * set of PF resources used to store VF MAC addresses.
3604          */
3605         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3606                 return;
3607         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3608         if (diag == 0)
3609                 return;
3610         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3611 }
3612
3613 static void
3614 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3615 {
3616         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3618         struct ether_addr *mac_addr;
3619         uint32_t i;
3620         int diag;
3621
3622         /*
3623          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3624          * not support the deletion of a given MAC address.
3625          * Instead, it imposes to delete all MAC addresses, then to add again
3626          * all MAC addresses with the exception of the one to be deleted.
3627          */
3628         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3629
3630         /*
3631          * Add again all MAC addresses, with the exception of the deleted one
3632          * and of the permanent MAC address.
3633          */
3634         for (i = 0, mac_addr = dev->data->mac_addrs;
3635              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3636                 /* Skip the deleted MAC address */
3637                 if (i == index)
3638                         continue;
3639                 /* Skip NULL MAC addresses */
3640                 if (is_zero_ether_addr(mac_addr))
3641                         continue;
3642                 /* Skip the permanent MAC address */
3643                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3644                         continue;
3645                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3646                 if (diag != 0)
3647                         PMD_DRV_LOG(ERR,
3648                                     "Adding again MAC address "
3649                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3650                                     "diag=%d",
3651                                     mac_addr->addr_bytes[0],
3652                                     mac_addr->addr_bytes[1],
3653                                     mac_addr->addr_bytes[2],
3654                                     mac_addr->addr_bytes[3],
3655                                     mac_addr->addr_bytes[4],
3656                                     mac_addr->addr_bytes[5],
3657                                     diag);
3658         }
3659 }
3660
3661 /*
3662  * add syn filter
3663  *
3664  * @param
3665  * dev: Pointer to struct rte_eth_dev.
3666  * filter: ponter to the filter that will be added.
3667  * rx_queue: the queue id the filter assigned to.
3668  *
3669  * @return
3670  *    - On success, zero.
3671  *    - On failure, a negative value.
3672  */
3673 static int
3674 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3675                         struct rte_syn_filter *filter, uint16_t rx_queue)
3676 {
3677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3678         uint32_t synqf;
3679
3680         if (hw->mac.type != ixgbe_mac_82599EB)
3681                 return -ENOSYS;
3682
3683         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3684                 return -EINVAL;
3685
3686         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3687
3688         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3689                 return -EINVAL;
3690
3691         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3692                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3693
3694         if (filter->hig_pri)
3695                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3696         else
3697                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3698
3699         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3700         return 0;
3701 }
3702
3703 /*
3704  * remove syn filter
3705  *
3706  * @param
3707  * dev: Pointer to struct rte_eth_dev.
3708  *
3709  * @return
3710  *    - On success, zero.
3711  *    - On failure, a negative value.
3712  */
3713 static int
3714 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3715 {
3716         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3717         uint32_t synqf;
3718
3719         if (hw->mac.type != ixgbe_mac_82599EB)
3720                 return -ENOSYS;
3721
3722         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3723
3724         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3725
3726         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3727         return 0;
3728 }
3729
3730 /*
3731  * get the syn filter's info
3732  *
3733  * @param
3734  * dev: Pointer to struct rte_eth_dev.
3735  * filter: ponter to the filter that returns.
3736  * *rx_queue: pointer to the queue id the filter assigned to.
3737  *
3738  * @return
3739  *    - On success, zero.
3740  *    - On failure, a negative value.
3741  */
3742 static int
3743 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3744                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3745
3746 {
3747         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3748         uint32_t synqf;
3749
3750         if (hw->mac.type != ixgbe_mac_82599EB)
3751                 return -ENOSYS;
3752
3753         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3754         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3755                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3756                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3757                 return 0;
3758         }
3759         return -ENOENT;
3760 }
3761
3762 /*
3763  * add an ethertype filter
3764  *
3765  * @param
3766  * dev: Pointer to struct rte_eth_dev.
3767  * index: the index the filter allocates.
3768  * filter: ponter to the filter that will be added.
3769  * rx_queue: the queue id the filter assigned to.
3770  *
3771  * @return
3772  *    - On success, zero.
3773  *    - On failure, a negative value.
3774  */
3775 static int
3776 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3777                         uint16_t index, struct rte_ethertype_filter *filter,
3778                         uint16_t rx_queue)
3779 {
3780         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3781         uint32_t etqf, etqs = 0;
3782
3783         if (hw->mac.type != ixgbe_mac_82599EB)
3784                 return -ENOSYS;
3785
3786         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3787                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3788                 return -EINVAL;
3789
3790         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3791         if (etqf & IXGBE_ETQF_FILTER_EN)
3792                 return -EINVAL;  /* filter index is in use. */
3793
3794         etqf = 0;
3795         etqf |= IXGBE_ETQF_FILTER_EN;
3796         etqf |= (uint32_t)filter->ethertype;
3797
3798         if (filter->priority_en) {
3799                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3800                         return -EINVAL;
3801                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3802                 etqf |= IXGBE_ETQF_UP_EN;
3803         }
3804         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3805         etqs |= IXGBE_ETQS_QUEUE_EN;
3806
3807         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3808         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3809         return 0;
3810 }
3811
3812 /*
3813  * remove an ethertype filter
3814  *
3815  * @param
3816  * dev: Pointer to struct rte_eth_dev.
3817  * index: the index the filter allocates.
3818  *
3819  * @return
3820  *    - On success, zero.
3821  *    - On failure, a negative value.
3822  */
3823 static int
3824 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3825                         uint16_t index)
3826 {
3827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3828
3829         if (hw->mac.type != ixgbe_mac_82599EB)
3830                 return -ENOSYS;
3831
3832         if (index >= IXGBE_MAX_ETQF_FILTERS)
3833                 return -EINVAL;
3834
3835         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3836         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3837
3838         return 0;
3839 }
3840
3841 /*
3842  * get an ethertype filter
3843  *
3844  * @param
3845  * dev: Pointer to struct rte_eth_dev.
3846  * index: the index the filter allocates.
3847  * filter: ponter to the filter that will be gotten.
3848  * *rx_queue: the ponited of the queue id the filter assigned to.
3849  *
3850  * @return
3851  *    - On success, zero.
3852  *    - On failure, a negative value.
3853  */
3854 static int
3855 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3856                         uint16_t index, struct rte_ethertype_filter *filter,
3857                         uint16_t *rx_queue)
3858 {
3859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3860         uint32_t etqf, etqs;
3861
3862         if (hw->mac.type != ixgbe_mac_82599EB)
3863                 return -ENOSYS;
3864
3865         if (index >= IXGBE_MAX_ETQF_FILTERS)
3866                 return -EINVAL;
3867
3868         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3869         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3870         if (etqf & IXGBE_ETQF_FILTER_EN) {
3871                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3872                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3873                 if (filter->priority_en)
3874                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3875                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3876                 return 0;
3877         }
3878         return -ENOENT;
3879 }
3880
3881 static inline enum ixgbe_5tuple_protocol
3882 convert_protocol_type(uint8_t protocol_value)
3883 {
3884         if (protocol_value == IPPROTO_TCP)
3885                 return IXGBE_FILTER_PROTOCOL_TCP;
3886         else if (protocol_value == IPPROTO_UDP)
3887                 return IXGBE_FILTER_PROTOCOL_UDP;
3888         else if (protocol_value == IPPROTO_SCTP)
3889                 return IXGBE_FILTER_PROTOCOL_SCTP;
3890         else
3891                 return IXGBE_FILTER_PROTOCOL_NONE;
3892 }
3893
3894 static inline uint8_t
3895 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3896 {
3897         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3898                 return IPPROTO_TCP;
3899         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3900                 return IPPROTO_UDP;
3901         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3902                 return IPPROTO_SCTP;
3903         else
3904                 return 0;
3905 }
3906
3907 /*
3908  * add a 5tuple filter
3909  *
3910  * @param
3911  * dev: Pointer to struct rte_eth_dev.
3912  * index: the index the filter allocates.
3913  * filter: ponter to the filter that will be added.
3914  * rx_queue: the queue id the filter assigned to.
3915  *
3916  * @return
3917  *    - On success, zero.
3918  *    - On failure, a negative value.
3919  */
3920 static int
3921 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3922                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3923 {
3924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3925         uint32_t ftqf, sdpqf = 0;
3926         uint32_t l34timir = 0;
3927         uint8_t mask = 0xff;
3928
3929         if (hw->mac.type != ixgbe_mac_82599EB)
3930                 return -ENOSYS;
3931
3932         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3933                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3934                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3935                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3936                 return -EINVAL;  /* filter index is out of range. */
3937
3938         if (filter->tcp_flags) {
3939                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3940                 return -EINVAL;
3941         }
3942
3943         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3944         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3945                 return -EINVAL;  /* filter index is in use. */
3946
3947         ftqf = 0;
3948         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3949         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3950
3951         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3952                 IXGBE_FTQF_PROTOCOL_MASK);
3953         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3954                 IXGBE_FTQF_PRIORITY_SHIFT);
3955         if (filter->src_ip_mask == 0) /* 0 means compare. */
3956                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3957         if (filter->dst_ip_mask == 0)
3958                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3959         if (filter->src_port_mask == 0)
3960                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3961         if (filter->dst_port_mask == 0)
3962                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3963         if (filter->protocol_mask == 0)
3964                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3965         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3966         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3967         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3968
3969         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3970         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3971         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3972         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3973
3974         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3975         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3976         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3977         return 0;
3978 }
3979
3980 /*
3981  * remove a 5tuple filter
3982  *
3983  * @param
3984  * dev: Pointer to struct rte_eth_dev.
3985  * index: the index the filter allocates.
3986  *
3987  * @return
3988  *    - On success, zero.
3989  *    - On failure, a negative value.
3990  */
3991 static int
3992 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3993                         uint16_t index)
3994 {
3995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3996
3997         if (hw->mac.type != ixgbe_mac_82599EB)
3998                 return -ENOSYS;
3999
4000         if (index >= IXGBE_MAX_FTQF_FILTERS)
4001                 return -EINVAL;  /* filter index is out of range. */
4002
4003         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4004         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4005         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4006         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4007         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4008         return 0;
4009 }
4010
4011 /*
4012  * get a 5tuple filter
4013  *
4014  * @param
4015  * dev: Pointer to struct rte_eth_dev.
4016  * index: the index the filter allocates
4017  * filter: ponter to the filter that returns.
4018  * *rx_queue: pointer of the queue id the filter assigned to.
4019  *
4020  * @return
4021  *    - On success, zero.
4022  *    - On failure, a negative value.
4023  */
4024 static int
4025 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
4026                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
4027 {
4028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4029         uint32_t sdpqf, ftqf, l34timir;
4030         uint8_t mask;
4031         enum ixgbe_5tuple_protocol proto;
4032
4033         if (hw->mac.type != ixgbe_mac_82599EB)
4034                 return -ENOSYS;
4035
4036         if (index >= IXGBE_MAX_FTQF_FILTERS)
4037                 return -EINVAL;  /* filter index is out of range. */
4038
4039         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
4040         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
4041                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
4042                 filter->protocol = revert_protocol_type(proto);
4043                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
4044                                         IXGBE_FTQF_PRIORITY_MASK;
4045                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
4046                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
4047                 filter->src_ip_mask =
4048                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
4049                 filter->dst_ip_mask =
4050                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
4051                 filter->src_port_mask =
4052                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
4053                 filter->dst_port_mask =
4054                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
4055                 filter->protocol_mask =
4056                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
4057
4058                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
4059                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
4060                                         IXGBE_SDPQF_DSTPORT_SHIFT;
4061                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
4062                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
4063                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
4064
4065                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
4066                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
4067                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
4068                 return 0;
4069         }
4070         return -ENOENT;
4071 }
4072
4073 static int
4074 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4075 {
4076         struct ixgbe_hw *hw;
4077         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4078
4079         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080
4081         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4082                 return -EINVAL;
4083
4084         /* refuse mtu that requires the support of scattered packets when this
4085          * feature has not been enabled before. */
4086         if (!dev->data->scattered_rx &&
4087             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4088              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4089                 return -EINVAL;
4090
4091         /*
4092          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4093          * request of the version 2.0 of the mailbox API.
4094          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4095          * of the mailbox API.
4096          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4097          * prior to 3.11.33 which contains the following change:
4098          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4099          */
4100         ixgbevf_rlpml_set_vf(hw, max_frame);
4101
4102         /* update max frame size */
4103         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4104         return 0;
4105 }
4106
4107 static struct rte_driver rte_ixgbe_driver = {
4108         .type = PMD_PDEV,
4109         .init = rte_ixgbe_pmd_init,
4110 };
4111
4112 static struct rte_driver rte_ixgbevf_driver = {
4113         .type = PMD_PDEV,
4114         .init = rte_ixgbevf_pmd_init,
4115 };
4116
4117 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4118 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);