lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72
  73 /*
  74  * High threshold controlling when to start sending XOFF frames. Must be at
  75  * least 8 bytes less than receive packet buffer size. This value is in units
  76  * of 1024 bytes.
  77  */
  78 #define IXGBE_FC_HI    0x80
  79
  80 /*
  81  * Low threshold controlling when to start sending XON frames. This value is
  82  * in units of 1024 bytes.
  83  */
  84 #define IXGBE_FC_LO    0x40
  85
  86 /* Timer value included in XOFF frames. */
  87 #define IXGBE_FC_PAUSE 0x680
  88
  89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  90 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  91 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  92
  93 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  94 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  95
  96 /*
  97  *  Default values for RX/TX configuration
  98  */
  99 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 100 #define IXGBE_DEFAULT_RX_PTHRESH      8
 101 #define IXGBE_DEFAULT_RX_HTHRESH      8
 102 #define IXGBE_DEFAULT_RX_WTHRESH      0
 103
 104 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 105 #define IXGBE_DEFAULT_TX_PTHRESH      32
 106 #define IXGBE_DEFAULT_TX_HTHRESH      0
 107 #define IXGBE_DEFAULT_TX_WTHRESH      0
 108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 109
 110 /* Bit shift and mask */
 111 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 112 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 113 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 114 #define IXGBE_8_BIT_MASK   UINT8_MAX
 115
 116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 117
 118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 119
 120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 121                 struct rte_eth_dev *eth_dev);
 122 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 125 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 126 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 133                                 int wait_to_complete);
 134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 135                                 struct rte_eth_stats *stats);
 136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 138                                              uint16_t queue_id,
 139                                              uint8_t stat_idx,
 140                                              uint8_t is_rx);
 141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 142                                struct rte_eth_dev_info *dev_info);
 143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 144                                  struct rte_eth_dev_info *dev_info);
 145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 146
 147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 148                 uint16_t vlan_id, int on);
 149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 151                 uint16_t queue, bool on);
 152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 153                 int on);
 154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 165                                struct rte_eth_fc_conf *fc_conf);
 166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 167                 struct rte_eth_pfc_conf *pfc_conf);
 168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 169                         struct rte_eth_rss_reta_entry64 *reta_conf,
 170                         uint16_t reta_size);
 171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 172                         struct rte_eth_rss_reta_entry64 *reta_conf,
 173                         uint16_t reta_size);
 174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 179                 void *param);
 180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 182                 uint32_t index, uint32_t pool);
 183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 185
 186 /* For Virtual Function support */
 187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 188                 struct rte_eth_dev *eth_dev);
 189 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 190 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 195                 struct rte_eth_stats *stats);
 196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 198                 uint16_t vlan_id, int on);
 199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 200                 uint16_t queue, int on);
 201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203
 204 /* For Eth VMDQ APIs support */
 205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 206                 ether_addr* mac_addr,uint8_t on);
 207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 208 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 209                 uint16_t rx_mask, uint8_t on);
 210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 213                 uint64_t pool_mask,uint8_t vlan_on);
 214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 216                 uint8_t rule_id, uint8_t on);
 217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 218                 uint8_t rule_id);
 219
 220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 221                 uint16_t queue_idx, uint16_t tx_rate);
 222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 223                 uint16_t tx_rate, uint64_t q_msk);
 224
 225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 226                                  struct ether_addr *mac_addr,
 227                                  uint32_t index, uint32_t pool);
 228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 229 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 230                         struct rte_syn_filter *filter, uint16_t rx_queue);
 231 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 232 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 233                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 234 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 235                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 236 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 237                         uint16_t index);
 238 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 239                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 240 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 241                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 242 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 243                         uint16_t index);
 244 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 245                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 246
 247 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 248
 249 /*
 250  * Define VF Stats MACRO for Non "cleared on read" register
 251  */
 252 #define UPDATE_VF_STAT(reg, last, cur)                          \
 253 {                                                               \
 254         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 255         cur += latest - last;                                   \
 256         last = latest;                                          \
 257 }
 258
 259 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 260 {                                                                \
 261         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 262         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 263         u64 latest = ((new_msb << 32) | new_lsb);                \
 264         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 265         last = latest;                                           \
 266 }
 267
 268 #define IXGBE_SET_HWSTRIP(h, q) do{\
 269                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 270                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 271                 (h)->bitmap[idx] |= 1 << bit;\
 272         }while(0)
 273
 274 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 275                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 276                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 277                 (h)->bitmap[idx] &= ~(1 << bit);\
 278         }while(0)
 279
 280 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 281                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 283                 (r) = (h)->bitmap[idx] >> bit & 1;\
 284         }while(0)
 285
 286 /*
 287  * The set of PCI devices this driver supports
 288  */
 289 static struct rte_pci_id pci_id_ixgbe_map[] = {
 290
 291 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 292 #include "rte_pci_dev_ids.h"
 293
 294 { .vendor_id = 0, /* sentinel */ },
 295 };
 296
 297
 298 /*
 299  * The set of PCI devices this driver supports (for 82599 VF)
 300  */
 301 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 302
 303 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 304 #include "rte_pci_dev_ids.h"
 305 { .vendor_id = 0, /* sentinel */ },
 306
 307 };
 308
 309 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 310         .dev_configure        = ixgbe_dev_configure,
 311         .dev_start            = ixgbe_dev_start,
 312         .dev_stop             = ixgbe_dev_stop,
 313         .dev_set_link_up    = ixgbe_dev_set_link_up,
 314         .dev_set_link_down  = ixgbe_dev_set_link_down,
 315         .dev_close            = ixgbe_dev_close,
 316         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 317         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 318         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 319         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 320         .link_update          = ixgbe_dev_link_update,
 321         .stats_get            = ixgbe_dev_stats_get,
 322         .stats_reset          = ixgbe_dev_stats_reset,
 323         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 324         .dev_infos_get        = ixgbe_dev_info_get,
 325         .mtu_set              = ixgbe_dev_mtu_set,
 326         .vlan_filter_set      = ixgbe_vlan_filter_set,
 327         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 328         .vlan_offload_set     = ixgbe_vlan_offload_set,
 329         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 330         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 331         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 332         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 333         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 334         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 335         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 336         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 337         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 338         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 339         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 340         .dev_led_on           = ixgbe_dev_led_on,
 341         .dev_led_off          = ixgbe_dev_led_off,
 342         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 343         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 344         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 345         .mac_addr_add         = ixgbe_add_rar,
 346         .mac_addr_remove      = ixgbe_remove_rar,
 347         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 348         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 349         .mirror_rule_set      = ixgbe_mirror_rule_set,
 350         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 351         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 352         .set_vf_rx            = ixgbe_set_pool_rx,
 353         .set_vf_tx            = ixgbe_set_pool_tx,
 354         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 355         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 356         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 357         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 358         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 359         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 360         .fdir_infos_get               = ixgbe_fdir_info_get,
 361         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 362         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 363         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 364         .fdir_set_masks               = ixgbe_fdir_set_masks,
 365         .reta_update          = ixgbe_dev_rss_reta_update,
 366         .reta_query           = ixgbe_dev_rss_reta_query,
 367 #ifdef RTE_NIC_BYPASS
 368         .bypass_init          = ixgbe_bypass_init,
 369         .bypass_state_set     = ixgbe_bypass_state_store,
 370         .bypass_state_show    = ixgbe_bypass_state_show,
 371         .bypass_event_set     = ixgbe_bypass_event_store,
 372         .bypass_event_show    = ixgbe_bypass_event_show,
 373         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 374         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 375         .bypass_ver_show      = ixgbe_bypass_ver_show,
 376         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 377 #endif /* RTE_NIC_BYPASS */
 378         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 379         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 380         .add_syn_filter          = ixgbe_add_syn_filter,
 381         .remove_syn_filter       = ixgbe_remove_syn_filter,
 382         .get_syn_filter          = ixgbe_get_syn_filter,
 383         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 384         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 385         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 386         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 387         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 388         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 389 };
 390
 391 /*
 392  * dev_ops for virtual function, bare necessities for basic vf
 393  * operation have been implemented
 394  */
 395 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 396
 397         .dev_configure        = ixgbevf_dev_configure,
 398         .dev_start            = ixgbevf_dev_start,
 399         .dev_stop             = ixgbevf_dev_stop,
 400         .link_update          = ixgbe_dev_link_update,
 401         .stats_get            = ixgbevf_dev_stats_get,
 402         .stats_reset          = ixgbevf_dev_stats_reset,
 403         .dev_close            = ixgbevf_dev_close,
 404         .dev_infos_get        = ixgbevf_dev_info_get,
 405         .mtu_set              = ixgbevf_dev_set_mtu,
 406         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 407         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 408         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 409         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 410         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 411         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 412         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 413         .mac_addr_add         = ixgbevf_add_mac_addr,
 414         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 415 };
 416
 417 /**
 418  * Atomically reads the link status information from global
 419  * structure rte_eth_dev.
 420  *
 421  * @param dev
 422  *   - Pointer to the structure rte_eth_dev to read from.
 423  *   - Pointer to the buffer to be saved with the link status.
 424  *
 425  * @return
 426  *   - On success, zero.
 427  *   - On failure, negative value.
 428  */
 429 static inline int
 430 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 431                                 struct rte_eth_link *link)
 432 {
 433         struct rte_eth_link *dst = link;
 434         struct rte_eth_link *src = &(dev->data->dev_link);
 435
 436         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 437                                         *(uint64_t *)src) == 0)
 438                 return -1;
 439
 440         return 0;
 441 }
 442
 443 /**
 444  * Atomically writes the link status information into global
 445  * structure rte_eth_dev.
 446  *
 447  * @param dev
 448  *   - Pointer to the structure rte_eth_dev to read from.
 449  *   - Pointer to the buffer to be saved with the link status.
 450  *
 451  * @return
 452  *   - On success, zero.
 453  *   - On failure, negative value.
 454  */
 455 static inline int
 456 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 457                                 struct rte_eth_link *link)
 458 {
 459         struct rte_eth_link *dst = &(dev->data->dev_link);
 460         struct rte_eth_link *src = link;
 461
 462         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 463                                         *(uint64_t *)src) == 0)
 464                 return -1;
 465
 466         return 0;
 467 }
 468
 469 /*
 470  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 471  */
 472 static inline int
 473 ixgbe_is_sfp(struct ixgbe_hw *hw)
 474 {
 475         switch (hw->phy.type) {
 476         case ixgbe_phy_sfp_avago:
 477         case ixgbe_phy_sfp_ftl:
 478         case ixgbe_phy_sfp_intel:
 479         case ixgbe_phy_sfp_unknown:
 480         case ixgbe_phy_sfp_passive_tyco:
 481         case ixgbe_phy_sfp_passive_unknown:
 482                 return 1;
 483         default:
 484                 return 0;
 485         }
 486 }
 487
 488 static inline int32_t
 489 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 490 {
 491         uint32_t ctrl_ext;
 492         int32_t status;
 493
 494         status = ixgbe_reset_hw(hw);
 495
 496         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 497         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 498         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 499         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 500         IXGBE_WRITE_FLUSH(hw);
 501
 502         return status;
 503 }
 504
 505 static inline void
 506 ixgbe_enable_intr(struct rte_eth_dev *dev)
 507 {
 508         struct ixgbe_interrupt *intr =
 509                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 510         struct ixgbe_hw *hw =
 511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 512
 513         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 514         IXGBE_WRITE_FLUSH(hw);
 515 }
 516
 517 /*
 518  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 519  */
 520 static void
 521 ixgbe_disable_intr(struct ixgbe_hw *hw)
 522 {
 523         PMD_INIT_FUNC_TRACE();
 524
 525         if (hw->mac.type == ixgbe_mac_82598EB) {
 526                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 527         } else {
 528                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 529                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 530                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 531         }
 532         IXGBE_WRITE_FLUSH(hw);
 533 }
 534
 535 /*
 536  * This function resets queue statistics mapping registers.
 537  * From Niantic datasheet, Initialization of Statistics section:
 538  * "...if software requires the queue counters, the RQSMR and TQSM registers
 539  * must be re-programmed following a device reset.
 540  */
 541 static void
 542 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 543 {
 544         uint32_t i;
 545
 546         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 547                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 548                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 549         }
 550 }
 551
 552
 553 static int
 554 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 555                                   uint16_t queue_id,
 556                                   uint8_t stat_idx,
 557                                   uint8_t is_rx)
 558 {
 559 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 560 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 561 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 562
 563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 564         struct ixgbe_stat_mapping_registers *stat_mappings =
 565                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 566         uint32_t qsmr_mask = 0;
 567         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 568         uint32_t q_map;
 569         uint8_t n, offset;
 570
 571         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 572                 (hw->mac.type != ixgbe_mac_X540) &&
 573                 (hw->mac.type != ixgbe_mac_X550) &&
 574                 (hw->mac.type != ixgbe_mac_X550EM_x))
 575                 return -ENOSYS;
 576
 577         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 578                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 579                      queue_id, stat_idx);
 580
 581         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 582         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 583                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 584                 return -EIO;
 585         }
 586         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 587
 588         /* Now clear any previous stat_idx set */
 589         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 590         if (!is_rx)
 591                 stat_mappings->tqsm[n] &= ~clearing_mask;
 592         else
 593                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 594
 595         q_map = (uint32_t)stat_idx;
 596         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 597         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 598         if (!is_rx)
 599                 stat_mappings->tqsm[n] |= qsmr_mask;
 600         else
 601                 stat_mappings->rqsmr[n] |= qsmr_mask;
 602
 603         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 604                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 605                      queue_id, stat_idx);
 606         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 607                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 608
 609         /* Now write the mapping in the appropriate register */
 610         if (is_rx) {
 611                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 612                              stat_mappings->rqsmr[n], n);
 613                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 614         }
 615         else {
 616                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 617                              stat_mappings->tqsm[n], n);
 618                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 619         }
 620         return 0;
 621 }
 622
 623 static void
 624 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 625 {
 626         struct ixgbe_stat_mapping_registers *stat_mappings =
 627                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 629         int i;
 630
 631         /* write whatever was in stat mapping table to the NIC */
 632         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 633                 /* rx */
 634                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 635
 636                 /* tx */
 637                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 638         }
 639 }
 640
 641 static void
 642 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 643 {
 644         uint8_t i;
 645         struct ixgbe_dcb_tc_config *tc;
 646         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 647
 648         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 649         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 650         for (i = 0; i < dcb_max_tc; i++) {
 651                 tc = &dcb_config->tc_config[i];
 652                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 653                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 654                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 655                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 656                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 657                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 658                 tc->pfc = ixgbe_dcb_pfc_disabled;
 659         }
 660
 661         /* Initialize default user to priority mapping, UPx->TC0 */
 662         tc = &dcb_config->tc_config[0];
 663         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 664         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 665         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 666                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 667                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 668         }
 669         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 670         dcb_config->pfc_mode_enable = false;
 671         dcb_config->vt_mode = true;
 672         dcb_config->round_robin_enable = false;
 673         /* support all DCB capabilities in 82599 */
 674         dcb_config->support.capabilities = 0xFF;
 675
 676         /*we only support 4 Tcs for X540, X550 */
 677         if (hw->mac.type == ixgbe_mac_X540 ||
 678                 hw->mac.type == ixgbe_mac_X550 ||
 679                 hw->mac.type == ixgbe_mac_X550EM_x) {
 680                 dcb_config->num_tcs.pg_tcs = 4;
 681                 dcb_config->num_tcs.pfc_tcs = 4;
 682         }
 683 }
 684
 685 /*
 686  * Ensure that all locks are released before first NVM or PHY access
 687  */
 688 static void
 689 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 690 {
 691         uint16_t mask;
 692
 693         /*
 694          * Phy lock should not fail in this early stage. If this is the case,
 695          * it is due to an improper exit of the application.
 696          * So force the release of the faulty lock. Release of common lock
 697          * is done automatically by swfw_sync function.
 698          */
 699         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 700         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 701                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 702         }
 703         ixgbe_release_swfw_semaphore(hw, mask);
 704
 705         /*
 706          * These ones are more tricky since they are common to all ports; but
 707          * swfw_sync retries last long enough (1s) to be almost sure that if
 708          * lock can not be taken it is due to an improper lock of the
 709          * semaphore.
 710          */
 711         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 712         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 713                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 714         }
 715         ixgbe_release_swfw_semaphore(hw, mask);
 716 }
 717
 718 /*
 719  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 720  * It returns 0 on success.
 721  */
 722 static int
 723 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 724                      struct rte_eth_dev *eth_dev)
 725 {
 726         struct rte_pci_device *pci_dev;
 727         struct ixgbe_hw *hw =
 728                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 729         struct ixgbe_vfta * shadow_vfta =
 730                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 731         struct ixgbe_hwstrip *hwstrip =
 732                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 733         struct ixgbe_dcb_config *dcb_config =
 734                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 735         uint32_t ctrl_ext;
 736         uint16_t csum;
 737         int diag, i;
 738
 739         PMD_INIT_FUNC_TRACE();
 740
 741         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 742         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 743         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 744
 745         /*
 746          * For secondary processes, we don't initialise any further as primary
 747          * has already done this work. Only check we don't need a different
 748          * RX and TX function.
 749          */
 750         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 751                 struct igb_tx_queue *txq;
 752                 /* TX queue function in primary, set by last queue initialized
 753                  * Tx queue may not initialized by primary process */
 754                 if (eth_dev->data->tx_queues) {
 755                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 756                         set_tx_function(eth_dev, txq);
 757                 } else {
 758                         /* Use default TX function if we get here */
 759                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 760                                            "Using default TX function.");
 761                 }
 762
 763                 if (eth_dev->data->scattered_rx)
 764                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 765                 return 0;
 766         }
 767         pci_dev = eth_dev->pci_dev;
 768
 769         /* Vendor and Device ID need to be set before init of shared code */
 770         hw->device_id = pci_dev->id.device_id;
 771         hw->vendor_id = pci_dev->id.vendor_id;
 772         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 773         hw->allow_unsupported_sfp = 1;
 774
 775         /* Initialize the shared code (base driver) */
 776 #ifdef RTE_NIC_BYPASS
 777         diag = ixgbe_bypass_init_shared_code(hw);
 778 #else
 779         diag = ixgbe_init_shared_code(hw);
 780 #endif /* RTE_NIC_BYPASS */
 781
 782         if (diag != IXGBE_SUCCESS) {
 783                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 784                 return -EIO;
 785         }
 786
 787         /* pick up the PCI bus settings for reporting later */
 788         ixgbe_get_bus_info(hw);
 789
 790         /* Unlock any pending hardware semaphore */
 791         ixgbe_swfw_lock_reset(hw);
 792
 793         /* Initialize DCB configuration*/
 794         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 795         ixgbe_dcb_init(hw,dcb_config);
 796         /* Get Hardware Flow Control setting */
 797         hw->fc.requested_mode = ixgbe_fc_full;
 798         hw->fc.current_mode = ixgbe_fc_full;
 799         hw->fc.pause_time = IXGBE_FC_PAUSE;
 800         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 801                 hw->fc.low_water[i] = IXGBE_FC_LO;
 802                 hw->fc.high_water[i] = IXGBE_FC_HI;
 803         }
 804         hw->fc.send_xon = 1;
 805
 806         /* Make sure we have a good EEPROM before we read from it */
 807         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 808         if (diag != IXGBE_SUCCESS) {
 809                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 810                 return -EIO;
 811         }
 812
 813 #ifdef RTE_NIC_BYPASS
 814         diag = ixgbe_bypass_init_hw(hw);
 815 #else
 816         diag = ixgbe_init_hw(hw);
 817 #endif /* RTE_NIC_BYPASS */
 818
 819         /*
 820          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 821          * is called too soon after the kernel driver unbinding/binding occurs.
 822          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 823          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 824          * also called. See ixgbe_identify_phy_82599(). The reason for the
 825          * failure is not known, and only occuts when virtualisation features
 826          * are disabled in the bios. A delay of 100ms  was found to be enough by
 827          * trial-and-error, and is doubled to be safe.
 828          */
 829         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 830                 rte_delay_ms(200);
 831                 diag = ixgbe_init_hw(hw);
 832         }
 833
 834         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 835                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 836                     "LOM.  Please be aware there may be issues associated "
 837                     "with your hardware.");
 838                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 839                     "please contact your Intel or hardware representative "
 840                     "who provided you with this hardware.");
 841         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 842                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 843         if (diag) {
 844                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 845                 return -EIO;
 846         }
 847
 848         /* disable interrupt */
 849         ixgbe_disable_intr(hw);
 850
 851         /* reset mappings for queue statistics hw counters*/
 852         ixgbe_reset_qstat_mappings(hw);
 853
 854         /* Allocate memory for storing MAC addresses */
 855         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 856                         hw->mac.num_rar_entries, 0);
 857         if (eth_dev->data->mac_addrs == NULL) {
 858                 PMD_INIT_LOG(ERR,
 859                         "Failed to allocate %u bytes needed to store "
 860                         "MAC addresses",
 861                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 862                 return -ENOMEM;
 863         }
 864         /* Copy the permanent MAC address */
 865         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 866                         &eth_dev->data->mac_addrs[0]);
 867
 868         /* Allocate memory for storing hash filter MAC addresses */
 869         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 870                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 871         if (eth_dev->data->hash_mac_addrs == NULL) {
 872                 PMD_INIT_LOG(ERR,
 873                         "Failed to allocate %d bytes needed to store MAC addresses",
 874                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 875                 return -ENOMEM;
 876         }
 877
 878         /* initialize the vfta */
 879         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 880
 881         /* initialize the hw strip bitmap*/
 882         memset(hwstrip, 0, sizeof(*hwstrip));
 883
 884         /* initialize PF if max_vfs not zero */
 885         ixgbe_pf_host_init(eth_dev);
 886
 887         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 888         /* let hardware know driver is loaded */
 889         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 890         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 891         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 892         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 893         IXGBE_WRITE_FLUSH(hw);
 894
 895         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 896                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 897                              (int) hw->mac.type, (int) hw->phy.type,
 898                              (int) hw->phy.sfp_type);
 899         else
 900                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 901                              (int) hw->mac.type, (int) hw->phy.type);
 902
 903         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 904                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 905                         pci_dev->id.device_id);
 906
 907         rte_intr_callback_register(&(pci_dev->intr_handle),
 908                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 909
 910         /* enable uio intr after callback register */
 911         rte_intr_enable(&(pci_dev->intr_handle));
 912
 913         /* enable support intr */
 914         ixgbe_enable_intr(eth_dev);
 915
 916         return 0;
 917 }
 918
 919
 920 /*
 921  * Negotiate mailbox API version with the PF.
 922  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 923  * Then we try to negotiate starting with the most recent one.
 924  * If all negotiation attempts fail, then we will proceed with
 925  * the default one (ixgbe_mbox_api_10).
 926  */
 927 static void
 928 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 929 {
 930         int32_t i;
 931
 932         /* start with highest supported, proceed down */
 933         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 934                 ixgbe_mbox_api_11,
 935                 ixgbe_mbox_api_10,
 936         };
 937
 938         for (i = 0;
 939                         i != RTE_DIM(sup_ver) &&
 940                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 941                         i++)
 942                 ;
 943 }
 944
 945 static void
 946 generate_random_mac_addr(struct ether_addr *mac_addr)
 947 {
 948         uint64_t random;
 949
 950         /* Set Organizationally Unique Identifier (OUI) prefix. */
 951         mac_addr->addr_bytes[0] = 0x00;
 952         mac_addr->addr_bytes[1] = 0x09;
 953         mac_addr->addr_bytes[2] = 0xC0;
 954         /* Force indication of locally assigned MAC address. */
 955         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 956         /* Generate the last 3 bytes of the MAC address with a random number. */
 957         random = rte_rand();
 958         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 959 }
 960
 961 /*
 962  * Virtual Function device init
 963  */
 964 static int
 965 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 966                      struct rte_eth_dev *eth_dev)
 967 {
 968         int diag;
 969         uint32_t tc, tcs;
 970         struct rte_pci_device *pci_dev;
 971         struct ixgbe_hw *hw =
 972                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 973         struct ixgbe_vfta * shadow_vfta =
 974                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 975         struct ixgbe_hwstrip *hwstrip =
 976                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 977         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 978
 979         PMD_INIT_FUNC_TRACE();
 980
 981         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 982         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 983         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 984
 985         /* for secondary processes, we don't initialise any further as primary
 986          * has already done this work. Only check we don't need a different
 987          * RX function */
 988         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 989                 if (eth_dev->data->scattered_rx)
 990                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 991                 return 0;
 992         }
 993
 994         pci_dev = eth_dev->pci_dev;
 995
 996         hw->device_id = pci_dev->id.device_id;
 997         hw->vendor_id = pci_dev->id.vendor_id;
 998         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 999
1000         /* initialize the vfta */
1001         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1002
1003         /* initialize the hw strip bitmap*/
1004         memset(hwstrip, 0, sizeof(*hwstrip));
1005
1006         /* Initialize the shared code (base driver) */
1007         diag = ixgbe_init_shared_code(hw);
1008         if (diag != IXGBE_SUCCESS) {
1009                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1010                 return -EIO;
1011         }
1012
1013         /* init_mailbox_params */
1014         hw->mbx.ops.init_params(hw);
1015
1016         /* Disable the interrupts for VF */
1017         ixgbevf_intr_disable(hw);
1018
1019         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1020         diag = hw->mac.ops.reset_hw(hw);
1021
1022         /*
1023          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1024          * the underlying PF driver has not assigned a MAC address to the VF.
1025          * In this case, assign a random MAC address.
1026          */
1027         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1028                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1029                 return (diag);
1030         }
1031
1032         /* negotiate mailbox API version to use with the PF. */
1033         ixgbevf_negotiate_api(hw);
1034
1035         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1036         ixgbevf_get_queues(hw, &tcs, &tc);
1037
1038         /* Allocate memory for storing MAC addresses */
1039         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1040                         hw->mac.num_rar_entries, 0);
1041         if (eth_dev->data->mac_addrs == NULL) {
1042                 PMD_INIT_LOG(ERR,
1043                         "Failed to allocate %u bytes needed to store "
1044                         "MAC addresses",
1045                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1046                 return -ENOMEM;
1047         }
1048
1049         /* Generate a random MAC address, if none was assigned by PF. */
1050         if (is_zero_ether_addr(perm_addr)) {
1051                 generate_random_mac_addr(perm_addr);
1052                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1053                 if (diag) {
1054                         rte_free(eth_dev->data->mac_addrs);
1055                         eth_dev->data->mac_addrs = NULL;
1056                         return diag;
1057                 }
1058                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1059                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1060                              "%02x:%02x:%02x:%02x:%02x:%02x",
1061                              perm_addr->addr_bytes[0],
1062                              perm_addr->addr_bytes[1],
1063                              perm_addr->addr_bytes[2],
1064                              perm_addr->addr_bytes[3],
1065                              perm_addr->addr_bytes[4],
1066                              perm_addr->addr_bytes[5]);
1067         }
1068
1069         /* Copy the permanent MAC address */
1070         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1071
1072         /* reset the hardware with the new settings */
1073         diag = hw->mac.ops.start_hw(hw);
1074         switch (diag) {
1075                 case  0:
1076                         break;
1077
1078                 default:
1079                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1080                         return (-EIO);
1081         }
1082
1083         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1084                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1085                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1086
1087         return 0;
1088 }
1089
1090 static struct eth_driver rte_ixgbe_pmd = {
1091         {
1092                 .name = "rte_ixgbe_pmd",
1093                 .id_table = pci_id_ixgbe_map,
1094                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1095         },
1096         .eth_dev_init = eth_ixgbe_dev_init,
1097         .dev_private_size = sizeof(struct ixgbe_adapter),
1098 };
1099
1100 /*
1101  * virtual function driver struct
1102  */
1103 static struct eth_driver rte_ixgbevf_pmd = {
1104         {
1105                 .name = "rte_ixgbevf_pmd",
1106                 .id_table = pci_id_ixgbevf_map,
1107                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1108         },
1109         .eth_dev_init = eth_ixgbevf_dev_init,
1110         .dev_private_size = sizeof(struct ixgbe_adapter),
1111 };
1112
1113 /*
1114  * Driver initialization routine.
1115  * Invoked once at EAL init time.
1116  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1117  */
1118 static int
1119 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1120 {
1121         PMD_INIT_FUNC_TRACE();
1122
1123         rte_eth_driver_register(&rte_ixgbe_pmd);
1124         return 0;
1125 }
1126
1127 /*
1128  * VF Driver initialization routine.
1129  * Invoked one at EAL init time.
1130  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1131  */
1132 static int
1133 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1134 {
1135         PMD_INIT_FUNC_TRACE();
1136
1137         rte_eth_driver_register(&rte_ixgbevf_pmd);
1138         return (0);
1139 }
1140
1141 static int
1142 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1143 {
1144         struct ixgbe_hw *hw =
1145                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1146         struct ixgbe_vfta * shadow_vfta =
1147                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1148         uint32_t vfta;
1149         uint32_t vid_idx;
1150         uint32_t vid_bit;
1151
1152         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1153         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1154         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1155         if (on)
1156                 vfta |= vid_bit;
1157         else
1158                 vfta &= ~vid_bit;
1159         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1160
1161         /* update local VFTA copy */
1162         shadow_vfta->vfta[vid_idx] = vfta;
1163
1164         return 0;
1165 }
1166
1167 static void
1168 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1169 {
1170         if (on)
1171                 ixgbe_vlan_hw_strip_enable(dev, queue);
1172         else
1173                 ixgbe_vlan_hw_strip_disable(dev, queue);
1174 }
1175
1176 static void
1177 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1178 {
1179         struct ixgbe_hw *hw =
1180                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181
1182         /* Only the high 16-bits is valid */
1183         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1184 }
1185
1186 void
1187 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1188 {
1189         struct ixgbe_hw *hw =
1190                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191         uint32_t vlnctrl;
1192
1193         PMD_INIT_FUNC_TRACE();
1194
1195         /* Filter Table Disable */
1196         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1197         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1198
1199         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1200 }
1201
1202 void
1203 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1204 {
1205         struct ixgbe_hw *hw =
1206                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207         struct ixgbe_vfta * shadow_vfta =
1208                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1209         uint32_t vlnctrl;
1210         uint16_t i;
1211
1212         PMD_INIT_FUNC_TRACE();
1213
1214         /* Filter Table Enable */
1215         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1216         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1217         vlnctrl |= IXGBE_VLNCTRL_VFE;
1218
1219         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1220
1221         /* write whatever is in local vfta copy */
1222         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1223                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1224 }
1225
1226 static void
1227 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1228 {
1229         struct ixgbe_hwstrip *hwstrip =
1230                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1231
1232         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1233                 return;
1234
1235         if (on)
1236                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1237         else
1238                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1239 }
1240
1241 static void
1242 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1243 {
1244         struct ixgbe_hw *hw =
1245                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246         uint32_t ctrl;
1247
1248         PMD_INIT_FUNC_TRACE();
1249
1250         if (hw->mac.type == ixgbe_mac_82598EB) {
1251                 /* No queue level support */
1252                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1253                 return;
1254         }
1255         else {
1256                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1257                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1258                 ctrl &= ~IXGBE_RXDCTL_VME;
1259                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1260         }
1261         /* record those setting for HW strip per queue */
1262         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1263 }
1264
1265 static void
1266 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1267 {
1268         struct ixgbe_hw *hw =
1269                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1270         uint32_t ctrl;
1271
1272         PMD_INIT_FUNC_TRACE();
1273
1274         if (hw->mac.type == ixgbe_mac_82598EB) {
1275                 /* No queue level supported */
1276                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1277                 return;
1278         }
1279         else {
1280                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1281                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1282                 ctrl |= IXGBE_RXDCTL_VME;
1283                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1284         }
1285         /* record those setting for HW strip per queue */
1286         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1287 }
1288
1289 void
1290 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1291 {
1292         struct ixgbe_hw *hw =
1293                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1294         uint32_t ctrl;
1295         uint16_t i;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (hw->mac.type == ixgbe_mac_82598EB) {
1300                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1301                 ctrl &= ~IXGBE_VLNCTRL_VME;
1302                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1303         }
1304         else {
1305                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1306                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1307                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1308                         ctrl &= ~IXGBE_RXDCTL_VME;
1309                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1310
1311                         /* record those setting for HW strip per queue */
1312                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1313                 }
1314         }
1315 }
1316
1317 void
1318 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1319 {
1320         struct ixgbe_hw *hw =
1321                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1322         uint32_t ctrl;
1323         uint16_t i;
1324
1325         PMD_INIT_FUNC_TRACE();
1326
1327         if (hw->mac.type == ixgbe_mac_82598EB) {
1328                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1329                 ctrl |= IXGBE_VLNCTRL_VME;
1330                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1331         }
1332         else {
1333                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1334                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1335                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1336                         ctrl |= IXGBE_RXDCTL_VME;
1337                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1338
1339                         /* record those setting for HW strip per queue */
1340                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1341                 }
1342         }
1343 }
1344
1345 static void
1346 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1347 {
1348         struct ixgbe_hw *hw =
1349                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1350         uint32_t ctrl;
1351
1352         PMD_INIT_FUNC_TRACE();
1353
1354         /* DMATXCTRL: Geric Double VLAN Disable */
1355         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1356         ctrl &= ~IXGBE_DMATXCTL_GDV;
1357         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1358
1359         /* CTRL_EXT: Global Double VLAN Disable */
1360         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1361         ctrl &= ~IXGBE_EXTENDED_VLAN;
1362         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1363
1364 }
1365
1366 static void
1367 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1368 {
1369         struct ixgbe_hw *hw =
1370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1371         uint32_t ctrl;
1372
1373         PMD_INIT_FUNC_TRACE();
1374
1375         /* DMATXCTRL: Geric Double VLAN Enable */
1376         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1377         ctrl |= IXGBE_DMATXCTL_GDV;
1378         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1379
1380         /* CTRL_EXT: Global Double VLAN Enable */
1381         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1382         ctrl |= IXGBE_EXTENDED_VLAN;
1383         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1384
1385         /*
1386          * VET EXT field in the EXVET register = 0x8100 by default
1387          * So no need to change. Same to VT field of DMATXCTL register
1388          */
1389 }
1390
1391 static void
1392 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1393 {
1394         if(mask & ETH_VLAN_STRIP_MASK){
1395                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1396                         ixgbe_vlan_hw_strip_enable_all(dev);
1397                 else
1398                         ixgbe_vlan_hw_strip_disable_all(dev);
1399         }
1400
1401         if(mask & ETH_VLAN_FILTER_MASK){
1402                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1403                         ixgbe_vlan_hw_filter_enable(dev);
1404                 else
1405                         ixgbe_vlan_hw_filter_disable(dev);
1406         }
1407
1408         if(mask & ETH_VLAN_EXTEND_MASK){
1409                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1410                         ixgbe_vlan_hw_extend_enable(dev);
1411                 else
1412                         ixgbe_vlan_hw_extend_disable(dev);
1413         }
1414 }
1415
1416 static void
1417 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1418 {
1419         struct ixgbe_hw *hw =
1420                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1422         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1423         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1424         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1425 }
1426
1427 static int
1428 ixgbe_dev_configure(struct rte_eth_dev *dev)
1429 {
1430         struct ixgbe_interrupt *intr =
1431                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1432
1433         PMD_INIT_FUNC_TRACE();
1434
1435         /* set flag to update link status after init */
1436         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1437
1438         return 0;
1439 }
1440
1441 /*
1442  * Configure device link speed and setup link.
1443  * It returns 0 on success.
1444  */
1445 static int
1446 ixgbe_dev_start(struct rte_eth_dev *dev)
1447 {
1448         struct ixgbe_hw *hw =
1449                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1450         struct ixgbe_vf_info *vfinfo =
1451                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1452         int err, link_up = 0, negotiate = 0;
1453         uint32_t speed = 0;
1454         int mask = 0;
1455         int status;
1456         uint16_t vf, idx;
1457
1458         PMD_INIT_FUNC_TRACE();
1459
1460         /* IXGBE devices don't support half duplex */
1461         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1462                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1463                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1464                              dev->data->dev_conf.link_duplex,
1465                              dev->data->port_id);
1466                 return -EINVAL;
1467         }
1468
1469         /* stop adapter */
1470         hw->adapter_stopped = FALSE;
1471         ixgbe_stop_adapter(hw);
1472
1473         /* reinitialize adapter
1474          * this calls reset and start */
1475         status = ixgbe_pf_reset_hw(hw);
1476         if (status != 0)
1477                 return -1;
1478         hw->mac.ops.start_hw(hw);
1479
1480         /* configure PF module if SRIOV enabled */
1481         ixgbe_pf_host_configure(dev);
1482
1483         /* initialize transmission unit */
1484         ixgbe_dev_tx_init(dev);
1485
1486         /* This can fail when allocating mbufs for descriptor rings */
1487         err = ixgbe_dev_rx_init(dev);
1488         if (err) {
1489                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1490                 goto error;
1491         }
1492
1493         ixgbe_dev_rxtx_start(dev);
1494
1495         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1496                 err = hw->mac.ops.setup_sfp(hw);
1497                 if (err)
1498                         goto error;
1499         }
1500
1501         /* Turn on the laser */
1502         ixgbe_enable_tx_laser(hw);
1503
1504         /* Skip link setup if loopback mode is enabled for 82599. */
1505         if (hw->mac.type == ixgbe_mac_82599EB &&
1506                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1507                 goto skip_link_setup;
1508
1509         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1510         if (err)
1511                 goto error;
1512         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1513         if (err)
1514                 goto error;
1515
1516         switch(dev->data->dev_conf.link_speed) {
1517         case ETH_LINK_SPEED_AUTONEG:
1518                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1519                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1520                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1521                 break;
1522         case ETH_LINK_SPEED_100:
1523                 /*
1524                  * Invalid for 82598 but error will be detected by
1525                  * ixgbe_setup_link()
1526                  */
1527                 speed = IXGBE_LINK_SPEED_100_FULL;
1528                 break;
1529         case ETH_LINK_SPEED_1000:
1530                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1531                 break;
1532         case ETH_LINK_SPEED_10000:
1533                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1534                 break;
1535         default:
1536                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1537                              dev->data->dev_conf.link_speed,
1538                              dev->data->port_id);
1539                 goto error;
1540         }
1541
1542         err = ixgbe_setup_link(hw, speed, link_up);
1543         if (err)
1544                 goto error;
1545
1546 skip_link_setup:
1547
1548         /* check if lsc interrupt is enabled */
1549         if (dev->data->dev_conf.intr_conf.lsc != 0)
1550                 ixgbe_dev_lsc_interrupt_setup(dev);
1551
1552         /* resume enabled intr since hw reset */
1553         ixgbe_enable_intr(dev);
1554
1555         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1556                 ETH_VLAN_EXTEND_MASK;
1557         ixgbe_vlan_offload_set(dev, mask);
1558
1559         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1560                 /* Enable vlan filtering for VMDq */
1561                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1562         }
1563
1564         /* Configure DCB hw */
1565         ixgbe_configure_dcb(dev);
1566
1567         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1568                 err = ixgbe_fdir_configure(dev);
1569                 if (err)
1570                         goto error;
1571         }
1572
1573         /* Restore vf rate limit */
1574         if (vfinfo != NULL) {
1575                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1576                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1577                                 if (vfinfo[vf].tx_rate[idx] != 0)
1578                                         ixgbe_set_vf_rate_limit(dev, vf,
1579                                                 vfinfo[vf].tx_rate[idx],
1580                                                 1 << idx);
1581         }
1582
1583         ixgbe_restore_statistics_mapping(dev);
1584
1585         return (0);
1586
1587 error:
1588         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1589         ixgbe_dev_clear_queues(dev);
1590         return -EIO;
1591 }
1592
1593 /*
1594  * Stop device: disable rx and tx functions to allow for reconfiguring.
1595  */
1596 static void
1597 ixgbe_dev_stop(struct rte_eth_dev *dev)
1598 {
1599         struct rte_eth_link link;
1600         struct ixgbe_hw *hw =
1601                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1602         struct ixgbe_vf_info *vfinfo =
1603                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1604         int vf;
1605
1606         PMD_INIT_FUNC_TRACE();
1607
1608         /* disable interrupts */
1609         ixgbe_disable_intr(hw);
1610
1611         /* reset the NIC */
1612         ixgbe_pf_reset_hw(hw);
1613         hw->adapter_stopped = FALSE;
1614
1615         /* stop adapter */
1616         ixgbe_stop_adapter(hw);
1617
1618         for (vf = 0; vfinfo != NULL &&
1619                      vf < dev->pci_dev->max_vfs; vf++)
1620                 vfinfo[vf].clear_to_send = false;
1621
1622         /* Turn off the laser */
1623         ixgbe_disable_tx_laser(hw);
1624
1625         ixgbe_dev_clear_queues(dev);
1626
1627         /* Clear stored conf */
1628         dev->data->scattered_rx = 0;
1629
1630         /* Clear recorded link status */
1631         memset(&link, 0, sizeof(link));
1632         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1633 }
1634
1635 /*
1636  * Set device link up: enable tx laser.
1637  */
1638 static int
1639 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1640 {
1641         struct ixgbe_hw *hw =
1642                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1643         if (hw->mac.type == ixgbe_mac_82599EB) {
1644 #ifdef RTE_NIC_BYPASS
1645                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1646                         /* Not suported in bypass mode */
1647                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1648                                      "by device id 0x%x", hw->device_id);
1649                         return -ENOTSUP;
1650                 }
1651 #endif
1652                 /* Turn on the laser */
1653                 ixgbe_enable_tx_laser(hw);
1654                 return 0;
1655         }
1656
1657         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1658                      hw->device_id);
1659         return -ENOTSUP;
1660 }
1661
1662 /*
1663  * Set device link down: disable tx laser.
1664  */
1665 static int
1666 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1667 {
1668         struct ixgbe_hw *hw =
1669                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670         if (hw->mac.type == ixgbe_mac_82599EB) {
1671 #ifdef RTE_NIC_BYPASS
1672                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1673                         /* Not suported in bypass mode */
1674                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1675                                      "by device id 0x%x", hw->device_id);
1676                         return -ENOTSUP;
1677                 }
1678 #endif
1679                 /* Turn off the laser */
1680                 ixgbe_disable_tx_laser(hw);
1681                 return 0;
1682         }
1683
1684         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1685                      hw->device_id);
1686         return -ENOTSUP;
1687 }
1688
1689 /*
1690  * Reest and stop device.
1691  */
1692 static void
1693 ixgbe_dev_close(struct rte_eth_dev *dev)
1694 {
1695         struct ixgbe_hw *hw =
1696                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697
1698         PMD_INIT_FUNC_TRACE();
1699
1700         ixgbe_pf_reset_hw(hw);
1701
1702         ixgbe_dev_stop(dev);
1703         hw->adapter_stopped = 1;
1704
1705         ixgbe_disable_pcie_master(hw);
1706
1707         /* reprogram the RAR[0] in case user changed it. */
1708         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1709 }
1710
1711 /*
1712  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1713  */
1714 static void
1715 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1716 {
1717         struct ixgbe_hw *hw =
1718                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719         struct ixgbe_hw_stats *hw_stats =
1720                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1721         uint32_t bprc, lxon, lxoff, total;
1722         uint64_t total_missed_rx, total_qbrc, total_qprc;
1723         unsigned i;
1724
1725         total_missed_rx = 0;
1726         total_qbrc = 0;
1727         total_qprc = 0;
1728
1729         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1730         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1731         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1732         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1733
1734         for (i = 0; i < 8; i++) {
1735                 uint32_t mp;
1736                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1737                 /* global total per queue */
1738                 hw_stats->mpc[i] += mp;
1739                 /* Running comprehensive total for stats display */
1740                 total_missed_rx += hw_stats->mpc[i];
1741                 if (hw->mac.type == ixgbe_mac_82598EB)
1742                         hw_stats->rnbc[i] +=
1743                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1744                 hw_stats->pxontxc[i] +=
1745                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1746                 hw_stats->pxonrxc[i] +=
1747                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1748                 hw_stats->pxofftxc[i] +=
1749                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1750                 hw_stats->pxoffrxc[i] +=
1751                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1752                 hw_stats->pxon2offc[i] +=
1753                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1754         }
1755         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1756                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1757                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1758                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1759                 hw_stats->qbrc[i] +=
1760                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1761                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1762                 hw_stats->qbtc[i] +=
1763                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1764                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1765
1766                 total_qprc += hw_stats->qprc[i];
1767                 total_qbrc += hw_stats->qbrc[i];
1768         }
1769         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1770         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1771         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1772
1773         /* Note that gprc counts missed packets */
1774         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1775
1776         if (hw->mac.type != ixgbe_mac_82598EB) {
1777                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1778                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1779                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1780                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1781                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1782                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1783                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1784                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1785         } else {
1786                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1787                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1788                 /* 82598 only has a counter in the high register */
1789                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1790                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1791                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1792         }
1793
1794         /*
1795          * Workaround: mprc hardware is incorrectly counting
1796          * broadcasts, so for now we subtract those.
1797          */
1798         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1799         hw_stats->bprc += bprc;
1800         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1801         if (hw->mac.type == ixgbe_mac_82598EB)
1802                 hw_stats->mprc -= bprc;
1803
1804         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1805         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1806         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1807         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1808         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1809         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1810
1811         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1812         hw_stats->lxontxc += lxon;
1813         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1814         hw_stats->lxofftxc += lxoff;
1815         total = lxon + lxoff;
1816
1817         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1818         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1819         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1820         hw_stats->gptc -= total;
1821         hw_stats->mptc -= total;
1822         hw_stats->ptc64 -= total;
1823         hw_stats->gotc -= total * ETHER_MIN_LEN;
1824
1825         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1826         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1827         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1828         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1829         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1830         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1831         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1832         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1833         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1834         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1835         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1836         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1837         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1838         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1839         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1840         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1841         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1842         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1843         /* Only read FCOE on 82599 */
1844         if (hw->mac.type != ixgbe_mac_82598EB) {
1845                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1846                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1847                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1848                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1849                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1850         }
1851
1852         if (stats == NULL)
1853                 return;
1854
1855         /* Fill out the rte_eth_stats statistics structure */
1856         stats->ipackets = total_qprc;
1857         stats->ibytes = total_qbrc;
1858         stats->opackets = hw_stats->gptc;
1859         stats->obytes = hw_stats->gotc;
1860         stats->imcasts = hw_stats->mprc;
1861
1862         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1863                 stats->q_ipackets[i] = hw_stats->qprc[i];
1864                 stats->q_opackets[i] = hw_stats->qptc[i];
1865                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1866                 stats->q_obytes[i] = hw_stats->qbtc[i];
1867                 stats->q_errors[i] = hw_stats->qprdc[i];
1868         }
1869
1870         /* Rx Errors */
1871         stats->ibadcrc  = hw_stats->crcerrs;
1872         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1873         stats->imissed  = total_missed_rx;
1874         stats->ierrors  = stats->ibadcrc +
1875                           stats->ibadlen +
1876                           stats->imissed +
1877                           hw_stats->illerrc + hw_stats->errbc;
1878
1879         /* Tx Errors */
1880         stats->oerrors  = 0;
1881
1882         /* XON/XOFF pause frames */
1883         stats->tx_pause_xon  = hw_stats->lxontxc;
1884         stats->rx_pause_xon  = hw_stats->lxonrxc;
1885         stats->tx_pause_xoff = hw_stats->lxofftxc;
1886         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1887
1888         /* Flow Director Stats registers */
1889         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1890         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1891         stats->fdirmatch = hw_stats->fdirmatch;
1892         stats->fdirmiss = hw_stats->fdirmiss;
1893 }
1894
1895 static void
1896 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1897 {
1898         struct ixgbe_hw_stats *stats =
1899                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1900
1901         /* HW registers are cleared on read */
1902         ixgbe_dev_stats_get(dev, NULL);
1903
1904         /* Reset software totals */
1905         memset(stats, 0, sizeof(*stats));
1906 }
1907
1908 static void
1909 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1910 {
1911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1913                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1914
1915         /* Good Rx packet, include VF loopback */
1916         UPDATE_VF_STAT(IXGBE_VFGPRC,
1917             hw_stats->last_vfgprc, hw_stats->vfgprc);
1918
1919         /* Good Rx octets, include VF loopback */
1920         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1921             hw_stats->last_vfgorc, hw_stats->vfgorc);
1922
1923         /* Good Tx packet, include VF loopback */
1924         UPDATE_VF_STAT(IXGBE_VFGPTC,
1925             hw_stats->last_vfgptc, hw_stats->vfgptc);
1926
1927         /* Good Tx octets, include VF loopback */
1928         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1929             hw_stats->last_vfgotc, hw_stats->vfgotc);
1930
1931         /* Rx Multicst Packet */
1932         UPDATE_VF_STAT(IXGBE_VFMPRC,
1933             hw_stats->last_vfmprc, hw_stats->vfmprc);
1934
1935         if (stats == NULL)
1936                 return;
1937
1938         memset(stats, 0, sizeof(*stats));
1939         stats->ipackets = hw_stats->vfgprc;
1940         stats->ibytes = hw_stats->vfgorc;
1941         stats->opackets = hw_stats->vfgptc;
1942         stats->obytes = hw_stats->vfgotc;
1943         stats->imcasts = hw_stats->vfmprc;
1944 }
1945
1946 static void
1947 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1948 {
1949         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1950                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1951
1952         /* Sync HW register to the last stats */
1953         ixgbevf_dev_stats_get(dev, NULL);
1954
1955         /* reset HW current stats*/
1956         hw_stats->vfgprc = 0;
1957         hw_stats->vfgorc = 0;
1958         hw_stats->vfgptc = 0;
1959         hw_stats->vfgotc = 0;
1960         hw_stats->vfmprc = 0;
1961
1962 }
1963
1964 static void
1965 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1966 {
1967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1968
1969         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1970         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1971         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1972         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1973         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1974         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1975         dev_info->max_vfs = dev->pci_dev->max_vfs;
1976         if (hw->mac.type == ixgbe_mac_82598EB)
1977                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1978         else
1979                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1980         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1981         dev_info->rx_offload_capa =
1982                 DEV_RX_OFFLOAD_VLAN_STRIP |
1983                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1984                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1985                 DEV_RX_OFFLOAD_TCP_CKSUM;
1986         dev_info->tx_offload_capa =
1987                 DEV_TX_OFFLOAD_VLAN_INSERT |
1988                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1989                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1990                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1991                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1992                 DEV_TX_OFFLOAD_TCP_TSO;
1993
1994         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1995                 .rx_thresh = {
1996                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
1997                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
1998                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
1999                 },
2000                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2001                 .rx_drop_en = 0,
2002         };
2003
2004         dev_info->default_txconf = (struct rte_eth_txconf) {
2005                 .tx_thresh = {
2006                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2007                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2008                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2009                 },
2010                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2011                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2012                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2013                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2014         };
2015         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2016 }
2017
2018 static void
2019 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2020                      struct rte_eth_dev_info *dev_info)
2021 {
2022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023
2024         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2025         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2026         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2027         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2028         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2029         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2030         dev_info->max_vfs = dev->pci_dev->max_vfs;
2031         if (hw->mac.type == ixgbe_mac_82598EB)
2032                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2033         else
2034                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2035         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2036                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2037                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2038                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2039         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2040                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2041                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2042                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2043                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2044
2045         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2046                 .rx_thresh = {
2047                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2048                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2049                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2050                 },
2051                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2052                 .rx_drop_en = 0,
2053         };
2054
2055         dev_info->default_txconf = (struct rte_eth_txconf) {
2056                 .tx_thresh = {
2057                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2058                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2059                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2060                 },
2061                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2062                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2063                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2064                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2065         };
2066 }
2067
2068 /* return 0 means link status changed, -1 means not changed */
2069 static int
2070 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2071 {
2072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073         struct rte_eth_link link, old;
2074         ixgbe_link_speed link_speed;
2075         int link_up;
2076         int diag;
2077
2078         link.link_status = 0;
2079         link.link_speed = 0;
2080         link.link_duplex = 0;
2081         memset(&old, 0, sizeof(old));
2082         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2083
2084         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2085         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2086                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2087         else
2088                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2089         if (diag != 0) {
2090                 link.link_speed = ETH_LINK_SPEED_100;
2091                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2092                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2093                 if (link.link_status == old.link_status)
2094                         return -1;
2095                 return 0;
2096         }
2097
2098         if (link_up == 0) {
2099                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2100                 if (link.link_status == old.link_status)
2101                         return -1;
2102                 return 0;
2103         }
2104         link.link_status = 1;
2105         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2106
2107         switch (link_speed) {
2108         default:
2109         case IXGBE_LINK_SPEED_UNKNOWN:
2110                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2111                 link.link_speed = ETH_LINK_SPEED_100;
2112                 break;
2113
2114         case IXGBE_LINK_SPEED_100_FULL:
2115                 link.link_speed = ETH_LINK_SPEED_100;
2116                 break;
2117
2118         case IXGBE_LINK_SPEED_1GB_FULL:
2119                 link.link_speed = ETH_LINK_SPEED_1000;
2120                 break;
2121
2122         case IXGBE_LINK_SPEED_10GB_FULL:
2123                 link.link_speed = ETH_LINK_SPEED_10000;
2124                 break;
2125         }
2126         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2127
2128         if (link.link_status == old.link_status)
2129                 return -1;
2130
2131         return 0;
2132 }
2133
2134 static void
2135 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2136 {
2137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2138         uint32_t fctrl;
2139
2140         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2141         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2142         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2143 }
2144
2145 static void
2146 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2147 {
2148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149         uint32_t fctrl;
2150
2151         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2152         fctrl &= (~IXGBE_FCTRL_UPE);
2153         if (dev->data->all_multicast == 1)
2154                 fctrl |= IXGBE_FCTRL_MPE;
2155         else
2156                 fctrl &= (~IXGBE_FCTRL_MPE);
2157         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2158 }
2159
2160 static void
2161 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2162 {
2163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164         uint32_t fctrl;
2165
2166         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2167         fctrl |= IXGBE_FCTRL_MPE;
2168         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2169 }
2170
2171 static void
2172 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2173 {
2174         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175         uint32_t fctrl;
2176
2177         if (dev->data->promiscuous == 1)
2178                 return; /* must remain in all_multicast mode */
2179
2180         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2181         fctrl &= (~IXGBE_FCTRL_MPE);
2182         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2183 }
2184
2185 /**
2186  * It clears the interrupt causes and enables the interrupt.
2187  * It will be called once only during nic initialized.
2188  *
2189  * @param dev
2190  *  Pointer to struct rte_eth_dev.
2191  *
2192  * @return
2193  *  - On success, zero.
2194  *  - On failure, a negative value.
2195  */
2196 static int
2197 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2198 {
2199         struct ixgbe_interrupt *intr =
2200                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2201
2202         ixgbe_dev_link_status_print(dev);
2203         intr->mask |= IXGBE_EICR_LSC;
2204
2205         return 0;
2206 }
2207
2208 /*
2209  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2210  *
2211  * @param dev
2212  *  Pointer to struct rte_eth_dev.
2213  *
2214  * @return
2215  *  - On success, zero.
2216  *  - On failure, a negative value.
2217  */
2218 static int
2219 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2220 {
2221         uint32_t eicr;
2222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2223         struct ixgbe_interrupt *intr =
2224                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2225
2226         /* clear all cause mask */
2227         ixgbe_disable_intr(hw);
2228
2229         /* read-on-clear nic registers here */
2230         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2231         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2232
2233         intr->flags = 0;
2234         if (eicr & IXGBE_EICR_LSC) {
2235                 /* set flag for async link update */
2236                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2237         }
2238
2239         if (eicr & IXGBE_EICR_MAILBOX)
2240                 intr->flags |= IXGBE_FLAG_MAILBOX;
2241
2242         return 0;
2243 }
2244
2245 /**
2246  * It gets and then prints the link status.
2247  *
2248  * @param dev
2249  *  Pointer to struct rte_eth_dev.
2250  *
2251  * @return
2252  *  - On success, zero.
2253  *  - On failure, a negative value.
2254  */
2255 static void
2256 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2257 {
2258         struct rte_eth_link link;
2259
2260         memset(&link, 0, sizeof(link));
2261         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2262         if (link.link_status) {
2263                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2264                                         (int)(dev->data->port_id),
2265                                         (unsigned)link.link_speed,
2266                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2267                                         "full-duplex" : "half-duplex");
2268         } else {
2269                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2270                                 (int)(dev->data->port_id));
2271         }
2272         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2273                                 dev->pci_dev->addr.domain,
2274                                 dev->pci_dev->addr.bus,
2275                                 dev->pci_dev->addr.devid,
2276                                 dev->pci_dev->addr.function);
2277 }
2278
2279 /*
2280  * It executes link_update after knowing an interrupt occurred.
2281  *
2282  * @param dev
2283  *  Pointer to struct rte_eth_dev.
2284  *
2285  * @return
2286  *  - On success, zero.
2287  *  - On failure, a negative value.
2288  */
2289 static int
2290 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2291 {
2292         struct ixgbe_interrupt *intr =
2293                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2294         int64_t timeout;
2295         struct rte_eth_link link;
2296         int intr_enable_delay = false;
2297
2298         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2299
2300         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2301                 ixgbe_pf_mbx_process(dev);
2302                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2303         }
2304
2305         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2306                 /* get the link status before link update, for predicting later */
2307                 memset(&link, 0, sizeof(link));
2308                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2309
2310                 ixgbe_dev_link_update(dev, 0);
2311
2312                 /* likely to up */
2313                 if (!link.link_status)
2314                         /* handle it 1 sec later, wait it being stable */
2315                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2316                 /* likely to down */
2317                 else
2318                         /* handle it 4 sec later, wait it being stable */
2319                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2320
2321                 ixgbe_dev_link_status_print(dev);
2322
2323                 intr_enable_delay = true;
2324         }
2325
2326         if (intr_enable_delay) {
2327                 if (rte_eal_alarm_set(timeout * 1000,
2328                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2329                         PMD_DRV_LOG(ERR, "Error setting alarm");
2330         } else {
2331                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2332                 ixgbe_enable_intr(dev);
2333                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2334         }
2335
2336
2337         return 0;
2338 }
2339
2340 /**
2341  * Interrupt handler which shall be registered for alarm callback for delayed
2342  * handling specific interrupt to wait for the stable nic state. As the
2343  * NIC interrupt state is not stable for ixgbe after link is just down,
2344  * it needs to wait 4 seconds to get the stable status.
2345  *
2346  * @param handle
2347  *  Pointer to interrupt handle.
2348  * @param param
2349  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2350  *
2351  * @return
2352  *  void
2353  */
2354 static void
2355 ixgbe_dev_interrupt_delayed_handler(void *param)
2356 {
2357         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2358         struct ixgbe_interrupt *intr =
2359                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2360         struct ixgbe_hw *hw =
2361                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2362         uint32_t eicr;
2363
2364         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2365         if (eicr & IXGBE_EICR_MAILBOX)
2366                 ixgbe_pf_mbx_process(dev);
2367
2368         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2369                 ixgbe_dev_link_update(dev, 0);
2370                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2371                 ixgbe_dev_link_status_print(dev);
2372                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2373         }
2374
2375         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2376         ixgbe_enable_intr(dev);
2377         rte_intr_enable(&(dev->pci_dev->intr_handle));
2378 }
2379
2380 /**
2381  * Interrupt handler triggered by NIC  for handling
2382  * specific interrupt.
2383  *
2384  * @param handle
2385  *  Pointer to interrupt handle.
2386  * @param param
2387  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2388  *
2389  * @return
2390  *  void
2391  */
2392 static void
2393 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2394                                                         void *param)
2395 {
2396         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2397         ixgbe_dev_interrupt_get_status(dev);
2398         ixgbe_dev_interrupt_action(dev);
2399 }
2400
2401 static int
2402 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2403 {
2404         struct ixgbe_hw *hw;
2405
2406         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2408 }
2409
2410 static int
2411 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2412 {
2413         struct ixgbe_hw *hw;
2414
2415         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2416         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2417 }
2418
2419 static int
2420 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2421 {
2422         struct ixgbe_hw *hw;
2423         uint32_t mflcn_reg;
2424         uint32_t fccfg_reg;
2425         int rx_pause;
2426         int tx_pause;
2427
2428         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2429
2430         fc_conf->pause_time = hw->fc.pause_time;
2431         fc_conf->high_water = hw->fc.high_water[0];
2432         fc_conf->low_water = hw->fc.low_water[0];
2433         fc_conf->send_xon = hw->fc.send_xon;
2434         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2435
2436         /*
2437          * Return rx_pause status according to actual setting of
2438          * MFLCN register.
2439          */
2440         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2441         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2442                 rx_pause = 1;
2443         else
2444                 rx_pause = 0;
2445
2446         /*
2447          * Return tx_pause status according to actual setting of
2448          * FCCFG register.
2449          */
2450         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2451         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2452                 tx_pause = 1;
2453         else
2454                 tx_pause = 0;
2455
2456         if (rx_pause && tx_pause)
2457                 fc_conf->mode = RTE_FC_FULL;
2458         else if (rx_pause)
2459                 fc_conf->mode = RTE_FC_RX_PAUSE;
2460         else if (tx_pause)
2461                 fc_conf->mode = RTE_FC_TX_PAUSE;
2462         else
2463                 fc_conf->mode = RTE_FC_NONE;
2464
2465         return 0;
2466 }
2467
2468 static int
2469 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2470 {
2471         struct ixgbe_hw *hw;
2472         int err;
2473         uint32_t rx_buf_size;
2474         uint32_t max_high_water;
2475         uint32_t mflcn;
2476         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2477                 ixgbe_fc_none,
2478                 ixgbe_fc_rx_pause,
2479                 ixgbe_fc_tx_pause,
2480                 ixgbe_fc_full
2481         };
2482
2483         PMD_INIT_FUNC_TRACE();
2484
2485         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2487                 return -ENOTSUP;
2488         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2489         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2490
2491         /*
2492          * At least reserve one Ethernet frame for watermark
2493          * high_water/low_water in kilo bytes for ixgbe
2494          */
2495         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2496         if ((fc_conf->high_water > max_high_water) ||
2497                 (fc_conf->high_water < fc_conf->low_water)) {
2498                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2499                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2500                 return (-EINVAL);
2501         }
2502
2503         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2504         hw->fc.pause_time     = fc_conf->pause_time;
2505         hw->fc.high_water[0]  = fc_conf->high_water;
2506         hw->fc.low_water[0]   = fc_conf->low_water;
2507         hw->fc.send_xon       = fc_conf->send_xon;
2508
2509         err = ixgbe_fc_enable(hw);
2510
2511         /* Not negotiated is not an error case */
2512         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2513
2514                 /* check if we want to forward MAC frames - driver doesn't have native
2515                  * capability to do that, so we'll write the registers ourselves */
2516
2517                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2518
2519                 /* set or clear MFLCN.PMCF bit depending on configuration */
2520                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2521                         mflcn |= IXGBE_MFLCN_PMCF;
2522                 else
2523                         mflcn &= ~IXGBE_MFLCN_PMCF;
2524
2525                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2526                 IXGBE_WRITE_FLUSH(hw);
2527
2528                 return 0;
2529         }
2530
2531         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2532         return -EIO;
2533 }
2534
2535 /**
2536  *  ixgbe_pfc_enable_generic - Enable flow control
2537  *  @hw: pointer to hardware structure
2538  *  @tc_num: traffic class number
2539  *  Enable flow control according to the current settings.
2540  */
2541 static int
2542 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2543 {
2544         int ret_val = 0;
2545         uint32_t mflcn_reg, fccfg_reg;
2546         uint32_t reg;
2547         uint32_t fcrtl, fcrth;
2548         uint8_t i;
2549         uint8_t nb_rx_en;
2550
2551         /* Validate the water mark configuration */
2552         if (!hw->fc.pause_time) {
2553                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2554                 goto out;
2555         }
2556
2557         /* Low water mark of zero causes XOFF floods */
2558         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2559                  /* High/Low water can not be 0 */
2560                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2561                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2562                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2563                         goto out;
2564                 }
2565
2566                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2567                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2568                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2569                         goto out;
2570                 }
2571         }
2572         /* Negotiate the fc mode to use */
2573         ixgbe_fc_autoneg(hw);
2574
2575         /* Disable any previous flow control settings */
2576         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2577         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2578
2579         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2580         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2581
2582         switch (hw->fc.current_mode) {
2583         case ixgbe_fc_none:
2584                 /*
2585                  * If the count of enabled RX Priority Flow control >1,
2586                  * and the TX pause can not be disabled
2587                  */
2588                 nb_rx_en = 0;
2589                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2590                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2591                         if (reg & IXGBE_FCRTH_FCEN)
2592                                 nb_rx_en++;
2593                 }
2594                 if (nb_rx_en > 1)
2595                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2596                 break;
2597         case ixgbe_fc_rx_pause:
2598                 /*
2599                  * Rx Flow control is enabled and Tx Flow control is
2600                  * disabled by software override. Since there really
2601                  * isn't a way to advertise that we are capable of RX
2602                  * Pause ONLY, we will advertise that we support both
2603                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2604                  * disable the adapter's ability to send PAUSE frames.
2605                  */
2606                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2607                 /*
2608                  * If the count of enabled RX Priority Flow control >1,
2609                  * and the TX pause can not be disabled
2610                  */
2611                 nb_rx_en = 0;
2612                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2613                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2614                         if (reg & IXGBE_FCRTH_FCEN)
2615                                 nb_rx_en++;
2616                 }
2617                 if (nb_rx_en > 1)
2618                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2619                 break;
2620         case ixgbe_fc_tx_pause:
2621                 /*
2622                  * Tx Flow control is enabled, and Rx Flow control is
2623                  * disabled by software override.
2624                  */
2625                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2626                 break;
2627         case ixgbe_fc_full:
2628                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2629                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2630                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2631                 break;
2632         default:
2633                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2634                 ret_val = IXGBE_ERR_CONFIG;
2635                 goto out;
2636                 break;
2637         }
2638
2639         /* Set 802.3x based flow control settings. */
2640         mflcn_reg |= IXGBE_MFLCN_DPF;
2641         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2642         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2643
2644         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2645         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2646                 hw->fc.high_water[tc_num]) {
2647                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2648                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2649                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2650         } else {
2651                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2652                 /*
2653                  * In order to prevent Tx hangs when the internal Tx
2654                  * switch is enabled we must set the high water mark
2655                  * to the maximum FCRTH value.  This allows the Tx
2656                  * switch to function even under heavy Rx workloads.
2657                  */
2658                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2659         }
2660         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2661
2662         /* Configure pause time (2 TCs per register) */
2663         reg = hw->fc.pause_time * 0x00010001;
2664         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2665                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2666
2667         /* Configure flow control refresh threshold value */
2668         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2669
2670 out:
2671         return ret_val;
2672 }
2673
2674 static int
2675 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2676 {
2677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2678         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2679
2680         if(hw->mac.type != ixgbe_mac_82598EB) {
2681                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2682         }
2683         return ret_val;
2684 }
2685
2686 static int
2687 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2688 {
2689         int err;
2690         uint32_t rx_buf_size;
2691         uint32_t max_high_water;
2692         uint8_t tc_num;
2693         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2694         struct ixgbe_hw *hw =
2695                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2696         struct ixgbe_dcb_config *dcb_config =
2697                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2698
2699         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2700                 ixgbe_fc_none,
2701                 ixgbe_fc_rx_pause,
2702                 ixgbe_fc_tx_pause,
2703                 ixgbe_fc_full
2704         };
2705
2706         PMD_INIT_FUNC_TRACE();
2707
2708         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2709         tc_num = map[pfc_conf->priority];
2710         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2711         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2712         /*
2713          * At least reserve one Ethernet frame for watermark
2714          * high_water/low_water in kilo bytes for ixgbe
2715          */
2716         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2717         if ((pfc_conf->fc.high_water > max_high_water) ||
2718             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2719                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2720                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2721                 return (-EINVAL);
2722         }
2723
2724         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2725         hw->fc.pause_time = pfc_conf->fc.pause_time;
2726         hw->fc.send_xon = pfc_conf->fc.send_xon;
2727         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2728         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2729
2730         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2731
2732         /* Not negotiated is not an error case */
2733         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2734                 return 0;
2735
2736         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2737         return -EIO;
2738 }
2739
2740 static int
2741 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2742                           struct rte_eth_rss_reta_entry64 *reta_conf,
2743                           uint16_t reta_size)
2744 {
2745         uint8_t i, j, mask;
2746         uint32_t reta, r;
2747         uint16_t idx, shift;
2748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2749
2750         PMD_INIT_FUNC_TRACE();
2751         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2752                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2753                         "(%d) doesn't match the number hardware can supported "
2754                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2755                 return -EINVAL;
2756         }
2757
2758         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2759                 idx = i / RTE_RETA_GROUP_SIZE;
2760                 shift = i % RTE_RETA_GROUP_SIZE;
2761                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2762                                                 IXGBE_4_BIT_MASK);
2763                 if (!mask)
2764                         continue;
2765                 if (mask == IXGBE_4_BIT_MASK)
2766                         r = 0;
2767                 else
2768                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2769                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2770                         if (mask & (0x1 << j))
2771                                 reta |= reta_conf[idx].reta[shift + j] <<
2772                                                         (CHAR_BIT * j);
2773                         else
2774                                 reta |= r & (IXGBE_8_BIT_MASK <<
2775                                                 (CHAR_BIT * j));
2776                 }
2777                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2778         }
2779
2780         return 0;
2781 }
2782
2783 static int
2784 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2785                          struct rte_eth_rss_reta_entry64 *reta_conf,
2786                          uint16_t reta_size)
2787 {
2788         uint8_t i, j, mask;
2789         uint32_t reta;
2790         uint16_t idx, shift;
2791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792
2793         PMD_INIT_FUNC_TRACE();
2794         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2795                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2796                         "(%d) doesn't match the number hardware can supported "
2797                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2798                 return -EINVAL;
2799         }
2800
2801         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2802                 idx = i / RTE_RETA_GROUP_SIZE;
2803                 shift = i % RTE_RETA_GROUP_SIZE;
2804                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2805                                                 IXGBE_4_BIT_MASK);
2806                 if (!mask)
2807                         continue;
2808
2809                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2810                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2811                         if (mask & (0x1 << j))
2812                                 reta_conf[idx].reta[shift + j] =
2813                                         ((reta >> (CHAR_BIT * j)) &
2814                                                 IXGBE_8_BIT_MASK);
2815                 }
2816         }
2817
2818         return 0;
2819 }
2820
2821 static void
2822 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2823                                 uint32_t index, uint32_t pool)
2824 {
2825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2826         uint32_t enable_addr = 1;
2827
2828         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2829 }
2830
2831 static void
2832 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2833 {
2834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835
2836         ixgbe_clear_rar(hw, index);
2837 }
2838
2839 static int
2840 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2841 {
2842         uint32_t hlreg0;
2843         uint32_t maxfrs;
2844         struct ixgbe_hw *hw;
2845         struct rte_eth_dev_info dev_info;
2846         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2847
2848         ixgbe_dev_info_get(dev, &dev_info);
2849
2850         /* check that mtu is within the allowed range */
2851         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2852                 return -EINVAL;
2853
2854         /* refuse mtu that requires the support of scattered packets when this
2855          * feature has not been enabled before. */
2856         if (!dev->data->scattered_rx &&
2857             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2858              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2859                 return -EINVAL;
2860
2861         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2863
2864         /* switch to jumbo mode if needed */
2865         if (frame_size > ETHER_MAX_LEN) {
2866                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2867                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2868         } else {
2869                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2870                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2871         }
2872         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2873
2874         /* update max frame size */
2875         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2876
2877         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2878         maxfrs &= 0x0000FFFF;
2879         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2880         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2881
2882         return 0;
2883 }
2884
2885 /*
2886  * Virtual Function operations
2887  */
2888 static void
2889 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2890 {
2891         PMD_INIT_FUNC_TRACE();
2892
2893         /* Clear interrupt mask to stop from interrupts being generated */
2894         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2895
2896         IXGBE_WRITE_FLUSH(hw);
2897 }
2898
2899 static int
2900 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2901 {
2902         struct rte_eth_conf* conf = &dev->data->dev_conf;
2903
2904         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2905                      dev->data->port_id);
2906
2907         /*
2908          * VF has no ability to enable/disable HW CRC
2909          * Keep the persistent behavior the same as Host PF
2910          */
2911 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2912         if (!conf->rxmode.hw_strip_crc) {
2913                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2914                 conf->rxmode.hw_strip_crc = 1;
2915         }
2916 #else
2917         if (conf->rxmode.hw_strip_crc) {
2918                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2919                 conf->rxmode.hw_strip_crc = 0;
2920         }
2921 #endif
2922
2923         return 0;
2924 }
2925
2926 static int
2927 ixgbevf_dev_start(struct rte_eth_dev *dev)
2928 {
2929         struct ixgbe_hw *hw =
2930                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931         int err, mask = 0;
2932
2933         PMD_INIT_FUNC_TRACE();
2934
2935         hw->mac.ops.reset_hw(hw);
2936
2937         /* negotiate mailbox API version to use with the PF. */
2938         ixgbevf_negotiate_api(hw);
2939
2940         ixgbevf_dev_tx_init(dev);
2941
2942         /* This can fail when allocating mbufs for descriptor rings */
2943         err = ixgbevf_dev_rx_init(dev);
2944         if (err) {
2945                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2946                 ixgbe_dev_clear_queues(dev);
2947                 return err;
2948         }
2949
2950         /* Set vfta */
2951         ixgbevf_set_vfta_all(dev,1);
2952
2953         /* Set HW strip */
2954         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2955                 ETH_VLAN_EXTEND_MASK;
2956         ixgbevf_vlan_offload_set(dev, mask);
2957
2958         ixgbevf_dev_rxtx_start(dev);
2959
2960         return 0;
2961 }
2962
2963 static void
2964 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2965 {
2966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967
2968         PMD_INIT_FUNC_TRACE();
2969
2970         hw->adapter_stopped = TRUE;
2971         ixgbe_stop_adapter(hw);
2972
2973         /*
2974           * Clear what we set, but we still keep shadow_vfta to
2975           * restore after device starts
2976           */
2977         ixgbevf_set_vfta_all(dev,0);
2978
2979         /* Clear stored conf */
2980         dev->data->scattered_rx = 0;
2981
2982         ixgbe_dev_clear_queues(dev);
2983 }
2984
2985 static void
2986 ixgbevf_dev_close(struct rte_eth_dev *dev)
2987 {
2988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2989
2990         PMD_INIT_FUNC_TRACE();
2991
2992         ixgbe_reset_hw(hw);
2993
2994         ixgbevf_dev_stop(dev);
2995
2996         /* reprogram the RAR[0] in case user changed it. */
2997         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2998 }
2999
3000 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3001 {
3002         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3003         struct ixgbe_vfta * shadow_vfta =
3004                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3005         int i = 0, j = 0, vfta = 0, mask = 1;
3006
3007         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3008                 vfta = shadow_vfta->vfta[i];
3009                 if(vfta){
3010                         mask = 1;
3011                         for (j = 0; j < 32; j++){
3012                                 if(vfta & mask)
3013                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3014                                 mask<<=1;
3015                         }
3016                 }
3017         }
3018
3019 }
3020
3021 static int
3022 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3023 {
3024         struct ixgbe_hw *hw =
3025                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3026         struct ixgbe_vfta * shadow_vfta =
3027                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3028         uint32_t vid_idx = 0;
3029         uint32_t vid_bit = 0;
3030         int ret = 0;
3031
3032         PMD_INIT_FUNC_TRACE();
3033
3034         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3035         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3036         if(ret){
3037                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3038                 return ret;
3039         }
3040         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3041         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3042
3043         /* Save what we set and retore it after device reset */
3044         if (on)
3045                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3046         else
3047                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3048
3049         return 0;
3050 }
3051
3052 static void
3053 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3054 {
3055         struct ixgbe_hw *hw =
3056                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3057         uint32_t ctrl;
3058
3059         PMD_INIT_FUNC_TRACE();
3060
3061         if(queue >= hw->mac.max_rx_queues)
3062                 return;
3063
3064         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3065         if(on)
3066                 ctrl |= IXGBE_RXDCTL_VME;
3067         else
3068                 ctrl &= ~IXGBE_RXDCTL_VME;
3069         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3070
3071         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3072 }
3073
3074 static void
3075 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3076 {
3077         struct ixgbe_hw *hw =
3078                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079         uint16_t i;
3080         int on = 0;
3081
3082         /* VF function only support hw strip feature, others are not support */
3083         if(mask & ETH_VLAN_STRIP_MASK){
3084                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3085
3086                 for(i=0; i < hw->mac.max_rx_queues; i++)
3087                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3088         }
3089 }
3090
3091 static int
3092 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3093 {
3094         uint32_t reg_val;
3095
3096         /* we only need to do this if VMDq is enabled */
3097         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3098         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3099                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3100                 return (-1);
3101         }
3102
3103         return 0;
3104 }
3105
3106 static uint32_t
3107 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3108 {
3109         uint32_t vector = 0;
3110         switch (hw->mac.mc_filter_type) {
3111         case 0:   /* use bits [47:36] of the address */
3112                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3113                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3114                 break;
3115         case 1:   /* use bits [46:35] of the address */
3116                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3117                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3118                 break;
3119         case 2:   /* use bits [45:34] of the address */
3120                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3121                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3122                 break;
3123         case 3:   /* use bits [43:32] of the address */
3124                 vector = ((uc_addr->addr_bytes[4]) |
3125                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3126                 break;
3127         default:  /* Invalid mc_filter_type */
3128                 break;
3129         }
3130
3131         /* vector can only be 12-bits or boundary will be exceeded */
3132         vector &= 0xFFF;
3133         return vector;
3134 }
3135
3136 static int
3137 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3138                                uint8_t on)
3139 {
3140         uint32_t vector;
3141         uint32_t uta_idx;
3142         uint32_t reg_val;
3143         uint32_t uta_shift;
3144         uint32_t rc;
3145         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3146         const uint32_t ixgbe_uta_bit_shift = 5;
3147         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3148         const uint32_t bit1 = 0x1;
3149
3150         struct ixgbe_hw *hw =
3151                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3152         struct ixgbe_uta_info *uta_info =
3153                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3154
3155         /* The UTA table only exists on 82599 hardware and newer */
3156         if (hw->mac.type < ixgbe_mac_82599EB)
3157                 return (-ENOTSUP);
3158
3159         vector = ixgbe_uta_vector(hw,mac_addr);
3160         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3161         uta_shift = vector & ixgbe_uta_bit_mask;
3162
3163         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3164         if(rc == on)
3165                 return 0;
3166
3167         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3168         if (on) {
3169                 uta_info->uta_in_use++;
3170                 reg_val |= (bit1 << uta_shift);
3171                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3172         } else {
3173                 uta_info->uta_in_use--;
3174                 reg_val &= ~(bit1 << uta_shift);
3175                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3176         }
3177
3178         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3179
3180         if (uta_info->uta_in_use > 0)
3181                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3182                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3183         else
3184                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3185
3186         return 0;
3187 }
3188
3189 static int
3190 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3191 {
3192         int i;
3193         struct ixgbe_hw *hw =
3194                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3195         struct ixgbe_uta_info *uta_info =
3196                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3197
3198         /* The UTA table only exists on 82599 hardware and newer */
3199         if (hw->mac.type < ixgbe_mac_82599EB)
3200                 return (-ENOTSUP);
3201
3202         if(on) {
3203                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3204                         uta_info->uta_shadow[i] = ~0;
3205                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3206                 }
3207         } else {
3208                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3209                         uta_info->uta_shadow[i] = 0;
3210                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3211                 }
3212         }
3213         return 0;
3214
3215 }
3216
3217 uint32_t
3218 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3219 {
3220         uint32_t new_val = orig_val;
3221
3222         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3223                 new_val |= IXGBE_VMOLR_AUPE;
3224         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3225                 new_val |= IXGBE_VMOLR_ROMPE;
3226         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3227                 new_val |= IXGBE_VMOLR_ROPE;
3228         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3229                 new_val |= IXGBE_VMOLR_BAM;
3230         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3231                 new_val |= IXGBE_VMOLR_MPE;
3232
3233         return new_val;
3234 }
3235
3236 static int
3237 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3238                                uint16_t rx_mask, uint8_t on)
3239 {
3240         int val = 0;
3241
3242         struct ixgbe_hw *hw =
3243                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3244         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3245
3246         if (hw->mac.type == ixgbe_mac_82598EB) {
3247                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3248                              " on 82599 hardware and newer");
3249                 return (-ENOTSUP);
3250         }
3251         if (ixgbe_vmdq_mode_check(hw) < 0)
3252                 return (-ENOTSUP);
3253
3254         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3255
3256         if (on)
3257                 vmolr |= val;
3258         else
3259                 vmolr &= ~val;
3260
3261         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3262
3263         return 0;
3264 }
3265
3266 static int
3267 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3268 {
3269         uint32_t reg,addr;
3270         uint32_t val;
3271         const uint8_t bit1 = 0x1;
3272
3273         struct ixgbe_hw *hw =
3274                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3275
3276         if (ixgbe_vmdq_mode_check(hw) < 0)
3277                 return (-ENOTSUP);
3278
3279         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3280         reg = IXGBE_READ_REG(hw, addr);
3281         val = bit1 << pool;
3282
3283         if (on)
3284                 reg |= val;
3285         else
3286                 reg &= ~val;
3287
3288         IXGBE_WRITE_REG(hw, addr,reg);
3289
3290         return 0;
3291 }
3292
3293 static int
3294 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3295 {
3296         uint32_t reg,addr;
3297         uint32_t val;
3298         const uint8_t bit1 = 0x1;
3299
3300         struct ixgbe_hw *hw =
3301                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302
3303         if (ixgbe_vmdq_mode_check(hw) < 0)
3304                 return (-ENOTSUP);
3305
3306         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3307         reg = IXGBE_READ_REG(hw, addr);
3308         val = bit1 << pool;
3309
3310         if (on)
3311                 reg |= val;
3312         else
3313                 reg &= ~val;
3314
3315         IXGBE_WRITE_REG(hw, addr,reg);
3316
3317         return 0;
3318 }
3319
3320 static int
3321 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3322                         uint64_t pool_mask, uint8_t vlan_on)
3323 {
3324         int ret = 0;
3325         uint16_t pool_idx;
3326         struct ixgbe_hw *hw =
3327                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3328
3329         if (ixgbe_vmdq_mode_check(hw) < 0)
3330                 return (-ENOTSUP);
3331         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3332                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3333                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3334                         if (ret < 0)
3335                                 return ret;
3336         }
3337
3338         return ret;
3339 }
3340
3341 static int
3342 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3343                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3344                         uint8_t rule_id, uint8_t on)
3345 {
3346         uint32_t mr_ctl,vlvf;
3347         uint32_t mp_lsb = 0;
3348         uint32_t mv_msb = 0;
3349         uint32_t mv_lsb = 0;
3350         uint32_t mp_msb = 0;
3351         uint8_t i = 0;
3352         int reg_index = 0;
3353         uint64_t vlan_mask = 0;
3354
3355         const uint8_t pool_mask_offset = 32;
3356         const uint8_t vlan_mask_offset = 32;
3357         const uint8_t dst_pool_offset = 8;
3358         const uint8_t rule_mr_offset  = 4;
3359         const uint8_t mirror_rule_mask= 0x0F;
3360
3361         struct ixgbe_mirror_info *mr_info =
3362                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3363         struct ixgbe_hw *hw =
3364                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3365
3366         if (ixgbe_vmdq_mode_check(hw) < 0)
3367                 return (-ENOTSUP);
3368
3369         /* Check if vlan mask is valid */
3370         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3371                 if (mirror_conf->vlan.vlan_mask == 0)
3372                         return (-EINVAL);
3373         }
3374
3375         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3376         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3377                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3378                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3379                                 /* search vlan id related pool vlan filter index */
3380                                 reg_index = ixgbe_find_vlvf_slot(hw,
3381                                                 mirror_conf->vlan.vlan_id[i]);
3382                                 if(reg_index < 0)
3383                                         return (-EINVAL);
3384                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3385                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3386                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3387                                                 == mirror_conf->vlan.vlan_id[i]))
3388                                         vlan_mask |= (1ULL << reg_index);
3389                                 else
3390                                         return (-EINVAL);
3391                         }
3392                 }
3393
3394                 if (on) {
3395                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3396                         mv_msb = vlan_mask >> vlan_mask_offset;
3397
3398                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3399                                                 mirror_conf->vlan.vlan_mask;
3400                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3401                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3402                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3403                                                 mirror_conf->vlan.vlan_id[i];
3404                         }
3405                 } else {
3406                         mv_lsb = 0;
3407                         mv_msb = 0;
3408                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3409                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3410                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3411                 }
3412         }
3413
3414         /*
3415          * if enable pool mirror, write related pool mask register,if disable
3416          * pool mirror, clear PFMRVM register
3417          */
3418         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3419                 if (on) {
3420                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3421                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3422                         mr_info->mr_conf[rule_id].pool_mask =
3423                                         mirror_conf->pool_mask;
3424
3425                 } else {
3426                         mp_lsb = 0;
3427                         mp_msb = 0;
3428                         mr_info->mr_conf[rule_id].pool_mask = 0;
3429                 }
3430         }
3431
3432         /* read  mirror control register and recalculate it */
3433         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3434
3435         if (on) {
3436                 mr_ctl |= mirror_conf->rule_type_mask;
3437                 mr_ctl &= mirror_rule_mask;
3438                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3439         } else
3440                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3441
3442         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3443         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3444
3445         /* write mirrror control  register */
3446         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3447
3448         /* write pool mirrror control  register */
3449         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3450                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3451                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3452                                 mp_msb);
3453         }
3454         /* write VLAN mirrror control  register */
3455         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3456                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3457                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3458                                 mv_msb);
3459         }
3460
3461         return 0;
3462 }
3463
3464 static int
3465 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3466 {
3467         int mr_ctl = 0;
3468         uint32_t lsb_val = 0;
3469         uint32_t msb_val = 0;
3470         const uint8_t rule_mr_offset = 4;
3471
3472         struct ixgbe_hw *hw =
3473                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3474         struct ixgbe_mirror_info *mr_info =
3475                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3476
3477         if (ixgbe_vmdq_mode_check(hw) < 0)
3478                 return (-ENOTSUP);
3479
3480         memset(&mr_info->mr_conf[rule_id], 0,
3481                 sizeof(struct rte_eth_vmdq_mirror_conf));
3482
3483         /* clear PFVMCTL register */
3484         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3485
3486         /* clear pool mask register */
3487         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3488         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3489
3490         /* clear vlan mask register */
3491         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3492         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3493
3494         return 0;
3495 }
3496
3497 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3498         uint16_t queue_idx, uint16_t tx_rate)
3499 {
3500         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3501         uint32_t rf_dec, rf_int;
3502         uint32_t bcnrc_val;
3503         uint16_t link_speed = dev->data->dev_link.link_speed;
3504
3505         if (queue_idx >= hw->mac.max_tx_queues)
3506                 return -EINVAL;
3507
3508         if (tx_rate != 0) {
3509                 /* Calculate the rate factor values to set */
3510                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3511                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3512                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3513
3514                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3515                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3516                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3517                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3518         } else {
3519                 bcnrc_val = 0;
3520         }
3521
3522         /*
3523          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3524          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3525          * set as 0x4.
3526          */
3527         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3528                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3529                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3530                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3531                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3532         else
3533                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3534                         IXGBE_MMW_SIZE_DEFAULT);
3535
3536         /* Set RTTBCNRC of queue X */
3537         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3538         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3539         IXGBE_WRITE_FLUSH(hw);
3540
3541         return 0;
3542 }
3543
3544 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3545         uint16_t tx_rate, uint64_t q_msk)
3546 {
3547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548         struct ixgbe_vf_info *vfinfo =
3549                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3550         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3551         uint32_t queue_stride =
3552                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3553         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3554         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3555         uint16_t total_rate = 0;
3556
3557         if (queue_end >= hw->mac.max_tx_queues)
3558                 return -EINVAL;
3559
3560         if (vfinfo != NULL) {
3561                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3562                         if (vf_idx == vf)
3563                                 continue;
3564                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3565                                 idx++)
3566                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3567                 }
3568         } else
3569                 return -EINVAL;
3570
3571         /* Store tx_rate for this vf. */
3572         for (idx = 0; idx < nb_q_per_pool; idx++) {
3573                 if (((uint64_t)0x1 << idx) & q_msk) {
3574                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3575                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3576                         total_rate += tx_rate;
3577                 }
3578         }
3579
3580         if (total_rate > dev->data->dev_link.link_speed) {
3581                 /*
3582                  * Reset stored TX rate of the VF if it causes exceed
3583                  * link speed.
3584                  */
3585                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3586                 return -EINVAL;
3587         }
3588
3589         /* Set RTTBCNRC of each queue/pool for vf X  */
3590         for (; queue_idx <= queue_end; queue_idx++) {
3591                 if (0x1 & q_msk)
3592                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3593                 q_msk = q_msk >> 1;
3594         }
3595
3596         return 0;
3597 }
3598
3599 static void
3600 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3601                      __attribute__((unused)) uint32_t index,
3602                      __attribute__((unused)) uint32_t pool)
3603 {
3604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605         int diag;
3606
3607         /*
3608          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3609          * operation. Trap this case to avoid exhausting the [very limited]
3610          * set of PF resources used to store VF MAC addresses.
3611          */
3612         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3613                 return;
3614         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3615         if (diag == 0)
3616                 return;
3617         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3618 }
3619
3620 static void
3621 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3622 {
3623         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3624         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3625         struct ether_addr *mac_addr;
3626         uint32_t i;
3627         int diag;
3628
3629         /*
3630          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3631          * not support the deletion of a given MAC address.
3632          * Instead, it imposes to delete all MAC addresses, then to add again
3633          * all MAC addresses with the exception of the one to be deleted.
3634          */
3635         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3636
3637         /*
3638          * Add again all MAC addresses, with the exception of the deleted one
3639          * and of the permanent MAC address.
3640          */
3641         for (i = 0, mac_addr = dev->data->mac_addrs;
3642              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3643                 /* Skip the deleted MAC address */
3644                 if (i == index)
3645                         continue;
3646                 /* Skip NULL MAC addresses */
3647                 if (is_zero_ether_addr(mac_addr))
3648                         continue;
3649                 /* Skip the permanent MAC address */
3650                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3651                         continue;
3652                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3653                 if (diag != 0)
3654                         PMD_DRV_LOG(ERR,
3655                                     "Adding again MAC address "
3656                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3657                                     "diag=%d",
3658                                     mac_addr->addr_bytes[0],
3659                                     mac_addr->addr_bytes[1],
3660                                     mac_addr->addr_bytes[2],
3661                                     mac_addr->addr_bytes[3],
3662                                     mac_addr->addr_bytes[4],
3663                                     mac_addr->addr_bytes[5],
3664                                     diag);
3665         }
3666 }
3667
3668 /*
3669  * add syn filter
3670  *
3671  * @param
3672  * dev: Pointer to struct rte_eth_dev.
3673  * filter: ponter to the filter that will be added.
3674  * rx_queue: the queue id the filter assigned to.
3675  *
3676  * @return
3677  *    - On success, zero.
3678  *    - On failure, a negative value.
3679  */
3680 static int
3681 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3682                         struct rte_syn_filter *filter, uint16_t rx_queue)
3683 {
3684         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3685         uint32_t synqf;
3686
3687         if (hw->mac.type != ixgbe_mac_82599EB)
3688                 return -ENOSYS;
3689
3690         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3691                 return -EINVAL;
3692
3693         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3694
3695         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3696                 return -EINVAL;
3697
3698         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3699                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3700
3701         if (filter->hig_pri)
3702                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3703         else
3704                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3705
3706         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3707         return 0;
3708 }
3709
3710 /*
3711  * remove syn filter
3712  *
3713  * @param
3714  * dev: Pointer to struct rte_eth_dev.
3715  *
3716  * @return
3717  *    - On success, zero.
3718  *    - On failure, a negative value.
3719  */
3720 static int
3721 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3722 {
3723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3724         uint32_t synqf;
3725
3726         if (hw->mac.type != ixgbe_mac_82599EB)
3727                 return -ENOSYS;
3728
3729         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3730
3731         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3732
3733         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3734         return 0;
3735 }
3736
3737 /*
3738  * get the syn filter's info
3739  *
3740  * @param
3741  * dev: Pointer to struct rte_eth_dev.
3742  * filter: ponter to the filter that returns.
3743  * *rx_queue: pointer to the queue id the filter assigned to.
3744  *
3745  * @return
3746  *    - On success, zero.
3747  *    - On failure, a negative value.
3748  */
3749 static int
3750 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3751                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3752
3753 {
3754         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3755         uint32_t synqf;
3756
3757         if (hw->mac.type != ixgbe_mac_82599EB)
3758                 return -ENOSYS;
3759
3760         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3761         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3762                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3763                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3764                 return 0;
3765         }
3766         return -ENOENT;
3767 }
3768
3769 /*
3770  * add an ethertype filter
3771  *
3772  * @param
3773  * dev: Pointer to struct rte_eth_dev.
3774  * index: the index the filter allocates.
3775  * filter: ponter to the filter that will be added.
3776  * rx_queue: the queue id the filter assigned to.
3777  *
3778  * @return
3779  *    - On success, zero.
3780  *    - On failure, a negative value.
3781  */
3782 static int
3783 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3784                         uint16_t index, struct rte_ethertype_filter *filter,
3785                         uint16_t rx_queue)
3786 {
3787         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3788         uint32_t etqf, etqs = 0;
3789
3790         if (hw->mac.type != ixgbe_mac_82599EB)
3791                 return -ENOSYS;
3792
3793         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3794                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3795                 return -EINVAL;
3796
3797         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3798         if (etqf & IXGBE_ETQF_FILTER_EN)
3799                 return -EINVAL;  /* filter index is in use. */
3800
3801         etqf = 0;
3802         etqf |= IXGBE_ETQF_FILTER_EN;
3803         etqf |= (uint32_t)filter->ethertype;
3804
3805         if (filter->priority_en) {
3806                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3807                         return -EINVAL;
3808                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3809                 etqf |= IXGBE_ETQF_UP_EN;
3810         }
3811         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3812         etqs |= IXGBE_ETQS_QUEUE_EN;
3813
3814         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3815         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3816         return 0;
3817 }
3818
3819 /*
3820  * remove an ethertype filter
3821  *
3822  * @param
3823  * dev: Pointer to struct rte_eth_dev.
3824  * index: the index the filter allocates.
3825  *
3826  * @return
3827  *    - On success, zero.
3828  *    - On failure, a negative value.
3829  */
3830 static int
3831 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3832                         uint16_t index)
3833 {
3834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835
3836         if (hw->mac.type != ixgbe_mac_82599EB)
3837                 return -ENOSYS;
3838
3839         if (index >= IXGBE_MAX_ETQF_FILTERS)
3840                 return -EINVAL;
3841
3842         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3843         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3844
3845         return 0;
3846 }
3847
3848 /*
3849  * get an ethertype filter
3850  *
3851  * @param
3852  * dev: Pointer to struct rte_eth_dev.
3853  * index: the index the filter allocates.
3854  * filter: ponter to the filter that will be gotten.
3855  * *rx_queue: the ponited of the queue id the filter assigned to.
3856  *
3857  * @return
3858  *    - On success, zero.
3859  *    - On failure, a negative value.
3860  */
3861 static int
3862 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3863                         uint16_t index, struct rte_ethertype_filter *filter,
3864                         uint16_t *rx_queue)
3865 {
3866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3867         uint32_t etqf, etqs;
3868
3869         if (hw->mac.type != ixgbe_mac_82599EB)
3870                 return -ENOSYS;
3871
3872         if (index >= IXGBE_MAX_ETQF_FILTERS)
3873                 return -EINVAL;
3874
3875         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3876         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3877         if (etqf & IXGBE_ETQF_FILTER_EN) {
3878                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3879                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3880                 if (filter->priority_en)
3881                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3882                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3883                 return 0;
3884         }
3885         return -ENOENT;
3886 }
3887
3888 static inline enum ixgbe_5tuple_protocol
3889 convert_protocol_type(uint8_t protocol_value)
3890 {
3891         if (protocol_value == IPPROTO_TCP)
3892                 return IXGBE_FILTER_PROTOCOL_TCP;
3893         else if (protocol_value == IPPROTO_UDP)
3894                 return IXGBE_FILTER_PROTOCOL_UDP;
3895         else if (protocol_value == IPPROTO_SCTP)
3896                 return IXGBE_FILTER_PROTOCOL_SCTP;
3897         else
3898                 return IXGBE_FILTER_PROTOCOL_NONE;
3899 }
3900
3901 static inline uint8_t
3902 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3903 {
3904         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3905                 return IPPROTO_TCP;
3906         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3907                 return IPPROTO_UDP;
3908         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3909                 return IPPROTO_SCTP;
3910         else
3911                 return 0;
3912 }
3913
3914 /*
3915  * add a 5tuple filter
3916  *
3917  * @param
3918  * dev: Pointer to struct rte_eth_dev.
3919  * index: the index the filter allocates.
3920  * filter: ponter to the filter that will be added.
3921  * rx_queue: the queue id the filter assigned to.
3922  *
3923  * @return
3924  *    - On success, zero.
3925  *    - On failure, a negative value.
3926  */
3927 static int
3928 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3929                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3930 {
3931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3932         uint32_t ftqf, sdpqf = 0;
3933         uint32_t l34timir = 0;
3934         uint8_t mask = 0xff;
3935
3936         if (hw->mac.type != ixgbe_mac_82599EB)
3937                 return -ENOSYS;
3938
3939         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3940                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3941                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3942                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3943                 return -EINVAL;  /* filter index is out of range. */
3944
3945         if (filter->tcp_flags) {
3946                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3947                 return -EINVAL;
3948         }
3949
3950         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3951         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3952                 return -EINVAL;  /* filter index is in use. */
3953
3954         ftqf = 0;
3955         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3956         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3957
3958         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3959                 IXGBE_FTQF_PROTOCOL_MASK);
3960         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3961                 IXGBE_FTQF_PRIORITY_SHIFT);
3962         if (filter->src_ip_mask == 0) /* 0 means compare. */
3963                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3964         if (filter->dst_ip_mask == 0)
3965                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3966         if (filter->src_port_mask == 0)
3967                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3968         if (filter->dst_port_mask == 0)
3969                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3970         if (filter->protocol_mask == 0)
3971                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3972         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3973         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3974         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3975
3976         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3977         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3978         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3979         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3980
3981         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3982         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3983         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3984         return 0;
3985 }
3986
3987 /*
3988  * remove a 5tuple filter
3989  *
3990  * @param
3991  * dev: Pointer to struct rte_eth_dev.
3992  * index: the index the filter allocates.
3993  *
3994  * @return
3995  *    - On success, zero.
3996  *    - On failure, a negative value.
3997  */
3998 static int
3999 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4000                         uint16_t index)
4001 {
4002         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4003
4004         if (hw->mac.type != ixgbe_mac_82599EB)
4005                 return -ENOSYS;
4006
4007         if (index >= IXGBE_MAX_FTQF_FILTERS)
4008                 return -EINVAL;  /* filter index is out of range. */
4009
4010         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4011         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4012         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4013         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4014         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4015         return 0;
4016 }
4017
4018 /*
4019  * get a 5tuple filter
4020  *
4021  * @param
4022  * dev: Pointer to struct rte_eth_dev.
4023  * index: the index the filter allocates
4024  * filter: ponter to the filter that returns.
4025  * *rx_queue: pointer of the queue id the filter assigned to.
4026  *
4027  * @return
4028  *    - On success, zero.
4029  *    - On failure, a negative value.
4030  */
4031 static int
4032 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
4033                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
4034 {
4035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4036         uint32_t sdpqf, ftqf, l34timir;
4037         uint8_t mask;
4038         enum ixgbe_5tuple_protocol proto;
4039
4040         if (hw->mac.type != ixgbe_mac_82599EB)
4041                 return -ENOSYS;
4042
4043         if (index >= IXGBE_MAX_FTQF_FILTERS)
4044                 return -EINVAL;  /* filter index is out of range. */
4045
4046         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
4047         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
4048                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
4049                 filter->protocol = revert_protocol_type(proto);
4050                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
4051                                         IXGBE_FTQF_PRIORITY_MASK;
4052                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
4053                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
4054                 filter->src_ip_mask =
4055                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
4056                 filter->dst_ip_mask =
4057                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
4058                 filter->src_port_mask =
4059                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
4060                 filter->dst_port_mask =
4061                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
4062                 filter->protocol_mask =
4063                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
4064
4065                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
4066                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
4067                                         IXGBE_SDPQF_DSTPORT_SHIFT;
4068                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
4069                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
4070                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
4071
4072                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
4073                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
4074                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
4075                 return 0;
4076         }
4077         return -ENOENT;
4078 }
4079
4080 static int
4081 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4082 {
4083         struct ixgbe_hw *hw;
4084         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4085
4086         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4087
4088         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4089                 return -EINVAL;
4090
4091         /* refuse mtu that requires the support of scattered packets when this
4092          * feature has not been enabled before. */
4093         if (!dev->data->scattered_rx &&
4094             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4095              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4096                 return -EINVAL;
4097
4098         /*
4099          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4100          * request of the version 2.0 of the mailbox API.
4101          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4102          * of the mailbox API.
4103          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4104          * prior to 3.11.33 which contains the following change:
4105          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4106          */
4107         ixgbevf_rlpml_set_vf(hw, max_frame);
4108
4109         /* update max frame size */
4110         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4111         return 0;
4112 }
4113
4114 static struct rte_driver rte_ixgbe_driver = {
4115         .type = PMD_PDEV,
4116         .init = rte_ixgbe_pmd_init,
4117 };
4118
4119 static struct rte_driver rte_ixgbevf_driver = {
4120         .type = PMD_PDEV,
4121         .init = rte_ixgbevf_pmd_init,
4122 };
4123
4124 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4125 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);