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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
65 #include "ixgbe_logs.h"
66 #include "ixgbe/ixgbe_api.h"
67 #include "ixgbe/ixgbe_vf.h"
68 #include "ixgbe/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
74 * High threshold controlling when to start sending XOFF frames. Must be at
75 * least 8 bytes less than receive packet buffer size. This value is in units
78 #define IXGBE_FC_HI 0x80
81 * Low threshold controlling when to start sending XON frames. This value is
82 * in units of 1024 bytes.
84 #define IXGBE_FC_LO 0x40
86 /* Timer value included in XOFF frames. */
87 #define IXGBE_FC_PAUSE 0x680
89 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
90 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
91 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
93 #define IXGBE_MMW_SIZE_DEFAULT 0x4
94 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
97 * Default values for RX/TX configuration
99 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
100 #define IXGBE_DEFAULT_RX_PTHRESH 8
101 #define IXGBE_DEFAULT_RX_HTHRESH 8
102 #define IXGBE_DEFAULT_RX_WTHRESH 0
104 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
105 #define IXGBE_DEFAULT_TX_PTHRESH 32
106 #define IXGBE_DEFAULT_TX_HTHRESH 0
107 #define IXGBE_DEFAULT_TX_WTHRESH 0
108 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
110 /* Bit shift and mask */
111 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
112 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
113 #define IXGBE_8_BIT_WIDTH CHAR_BIT
114 #define IXGBE_8_BIT_MASK UINT8_MAX
116 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
118 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
120 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
121 struct rte_eth_dev *eth_dev);
122 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
123 static int ixgbe_dev_start(struct rte_eth_dev *dev);
124 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
125 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
126 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
127 static void ixgbe_dev_close(struct rte_eth_dev *dev);
128 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
129 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
130 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
131 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
132 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
133 int wait_to_complete);
134 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
135 struct rte_eth_stats *stats);
136 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
137 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
141 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
142 struct rte_eth_dev_info *dev_info);
143 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
144 struct rte_eth_dev_info *dev_info);
145 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
147 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
148 uint16_t vlan_id, int on);
149 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
150 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
151 uint16_t queue, bool on);
152 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
154 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
155 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
156 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
157 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
158 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
160 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
161 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
162 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
163 struct rte_eth_fc_conf *fc_conf);
164 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
165 struct rte_eth_fc_conf *fc_conf);
166 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
167 struct rte_eth_pfc_conf *pfc_conf);
168 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
169 struct rte_eth_rss_reta_entry64 *reta_conf,
171 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
172 struct rte_eth_rss_reta_entry64 *reta_conf,
174 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
175 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
176 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
177 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
178 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
180 static void ixgbe_dev_interrupt_delayed_handler(void *param);
181 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
182 uint32_t index, uint32_t pool);
183 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
184 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
186 /* For Virtual Function support */
187 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
188 struct rte_eth_dev *eth_dev);
189 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
190 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
191 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
192 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
193 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
194 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
195 struct rte_eth_stats *stats);
196 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
197 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
198 uint16_t vlan_id, int on);
199 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
200 uint16_t queue, int on);
201 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
202 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
204 /* For Eth VMDQ APIs support */
205 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
206 ether_addr* mac_addr,uint8_t on);
207 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
208 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
209 uint16_t rx_mask, uint8_t on);
210 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
211 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
212 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
213 uint64_t pool_mask,uint8_t vlan_on);
214 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
215 struct rte_eth_vmdq_mirror_conf *mirror_conf,
216 uint8_t rule_id, uint8_t on);
217 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
220 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
221 uint16_t queue_idx, uint16_t tx_rate);
222 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
223 uint16_t tx_rate, uint64_t q_msk);
225 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
226 struct ether_addr *mac_addr,
227 uint32_t index, uint32_t pool);
228 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
229 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
230 struct rte_syn_filter *filter, uint16_t rx_queue);
231 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
232 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
233 struct rte_syn_filter *filter, uint16_t *rx_queue);
234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
235 struct rte_5tuple_filter *filter, uint16_t rx_queue);
236 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
238 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
239 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
241 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
242 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
243 struct rte_eth_ethertype_filter *filter,
245 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
246 enum rte_filter_op filter_op,
248 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
249 struct rte_eth_ethertype_filter *filter);
250 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
251 enum rte_filter_type filter_type,
252 enum rte_filter_op filter_op,
256 * Define VF Stats MACRO for Non "cleared on read" register
258 #define UPDATE_VF_STAT(reg, last, cur) \
260 u32 latest = IXGBE_READ_REG(hw, reg); \
261 cur += latest - last; \
265 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
267 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
268 u64 new_msb = IXGBE_READ_REG(hw, msb); \
269 u64 latest = ((new_msb << 32) | new_lsb); \
270 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
274 #define IXGBE_SET_HWSTRIP(h, q) do{\
275 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
276 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
277 (h)->bitmap[idx] |= 1 << bit;\
280 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
281 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
282 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
283 (h)->bitmap[idx] &= ~(1 << bit);\
286 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
287 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
288 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
289 (r) = (h)->bitmap[idx] >> bit & 1;\
293 * The set of PCI devices this driver supports
295 static struct rte_pci_id pci_id_ixgbe_map[] = {
297 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
298 #include "rte_pci_dev_ids.h"
300 { .vendor_id = 0, /* sentinel */ },
305 * The set of PCI devices this driver supports (for 82599 VF)
307 static struct rte_pci_id pci_id_ixgbevf_map[] = {
309 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
310 #include "rte_pci_dev_ids.h"
311 { .vendor_id = 0, /* sentinel */ },
315 static struct eth_dev_ops ixgbe_eth_dev_ops = {
316 .dev_configure = ixgbe_dev_configure,
317 .dev_start = ixgbe_dev_start,
318 .dev_stop = ixgbe_dev_stop,
319 .dev_set_link_up = ixgbe_dev_set_link_up,
320 .dev_set_link_down = ixgbe_dev_set_link_down,
321 .dev_close = ixgbe_dev_close,
322 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
323 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
324 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
325 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
326 .link_update = ixgbe_dev_link_update,
327 .stats_get = ixgbe_dev_stats_get,
328 .stats_reset = ixgbe_dev_stats_reset,
329 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
330 .dev_infos_get = ixgbe_dev_info_get,
331 .mtu_set = ixgbe_dev_mtu_set,
332 .vlan_filter_set = ixgbe_vlan_filter_set,
333 .vlan_tpid_set = ixgbe_vlan_tpid_set,
334 .vlan_offload_set = ixgbe_vlan_offload_set,
335 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
336 .rx_queue_start = ixgbe_dev_rx_queue_start,
337 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
338 .tx_queue_start = ixgbe_dev_tx_queue_start,
339 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
340 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
341 .rx_queue_release = ixgbe_dev_rx_queue_release,
342 .rx_queue_count = ixgbe_dev_rx_queue_count,
343 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
344 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
345 .tx_queue_release = ixgbe_dev_tx_queue_release,
346 .dev_led_on = ixgbe_dev_led_on,
347 .dev_led_off = ixgbe_dev_led_off,
348 .flow_ctrl_get = ixgbe_flow_ctrl_get,
349 .flow_ctrl_set = ixgbe_flow_ctrl_set,
350 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
351 .mac_addr_add = ixgbe_add_rar,
352 .mac_addr_remove = ixgbe_remove_rar,
353 .uc_hash_table_set = ixgbe_uc_hash_table_set,
354 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
355 .mirror_rule_set = ixgbe_mirror_rule_set,
356 .mirror_rule_reset = ixgbe_mirror_rule_reset,
357 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
358 .set_vf_rx = ixgbe_set_pool_rx,
359 .set_vf_tx = ixgbe_set_pool_tx,
360 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
361 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
362 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
363 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
364 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
365 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
366 .fdir_infos_get = ixgbe_fdir_info_get,
367 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
368 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
369 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
370 .fdir_set_masks = ixgbe_fdir_set_masks,
371 .reta_update = ixgbe_dev_rss_reta_update,
372 .reta_query = ixgbe_dev_rss_reta_query,
373 #ifdef RTE_NIC_BYPASS
374 .bypass_init = ixgbe_bypass_init,
375 .bypass_state_set = ixgbe_bypass_state_store,
376 .bypass_state_show = ixgbe_bypass_state_show,
377 .bypass_event_set = ixgbe_bypass_event_store,
378 .bypass_event_show = ixgbe_bypass_event_show,
379 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
380 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
381 .bypass_ver_show = ixgbe_bypass_ver_show,
382 .bypass_wd_reset = ixgbe_bypass_wd_reset,
383 #endif /* RTE_NIC_BYPASS */
384 .rss_hash_update = ixgbe_dev_rss_hash_update,
385 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
386 .add_syn_filter = ixgbe_add_syn_filter,
387 .remove_syn_filter = ixgbe_remove_syn_filter,
388 .get_syn_filter = ixgbe_get_syn_filter,
389 .add_5tuple_filter = ixgbe_add_5tuple_filter,
390 .remove_5tuple_filter = ixgbe_remove_5tuple_filter,
391 .get_5tuple_filter = ixgbe_get_5tuple_filter,
392 .filter_ctrl = ixgbe_dev_filter_ctrl,
396 * dev_ops for virtual function, bare necessities for basic vf
397 * operation have been implemented
399 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
401 .dev_configure = ixgbevf_dev_configure,
402 .dev_start = ixgbevf_dev_start,
403 .dev_stop = ixgbevf_dev_stop,
404 .link_update = ixgbe_dev_link_update,
405 .stats_get = ixgbevf_dev_stats_get,
406 .stats_reset = ixgbevf_dev_stats_reset,
407 .dev_close = ixgbevf_dev_close,
408 .dev_infos_get = ixgbevf_dev_info_get,
409 .mtu_set = ixgbevf_dev_set_mtu,
410 .vlan_filter_set = ixgbevf_vlan_filter_set,
411 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
412 .vlan_offload_set = ixgbevf_vlan_offload_set,
413 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
414 .rx_queue_release = ixgbe_dev_rx_queue_release,
415 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
416 .tx_queue_release = ixgbe_dev_tx_queue_release,
417 .mac_addr_add = ixgbevf_add_mac_addr,
418 .mac_addr_remove = ixgbevf_remove_mac_addr,
422 * Atomically reads the link status information from global
423 * structure rte_eth_dev.
426 * - Pointer to the structure rte_eth_dev to read from.
427 * - Pointer to the buffer to be saved with the link status.
430 * - On success, zero.
431 * - On failure, negative value.
434 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
435 struct rte_eth_link *link)
437 struct rte_eth_link *dst = link;
438 struct rte_eth_link *src = &(dev->data->dev_link);
440 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
441 *(uint64_t *)src) == 0)
448 * Atomically writes the link status information into global
449 * structure rte_eth_dev.
452 * - Pointer to the structure rte_eth_dev to read from.
453 * - Pointer to the buffer to be saved with the link status.
456 * - On success, zero.
457 * - On failure, negative value.
460 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
461 struct rte_eth_link *link)
463 struct rte_eth_link *dst = &(dev->data->dev_link);
464 struct rte_eth_link *src = link;
466 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
467 *(uint64_t *)src) == 0)
474 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
477 ixgbe_is_sfp(struct ixgbe_hw *hw)
479 switch (hw->phy.type) {
480 case ixgbe_phy_sfp_avago:
481 case ixgbe_phy_sfp_ftl:
482 case ixgbe_phy_sfp_intel:
483 case ixgbe_phy_sfp_unknown:
484 case ixgbe_phy_sfp_passive_tyco:
485 case ixgbe_phy_sfp_passive_unknown:
492 static inline int32_t
493 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
498 status = ixgbe_reset_hw(hw);
500 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
501 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
502 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
503 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
504 IXGBE_WRITE_FLUSH(hw);
510 ixgbe_enable_intr(struct rte_eth_dev *dev)
512 struct ixgbe_interrupt *intr =
513 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
514 struct ixgbe_hw *hw =
515 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
517 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
518 IXGBE_WRITE_FLUSH(hw);
522 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
525 ixgbe_disable_intr(struct ixgbe_hw *hw)
527 PMD_INIT_FUNC_TRACE();
529 if (hw->mac.type == ixgbe_mac_82598EB) {
530 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
532 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
533 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
534 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
536 IXGBE_WRITE_FLUSH(hw);
540 * This function resets queue statistics mapping registers.
541 * From Niantic datasheet, Initialization of Statistics section:
542 * "...if software requires the queue counters, the RQSMR and TQSM registers
543 * must be re-programmed following a device reset.
546 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
550 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
551 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
552 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
558 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
563 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
564 #define NB_QMAP_FIELDS_PER_QSM_REG 4
565 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
567 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
568 struct ixgbe_stat_mapping_registers *stat_mappings =
569 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
570 uint32_t qsmr_mask = 0;
571 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
575 if ((hw->mac.type != ixgbe_mac_82599EB) &&
576 (hw->mac.type != ixgbe_mac_X540) &&
577 (hw->mac.type != ixgbe_mac_X550) &&
578 (hw->mac.type != ixgbe_mac_X550EM_x))
581 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
582 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
585 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
586 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
587 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
590 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
592 /* Now clear any previous stat_idx set */
593 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
595 stat_mappings->tqsm[n] &= ~clearing_mask;
597 stat_mappings->rqsmr[n] &= ~clearing_mask;
599 q_map = (uint32_t)stat_idx;
600 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
601 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
603 stat_mappings->tqsm[n] |= qsmr_mask;
605 stat_mappings->rqsmr[n] |= qsmr_mask;
607 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
608 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
610 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
611 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
613 /* Now write the mapping in the appropriate register */
615 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
616 stat_mappings->rqsmr[n], n);
617 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
620 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
621 stat_mappings->tqsm[n], n);
622 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
628 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
630 struct ixgbe_stat_mapping_registers *stat_mappings =
631 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
632 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
635 /* write whatever was in stat mapping table to the NIC */
636 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
638 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
641 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
646 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
649 struct ixgbe_dcb_tc_config *tc;
650 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
652 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
653 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
654 for (i = 0; i < dcb_max_tc; i++) {
655 tc = &dcb_config->tc_config[i];
656 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
657 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
658 (uint8_t)(100/dcb_max_tc + (i & 1));
659 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
660 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
661 (uint8_t)(100/dcb_max_tc + (i & 1));
662 tc->pfc = ixgbe_dcb_pfc_disabled;
665 /* Initialize default user to priority mapping, UPx->TC0 */
666 tc = &dcb_config->tc_config[0];
667 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
668 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
669 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
670 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
671 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
673 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
674 dcb_config->pfc_mode_enable = false;
675 dcb_config->vt_mode = true;
676 dcb_config->round_robin_enable = false;
677 /* support all DCB capabilities in 82599 */
678 dcb_config->support.capabilities = 0xFF;
680 /*we only support 4 Tcs for X540, X550 */
681 if (hw->mac.type == ixgbe_mac_X540 ||
682 hw->mac.type == ixgbe_mac_X550 ||
683 hw->mac.type == ixgbe_mac_X550EM_x) {
684 dcb_config->num_tcs.pg_tcs = 4;
685 dcb_config->num_tcs.pfc_tcs = 4;
690 * Ensure that all locks are released before first NVM or PHY access
693 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
698 * Phy lock should not fail in this early stage. If this is the case,
699 * it is due to an improper exit of the application.
700 * So force the release of the faulty lock. Release of common lock
701 * is done automatically by swfw_sync function.
703 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
704 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
705 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
707 ixgbe_release_swfw_semaphore(hw, mask);
710 * These ones are more tricky since they are common to all ports; but
711 * swfw_sync retries last long enough (1s) to be almost sure that if
712 * lock can not be taken it is due to an improper lock of the
715 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
716 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
717 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
719 ixgbe_release_swfw_semaphore(hw, mask);
723 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
724 * It returns 0 on success.
727 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
728 struct rte_eth_dev *eth_dev)
730 struct rte_pci_device *pci_dev;
731 struct ixgbe_hw *hw =
732 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
733 struct ixgbe_vfta * shadow_vfta =
734 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
735 struct ixgbe_hwstrip *hwstrip =
736 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
737 struct ixgbe_dcb_config *dcb_config =
738 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
743 PMD_INIT_FUNC_TRACE();
745 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
746 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
747 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
750 * For secondary processes, we don't initialise any further as primary
751 * has already done this work. Only check we don't need a different
752 * RX and TX function.
754 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
755 struct igb_tx_queue *txq;
756 /* TX queue function in primary, set by last queue initialized
757 * Tx queue may not initialized by primary process */
758 if (eth_dev->data->tx_queues) {
759 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
760 set_tx_function(eth_dev, txq);
762 /* Use default TX function if we get here */
763 PMD_INIT_LOG(INFO, "No TX queues configured yet. "
764 "Using default TX function.");
767 if (eth_dev->data->scattered_rx)
768 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
771 pci_dev = eth_dev->pci_dev;
773 /* Vendor and Device ID need to be set before init of shared code */
774 hw->device_id = pci_dev->id.device_id;
775 hw->vendor_id = pci_dev->id.vendor_id;
776 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
777 hw->allow_unsupported_sfp = 1;
779 /* Initialize the shared code (base driver) */
780 #ifdef RTE_NIC_BYPASS
781 diag = ixgbe_bypass_init_shared_code(hw);
783 diag = ixgbe_init_shared_code(hw);
784 #endif /* RTE_NIC_BYPASS */
786 if (diag != IXGBE_SUCCESS) {
787 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
791 /* pick up the PCI bus settings for reporting later */
792 ixgbe_get_bus_info(hw);
794 /* Unlock any pending hardware semaphore */
795 ixgbe_swfw_lock_reset(hw);
797 /* Initialize DCB configuration*/
798 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
799 ixgbe_dcb_init(hw,dcb_config);
800 /* Get Hardware Flow Control setting */
801 hw->fc.requested_mode = ixgbe_fc_full;
802 hw->fc.current_mode = ixgbe_fc_full;
803 hw->fc.pause_time = IXGBE_FC_PAUSE;
804 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
805 hw->fc.low_water[i] = IXGBE_FC_LO;
806 hw->fc.high_water[i] = IXGBE_FC_HI;
810 /* Make sure we have a good EEPROM before we read from it */
811 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
812 if (diag != IXGBE_SUCCESS) {
813 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
817 #ifdef RTE_NIC_BYPASS
818 diag = ixgbe_bypass_init_hw(hw);
820 diag = ixgbe_init_hw(hw);
821 #endif /* RTE_NIC_BYPASS */
824 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
825 * is called too soon after the kernel driver unbinding/binding occurs.
826 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
827 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
828 * also called. See ixgbe_identify_phy_82599(). The reason for the
829 * failure is not known, and only occuts when virtualisation features
830 * are disabled in the bios. A delay of 100ms was found to be enough by
831 * trial-and-error, and is doubled to be safe.
833 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
835 diag = ixgbe_init_hw(hw);
838 if (diag == IXGBE_ERR_EEPROM_VERSION) {
839 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
840 "LOM. Please be aware there may be issues associated "
841 "with your hardware.");
842 PMD_INIT_LOG(ERR, "If you are experiencing problems "
843 "please contact your Intel or hardware representative "
844 "who provided you with this hardware.");
845 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
846 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
848 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
852 /* disable interrupt */
853 ixgbe_disable_intr(hw);
855 /* reset mappings for queue statistics hw counters*/
856 ixgbe_reset_qstat_mappings(hw);
858 /* Allocate memory for storing MAC addresses */
859 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
860 hw->mac.num_rar_entries, 0);
861 if (eth_dev->data->mac_addrs == NULL) {
863 "Failed to allocate %u bytes needed to store "
865 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
868 /* Copy the permanent MAC address */
869 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
870 ð_dev->data->mac_addrs[0]);
872 /* Allocate memory for storing hash filter MAC addresses */
873 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
874 IXGBE_VMDQ_NUM_UC_MAC, 0);
875 if (eth_dev->data->hash_mac_addrs == NULL) {
877 "Failed to allocate %d bytes needed to store MAC addresses",
878 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
882 /* initialize the vfta */
883 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
885 /* initialize the hw strip bitmap*/
886 memset(hwstrip, 0, sizeof(*hwstrip));
888 /* initialize PF if max_vfs not zero */
889 ixgbe_pf_host_init(eth_dev);
891 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
892 /* let hardware know driver is loaded */
893 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
894 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
895 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
896 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
897 IXGBE_WRITE_FLUSH(hw);
899 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
900 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
901 (int) hw->mac.type, (int) hw->phy.type,
902 (int) hw->phy.sfp_type);
904 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
905 (int) hw->mac.type, (int) hw->phy.type);
907 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
908 eth_dev->data->port_id, pci_dev->id.vendor_id,
909 pci_dev->id.device_id);
911 rte_intr_callback_register(&(pci_dev->intr_handle),
912 ixgbe_dev_interrupt_handler, (void *)eth_dev);
914 /* enable uio intr after callback register */
915 rte_intr_enable(&(pci_dev->intr_handle));
917 /* enable support intr */
918 ixgbe_enable_intr(eth_dev);
925 * Negotiate mailbox API version with the PF.
926 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
927 * Then we try to negotiate starting with the most recent one.
928 * If all negotiation attempts fail, then we will proceed with
929 * the default one (ixgbe_mbox_api_10).
932 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
936 /* start with highest supported, proceed down */
937 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
943 i != RTE_DIM(sup_ver) &&
944 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
950 generate_random_mac_addr(struct ether_addr *mac_addr)
954 /* Set Organizationally Unique Identifier (OUI) prefix. */
955 mac_addr->addr_bytes[0] = 0x00;
956 mac_addr->addr_bytes[1] = 0x09;
957 mac_addr->addr_bytes[2] = 0xC0;
958 /* Force indication of locally assigned MAC address. */
959 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
960 /* Generate the last 3 bytes of the MAC address with a random number. */
962 memcpy(&mac_addr->addr_bytes[3], &random, 3);
966 * Virtual Function device init
969 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
970 struct rte_eth_dev *eth_dev)
974 struct rte_pci_device *pci_dev;
975 struct ixgbe_hw *hw =
976 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
977 struct ixgbe_vfta * shadow_vfta =
978 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
979 struct ixgbe_hwstrip *hwstrip =
980 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
981 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
983 PMD_INIT_FUNC_TRACE();
985 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
986 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
987 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
989 /* for secondary processes, we don't initialise any further as primary
990 * has already done this work. Only check we don't need a different
992 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
993 if (eth_dev->data->scattered_rx)
994 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
998 pci_dev = eth_dev->pci_dev;
1000 hw->device_id = pci_dev->id.device_id;
1001 hw->vendor_id = pci_dev->id.vendor_id;
1002 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1004 /* initialize the vfta */
1005 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1007 /* initialize the hw strip bitmap*/
1008 memset(hwstrip, 0, sizeof(*hwstrip));
1010 /* Initialize the shared code (base driver) */
1011 diag = ixgbe_init_shared_code(hw);
1012 if (diag != IXGBE_SUCCESS) {
1013 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1017 /* init_mailbox_params */
1018 hw->mbx.ops.init_params(hw);
1020 /* Disable the interrupts for VF */
1021 ixgbevf_intr_disable(hw);
1023 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1024 diag = hw->mac.ops.reset_hw(hw);
1027 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1028 * the underlying PF driver has not assigned a MAC address to the VF.
1029 * In this case, assign a random MAC address.
1031 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1032 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1036 /* negotiate mailbox API version to use with the PF. */
1037 ixgbevf_negotiate_api(hw);
1039 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1040 ixgbevf_get_queues(hw, &tcs, &tc);
1042 /* Allocate memory for storing MAC addresses */
1043 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1044 hw->mac.num_rar_entries, 0);
1045 if (eth_dev->data->mac_addrs == NULL) {
1047 "Failed to allocate %u bytes needed to store "
1049 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1053 /* Generate a random MAC address, if none was assigned by PF. */
1054 if (is_zero_ether_addr(perm_addr)) {
1055 generate_random_mac_addr(perm_addr);
1056 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1058 rte_free(eth_dev->data->mac_addrs);
1059 eth_dev->data->mac_addrs = NULL;
1062 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1063 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1064 "%02x:%02x:%02x:%02x:%02x:%02x",
1065 perm_addr->addr_bytes[0],
1066 perm_addr->addr_bytes[1],
1067 perm_addr->addr_bytes[2],
1068 perm_addr->addr_bytes[3],
1069 perm_addr->addr_bytes[4],
1070 perm_addr->addr_bytes[5]);
1073 /* Copy the permanent MAC address */
1074 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1076 /* reset the hardware with the new settings */
1077 diag = hw->mac.ops.start_hw(hw);
1083 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1087 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1088 eth_dev->data->port_id, pci_dev->id.vendor_id,
1089 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1094 static struct eth_driver rte_ixgbe_pmd = {
1096 .name = "rte_ixgbe_pmd",
1097 .id_table = pci_id_ixgbe_map,
1098 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1100 .eth_dev_init = eth_ixgbe_dev_init,
1101 .dev_private_size = sizeof(struct ixgbe_adapter),
1105 * virtual function driver struct
1107 static struct eth_driver rte_ixgbevf_pmd = {
1109 .name = "rte_ixgbevf_pmd",
1110 .id_table = pci_id_ixgbevf_map,
1111 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1113 .eth_dev_init = eth_ixgbevf_dev_init,
1114 .dev_private_size = sizeof(struct ixgbe_adapter),
1118 * Driver initialization routine.
1119 * Invoked once at EAL init time.
1120 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1123 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1125 PMD_INIT_FUNC_TRACE();
1127 rte_eth_driver_register(&rte_ixgbe_pmd);
1132 * VF Driver initialization routine.
1133 * Invoked one at EAL init time.
1134 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1137 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1139 PMD_INIT_FUNC_TRACE();
1141 rte_eth_driver_register(&rte_ixgbevf_pmd);
1146 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1148 struct ixgbe_hw *hw =
1149 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1150 struct ixgbe_vfta * shadow_vfta =
1151 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1156 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1157 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1158 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1163 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1165 /* update local VFTA copy */
1166 shadow_vfta->vfta[vid_idx] = vfta;
1172 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1175 ixgbe_vlan_hw_strip_enable(dev, queue);
1177 ixgbe_vlan_hw_strip_disable(dev, queue);
1181 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1183 struct ixgbe_hw *hw =
1184 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186 /* Only the high 16-bits is valid */
1187 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1191 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1193 struct ixgbe_hw *hw =
1194 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1197 PMD_INIT_FUNC_TRACE();
1199 /* Filter Table Disable */
1200 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1201 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1203 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1207 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1209 struct ixgbe_hw *hw =
1210 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211 struct ixgbe_vfta * shadow_vfta =
1212 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1216 PMD_INIT_FUNC_TRACE();
1218 /* Filter Table Enable */
1219 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1220 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1221 vlnctrl |= IXGBE_VLNCTRL_VFE;
1223 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1225 /* write whatever is in local vfta copy */
1226 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1227 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1231 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1233 struct ixgbe_hwstrip *hwstrip =
1234 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1236 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1240 IXGBE_SET_HWSTRIP(hwstrip, queue);
1242 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1246 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1248 struct ixgbe_hw *hw =
1249 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1252 PMD_INIT_FUNC_TRACE();
1254 if (hw->mac.type == ixgbe_mac_82598EB) {
1255 /* No queue level support */
1256 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1260 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1261 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1262 ctrl &= ~IXGBE_RXDCTL_VME;
1263 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1265 /* record those setting for HW strip per queue */
1266 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1270 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1272 struct ixgbe_hw *hw =
1273 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276 PMD_INIT_FUNC_TRACE();
1278 if (hw->mac.type == ixgbe_mac_82598EB) {
1279 /* No queue level supported */
1280 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1284 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1285 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1286 ctrl |= IXGBE_RXDCTL_VME;
1287 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1289 /* record those setting for HW strip per queue */
1290 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1294 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1296 struct ixgbe_hw *hw =
1297 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301 PMD_INIT_FUNC_TRACE();
1303 if (hw->mac.type == ixgbe_mac_82598EB) {
1304 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1305 ctrl &= ~IXGBE_VLNCTRL_VME;
1306 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1309 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1310 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1311 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1312 ctrl &= ~IXGBE_RXDCTL_VME;
1313 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1315 /* record those setting for HW strip per queue */
1316 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1322 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1324 struct ixgbe_hw *hw =
1325 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1329 PMD_INIT_FUNC_TRACE();
1331 if (hw->mac.type == ixgbe_mac_82598EB) {
1332 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1333 ctrl |= IXGBE_VLNCTRL_VME;
1334 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1337 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1338 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1339 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1340 ctrl |= IXGBE_RXDCTL_VME;
1341 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1343 /* record those setting for HW strip per queue */
1344 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1350 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1352 struct ixgbe_hw *hw =
1353 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1356 PMD_INIT_FUNC_TRACE();
1358 /* DMATXCTRL: Geric Double VLAN Disable */
1359 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1360 ctrl &= ~IXGBE_DMATXCTL_GDV;
1361 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1363 /* CTRL_EXT: Global Double VLAN Disable */
1364 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1365 ctrl &= ~IXGBE_EXTENDED_VLAN;
1366 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1371 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1373 struct ixgbe_hw *hw =
1374 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1377 PMD_INIT_FUNC_TRACE();
1379 /* DMATXCTRL: Geric Double VLAN Enable */
1380 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1381 ctrl |= IXGBE_DMATXCTL_GDV;
1382 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1384 /* CTRL_EXT: Global Double VLAN Enable */
1385 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1386 ctrl |= IXGBE_EXTENDED_VLAN;
1387 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1390 * VET EXT field in the EXVET register = 0x8100 by default
1391 * So no need to change. Same to VT field of DMATXCTL register
1396 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1398 if(mask & ETH_VLAN_STRIP_MASK){
1399 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1400 ixgbe_vlan_hw_strip_enable_all(dev);
1402 ixgbe_vlan_hw_strip_disable_all(dev);
1405 if(mask & ETH_VLAN_FILTER_MASK){
1406 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1407 ixgbe_vlan_hw_filter_enable(dev);
1409 ixgbe_vlan_hw_filter_disable(dev);
1412 if(mask & ETH_VLAN_EXTEND_MASK){
1413 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1414 ixgbe_vlan_hw_extend_enable(dev);
1416 ixgbe_vlan_hw_extend_disable(dev);
1421 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1423 struct ixgbe_hw *hw =
1424 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1425 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1426 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1427 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1428 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1432 ixgbe_dev_configure(struct rte_eth_dev *dev)
1434 struct ixgbe_interrupt *intr =
1435 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1437 PMD_INIT_FUNC_TRACE();
1439 /* set flag to update link status after init */
1440 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1446 * Configure device link speed and setup link.
1447 * It returns 0 on success.
1450 ixgbe_dev_start(struct rte_eth_dev *dev)
1452 struct ixgbe_hw *hw =
1453 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454 struct ixgbe_vf_info *vfinfo =
1455 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1456 int err, link_up = 0, negotiate = 0;
1462 PMD_INIT_FUNC_TRACE();
1464 /* IXGBE devices don't support half duplex */
1465 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1466 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1467 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1468 dev->data->dev_conf.link_duplex,
1469 dev->data->port_id);
1474 hw->adapter_stopped = FALSE;
1475 ixgbe_stop_adapter(hw);
1477 /* reinitialize adapter
1478 * this calls reset and start */
1479 status = ixgbe_pf_reset_hw(hw);
1482 hw->mac.ops.start_hw(hw);
1483 hw->mac.get_link_status = true;
1485 /* configure PF module if SRIOV enabled */
1486 ixgbe_pf_host_configure(dev);
1488 /* initialize transmission unit */
1489 ixgbe_dev_tx_init(dev);
1491 /* This can fail when allocating mbufs for descriptor rings */
1492 err = ixgbe_dev_rx_init(dev);
1494 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1498 ixgbe_dev_rxtx_start(dev);
1500 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1501 err = hw->mac.ops.setup_sfp(hw);
1506 /* Turn on the laser */
1507 ixgbe_enable_tx_laser(hw);
1509 /* Skip link setup if loopback mode is enabled for 82599. */
1510 if (hw->mac.type == ixgbe_mac_82599EB &&
1511 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1512 goto skip_link_setup;
1514 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1517 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1521 switch(dev->data->dev_conf.link_speed) {
1522 case ETH_LINK_SPEED_AUTONEG:
1523 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1524 IXGBE_LINK_SPEED_82599_AUTONEG :
1525 IXGBE_LINK_SPEED_82598_AUTONEG;
1527 case ETH_LINK_SPEED_100:
1529 * Invalid for 82598 but error will be detected by
1530 * ixgbe_setup_link()
1532 speed = IXGBE_LINK_SPEED_100_FULL;
1534 case ETH_LINK_SPEED_1000:
1535 speed = IXGBE_LINK_SPEED_1GB_FULL;
1537 case ETH_LINK_SPEED_10000:
1538 speed = IXGBE_LINK_SPEED_10GB_FULL;
1541 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1542 dev->data->dev_conf.link_speed,
1543 dev->data->port_id);
1547 err = ixgbe_setup_link(hw, speed, link_up);
1553 /* check if lsc interrupt is enabled */
1554 if (dev->data->dev_conf.intr_conf.lsc != 0)
1555 ixgbe_dev_lsc_interrupt_setup(dev);
1557 /* resume enabled intr since hw reset */
1558 ixgbe_enable_intr(dev);
1560 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1561 ETH_VLAN_EXTEND_MASK;
1562 ixgbe_vlan_offload_set(dev, mask);
1564 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1565 /* Enable vlan filtering for VMDq */
1566 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1569 /* Configure DCB hw */
1570 ixgbe_configure_dcb(dev);
1572 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1573 err = ixgbe_fdir_configure(dev);
1578 /* Restore vf rate limit */
1579 if (vfinfo != NULL) {
1580 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1581 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1582 if (vfinfo[vf].tx_rate[idx] != 0)
1583 ixgbe_set_vf_rate_limit(dev, vf,
1584 vfinfo[vf].tx_rate[idx],
1588 ixgbe_restore_statistics_mapping(dev);
1593 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1594 ixgbe_dev_clear_queues(dev);
1599 * Stop device: disable rx and tx functions to allow for reconfiguring.
1602 ixgbe_dev_stop(struct rte_eth_dev *dev)
1604 struct rte_eth_link link;
1605 struct ixgbe_hw *hw =
1606 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607 struct ixgbe_vf_info *vfinfo =
1608 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1611 PMD_INIT_FUNC_TRACE();
1613 /* disable interrupts */
1614 ixgbe_disable_intr(hw);
1617 ixgbe_pf_reset_hw(hw);
1618 hw->adapter_stopped = FALSE;
1621 ixgbe_stop_adapter(hw);
1623 for (vf = 0; vfinfo != NULL &&
1624 vf < dev->pci_dev->max_vfs; vf++)
1625 vfinfo[vf].clear_to_send = false;
1627 /* Turn off the laser */
1628 ixgbe_disable_tx_laser(hw);
1630 ixgbe_dev_clear_queues(dev);
1632 /* Clear stored conf */
1633 dev->data->scattered_rx = 0;
1635 /* Clear recorded link status */
1636 memset(&link, 0, sizeof(link));
1637 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1641 * Set device link up: enable tx laser.
1644 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1646 struct ixgbe_hw *hw =
1647 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648 if (hw->mac.type == ixgbe_mac_82599EB) {
1649 #ifdef RTE_NIC_BYPASS
1650 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1651 /* Not suported in bypass mode */
1652 PMD_INIT_LOG(ERR, "Set link up is not supported "
1653 "by device id 0x%x", hw->device_id);
1657 /* Turn on the laser */
1658 ixgbe_enable_tx_laser(hw);
1662 PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1668 * Set device link down: disable tx laser.
1671 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1673 struct ixgbe_hw *hw =
1674 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675 if (hw->mac.type == ixgbe_mac_82599EB) {
1676 #ifdef RTE_NIC_BYPASS
1677 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1678 /* Not suported in bypass mode */
1679 PMD_INIT_LOG(ERR, "Set link down is not supported "
1680 "by device id 0x%x", hw->device_id);
1684 /* Turn off the laser */
1685 ixgbe_disable_tx_laser(hw);
1689 PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1695 * Reest and stop device.
1698 ixgbe_dev_close(struct rte_eth_dev *dev)
1700 struct ixgbe_hw *hw =
1701 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1703 PMD_INIT_FUNC_TRACE();
1705 ixgbe_pf_reset_hw(hw);
1707 ixgbe_dev_stop(dev);
1708 hw->adapter_stopped = 1;
1710 ixgbe_disable_pcie_master(hw);
1712 /* reprogram the RAR[0] in case user changed it. */
1713 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1717 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1720 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1722 struct ixgbe_hw *hw =
1723 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724 struct ixgbe_hw_stats *hw_stats =
1725 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1726 uint32_t bprc, lxon, lxoff, total;
1727 uint64_t total_missed_rx, total_qbrc, total_qprc;
1730 total_missed_rx = 0;
1734 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1735 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1736 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1737 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1739 for (i = 0; i < 8; i++) {
1741 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1742 /* global total per queue */
1743 hw_stats->mpc[i] += mp;
1744 /* Running comprehensive total for stats display */
1745 total_missed_rx += hw_stats->mpc[i];
1746 if (hw->mac.type == ixgbe_mac_82598EB)
1747 hw_stats->rnbc[i] +=
1748 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1749 hw_stats->pxontxc[i] +=
1750 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1751 hw_stats->pxonrxc[i] +=
1752 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1753 hw_stats->pxofftxc[i] +=
1754 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1755 hw_stats->pxoffrxc[i] +=
1756 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1757 hw_stats->pxon2offc[i] +=
1758 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1760 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1761 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1762 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1763 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1764 hw_stats->qbrc[i] +=
1765 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1766 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1767 hw_stats->qbtc[i] +=
1768 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1769 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1771 total_qprc += hw_stats->qprc[i];
1772 total_qbrc += hw_stats->qbrc[i];
1774 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1775 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1776 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1778 /* Note that gprc counts missed packets */
1779 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1781 if (hw->mac.type != ixgbe_mac_82598EB) {
1782 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1783 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1784 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1785 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1786 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1787 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1788 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1789 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1791 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1792 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1793 /* 82598 only has a counter in the high register */
1794 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1795 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1796 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1800 * Workaround: mprc hardware is incorrectly counting
1801 * broadcasts, so for now we subtract those.
1803 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1804 hw_stats->bprc += bprc;
1805 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1806 if (hw->mac.type == ixgbe_mac_82598EB)
1807 hw_stats->mprc -= bprc;
1809 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1810 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1811 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1812 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1813 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1814 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1816 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1817 hw_stats->lxontxc += lxon;
1818 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1819 hw_stats->lxofftxc += lxoff;
1820 total = lxon + lxoff;
1822 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1823 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1824 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1825 hw_stats->gptc -= total;
1826 hw_stats->mptc -= total;
1827 hw_stats->ptc64 -= total;
1828 hw_stats->gotc -= total * ETHER_MIN_LEN;
1830 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1831 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1832 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1833 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1834 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1835 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1836 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1837 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1838 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1839 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1840 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1841 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1842 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1843 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1844 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1845 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1846 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1847 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1848 /* Only read FCOE on 82599 */
1849 if (hw->mac.type != ixgbe_mac_82598EB) {
1850 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1851 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1852 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1853 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1854 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1860 /* Fill out the rte_eth_stats statistics structure */
1861 stats->ipackets = total_qprc;
1862 stats->ibytes = total_qbrc;
1863 stats->opackets = hw_stats->gptc;
1864 stats->obytes = hw_stats->gotc;
1865 stats->imcasts = hw_stats->mprc;
1867 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1868 stats->q_ipackets[i] = hw_stats->qprc[i];
1869 stats->q_opackets[i] = hw_stats->qptc[i];
1870 stats->q_ibytes[i] = hw_stats->qbrc[i];
1871 stats->q_obytes[i] = hw_stats->qbtc[i];
1872 stats->q_errors[i] = hw_stats->qprdc[i];
1876 stats->ibadcrc = hw_stats->crcerrs;
1877 stats->ibadlen = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1878 stats->imissed = total_missed_rx;
1879 stats->ierrors = stats->ibadcrc +
1882 hw_stats->illerrc + hw_stats->errbc;
1887 /* XON/XOFF pause frames */
1888 stats->tx_pause_xon = hw_stats->lxontxc;
1889 stats->rx_pause_xon = hw_stats->lxonrxc;
1890 stats->tx_pause_xoff = hw_stats->lxofftxc;
1891 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1893 /* Flow Director Stats registers */
1894 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1895 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1896 stats->fdirmatch = hw_stats->fdirmatch;
1897 stats->fdirmiss = hw_stats->fdirmiss;
1901 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1903 struct ixgbe_hw_stats *stats =
1904 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1906 /* HW registers are cleared on read */
1907 ixgbe_dev_stats_get(dev, NULL);
1909 /* Reset software totals */
1910 memset(stats, 0, sizeof(*stats));
1914 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1916 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1918 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1920 /* Good Rx packet, include VF loopback */
1921 UPDATE_VF_STAT(IXGBE_VFGPRC,
1922 hw_stats->last_vfgprc, hw_stats->vfgprc);
1924 /* Good Rx octets, include VF loopback */
1925 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1926 hw_stats->last_vfgorc, hw_stats->vfgorc);
1928 /* Good Tx packet, include VF loopback */
1929 UPDATE_VF_STAT(IXGBE_VFGPTC,
1930 hw_stats->last_vfgptc, hw_stats->vfgptc);
1932 /* Good Tx octets, include VF loopback */
1933 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1934 hw_stats->last_vfgotc, hw_stats->vfgotc);
1936 /* Rx Multicst Packet */
1937 UPDATE_VF_STAT(IXGBE_VFMPRC,
1938 hw_stats->last_vfmprc, hw_stats->vfmprc);
1943 memset(stats, 0, sizeof(*stats));
1944 stats->ipackets = hw_stats->vfgprc;
1945 stats->ibytes = hw_stats->vfgorc;
1946 stats->opackets = hw_stats->vfgptc;
1947 stats->obytes = hw_stats->vfgotc;
1948 stats->imcasts = hw_stats->vfmprc;
1952 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1954 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1955 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1957 /* Sync HW register to the last stats */
1958 ixgbevf_dev_stats_get(dev, NULL);
1960 /* reset HW current stats*/
1961 hw_stats->vfgprc = 0;
1962 hw_stats->vfgorc = 0;
1963 hw_stats->vfgptc = 0;
1964 hw_stats->vfgotc = 0;
1965 hw_stats->vfmprc = 0;
1970 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1972 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1975 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1976 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1977 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1978 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1979 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1980 dev_info->max_vfs = dev->pci_dev->max_vfs;
1981 if (hw->mac.type == ixgbe_mac_82598EB)
1982 dev_info->max_vmdq_pools = ETH_16_POOLS;
1984 dev_info->max_vmdq_pools = ETH_64_POOLS;
1985 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1986 dev_info->rx_offload_capa =
1987 DEV_RX_OFFLOAD_VLAN_STRIP |
1988 DEV_RX_OFFLOAD_IPV4_CKSUM |
1989 DEV_RX_OFFLOAD_UDP_CKSUM |
1990 DEV_RX_OFFLOAD_TCP_CKSUM;
1991 dev_info->tx_offload_capa =
1992 DEV_TX_OFFLOAD_VLAN_INSERT |
1993 DEV_TX_OFFLOAD_IPV4_CKSUM |
1994 DEV_TX_OFFLOAD_UDP_CKSUM |
1995 DEV_TX_OFFLOAD_TCP_CKSUM |
1996 DEV_TX_OFFLOAD_SCTP_CKSUM |
1997 DEV_TX_OFFLOAD_TCP_TSO;
1999 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2001 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2002 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2003 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2005 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2009 dev_info->default_txconf = (struct rte_eth_txconf) {
2011 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2012 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2013 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2015 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2016 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2017 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2018 ETH_TXQ_FLAGS_NOOFFLOADS,
2020 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2024 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2025 struct rte_eth_dev_info *dev_info)
2027 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2030 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2031 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2032 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2033 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2034 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2035 dev_info->max_vfs = dev->pci_dev->max_vfs;
2036 if (hw->mac.type == ixgbe_mac_82598EB)
2037 dev_info->max_vmdq_pools = ETH_16_POOLS;
2039 dev_info->max_vmdq_pools = ETH_64_POOLS;
2040 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2041 DEV_RX_OFFLOAD_IPV4_CKSUM |
2042 DEV_RX_OFFLOAD_UDP_CKSUM |
2043 DEV_RX_OFFLOAD_TCP_CKSUM;
2044 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2045 DEV_TX_OFFLOAD_IPV4_CKSUM |
2046 DEV_TX_OFFLOAD_UDP_CKSUM |
2047 DEV_TX_OFFLOAD_TCP_CKSUM |
2048 DEV_TX_OFFLOAD_SCTP_CKSUM;
2050 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2052 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2053 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2054 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2056 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2060 dev_info->default_txconf = (struct rte_eth_txconf) {
2062 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2063 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2064 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2066 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2067 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2068 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2069 ETH_TXQ_FLAGS_NOOFFLOADS,
2073 /* return 0 means link status changed, -1 means not changed */
2075 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2077 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078 struct rte_eth_link link, old;
2079 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2083 link.link_status = 0;
2084 link.link_speed = 0;
2085 link.link_duplex = 0;
2086 memset(&old, 0, sizeof(old));
2087 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2089 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2090 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2091 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2093 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2095 link.link_speed = ETH_LINK_SPEED_100;
2096 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2097 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2098 if (link.link_status == old.link_status)
2103 if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2104 !hw->mac.get_link_status) {
2105 memcpy(&link, &old, sizeof(link));
2110 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2111 if (link.link_status == old.link_status)
2115 link.link_status = 1;
2116 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2118 switch (link_speed) {
2120 case IXGBE_LINK_SPEED_UNKNOWN:
2121 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2122 link.link_speed = ETH_LINK_SPEED_100;
2125 case IXGBE_LINK_SPEED_100_FULL:
2126 link.link_speed = ETH_LINK_SPEED_100;
2129 case IXGBE_LINK_SPEED_1GB_FULL:
2130 link.link_speed = ETH_LINK_SPEED_1000;
2133 case IXGBE_LINK_SPEED_10GB_FULL:
2134 link.link_speed = ETH_LINK_SPEED_10000;
2137 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2139 if (link.link_status == old.link_status)
2146 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2148 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2152 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2153 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2157 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2159 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2162 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2163 fctrl &= (~IXGBE_FCTRL_UPE);
2164 if (dev->data->all_multicast == 1)
2165 fctrl |= IXGBE_FCTRL_MPE;
2167 fctrl &= (~IXGBE_FCTRL_MPE);
2168 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2172 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2174 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2178 fctrl |= IXGBE_FCTRL_MPE;
2179 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2183 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2185 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188 if (dev->data->promiscuous == 1)
2189 return; /* must remain in all_multicast mode */
2191 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2192 fctrl &= (~IXGBE_FCTRL_MPE);
2193 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2197 * It clears the interrupt causes and enables the interrupt.
2198 * It will be called once only during nic initialized.
2201 * Pointer to struct rte_eth_dev.
2204 * - On success, zero.
2205 * - On failure, a negative value.
2208 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2210 struct ixgbe_interrupt *intr =
2211 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2213 ixgbe_dev_link_status_print(dev);
2214 intr->mask |= IXGBE_EICR_LSC;
2220 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2223 * Pointer to struct rte_eth_dev.
2226 * - On success, zero.
2227 * - On failure, a negative value.
2230 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2234 struct ixgbe_interrupt *intr =
2235 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2237 /* clear all cause mask */
2238 ixgbe_disable_intr(hw);
2240 /* read-on-clear nic registers here */
2241 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2242 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2245 if (eicr & IXGBE_EICR_LSC) {
2246 /* set flag for async link update */
2247 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2250 if (eicr & IXGBE_EICR_MAILBOX)
2251 intr->flags |= IXGBE_FLAG_MAILBOX;
2257 * It gets and then prints the link status.
2260 * Pointer to struct rte_eth_dev.
2263 * - On success, zero.
2264 * - On failure, a negative value.
2267 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2269 struct rte_eth_link link;
2271 memset(&link, 0, sizeof(link));
2272 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2273 if (link.link_status) {
2274 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2275 (int)(dev->data->port_id),
2276 (unsigned)link.link_speed,
2277 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2278 "full-duplex" : "half-duplex");
2280 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2281 (int)(dev->data->port_id));
2283 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2284 dev->pci_dev->addr.domain,
2285 dev->pci_dev->addr.bus,
2286 dev->pci_dev->addr.devid,
2287 dev->pci_dev->addr.function);
2291 * It executes link_update after knowing an interrupt occurred.
2294 * Pointer to struct rte_eth_dev.
2297 * - On success, zero.
2298 * - On failure, a negative value.
2301 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2303 struct ixgbe_interrupt *intr =
2304 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2306 struct rte_eth_link link;
2307 int intr_enable_delay = false;
2309 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2311 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2312 ixgbe_pf_mbx_process(dev);
2313 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2316 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2317 /* get the link status before link update, for predicting later */
2318 memset(&link, 0, sizeof(link));
2319 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2321 ixgbe_dev_link_update(dev, 0);
2324 if (!link.link_status)
2325 /* handle it 1 sec later, wait it being stable */
2326 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2327 /* likely to down */
2329 /* handle it 4 sec later, wait it being stable */
2330 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2332 ixgbe_dev_link_status_print(dev);
2334 intr_enable_delay = true;
2337 if (intr_enable_delay) {
2338 if (rte_eal_alarm_set(timeout * 1000,
2339 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2340 PMD_DRV_LOG(ERR, "Error setting alarm");
2342 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2343 ixgbe_enable_intr(dev);
2344 rte_intr_enable(&(dev->pci_dev->intr_handle));
2352 * Interrupt handler which shall be registered for alarm callback for delayed
2353 * handling specific interrupt to wait for the stable nic state. As the
2354 * NIC interrupt state is not stable for ixgbe after link is just down,
2355 * it needs to wait 4 seconds to get the stable status.
2358 * Pointer to interrupt handle.
2360 * The address of parameter (struct rte_eth_dev *) regsitered before.
2366 ixgbe_dev_interrupt_delayed_handler(void *param)
2368 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2369 struct ixgbe_interrupt *intr =
2370 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2371 struct ixgbe_hw *hw =
2372 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2376 if (eicr & IXGBE_EICR_MAILBOX)
2377 ixgbe_pf_mbx_process(dev);
2379 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2380 ixgbe_dev_link_update(dev, 0);
2381 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2382 ixgbe_dev_link_status_print(dev);
2383 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2386 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2387 ixgbe_enable_intr(dev);
2388 rte_intr_enable(&(dev->pci_dev->intr_handle));
2392 * Interrupt handler triggered by NIC for handling
2393 * specific interrupt.
2396 * Pointer to interrupt handle.
2398 * The address of parameter (struct rte_eth_dev *) regsitered before.
2404 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2407 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2408 ixgbe_dev_interrupt_get_status(dev);
2409 ixgbe_dev_interrupt_action(dev);
2413 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2415 struct ixgbe_hw *hw;
2417 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2418 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2422 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2424 struct ixgbe_hw *hw;
2426 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2431 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2433 struct ixgbe_hw *hw;
2439 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441 fc_conf->pause_time = hw->fc.pause_time;
2442 fc_conf->high_water = hw->fc.high_water[0];
2443 fc_conf->low_water = hw->fc.low_water[0];
2444 fc_conf->send_xon = hw->fc.send_xon;
2445 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2448 * Return rx_pause status according to actual setting of
2451 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2452 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2458 * Return tx_pause status according to actual setting of
2461 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2462 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2467 if (rx_pause && tx_pause)
2468 fc_conf->mode = RTE_FC_FULL;
2470 fc_conf->mode = RTE_FC_RX_PAUSE;
2472 fc_conf->mode = RTE_FC_TX_PAUSE;
2474 fc_conf->mode = RTE_FC_NONE;
2480 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2482 struct ixgbe_hw *hw;
2484 uint32_t rx_buf_size;
2485 uint32_t max_high_water;
2487 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2494 PMD_INIT_FUNC_TRACE();
2496 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497 if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2499 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2500 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2503 * At least reserve one Ethernet frame for watermark
2504 * high_water/low_water in kilo bytes for ixgbe
2506 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2507 if ((fc_conf->high_water > max_high_water) ||
2508 (fc_conf->high_water < fc_conf->low_water)) {
2509 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2510 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2514 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2515 hw->fc.pause_time = fc_conf->pause_time;
2516 hw->fc.high_water[0] = fc_conf->high_water;
2517 hw->fc.low_water[0] = fc_conf->low_water;
2518 hw->fc.send_xon = fc_conf->send_xon;
2520 err = ixgbe_fc_enable(hw);
2522 /* Not negotiated is not an error case */
2523 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2525 /* check if we want to forward MAC frames - driver doesn't have native
2526 * capability to do that, so we'll write the registers ourselves */
2528 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2530 /* set or clear MFLCN.PMCF bit depending on configuration */
2531 if (fc_conf->mac_ctrl_frame_fwd != 0)
2532 mflcn |= IXGBE_MFLCN_PMCF;
2534 mflcn &= ~IXGBE_MFLCN_PMCF;
2536 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2537 IXGBE_WRITE_FLUSH(hw);
2542 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2547 * ixgbe_pfc_enable_generic - Enable flow control
2548 * @hw: pointer to hardware structure
2549 * @tc_num: traffic class number
2550 * Enable flow control according to the current settings.
2553 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2556 uint32_t mflcn_reg, fccfg_reg;
2558 uint32_t fcrtl, fcrth;
2562 /* Validate the water mark configuration */
2563 if (!hw->fc.pause_time) {
2564 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2568 /* Low water mark of zero causes XOFF floods */
2569 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2570 /* High/Low water can not be 0 */
2571 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2572 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2573 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2577 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2578 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2579 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2583 /* Negotiate the fc mode to use */
2584 ixgbe_fc_autoneg(hw);
2586 /* Disable any previous flow control settings */
2587 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2588 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2590 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2591 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2593 switch (hw->fc.current_mode) {
2596 * If the count of enabled RX Priority Flow control >1,
2597 * and the TX pause can not be disabled
2600 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2601 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2602 if (reg & IXGBE_FCRTH_FCEN)
2606 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2608 case ixgbe_fc_rx_pause:
2610 * Rx Flow control is enabled and Tx Flow control is
2611 * disabled by software override. Since there really
2612 * isn't a way to advertise that we are capable of RX
2613 * Pause ONLY, we will advertise that we support both
2614 * symmetric and asymmetric Rx PAUSE. Later, we will
2615 * disable the adapter's ability to send PAUSE frames.
2617 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2619 * If the count of enabled RX Priority Flow control >1,
2620 * and the TX pause can not be disabled
2623 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2624 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2625 if (reg & IXGBE_FCRTH_FCEN)
2629 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2631 case ixgbe_fc_tx_pause:
2633 * Tx Flow control is enabled, and Rx Flow control is
2634 * disabled by software override.
2636 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2639 /* Flow control (both Rx and Tx) is enabled by SW override. */
2640 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2641 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2644 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2645 ret_val = IXGBE_ERR_CONFIG;
2650 /* Set 802.3x based flow control settings. */
2651 mflcn_reg |= IXGBE_MFLCN_DPF;
2652 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2653 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2655 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2656 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2657 hw->fc.high_water[tc_num]) {
2658 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2659 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2660 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2662 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2664 * In order to prevent Tx hangs when the internal Tx
2665 * switch is enabled we must set the high water mark
2666 * to the maximum FCRTH value. This allows the Tx
2667 * switch to function even under heavy Rx workloads.
2669 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2671 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2673 /* Configure pause time (2 TCs per register) */
2674 reg = hw->fc.pause_time * 0x00010001;
2675 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2676 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2678 /* Configure flow control refresh threshold value */
2679 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2686 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2688 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2691 if(hw->mac.type != ixgbe_mac_82598EB) {
2692 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2698 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2701 uint32_t rx_buf_size;
2702 uint32_t max_high_water;
2704 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2705 struct ixgbe_hw *hw =
2706 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707 struct ixgbe_dcb_config *dcb_config =
2708 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2710 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2717 PMD_INIT_FUNC_TRACE();
2719 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2720 tc_num = map[pfc_conf->priority];
2721 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2722 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2724 * At least reserve one Ethernet frame for watermark
2725 * high_water/low_water in kilo bytes for ixgbe
2727 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2728 if ((pfc_conf->fc.high_water > max_high_water) ||
2729 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2730 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2731 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2735 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2736 hw->fc.pause_time = pfc_conf->fc.pause_time;
2737 hw->fc.send_xon = pfc_conf->fc.send_xon;
2738 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2739 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2741 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2743 /* Not negotiated is not an error case */
2744 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2747 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2752 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2753 struct rte_eth_rss_reta_entry64 *reta_conf,
2758 uint16_t idx, shift;
2759 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2761 PMD_INIT_FUNC_TRACE();
2762 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2763 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2764 "(%d) doesn't match the number hardware can supported "
2765 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2769 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2770 idx = i / RTE_RETA_GROUP_SIZE;
2771 shift = i % RTE_RETA_GROUP_SIZE;
2772 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2776 if (mask == IXGBE_4_BIT_MASK)
2779 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2780 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2781 if (mask & (0x1 << j))
2782 reta |= reta_conf[idx].reta[shift + j] <<
2785 reta |= r & (IXGBE_8_BIT_MASK <<
2788 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2795 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2796 struct rte_eth_rss_reta_entry64 *reta_conf,
2801 uint16_t idx, shift;
2802 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2804 PMD_INIT_FUNC_TRACE();
2805 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2806 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2807 "(%d) doesn't match the number hardware can supported "
2808 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2812 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2813 idx = i / RTE_RETA_GROUP_SIZE;
2814 shift = i % RTE_RETA_GROUP_SIZE;
2815 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2820 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2821 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2822 if (mask & (0x1 << j))
2823 reta_conf[idx].reta[shift + j] =
2824 ((reta >> (CHAR_BIT * j)) &
2833 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2834 uint32_t index, uint32_t pool)
2836 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837 uint32_t enable_addr = 1;
2839 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2843 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2845 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847 ixgbe_clear_rar(hw, index);
2851 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2855 struct ixgbe_hw *hw;
2856 struct rte_eth_dev_info dev_info;
2857 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2859 ixgbe_dev_info_get(dev, &dev_info);
2861 /* check that mtu is within the allowed range */
2862 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2865 /* refuse mtu that requires the support of scattered packets when this
2866 * feature has not been enabled before. */
2867 if (!dev->data->scattered_rx &&
2868 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2869 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2872 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2875 /* switch to jumbo mode if needed */
2876 if (frame_size > ETHER_MAX_LEN) {
2877 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2878 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2880 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2881 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2883 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2885 /* update max frame size */
2886 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2888 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2889 maxfrs &= 0x0000FFFF;
2890 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2891 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2897 * Virtual Function operations
2900 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2902 PMD_INIT_FUNC_TRACE();
2904 /* Clear interrupt mask to stop from interrupts being generated */
2905 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2907 IXGBE_WRITE_FLUSH(hw);
2911 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2913 struct rte_eth_conf* conf = &dev->data->dev_conf;
2915 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2916 dev->data->port_id);
2919 * VF has no ability to enable/disable HW CRC
2920 * Keep the persistent behavior the same as Host PF
2922 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2923 if (!conf->rxmode.hw_strip_crc) {
2924 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2925 conf->rxmode.hw_strip_crc = 1;
2928 if (conf->rxmode.hw_strip_crc) {
2929 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2930 conf->rxmode.hw_strip_crc = 0;
2938 ixgbevf_dev_start(struct rte_eth_dev *dev)
2940 struct ixgbe_hw *hw =
2941 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2944 PMD_INIT_FUNC_TRACE();
2946 hw->mac.ops.reset_hw(hw);
2947 hw->mac.get_link_status = true;
2949 /* negotiate mailbox API version to use with the PF. */
2950 ixgbevf_negotiate_api(hw);
2952 ixgbevf_dev_tx_init(dev);
2954 /* This can fail when allocating mbufs for descriptor rings */
2955 err = ixgbevf_dev_rx_init(dev);
2957 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2958 ixgbe_dev_clear_queues(dev);
2963 ixgbevf_set_vfta_all(dev,1);
2966 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2967 ETH_VLAN_EXTEND_MASK;
2968 ixgbevf_vlan_offload_set(dev, mask);
2970 ixgbevf_dev_rxtx_start(dev);
2976 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2978 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2980 PMD_INIT_FUNC_TRACE();
2982 hw->adapter_stopped = TRUE;
2983 ixgbe_stop_adapter(hw);
2986 * Clear what we set, but we still keep shadow_vfta to
2987 * restore after device starts
2989 ixgbevf_set_vfta_all(dev,0);
2991 /* Clear stored conf */
2992 dev->data->scattered_rx = 0;
2994 ixgbe_dev_clear_queues(dev);
2998 ixgbevf_dev_close(struct rte_eth_dev *dev)
3000 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3002 PMD_INIT_FUNC_TRACE();
3006 ixgbevf_dev_stop(dev);
3008 /* reprogram the RAR[0] in case user changed it. */
3009 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3012 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3014 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015 struct ixgbe_vfta * shadow_vfta =
3016 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3017 int i = 0, j = 0, vfta = 0, mask = 1;
3019 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3020 vfta = shadow_vfta->vfta[i];
3023 for (j = 0; j < 32; j++){
3025 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3034 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3036 struct ixgbe_hw *hw =
3037 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3038 struct ixgbe_vfta * shadow_vfta =
3039 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3040 uint32_t vid_idx = 0;
3041 uint32_t vid_bit = 0;
3044 PMD_INIT_FUNC_TRACE();
3046 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3047 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3049 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3052 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3053 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3055 /* Save what we set and retore it after device reset */
3057 shadow_vfta->vfta[vid_idx] |= vid_bit;
3059 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3065 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3067 struct ixgbe_hw *hw =
3068 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3071 PMD_INIT_FUNC_TRACE();
3073 if(queue >= hw->mac.max_rx_queues)
3076 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3078 ctrl |= IXGBE_RXDCTL_VME;
3080 ctrl &= ~IXGBE_RXDCTL_VME;
3081 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3083 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3087 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3089 struct ixgbe_hw *hw =
3090 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3094 /* VF function only support hw strip feature, others are not support */
3095 if(mask & ETH_VLAN_STRIP_MASK){
3096 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3098 for(i=0; i < hw->mac.max_rx_queues; i++)
3099 ixgbevf_vlan_strip_queue_set(dev,i,on);
3104 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3108 /* we only need to do this if VMDq is enabled */
3109 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3110 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3111 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3119 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3121 uint32_t vector = 0;
3122 switch (hw->mac.mc_filter_type) {
3123 case 0: /* use bits [47:36] of the address */
3124 vector = ((uc_addr->addr_bytes[4] >> 4) |
3125 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3127 case 1: /* use bits [46:35] of the address */
3128 vector = ((uc_addr->addr_bytes[4] >> 3) |
3129 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3131 case 2: /* use bits [45:34] of the address */
3132 vector = ((uc_addr->addr_bytes[4] >> 2) |
3133 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3135 case 3: /* use bits [43:32] of the address */
3136 vector = ((uc_addr->addr_bytes[4]) |
3137 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3139 default: /* Invalid mc_filter_type */
3143 /* vector can only be 12-bits or boundary will be exceeded */
3149 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3157 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3158 const uint32_t ixgbe_uta_bit_shift = 5;
3159 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3160 const uint32_t bit1 = 0x1;
3162 struct ixgbe_hw *hw =
3163 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3164 struct ixgbe_uta_info *uta_info =
3165 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3167 /* The UTA table only exists on 82599 hardware and newer */
3168 if (hw->mac.type < ixgbe_mac_82599EB)
3171 vector = ixgbe_uta_vector(hw,mac_addr);
3172 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3173 uta_shift = vector & ixgbe_uta_bit_mask;
3175 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3179 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3181 uta_info->uta_in_use++;
3182 reg_val |= (bit1 << uta_shift);
3183 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3185 uta_info->uta_in_use--;
3186 reg_val &= ~(bit1 << uta_shift);
3187 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3190 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3192 if (uta_info->uta_in_use > 0)
3193 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3194 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3196 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3202 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3205 struct ixgbe_hw *hw =
3206 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3207 struct ixgbe_uta_info *uta_info =
3208 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3210 /* The UTA table only exists on 82599 hardware and newer */
3211 if (hw->mac.type < ixgbe_mac_82599EB)
3215 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3216 uta_info->uta_shadow[i] = ~0;
3217 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3220 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3221 uta_info->uta_shadow[i] = 0;
3222 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3230 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3232 uint32_t new_val = orig_val;
3234 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3235 new_val |= IXGBE_VMOLR_AUPE;
3236 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3237 new_val |= IXGBE_VMOLR_ROMPE;
3238 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3239 new_val |= IXGBE_VMOLR_ROPE;
3240 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3241 new_val |= IXGBE_VMOLR_BAM;
3242 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3243 new_val |= IXGBE_VMOLR_MPE;
3249 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3250 uint16_t rx_mask, uint8_t on)
3254 struct ixgbe_hw *hw =
3255 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3256 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3258 if (hw->mac.type == ixgbe_mac_82598EB) {
3259 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3260 " on 82599 hardware and newer");
3263 if (ixgbe_vmdq_mode_check(hw) < 0)
3266 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3273 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3279 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3283 const uint8_t bit1 = 0x1;
3285 struct ixgbe_hw *hw =
3286 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288 if (ixgbe_vmdq_mode_check(hw) < 0)
3291 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3292 reg = IXGBE_READ_REG(hw, addr);
3300 IXGBE_WRITE_REG(hw, addr,reg);
3306 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3310 const uint8_t bit1 = 0x1;
3312 struct ixgbe_hw *hw =
3313 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3315 if (ixgbe_vmdq_mode_check(hw) < 0)
3318 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3319 reg = IXGBE_READ_REG(hw, addr);
3327 IXGBE_WRITE_REG(hw, addr,reg);
3333 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3334 uint64_t pool_mask, uint8_t vlan_on)
3338 struct ixgbe_hw *hw =
3339 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3341 if (ixgbe_vmdq_mode_check(hw) < 0)
3343 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3344 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3345 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3354 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3355 struct rte_eth_vmdq_mirror_conf *mirror_conf,
3356 uint8_t rule_id, uint8_t on)
3358 uint32_t mr_ctl,vlvf;
3359 uint32_t mp_lsb = 0;
3360 uint32_t mv_msb = 0;
3361 uint32_t mv_lsb = 0;
3362 uint32_t mp_msb = 0;
3365 uint64_t vlan_mask = 0;
3367 const uint8_t pool_mask_offset = 32;
3368 const uint8_t vlan_mask_offset = 32;
3369 const uint8_t dst_pool_offset = 8;
3370 const uint8_t rule_mr_offset = 4;
3371 const uint8_t mirror_rule_mask= 0x0F;
3373 struct ixgbe_mirror_info *mr_info =
3374 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3375 struct ixgbe_hw *hw =
3376 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378 if (ixgbe_vmdq_mode_check(hw) < 0)
3381 /* Check if vlan mask is valid */
3382 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3383 if (mirror_conf->vlan.vlan_mask == 0)
3387 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3388 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3389 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3390 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3391 /* search vlan id related pool vlan filter index */
3392 reg_index = ixgbe_find_vlvf_slot(hw,
3393 mirror_conf->vlan.vlan_id[i]);
3396 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3397 if ((vlvf & IXGBE_VLVF_VIEN) &&
3398 ((vlvf & IXGBE_VLVF_VLANID_MASK)
3399 == mirror_conf->vlan.vlan_id[i]))
3400 vlan_mask |= (1ULL << reg_index);
3407 mv_lsb = vlan_mask & 0xFFFFFFFF;
3408 mv_msb = vlan_mask >> vlan_mask_offset;
3410 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3411 mirror_conf->vlan.vlan_mask;
3412 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3413 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3414 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3415 mirror_conf->vlan.vlan_id[i];
3420 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3421 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3422 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3427 * if enable pool mirror, write related pool mask register,if disable
3428 * pool mirror, clear PFMRVM register
3430 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3432 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3433 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3434 mr_info->mr_conf[rule_id].pool_mask =
3435 mirror_conf->pool_mask;
3440 mr_info->mr_conf[rule_id].pool_mask = 0;
3444 /* read mirror control register and recalculate it */
3445 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3448 mr_ctl |= mirror_conf->rule_type_mask;
3449 mr_ctl &= mirror_rule_mask;
3450 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3452 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3454 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3455 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3457 /* write mirrror control register */
3458 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3460 /* write pool mirrror control register */
3461 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3462 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3463 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3466 /* write VLAN mirrror control register */
3467 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3468 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3469 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3477 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3480 uint32_t lsb_val = 0;
3481 uint32_t msb_val = 0;
3482 const uint8_t rule_mr_offset = 4;
3484 struct ixgbe_hw *hw =
3485 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486 struct ixgbe_mirror_info *mr_info =
3487 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3489 if (ixgbe_vmdq_mode_check(hw) < 0)
3492 memset(&mr_info->mr_conf[rule_id], 0,
3493 sizeof(struct rte_eth_vmdq_mirror_conf));
3495 /* clear PFVMCTL register */
3496 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3498 /* clear pool mask register */
3499 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3500 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3502 /* clear vlan mask register */
3503 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3504 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3509 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3510 uint16_t queue_idx, uint16_t tx_rate)
3512 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3513 uint32_t rf_dec, rf_int;
3515 uint16_t link_speed = dev->data->dev_link.link_speed;
3517 if (queue_idx >= hw->mac.max_tx_queues)
3521 /* Calculate the rate factor values to set */
3522 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3523 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3524 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3526 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3527 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3528 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3529 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3535 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3536 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3539 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3540 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3541 IXGBE_MAX_JUMBO_FRAME_SIZE))
3542 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3543 IXGBE_MMW_SIZE_JUMBO_FRAME);
3545 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3546 IXGBE_MMW_SIZE_DEFAULT);
3548 /* Set RTTBCNRC of queue X */
3549 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3550 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3551 IXGBE_WRITE_FLUSH(hw);
3556 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3557 uint16_t tx_rate, uint64_t q_msk)
3559 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3560 struct ixgbe_vf_info *vfinfo =
3561 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3562 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3563 uint32_t queue_stride =
3564 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3565 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3566 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3567 uint16_t total_rate = 0;
3569 if (queue_end >= hw->mac.max_tx_queues)
3572 if (vfinfo != NULL) {
3573 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3576 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3578 total_rate += vfinfo[vf_idx].tx_rate[idx];
3583 /* Store tx_rate for this vf. */
3584 for (idx = 0; idx < nb_q_per_pool; idx++) {
3585 if (((uint64_t)0x1 << idx) & q_msk) {
3586 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3587 vfinfo[vf].tx_rate[idx] = tx_rate;
3588 total_rate += tx_rate;
3592 if (total_rate > dev->data->dev_link.link_speed) {
3594 * Reset stored TX rate of the VF if it causes exceed
3597 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3601 /* Set RTTBCNRC of each queue/pool for vf X */
3602 for (; queue_idx <= queue_end; queue_idx++) {
3604 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3612 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3613 __attribute__((unused)) uint32_t index,
3614 __attribute__((unused)) uint32_t pool)
3616 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3621 * operation. Trap this case to avoid exhausting the [very limited]
3622 * set of PF resources used to store VF MAC addresses.
3624 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3626 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3629 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3633 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3635 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3636 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3637 struct ether_addr *mac_addr;
3642 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3643 * not support the deletion of a given MAC address.
3644 * Instead, it imposes to delete all MAC addresses, then to add again
3645 * all MAC addresses with the exception of the one to be deleted.
3647 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3650 * Add again all MAC addresses, with the exception of the deleted one
3651 * and of the permanent MAC address.
3653 for (i = 0, mac_addr = dev->data->mac_addrs;
3654 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3655 /* Skip the deleted MAC address */
3658 /* Skip NULL MAC addresses */
3659 if (is_zero_ether_addr(mac_addr))
3661 /* Skip the permanent MAC address */
3662 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3664 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3667 "Adding again MAC address "
3668 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3670 mac_addr->addr_bytes[0],
3671 mac_addr->addr_bytes[1],
3672 mac_addr->addr_bytes[2],
3673 mac_addr->addr_bytes[3],
3674 mac_addr->addr_bytes[4],
3675 mac_addr->addr_bytes[5],
3684 * dev: Pointer to struct rte_eth_dev.
3685 * filter: ponter to the filter that will be added.
3686 * rx_queue: the queue id the filter assigned to.
3689 * - On success, zero.
3690 * - On failure, a negative value.
3693 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3694 struct rte_syn_filter *filter, uint16_t rx_queue)
3696 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3699 if (hw->mac.type != ixgbe_mac_82599EB)
3702 if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3705 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3707 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3710 synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3711 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3713 if (filter->hig_pri)
3714 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3716 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3718 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3726 * dev: Pointer to struct rte_eth_dev.
3729 * - On success, zero.
3730 * - On failure, a negative value.
3733 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3735 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3738 if (hw->mac.type != ixgbe_mac_82599EB)
3741 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3743 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3745 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3750 * get the syn filter's info
3753 * dev: Pointer to struct rte_eth_dev.
3754 * filter: ponter to the filter that returns.
3755 * *rx_queue: pointer to the queue id the filter assigned to.
3758 * - On success, zero.
3759 * - On failure, a negative value.
3762 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3763 struct rte_syn_filter *filter, uint16_t *rx_queue)
3766 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3769 if (hw->mac.type != ixgbe_mac_82599EB)
3772 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3773 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3774 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3775 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3781 static inline enum ixgbe_5tuple_protocol
3782 convert_protocol_type(uint8_t protocol_value)
3784 if (protocol_value == IPPROTO_TCP)
3785 return IXGBE_FILTER_PROTOCOL_TCP;
3786 else if (protocol_value == IPPROTO_UDP)
3787 return IXGBE_FILTER_PROTOCOL_UDP;
3788 else if (protocol_value == IPPROTO_SCTP)
3789 return IXGBE_FILTER_PROTOCOL_SCTP;
3791 return IXGBE_FILTER_PROTOCOL_NONE;
3794 static inline uint8_t
3795 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3797 if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3799 else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3801 else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3802 return IPPROTO_SCTP;
3808 * add a 5tuple filter
3811 * dev: Pointer to struct rte_eth_dev.
3812 * index: the index the filter allocates.
3813 * filter: ponter to the filter that will be added.
3814 * rx_queue: the queue id the filter assigned to.
3817 * - On success, zero.
3818 * - On failure, a negative value.
3821 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3822 struct rte_5tuple_filter *filter, uint16_t rx_queue)
3824 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3825 uint32_t ftqf, sdpqf = 0;
3826 uint32_t l34timir = 0;
3827 uint8_t mask = 0xff;
3829 if (hw->mac.type != ixgbe_mac_82599EB)
3832 if (index >= IXGBE_MAX_FTQF_FILTERS ||
3833 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3834 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3835 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3836 return -EINVAL; /* filter index is out of range. */
3838 if (filter->tcp_flags) {
3839 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3843 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3844 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3845 return -EINVAL; /* filter index is in use. */
3848 sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3849 sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3851 ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3852 IXGBE_FTQF_PROTOCOL_MASK);
3853 ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3854 IXGBE_FTQF_PRIORITY_SHIFT);
3855 if (filter->src_ip_mask == 0) /* 0 means compare. */
3856 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3857 if (filter->dst_ip_mask == 0)
3858 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3859 if (filter->src_port_mask == 0)
3860 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3861 if (filter->dst_port_mask == 0)
3862 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3863 if (filter->protocol_mask == 0)
3864 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3865 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3866 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3867 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3869 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3870 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3871 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3872 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3874 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3875 l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3876 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3881 * remove a 5tuple filter
3884 * dev: Pointer to struct rte_eth_dev.
3885 * index: the index the filter allocates.
3888 * - On success, zero.
3889 * - On failure, a negative value.
3892 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3895 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3897 if (hw->mac.type != ixgbe_mac_82599EB)
3900 if (index >= IXGBE_MAX_FTQF_FILTERS)
3901 return -EINVAL; /* filter index is out of range. */
3903 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3904 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3905 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3906 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3907 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3912 * get a 5tuple filter
3915 * dev: Pointer to struct rte_eth_dev.
3916 * index: the index the filter allocates
3917 * filter: ponter to the filter that returns.
3918 * *rx_queue: pointer of the queue id the filter assigned to.
3921 * - On success, zero.
3922 * - On failure, a negative value.
3925 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3926 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3928 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3929 uint32_t sdpqf, ftqf, l34timir;
3931 enum ixgbe_5tuple_protocol proto;
3933 if (hw->mac.type != ixgbe_mac_82599EB)
3936 if (index >= IXGBE_MAX_FTQF_FILTERS)
3937 return -EINVAL; /* filter index is out of range. */
3939 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3940 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3941 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3942 filter->protocol = revert_protocol_type(proto);
3943 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3944 IXGBE_FTQF_PRIORITY_MASK;
3945 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3946 IXGBE_FTQF_5TUPLE_MASK_MASK);
3947 filter->src_ip_mask =
3948 (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3949 filter->dst_ip_mask =
3950 (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3951 filter->src_port_mask =
3952 (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3953 filter->dst_port_mask =
3954 (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3955 filter->protocol_mask =
3956 (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3958 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3959 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3960 IXGBE_SDPQF_DSTPORT_SHIFT;
3961 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3962 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3963 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3965 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3966 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3967 IXGBE_L34T_IMIR_QUEUE_SHIFT;
3974 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3976 struct ixgbe_hw *hw;
3977 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3979 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3981 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3984 /* refuse mtu that requires the support of scattered packets when this
3985 * feature has not been enabled before. */
3986 if (!dev->data->scattered_rx &&
3987 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3988 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3992 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3993 * request of the version 2.0 of the mailbox API.
3994 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3995 * of the mailbox API.
3996 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3997 * prior to 3.11.33 which contains the following change:
3998 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4000 ixgbevf_rlpml_set_vf(hw, max_frame);
4002 /* update max frame size */
4003 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4007 #define MAC_TYPE_FILTER_SUP(type) do {\
4008 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4009 (type) != ixgbe_mac_X550)\
4014 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4019 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4020 if (filter_info->ethertype_filters[i] == ethertype &&
4021 (filter_info->ethertype_mask & (1 << i)))
4028 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4033 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4034 if (!(filter_info->ethertype_mask & (1 << i))) {
4035 filter_info->ethertype_mask |= 1 << i;
4036 filter_info->ethertype_filters[i] = ethertype;
4044 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4047 if (idx >= IXGBE_MAX_ETQF_FILTERS)
4049 filter_info->ethertype_mask &= ~(1 << idx);
4050 filter_info->ethertype_filters[idx] = 0;
4055 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4056 struct rte_eth_ethertype_filter *filter,
4059 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4060 struct ixgbe_filter_info *filter_info =
4061 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4066 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4069 if (filter->ether_type == ETHER_TYPE_IPv4 ||
4070 filter->ether_type == ETHER_TYPE_IPv6) {
4071 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4072 " ethertype filter.", filter->ether_type);
4076 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4077 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4080 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4081 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4085 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4086 if (ret >= 0 && add) {
4087 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4088 filter->ether_type);
4091 if (ret < 0 && !add) {
4092 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4093 filter->ether_type);
4098 ret = ixgbe_ethertype_filter_insert(filter_info,
4099 filter->ether_type);
4101 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4104 etqf = IXGBE_ETQF_FILTER_EN;
4105 etqf |= (uint32_t)filter->ether_type;
4106 etqs |= (uint32_t)((filter->queue <<
4107 IXGBE_ETQS_RX_QUEUE_SHIFT) &
4108 IXGBE_ETQS_RX_QUEUE);
4109 etqs |= IXGBE_ETQS_QUEUE_EN;
4111 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4115 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4116 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4117 IXGBE_WRITE_FLUSH(hw);
4123 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4124 struct rte_eth_ethertype_filter *filter)
4126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127 struct ixgbe_filter_info *filter_info =
4128 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4129 uint32_t etqf, etqs;
4132 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4134 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4135 filter->ether_type);
4139 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4140 if (etqf & IXGBE_ETQF_FILTER_EN) {
4141 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4142 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4144 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4145 IXGBE_ETQS_RX_QUEUE_SHIFT;
4152 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4153 * @dev: pointer to rte_eth_dev structure
4154 * @filter_op:operation will be taken.
4155 * @arg: a pointer to specific structure corresponding to the filter_op
4158 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4159 enum rte_filter_op filter_op,
4162 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4165 MAC_TYPE_FILTER_SUP(hw->mac.type);
4167 if (filter_op == RTE_ETH_FILTER_NOP)
4171 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4176 switch (filter_op) {
4177 case RTE_ETH_FILTER_ADD:
4178 ret = ixgbe_add_del_ethertype_filter(dev,
4179 (struct rte_eth_ethertype_filter *)arg,
4182 case RTE_ETH_FILTER_DELETE:
4183 ret = ixgbe_add_del_ethertype_filter(dev,
4184 (struct rte_eth_ethertype_filter *)arg,
4187 case RTE_ETH_FILTER_GET:
4188 ret = ixgbe_get_ethertype_filter(dev,
4189 (struct rte_eth_ethertype_filter *)arg);
4192 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4200 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4201 enum rte_filter_type filter_type,
4202 enum rte_filter_op filter_op,
4207 switch (filter_type) {
4208 case RTE_ETH_FILTER_ETHERTYPE:
4209 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4212 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4220 static struct rte_driver rte_ixgbe_driver = {
4222 .init = rte_ixgbe_pmd_init,
4225 static struct rte_driver rte_ixgbevf_driver = {
4227 .init = rte_ixgbevf_pmd_init,
4230 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4231 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);