lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  96
  97 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  98
  99 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 100                 struct rte_eth_dev *eth_dev);
 101 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 102 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 104 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 105 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 106 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 107 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 108 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 109 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 110 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 111 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 112                                 int wait_to_complete);
 113 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_stats *stats);
 115 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 116 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 117                                              uint16_t queue_id,
 118                                              uint8_t stat_idx,
 119                                              uint8_t is_rx);
 120 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 121                                 struct rte_eth_dev_info *dev_info);
 122
 123 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 128 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 129                 uint16_t queue, bool on);
 130 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 131                 int on);
 132 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 133 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 134 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 135 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 136 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 137
 138 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 139 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 140 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 141                                struct rte_eth_fc_conf *fc_conf);
 142 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 143                                struct rte_eth_fc_conf *fc_conf);
 144 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 145                 struct rte_eth_pfc_conf *pfc_conf);
 146 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 147                 struct rte_eth_rss_reta *reta_conf);
 148 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 149                 struct rte_eth_rss_reta *reta_conf);
 150 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 154 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 155                 void *param);
 156 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 157 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 158                 uint32_t index, uint32_t pool);
 159 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 160 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 161
 162 /* For Virtual Function support */
 163 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 164                 struct rte_eth_dev *eth_dev);
 165 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 166 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 167 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 168 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 169 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 170 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 171                 struct rte_eth_stats *stats);
 172 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 173 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 174                 uint16_t vlan_id, int on);
 175 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 176                 uint16_t queue, int on);
 177 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 178 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 179
 180 /* For Eth VMDQ APIs support */
 181 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 182                 ether_addr* mac_addr,uint8_t on);
 183 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 184 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 185                 uint16_t rx_mask, uint8_t on);
 186 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 187 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 188 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 189                 uint64_t pool_mask,uint8_t vlan_on);
 190 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 191                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 192                 uint8_t rule_id, uint8_t on);
 193 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 194                 uint8_t rule_id);
 195
 196 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 197                 uint16_t queue_idx, uint16_t tx_rate);
 198 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 199                 uint16_t tx_rate, uint64_t q_msk);
 200
 201 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 202                                  struct ether_addr *mac_addr,
 203                                  uint32_t index, uint32_t pool);
 204 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 205 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 206                         struct rte_syn_filter *filter, uint16_t rx_queue);
 207 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 208 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 209                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 210 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 211                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 212 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 213                         uint16_t index);
 214 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 215                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 216 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 217                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 218 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 219                         uint16_t index);
 220 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 221                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 222
 223 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 224
 225 /*
 226  * Define VF Stats MACRO for Non "cleared on read" register
 227  */
 228 #define UPDATE_VF_STAT(reg, last, cur)                          \
 229 {                                                               \
 230         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 231         cur += latest - last;                                   \
 232         last = latest;                                          \
 233 }
 234
 235 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 236 {                                                                \
 237         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 238         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 239         u64 latest = ((new_msb << 32) | new_lsb);                \
 240         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 241         last = latest;                                           \
 242 }
 243
 244 #define IXGBE_SET_HWSTRIP(h, q) do{\
 245                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 246                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 247                 (h)->bitmap[idx] |= 1 << bit;\
 248         }while(0)
 249
 250 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 251                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 252                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 253                 (h)->bitmap[idx] &= ~(1 << bit);\
 254         }while(0)
 255
 256 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 257                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 258                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 259                 (r) = (h)->bitmap[idx] >> bit & 1;\
 260         }while(0)
 261
 262 /*
 263  * The set of PCI devices this driver supports
 264  */
 265 static struct rte_pci_id pci_id_ixgbe_map[] = {
 266
 267 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 268 #include "rte_pci_dev_ids.h"
 269
 270 { .vendor_id = 0, /* sentinel */ },
 271 };
 272
 273
 274 /*
 275  * The set of PCI devices this driver supports (for 82599 VF)
 276  */
 277 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 278
 279 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 280 #include "rte_pci_dev_ids.h"
 281 { .vendor_id = 0, /* sentinel */ },
 282
 283 };
 284
 285 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 286         .dev_configure        = ixgbe_dev_configure,
 287         .dev_start            = ixgbe_dev_start,
 288         .dev_stop             = ixgbe_dev_stop,
 289         .dev_set_link_up    = ixgbe_dev_set_link_up,
 290         .dev_set_link_down  = ixgbe_dev_set_link_down,
 291         .dev_close            = ixgbe_dev_close,
 292         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 293         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 294         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 295         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 296         .link_update          = ixgbe_dev_link_update,
 297         .stats_get            = ixgbe_dev_stats_get,
 298         .stats_reset          = ixgbe_dev_stats_reset,
 299         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 300         .dev_infos_get        = ixgbe_dev_info_get,
 301         .mtu_set              = ixgbe_dev_mtu_set,
 302         .vlan_filter_set      = ixgbe_vlan_filter_set,
 303         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 304         .vlan_offload_set     = ixgbe_vlan_offload_set,
 305         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 306         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 307         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 308         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 309         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 310         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 311         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 312         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 313         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 314         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 315         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 316         .dev_led_on           = ixgbe_dev_led_on,
 317         .dev_led_off          = ixgbe_dev_led_off,
 318         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 319         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 320         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 321         .mac_addr_add         = ixgbe_add_rar,
 322         .mac_addr_remove      = ixgbe_remove_rar,
 323         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 324         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 325         .mirror_rule_set      = ixgbe_mirror_rule_set,
 326         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 327         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 328         .set_vf_rx            = ixgbe_set_pool_rx,
 329         .set_vf_tx            = ixgbe_set_pool_tx,
 330         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 331         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 332         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 333         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 334         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 335         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 336         .fdir_infos_get               = ixgbe_fdir_info_get,
 337         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 338         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 339         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 340         .fdir_set_masks               = ixgbe_fdir_set_masks,
 341         .reta_update          = ixgbe_dev_rss_reta_update,
 342         .reta_query           = ixgbe_dev_rss_reta_query,
 343 #ifdef RTE_NIC_BYPASS
 344         .bypass_init          = ixgbe_bypass_init,
 345         .bypass_state_set     = ixgbe_bypass_state_store,
 346         .bypass_state_show    = ixgbe_bypass_state_show,
 347         .bypass_event_set     = ixgbe_bypass_event_store,
 348         .bypass_event_show    = ixgbe_bypass_event_show,
 349         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 350         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 351         .bypass_ver_show      = ixgbe_bypass_ver_show,
 352         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 353 #endif /* RTE_NIC_BYPASS */
 354         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 355         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 356         .add_syn_filter          = ixgbe_add_syn_filter,
 357         .remove_syn_filter       = ixgbe_remove_syn_filter,
 358         .get_syn_filter          = ixgbe_get_syn_filter,
 359         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 360         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 361         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 362         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 363         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 364         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 365 };
 366
 367 /*
 368  * dev_ops for virtual function, bare necessities for basic vf
 369  * operation have been implemented
 370  */
 371 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 372
 373         .dev_configure        = ixgbevf_dev_configure,
 374         .dev_start            = ixgbevf_dev_start,
 375         .dev_stop             = ixgbevf_dev_stop,
 376         .link_update          = ixgbe_dev_link_update,
 377         .stats_get            = ixgbevf_dev_stats_get,
 378         .stats_reset          = ixgbevf_dev_stats_reset,
 379         .dev_close            = ixgbevf_dev_close,
 380         .dev_infos_get        = ixgbe_dev_info_get,
 381         .mtu_set              = ixgbevf_dev_set_mtu,
 382         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 383         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 384         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 385         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 386         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 387         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 388         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 389         .mac_addr_add         = ixgbevf_add_mac_addr,
 390         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 391 };
 392
 393 /**
 394  * Atomically reads the link status information from global
 395  * structure rte_eth_dev.
 396  *
 397  * @param dev
 398  *   - Pointer to the structure rte_eth_dev to read from.
 399  *   - Pointer to the buffer to be saved with the link status.
 400  *
 401  * @return
 402  *   - On success, zero.
 403  *   - On failure, negative value.
 404  */
 405 static inline int
 406 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 407                                 struct rte_eth_link *link)
 408 {
 409         struct rte_eth_link *dst = link;
 410         struct rte_eth_link *src = &(dev->data->dev_link);
 411
 412         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 413                                         *(uint64_t *)src) == 0)
 414                 return -1;
 415
 416         return 0;
 417 }
 418
 419 /**
 420  * Atomically writes the link status information into global
 421  * structure rte_eth_dev.
 422  *
 423  * @param dev
 424  *   - Pointer to the structure rte_eth_dev to read from.
 425  *   - Pointer to the buffer to be saved with the link status.
 426  *
 427  * @return
 428  *   - On success, zero.
 429  *   - On failure, negative value.
 430  */
 431 static inline int
 432 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 433                                 struct rte_eth_link *link)
 434 {
 435         struct rte_eth_link *dst = &(dev->data->dev_link);
 436         struct rte_eth_link *src = link;
 437
 438         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 439                                         *(uint64_t *)src) == 0)
 440                 return -1;
 441
 442         return 0;
 443 }
 444
 445 /*
 446  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 447  */
 448 static inline int
 449 ixgbe_is_sfp(struct ixgbe_hw *hw)
 450 {
 451         switch (hw->phy.type) {
 452         case ixgbe_phy_sfp_avago:
 453         case ixgbe_phy_sfp_ftl:
 454         case ixgbe_phy_sfp_intel:
 455         case ixgbe_phy_sfp_unknown:
 456         case ixgbe_phy_sfp_passive_tyco:
 457         case ixgbe_phy_sfp_passive_unknown:
 458                 return 1;
 459         default:
 460                 return 0;
 461         }
 462 }
 463
 464 static inline int32_t
 465 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 466 {
 467         uint32_t ctrl_ext;
 468         int32_t status;
 469
 470         status = ixgbe_reset_hw(hw);
 471
 472         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 473         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 474         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 475         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 476         IXGBE_WRITE_FLUSH(hw);
 477
 478         return status;
 479 }
 480
 481 static inline void
 482 ixgbe_enable_intr(struct rte_eth_dev *dev)
 483 {
 484         struct ixgbe_interrupt *intr =
 485                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 486         struct ixgbe_hw *hw =
 487                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 488
 489         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 490         IXGBE_WRITE_FLUSH(hw);
 491 }
 492
 493 /*
 494  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 495  */
 496 static void
 497 ixgbe_disable_intr(struct ixgbe_hw *hw)
 498 {
 499         PMD_INIT_FUNC_TRACE();
 500
 501         if (hw->mac.type == ixgbe_mac_82598EB) {
 502                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 503         } else {
 504                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 505                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 506                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 507         }
 508         IXGBE_WRITE_FLUSH(hw);
 509 }
 510
 511 /*
 512  * This function resets queue statistics mapping registers.
 513  * From Niantic datasheet, Initialization of Statistics section:
 514  * "...if software requires the queue counters, the RQSMR and TQSM registers
 515  * must be re-programmed following a device reset.
 516  */
 517 static void
 518 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 519 {
 520         uint32_t i;
 521
 522         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 523                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 524                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 525         }
 526 }
 527
 528
 529 static int
 530 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 531                                   uint16_t queue_id,
 532                                   uint8_t stat_idx,
 533                                   uint8_t is_rx)
 534 {
 535 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 536 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 537 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 538
 539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 540         struct ixgbe_stat_mapping_registers *stat_mappings =
 541                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 542         uint32_t qsmr_mask = 0;
 543         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 544         uint32_t q_map;
 545         uint8_t n, offset;
 546
 547         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 548                 return -ENOSYS;
 549
 550         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 551                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 552
 553         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 554         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 555                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 556                 return -EIO;
 557         }
 558         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 559
 560         /* Now clear any previous stat_idx set */
 561         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 562         if (!is_rx)
 563                 stat_mappings->tqsm[n] &= ~clearing_mask;
 564         else
 565                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 566
 567         q_map = (uint32_t)stat_idx;
 568         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 569         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 570         if (!is_rx)
 571                 stat_mappings->tqsm[n] |= qsmr_mask;
 572         else
 573                 stat_mappings->rqsmr[n] |= qsmr_mask;
 574
 575         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 576                      "%s[%d] = 0x%08x\n",
 577                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 578                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 579
 580         /* Now write the mapping in the appropriate register */
 581         if (is_rx) {
 582                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 583                              stat_mappings->rqsmr[n], n);
 584                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 585         }
 586         else {
 587                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 588                              stat_mappings->tqsm[n], n);
 589                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 590         }
 591         return 0;
 592 }
 593
 594 static void
 595 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 596 {
 597         struct ixgbe_stat_mapping_registers *stat_mappings =
 598                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 600         int i;
 601
 602         /* write whatever was in stat mapping table to the NIC */
 603         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 604                 /* rx */
 605                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 606
 607                 /* tx */
 608                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 609         }
 610 }
 611
 612 static void
 613 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 614 {
 615         uint8_t i;
 616         struct ixgbe_dcb_tc_config *tc;
 617         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 618
 619         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 620         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 621         for (i = 0; i < dcb_max_tc; i++) {
 622                 tc = &dcb_config->tc_config[i];
 623                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 624                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 625                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 626                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 627                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 628                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 629                 tc->pfc = ixgbe_dcb_pfc_disabled;
 630         }
 631
 632         /* Initialize default user to priority mapping, UPx->TC0 */
 633         tc = &dcb_config->tc_config[0];
 634         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 635         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 636         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 637                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 638                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 639         }
 640         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 641         dcb_config->pfc_mode_enable = false;
 642         dcb_config->vt_mode = true;
 643         dcb_config->round_robin_enable = false;
 644         /* support all DCB capabilities in 82599 */
 645         dcb_config->support.capabilities = 0xFF;
 646
 647         /*we only support 4 Tcs for X540*/
 648         if (hw->mac.type == ixgbe_mac_X540) {
 649                 dcb_config->num_tcs.pg_tcs = 4;
 650                 dcb_config->num_tcs.pfc_tcs = 4;
 651         }
 652 }
 653
 654 /*
 655  * Ensure that all locks are released before first NVM or PHY access
 656  */
 657 static void
 658 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 659 {
 660         uint16_t mask;
 661
 662         /*
 663          * Phy lock should not fail in this early stage. If this is the case,
 664          * it is due to an improper exit of the application.
 665          * So force the release of the faulty lock. Release of common lock
 666          * is done automatically by swfw_sync function.
 667          */
 668         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 669         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 670                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 671         }
 672         ixgbe_release_swfw_semaphore(hw, mask);
 673
 674         /*
 675          * These ones are more tricky since they are common to all ports; but
 676          * swfw_sync retries last long enough (1s) to be almost sure that if
 677          * lock can not be taken it is due to an improper lock of the
 678          * semaphore.
 679          */
 680         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 681         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 682                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 683         }
 684         ixgbe_release_swfw_semaphore(hw, mask);
 685 }
 686
 687 /*
 688  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 689  * It returns 0 on success.
 690  */
 691 static int
 692 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 693                      struct rte_eth_dev *eth_dev)
 694 {
 695         struct rte_pci_device *pci_dev;
 696         struct ixgbe_hw *hw =
 697                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 698         struct ixgbe_vfta * shadow_vfta =
 699                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 700         struct ixgbe_hwstrip *hwstrip =
 701                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 702         struct ixgbe_dcb_config *dcb_config =
 703                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 704         uint32_t ctrl_ext;
 705         uint16_t csum;
 706         int diag, i;
 707
 708         PMD_INIT_FUNC_TRACE();
 709
 710         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 711         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 712         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 713
 714         /* for secondary processes, we don't initialise any further as primary
 715          * has already done this work. Only check we don't need a different
 716          * RX function */
 717         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 718                 if (eth_dev->data->scattered_rx)
 719                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 720                 return 0;
 721         }
 722         pci_dev = eth_dev->pci_dev;
 723
 724         /* Vendor and Device ID need to be set before init of shared code */
 725         hw->device_id = pci_dev->id.device_id;
 726         hw->vendor_id = pci_dev->id.vendor_id;
 727         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 728 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 729         hw->allow_unsupported_sfp = 1;
 730 #endif
 731
 732         /* Initialize the shared code (base driver) */
 733 #ifdef RTE_NIC_BYPASS
 734         diag = ixgbe_bypass_init_shared_code(hw);
 735 #else
 736         diag = ixgbe_init_shared_code(hw);
 737 #endif /* RTE_NIC_BYPASS */
 738
 739         if (diag != IXGBE_SUCCESS) {
 740                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 741                 return -EIO;
 742         }
 743
 744         /* pick up the PCI bus settings for reporting later */
 745         ixgbe_get_bus_info(hw);
 746
 747         /* Unlock any pending hardware semaphore */
 748         ixgbe_swfw_lock_reset(hw);
 749
 750         /* Initialize DCB configuration*/
 751         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 752         ixgbe_dcb_init(hw,dcb_config);
 753         /* Get Hardware Flow Control setting */
 754         hw->fc.requested_mode = ixgbe_fc_full;
 755         hw->fc.current_mode = ixgbe_fc_full;
 756         hw->fc.pause_time = IXGBE_FC_PAUSE;
 757         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 758                 hw->fc.low_water[i] = IXGBE_FC_LO;
 759                 hw->fc.high_water[i] = IXGBE_FC_HI;
 760         }
 761         hw->fc.send_xon = 1;
 762
 763         /* Make sure we have a good EEPROM before we read from it */
 764         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 765         if (diag != IXGBE_SUCCESS) {
 766                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 767                 return -EIO;
 768         }
 769
 770 #ifdef RTE_NIC_BYPASS
 771         diag = ixgbe_bypass_init_hw(hw);
 772 #else
 773         diag = ixgbe_init_hw(hw);
 774 #endif /* RTE_NIC_BYPASS */
 775
 776         /*
 777          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 778          * is called too soon after the kernel driver unbinding/binding occurs.
 779          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 780          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 781          * also called. See ixgbe_identify_phy_82599(). The reason for the
 782          * failure is not known, and only occuts when virtualisation features
 783          * are disabled in the bios. A delay of 100ms  was found to be enough by
 784          * trial-and-error, and is doubled to be safe.
 785          */
 786         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 787                 rte_delay_ms(200);
 788                 diag = ixgbe_init_hw(hw);
 789         }
 790
 791         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 792                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 793                     "LOM.  Please be aware there may be issues associated "
 794                     "with your hardware.\n If you are experiencing problems "
 795                     "please contact your Intel or hardware representative "
 796                     "who provided you with this hardware.\n");
 797         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 798                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 799         if (diag) {
 800                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 801                 return -EIO;
 802         }
 803
 804         /* disable interrupt */
 805         ixgbe_disable_intr(hw);
 806
 807         /* reset mappings for queue statistics hw counters*/
 808         ixgbe_reset_qstat_mappings(hw);
 809
 810         /* Allocate memory for storing MAC addresses */
 811         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 812                         hw->mac.num_rar_entries, 0);
 813         if (eth_dev->data->mac_addrs == NULL) {
 814                 PMD_INIT_LOG(ERR,
 815                         "Failed to allocate %u bytes needed to store "
 816                         "MAC addresses",
 817                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 818                 return -ENOMEM;
 819         }
 820         /* Copy the permanent MAC address */
 821         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 822                         &eth_dev->data->mac_addrs[0]);
 823
 824         /* Allocate memory for storing hash filter MAC addresses */
 825         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 826                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 827         if (eth_dev->data->hash_mac_addrs == NULL) {
 828                 PMD_INIT_LOG(ERR,
 829                         "Failed to allocate %d bytes needed to store MAC addresses",
 830                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 831                 return -ENOMEM;
 832         }
 833
 834         /* initialize the vfta */
 835         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 836
 837         /* initialize the hw strip bitmap*/
 838         memset(hwstrip, 0, sizeof(*hwstrip));
 839
 840         /* initialize PF if max_vfs not zero */
 841         ixgbe_pf_host_init(eth_dev);
 842
 843         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 844         /* let hardware know driver is loaded */
 845         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 846         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 847         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 848         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 849         IXGBE_WRITE_FLUSH(hw);
 850
 851         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 852                 PMD_INIT_LOG(DEBUG,
 853                              "MAC: %d, PHY: %d, SFP+: %d<n",
 854                              (int) hw->mac.type, (int) hw->phy.type,
 855                              (int) hw->phy.sfp_type);
 856         else
 857                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 858                              (int) hw->mac.type, (int) hw->phy.type);
 859
 860         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 861                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 862                         pci_dev->id.device_id);
 863
 864         rte_intr_callback_register(&(pci_dev->intr_handle),
 865                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 866
 867         /* enable uio intr after callback register */
 868         rte_intr_enable(&(pci_dev->intr_handle));
 869
 870         /* enable support intr */
 871         ixgbe_enable_intr(eth_dev);
 872
 873         return 0;
 874 }
 875
 876
 877 /*
 878  * Negotiate mailbox API version with the PF.
 879  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 880  * Then we try to negotiate starting with the most recent one.
 881  * If all negotiation attempts fail, then we will proceed with
 882  * the default one (ixgbe_mbox_api_10).
 883  */
 884 static void
 885 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 886 {
 887         int32_t i;
 888
 889         /* start with highest supported, proceed down */
 890         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 891                 ixgbe_mbox_api_11,
 892                 ixgbe_mbox_api_10,
 893         };
 894
 895         for (i = 0;
 896                         i != RTE_DIM(sup_ver) &&
 897                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 898                         i++)
 899                 ;
 900 }
 901
 902 static void
 903 generate_random_mac_addr(struct ether_addr *mac_addr)
 904 {
 905         uint64_t random;
 906
 907         /* Set Organizationally Unique Identifier (OUI) prefix. */
 908         mac_addr->addr_bytes[0] = 0x00;
 909         mac_addr->addr_bytes[1] = 0x09;
 910         mac_addr->addr_bytes[2] = 0xC0;
 911         /* Force indication of locally assigned MAC address. */
 912         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 913         /* Generate the last 3 bytes of the MAC address with a random number. */
 914         random = rte_rand();
 915         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 916 }
 917
 918 /*
 919  * Virtual Function device init
 920  */
 921 static int
 922 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 923                      struct rte_eth_dev *eth_dev)
 924 {
 925         int diag;
 926         uint32_t tc, tcs;
 927         struct rte_pci_device *pci_dev;
 928         struct ixgbe_hw *hw =
 929                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 930         struct ixgbe_vfta * shadow_vfta =
 931                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 932         struct ixgbe_hwstrip *hwstrip =
 933                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 934         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 935
 936         PMD_INIT_FUNC_TRACE();
 937
 938         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 939         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 940         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 941
 942         /* for secondary processes, we don't initialise any further as primary
 943          * has already done this work. Only check we don't need a different
 944          * RX function */
 945         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 946                 if (eth_dev->data->scattered_rx)
 947                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 948                 return 0;
 949         }
 950
 951         pci_dev = eth_dev->pci_dev;
 952
 953         hw->device_id = pci_dev->id.device_id;
 954         hw->vendor_id = pci_dev->id.vendor_id;
 955         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 956
 957         /* initialize the vfta */
 958         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 959
 960         /* initialize the hw strip bitmap*/
 961         memset(hwstrip, 0, sizeof(*hwstrip));
 962
 963         /* Initialize the shared code (base driver) */
 964         diag = ixgbe_init_shared_code(hw);
 965         if (diag != IXGBE_SUCCESS) {
 966                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 967                 return -EIO;
 968         }
 969
 970         /* init_mailbox_params */
 971         hw->mbx.ops.init_params(hw);
 972
 973         /* Disable the interrupts for VF */
 974         ixgbevf_intr_disable(hw);
 975
 976         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
 977         diag = hw->mac.ops.reset_hw(hw);
 978
 979         /*
 980          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
 981          * the underlying PF driver has not assigned a MAC address to the VF.
 982          * In this case, assign a random MAC address.
 983          */
 984         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
 985                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 986                 return (diag);
 987         }
 988
 989         /* negotiate mailbox API version to use with the PF. */
 990         ixgbevf_negotiate_api(hw);
 991
 992         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
 993         ixgbevf_get_queues(hw, &tcs, &tc);
 994
 995         /* Allocate memory for storing MAC addresses */
 996         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 997                         hw->mac.num_rar_entries, 0);
 998         if (eth_dev->data->mac_addrs == NULL) {
 999                 PMD_INIT_LOG(ERR,
1000                         "Failed to allocate %u bytes needed to store "
1001                         "MAC addresses",
1002                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1003                 return -ENOMEM;
1004         }
1005
1006         /* Generate a random MAC address, if none was assigned by PF. */
1007         if (is_zero_ether_addr(perm_addr)) {
1008                 generate_random_mac_addr(perm_addr);
1009                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1010                 if (diag) {
1011                         rte_free(eth_dev->data->mac_addrs);
1012                         eth_dev->data->mac_addrs = NULL;
1013                         return diag;
1014                 }
1015                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1016                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1017                              "%02x:%02x:%02x:%02x:%02x:%02x",
1018                              perm_addr->addr_bytes[0],
1019                              perm_addr->addr_bytes[1],
1020                              perm_addr->addr_bytes[2],
1021                              perm_addr->addr_bytes[3],
1022                              perm_addr->addr_bytes[4],
1023                              perm_addr->addr_bytes[5]);
1024         }
1025
1026         /* Copy the permanent MAC address */
1027         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1028
1029         /* reset the hardware with the new settings */
1030         diag = hw->mac.ops.start_hw(hw);
1031         switch (diag) {
1032                 case  0:
1033                         break;
1034
1035                 default:
1036                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1037                         return (-EIO);
1038         }
1039
1040         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
1041                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
1042                          "ixgbe_mac_82599_vf");
1043
1044         return 0;
1045 }
1046
1047 static struct eth_driver rte_ixgbe_pmd = {
1048         {
1049                 .name = "rte_ixgbe_pmd",
1050                 .id_table = pci_id_ixgbe_map,
1051                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1052         },
1053         .eth_dev_init = eth_ixgbe_dev_init,
1054         .dev_private_size = sizeof(struct ixgbe_adapter),
1055 };
1056
1057 /*
1058  * virtual function driver struct
1059  */
1060 static struct eth_driver rte_ixgbevf_pmd = {
1061         {
1062                 .name = "rte_ixgbevf_pmd",
1063                 .id_table = pci_id_ixgbevf_map,
1064                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1065         },
1066         .eth_dev_init = eth_ixgbevf_dev_init,
1067         .dev_private_size = sizeof(struct ixgbe_adapter),
1068 };
1069
1070 /*
1071  * Driver initialization routine.
1072  * Invoked once at EAL init time.
1073  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1074  */
1075 static int
1076 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1077 {
1078         PMD_INIT_FUNC_TRACE();
1079
1080         rte_eth_driver_register(&rte_ixgbe_pmd);
1081         return 0;
1082 }
1083
1084 /*
1085  * VF Driver initialization routine.
1086  * Invoked one at EAL init time.
1087  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1088  */
1089 static int
1090 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1091 {
1092         PMD_INIT_FUNC_TRACE();
1093
1094         rte_eth_driver_register(&rte_ixgbevf_pmd);
1095         return (0);
1096 }
1097
1098 static int
1099 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1100 {
1101         struct ixgbe_hw *hw =
1102                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103         struct ixgbe_vfta * shadow_vfta =
1104                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1105         uint32_t vfta;
1106         uint32_t vid_idx;
1107         uint32_t vid_bit;
1108
1109         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1110         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1111         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1112         if (on)
1113                 vfta |= vid_bit;
1114         else
1115                 vfta &= ~vid_bit;
1116         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1117
1118         /* update local VFTA copy */
1119         shadow_vfta->vfta[vid_idx] = vfta;
1120
1121         return 0;
1122 }
1123
1124 static void
1125 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1126 {
1127         if (on)
1128                 ixgbe_vlan_hw_strip_enable(dev, queue);
1129         else
1130                 ixgbe_vlan_hw_strip_disable(dev, queue);
1131 }
1132
1133 static void
1134 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1135 {
1136         struct ixgbe_hw *hw =
1137                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1138
1139         /* Only the high 16-bits is valid */
1140         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1141 }
1142
1143 void
1144 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1145 {
1146         struct ixgbe_hw *hw =
1147                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1148         uint32_t vlnctrl;
1149
1150         PMD_INIT_FUNC_TRACE();
1151
1152         /* Filter Table Disable */
1153         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1154         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1155
1156         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1157 }
1158
1159 void
1160 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1161 {
1162         struct ixgbe_hw *hw =
1163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1164         struct ixgbe_vfta * shadow_vfta =
1165                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1166         uint32_t vlnctrl;
1167         uint16_t i;
1168
1169         PMD_INIT_FUNC_TRACE();
1170
1171         /* Filter Table Enable */
1172         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1173         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1174         vlnctrl |= IXGBE_VLNCTRL_VFE;
1175
1176         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1177
1178         /* write whatever is in local vfta copy */
1179         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1180                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1181 }
1182
1183 static void
1184 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1185 {
1186         struct ixgbe_hwstrip *hwstrip =
1187                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1188
1189         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1190                 return;
1191
1192         if (on)
1193                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1194         else
1195                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1196 }
1197
1198 static void
1199 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1200 {
1201         struct ixgbe_hw *hw =
1202                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203         uint32_t ctrl;
1204
1205         PMD_INIT_FUNC_TRACE();
1206
1207         if (hw->mac.type == ixgbe_mac_82598EB) {
1208                 /* No queue level support */
1209                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1210                 return;
1211         }
1212         else {
1213                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1214                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1215                 ctrl &= ~IXGBE_RXDCTL_VME;
1216                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1217         }
1218         /* record those setting for HW strip per queue */
1219         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1220 }
1221
1222 static void
1223 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1224 {
1225         struct ixgbe_hw *hw =
1226                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1227         uint32_t ctrl;
1228
1229         PMD_INIT_FUNC_TRACE();
1230
1231         if (hw->mac.type == ixgbe_mac_82598EB) {
1232                 /* No queue level supported */
1233                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1234                 return;
1235         }
1236         else {
1237                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1238                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1239                 ctrl |= IXGBE_RXDCTL_VME;
1240                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1241         }
1242         /* record those setting for HW strip per queue */
1243         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1244 }
1245
1246 void
1247 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1248 {
1249         struct ixgbe_hw *hw =
1250                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1251         uint32_t ctrl;
1252         uint16_t i;
1253
1254         PMD_INIT_FUNC_TRACE();
1255
1256         if (hw->mac.type == ixgbe_mac_82598EB) {
1257                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1258                 ctrl &= ~IXGBE_VLNCTRL_VME;
1259                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1260         }
1261         else {
1262                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1263                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1264                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1265                         ctrl &= ~IXGBE_RXDCTL_VME;
1266                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1267
1268                         /* record those setting for HW strip per queue */
1269                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1270                 }
1271         }
1272 }
1273
1274 void
1275 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1276 {
1277         struct ixgbe_hw *hw =
1278                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1279         uint32_t ctrl;
1280         uint16_t i;
1281
1282         PMD_INIT_FUNC_TRACE();
1283
1284         if (hw->mac.type == ixgbe_mac_82598EB) {
1285                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1286                 ctrl |= IXGBE_VLNCTRL_VME;
1287                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1288         }
1289         else {
1290                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1291                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1292                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1293                         ctrl |= IXGBE_RXDCTL_VME;
1294                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1295
1296                         /* record those setting for HW strip per queue */
1297                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1298                 }
1299         }
1300 }
1301
1302 static void
1303 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1304 {
1305         struct ixgbe_hw *hw =
1306                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307         uint32_t ctrl;
1308
1309         PMD_INIT_FUNC_TRACE();
1310
1311         /* DMATXCTRL: Geric Double VLAN Disable */
1312         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1313         ctrl &= ~IXGBE_DMATXCTL_GDV;
1314         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1315
1316         /* CTRL_EXT: Global Double VLAN Disable */
1317         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1318         ctrl &= ~IXGBE_EXTENDED_VLAN;
1319         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1320
1321 }
1322
1323 static void
1324 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1325 {
1326         struct ixgbe_hw *hw =
1327                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1328         uint32_t ctrl;
1329
1330         PMD_INIT_FUNC_TRACE();
1331
1332         /* DMATXCTRL: Geric Double VLAN Enable */
1333         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1334         ctrl |= IXGBE_DMATXCTL_GDV;
1335         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1336
1337         /* CTRL_EXT: Global Double VLAN Enable */
1338         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1339         ctrl |= IXGBE_EXTENDED_VLAN;
1340         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1341
1342         /*
1343          * VET EXT field in the EXVET register = 0x8100 by default
1344          * So no need to change. Same to VT field of DMATXCTL register
1345          */
1346 }
1347
1348 static void
1349 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1350 {
1351         if(mask & ETH_VLAN_STRIP_MASK){
1352                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1353                         ixgbe_vlan_hw_strip_enable_all(dev);
1354                 else
1355                         ixgbe_vlan_hw_strip_disable_all(dev);
1356         }
1357
1358         if(mask & ETH_VLAN_FILTER_MASK){
1359                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1360                         ixgbe_vlan_hw_filter_enable(dev);
1361                 else
1362                         ixgbe_vlan_hw_filter_disable(dev);
1363         }
1364
1365         if(mask & ETH_VLAN_EXTEND_MASK){
1366                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1367                         ixgbe_vlan_hw_extend_enable(dev);
1368                 else
1369                         ixgbe_vlan_hw_extend_disable(dev);
1370         }
1371 }
1372
1373 static void
1374 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1375 {
1376         struct ixgbe_hw *hw =
1377                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1379         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1380         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1381         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1382 }
1383
1384 static int
1385 ixgbe_dev_configure(struct rte_eth_dev *dev)
1386 {
1387         struct ixgbe_interrupt *intr =
1388                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1389
1390         PMD_INIT_FUNC_TRACE();
1391
1392         /* set flag to update link status after init */
1393         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1394
1395         return 0;
1396 }
1397
1398 /*
1399  * Configure device link speed and setup link.
1400  * It returns 0 on success.
1401  */
1402 static int
1403 ixgbe_dev_start(struct rte_eth_dev *dev)
1404 {
1405         struct ixgbe_hw *hw =
1406                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1407         struct ixgbe_vf_info *vfinfo =
1408                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1409         int err, link_up = 0, negotiate = 0;
1410         uint32_t speed = 0;
1411         int mask = 0;
1412         int status;
1413         uint16_t vf, idx;
1414
1415         PMD_INIT_FUNC_TRACE();
1416
1417         /* IXGBE devices don't support half duplex */
1418         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1419                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1420                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1421                                 dev->data->dev_conf.link_duplex,
1422                                 dev->data->port_id);
1423                 return -EINVAL;
1424         }
1425
1426         /* stop adapter */
1427         hw->adapter_stopped = FALSE;
1428         ixgbe_stop_adapter(hw);
1429
1430         /* reinitialize adapter
1431          * this calls reset and start */
1432         status = ixgbe_pf_reset_hw(hw);
1433         if (status != 0)
1434                 return -1;
1435         hw->mac.ops.start_hw(hw);
1436
1437         /* configure PF module if SRIOV enabled */
1438         ixgbe_pf_host_configure(dev);
1439
1440         /* initialize transmission unit */
1441         ixgbe_dev_tx_init(dev);
1442
1443         /* This can fail when allocating mbufs for descriptor rings */
1444         err = ixgbe_dev_rx_init(dev);
1445         if (err) {
1446                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1447                 goto error;
1448         }
1449
1450         ixgbe_dev_rxtx_start(dev);
1451
1452         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1453                 err = hw->mac.ops.setup_sfp(hw);
1454                 if (err)
1455                         goto error;
1456         }
1457
1458         /* Turn on the laser */
1459         ixgbe_enable_tx_laser(hw);
1460
1461         /* Skip link setup if loopback mode is enabled for 82599. */
1462         if (hw->mac.type == ixgbe_mac_82599EB &&
1463                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1464                 goto skip_link_setup;
1465
1466         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1467         if (err)
1468                 goto error;
1469         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1470         if (err)
1471                 goto error;
1472
1473         switch(dev->data->dev_conf.link_speed) {
1474         case ETH_LINK_SPEED_AUTONEG:
1475                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1476                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1477                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1478                 break;
1479         case ETH_LINK_SPEED_100:
1480                 /*
1481                  * Invalid for 82598 but error will be detected by
1482                  * ixgbe_setup_link()
1483                  */
1484                 speed = IXGBE_LINK_SPEED_100_FULL;
1485                 break;
1486         case ETH_LINK_SPEED_1000:
1487                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1488                 break;
1489         case ETH_LINK_SPEED_10000:
1490                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1491                 break;
1492         default:
1493                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1494                                 dev->data->dev_conf.link_speed,
1495                                 dev->data->port_id);
1496                 goto error;
1497         }
1498
1499         err = ixgbe_setup_link(hw, speed, link_up);
1500         if (err)
1501                 goto error;
1502
1503 skip_link_setup:
1504
1505         /* check if lsc interrupt is enabled */
1506         if (dev->data->dev_conf.intr_conf.lsc != 0)
1507                 ixgbe_dev_lsc_interrupt_setup(dev);
1508
1509         /* resume enabled intr since hw reset */
1510         ixgbe_enable_intr(dev);
1511
1512         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1513                 ETH_VLAN_EXTEND_MASK;
1514         ixgbe_vlan_offload_set(dev, mask);
1515
1516         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1517                 /* Enable vlan filtering for VMDq */
1518                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1519         }
1520
1521         /* Configure DCB hw */
1522         ixgbe_configure_dcb(dev);
1523
1524         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1525                 err = ixgbe_fdir_configure(dev);
1526                 if (err)
1527                         goto error;
1528         }
1529
1530         /* Restore vf rate limit */
1531         if (vfinfo != NULL) {
1532                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1533                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1534                                 if (vfinfo[vf].tx_rate[idx] != 0)
1535                                         ixgbe_set_vf_rate_limit(dev, vf,
1536                                                 vfinfo[vf].tx_rate[idx],
1537                                                 1 << idx);
1538         }
1539
1540         ixgbe_restore_statistics_mapping(dev);
1541
1542         return (0);
1543
1544 error:
1545         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1546         ixgbe_dev_clear_queues(dev);
1547         return -EIO;
1548 }
1549
1550 /*
1551  * Stop device: disable rx and tx functions to allow for reconfiguring.
1552  */
1553 static void
1554 ixgbe_dev_stop(struct rte_eth_dev *dev)
1555 {
1556         struct rte_eth_link link;
1557         struct ixgbe_hw *hw =
1558                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1559         struct ixgbe_vf_info *vfinfo =
1560                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1561         int vf;
1562
1563         PMD_INIT_FUNC_TRACE();
1564
1565         /* disable interrupts */
1566         ixgbe_disable_intr(hw);
1567
1568         /* reset the NIC */
1569         ixgbe_pf_reset_hw(hw);
1570         hw->adapter_stopped = FALSE;
1571
1572         /* stop adapter */
1573         ixgbe_stop_adapter(hw);
1574
1575         for (vf = 0; vfinfo != NULL &&
1576                      vf < dev->pci_dev->max_vfs; vf++)
1577                 vfinfo[vf].clear_to_send = false;
1578
1579         /* Turn off the laser */
1580         ixgbe_disable_tx_laser(hw);
1581
1582         ixgbe_dev_clear_queues(dev);
1583
1584         /* Clear recorded link status */
1585         memset(&link, 0, sizeof(link));
1586         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1587 }
1588
1589 /*
1590  * Set device link up: enable tx laser.
1591  */
1592 static int
1593 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1594 {
1595         struct ixgbe_hw *hw =
1596                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597         if (hw->mac.type == ixgbe_mac_82599EB) {
1598 #ifdef RTE_NIC_BYPASS
1599                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1600                         /* Not suported in bypass mode */
1601                         PMD_INIT_LOG(ERR,
1602                                 "\nSet link up is not supported "
1603                                 "by device id 0x%x\n",
1604                                 hw->device_id);
1605                         return -ENOTSUP;
1606                 }
1607 #endif
1608                 /* Turn on the laser */
1609                 ixgbe_enable_tx_laser(hw);
1610                 return 0;
1611         }
1612
1613         PMD_INIT_LOG(ERR, "\nSet link up is not supported by device id 0x%x\n",
1614                 hw->device_id);
1615         return -ENOTSUP;
1616 }
1617
1618 /*
1619  * Set device link down: disable tx laser.
1620  */
1621 static int
1622 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1623 {
1624         struct ixgbe_hw *hw =
1625                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626         if (hw->mac.type == ixgbe_mac_82599EB) {
1627 #ifdef RTE_NIC_BYPASS
1628                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1629                         /* Not suported in bypass mode */
1630                         PMD_INIT_LOG(ERR,
1631                                 "\nSet link down is not supported "
1632                                 "by device id 0x%x\n",
1633                                  hw->device_id);
1634                         return -ENOTSUP;
1635                 }
1636 #endif
1637                 /* Turn off the laser */
1638                 ixgbe_disable_tx_laser(hw);
1639                 return 0;
1640         }
1641
1642         PMD_INIT_LOG(ERR,
1643                 "\nSet link down is not supported by device id 0x%x\n",
1644                  hw->device_id);
1645         return -ENOTSUP;
1646 }
1647
1648 /*
1649  * Reest and stop device.
1650  */
1651 static void
1652 ixgbe_dev_close(struct rte_eth_dev *dev)
1653 {
1654         struct ixgbe_hw *hw =
1655                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656
1657         PMD_INIT_FUNC_TRACE();
1658
1659         ixgbe_pf_reset_hw(hw);
1660
1661         ixgbe_dev_stop(dev);
1662         hw->adapter_stopped = 1;
1663
1664         ixgbe_disable_pcie_master(hw);
1665
1666         /* reprogram the RAR[0] in case user changed it. */
1667         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1668 }
1669
1670 /*
1671  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1672  */
1673 static void
1674 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1675 {
1676         struct ixgbe_hw *hw =
1677                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678         struct ixgbe_hw_stats *hw_stats =
1679                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1680         uint32_t bprc, lxon, lxoff, total;
1681         uint64_t total_missed_rx, total_qbrc, total_qprc;
1682         unsigned i;
1683
1684         total_missed_rx = 0;
1685         total_qbrc = 0;
1686         total_qprc = 0;
1687
1688         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1689         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1690         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1691         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1692
1693         for (i = 0; i < 8; i++) {
1694                 uint32_t mp;
1695                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1696                 /* global total per queue */
1697                 hw_stats->mpc[i] += mp;
1698                 /* Running comprehensive total for stats display */
1699                 total_missed_rx += hw_stats->mpc[i];
1700                 if (hw->mac.type == ixgbe_mac_82598EB)
1701                         hw_stats->rnbc[i] +=
1702                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1703                 hw_stats->pxontxc[i] +=
1704                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1705                 hw_stats->pxonrxc[i] +=
1706                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1707                 hw_stats->pxofftxc[i] +=
1708                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1709                 hw_stats->pxoffrxc[i] +=
1710                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1711                 hw_stats->pxon2offc[i] +=
1712                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1713         }
1714         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1715                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1716                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1717                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1718                 hw_stats->qbrc[i] +=
1719                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1720                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1721                 hw_stats->qbtc[i] +=
1722                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1723                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1724
1725                 total_qprc += hw_stats->qprc[i];
1726                 total_qbrc += hw_stats->qbrc[i];
1727         }
1728         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1729         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1730         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1731
1732         /* Note that gprc counts missed packets */
1733         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1734
1735         if (hw->mac.type != ixgbe_mac_82598EB) {
1736                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1737                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1738                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1739                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1740                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1741                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1742                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1743                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1744         } else {
1745                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1746                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1747                 /* 82598 only has a counter in the high register */
1748                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1749                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1750                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1751         }
1752
1753         /*
1754          * Workaround: mprc hardware is incorrectly counting
1755          * broadcasts, so for now we subtract those.
1756          */
1757         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1758         hw_stats->bprc += bprc;
1759         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1760         if (hw->mac.type == ixgbe_mac_82598EB)
1761                 hw_stats->mprc -= bprc;
1762
1763         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1764         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1765         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1766         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1767         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1768         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1769
1770         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1771         hw_stats->lxontxc += lxon;
1772         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1773         hw_stats->lxofftxc += lxoff;
1774         total = lxon + lxoff;
1775
1776         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1777         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1778         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1779         hw_stats->gptc -= total;
1780         hw_stats->mptc -= total;
1781         hw_stats->ptc64 -= total;
1782         hw_stats->gotc -= total * ETHER_MIN_LEN;
1783
1784         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1785         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1786         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1787         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1788         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1789         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1790         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1791         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1792         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1793         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1794         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1795         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1796         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1797         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1798         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1799         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1800         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1801         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1802         /* Only read FCOE on 82599 */
1803         if (hw->mac.type != ixgbe_mac_82598EB) {
1804                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1805                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1806                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1807                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1808                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1809         }
1810
1811         if (stats == NULL)
1812                 return;
1813
1814         /* Fill out the rte_eth_stats statistics structure */
1815         stats->ipackets = total_qprc;
1816         stats->ibytes = total_qbrc;
1817         stats->opackets = hw_stats->gptc;
1818         stats->obytes = hw_stats->gotc;
1819         stats->imcasts = hw_stats->mprc;
1820
1821         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1822                 stats->q_ipackets[i] = hw_stats->qprc[i];
1823                 stats->q_opackets[i] = hw_stats->qptc[i];
1824                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1825                 stats->q_obytes[i] = hw_stats->qbtc[i];
1826                 stats->q_errors[i] = hw_stats->qprdc[i];
1827         }
1828
1829         /* Rx Errors */
1830         stats->ibadcrc  = hw_stats->crcerrs;
1831         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1832         stats->imissed  = total_missed_rx;
1833         stats->ierrors  = stats->ibadcrc +
1834                           stats->ibadlen +
1835                           stats->imissed +
1836                           hw_stats->illerrc + hw_stats->errbc;
1837
1838         /* Tx Errors */
1839         stats->oerrors  = 0;
1840
1841         /* XON/XOFF pause frames */
1842         stats->tx_pause_xon  = hw_stats->lxontxc;
1843         stats->rx_pause_xon  = hw_stats->lxonrxc;
1844         stats->tx_pause_xoff = hw_stats->lxofftxc;
1845         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1846
1847         /* Flow Director Stats registers */
1848         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1849         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1850         stats->fdirmatch = hw_stats->fdirmatch;
1851         stats->fdirmiss = hw_stats->fdirmiss;
1852 }
1853
1854 static void
1855 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1856 {
1857         struct ixgbe_hw_stats *stats =
1858                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1859
1860         /* HW registers are cleared on read */
1861         ixgbe_dev_stats_get(dev, NULL);
1862
1863         /* Reset software totals */
1864         memset(stats, 0, sizeof(*stats));
1865 }
1866
1867 static void
1868 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1869 {
1870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1872                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1873
1874         /* Good Rx packet, include VF loopback */
1875         UPDATE_VF_STAT(IXGBE_VFGPRC,
1876             hw_stats->last_vfgprc, hw_stats->vfgprc);
1877
1878         /* Good Rx octets, include VF loopback */
1879         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1880             hw_stats->last_vfgorc, hw_stats->vfgorc);
1881
1882         /* Good Tx packet, include VF loopback */
1883         UPDATE_VF_STAT(IXGBE_VFGPTC,
1884             hw_stats->last_vfgptc, hw_stats->vfgptc);
1885
1886         /* Good Tx octets, include VF loopback */
1887         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1888             hw_stats->last_vfgotc, hw_stats->vfgotc);
1889
1890         /* Rx Multicst Packet */
1891         UPDATE_VF_STAT(IXGBE_VFMPRC,
1892             hw_stats->last_vfmprc, hw_stats->vfmprc);
1893
1894         if (stats == NULL)
1895                 return;
1896
1897         memset(stats, 0, sizeof(*stats));
1898         stats->ipackets = hw_stats->vfgprc;
1899         stats->ibytes = hw_stats->vfgorc;
1900         stats->opackets = hw_stats->vfgptc;
1901         stats->obytes = hw_stats->vfgotc;
1902         stats->imcasts = hw_stats->vfmprc;
1903 }
1904
1905 static void
1906 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1907 {
1908         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1909                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1910
1911         /* Sync HW register to the last stats */
1912         ixgbevf_dev_stats_get(dev, NULL);
1913
1914         /* reset HW current stats*/
1915         hw_stats->vfgprc = 0;
1916         hw_stats->vfgorc = 0;
1917         hw_stats->vfgptc = 0;
1918         hw_stats->vfgotc = 0;
1919         hw_stats->vfmprc = 0;
1920
1921 }
1922
1923 static void
1924 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1925 {
1926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927
1928         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1929         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1930         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1931         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1932         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1933         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1934         dev_info->max_vfs = dev->pci_dev->max_vfs;
1935         if (hw->mac.type == ixgbe_mac_82598EB)
1936                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1937         else
1938                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1939         dev_info->rx_offload_capa =
1940                 DEV_RX_OFFLOAD_VLAN_STRIP |
1941                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1942                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1943                 DEV_RX_OFFLOAD_TCP_CKSUM;
1944         dev_info->tx_offload_capa =
1945                 DEV_TX_OFFLOAD_VLAN_INSERT |
1946                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1947                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1948                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1949                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1950 }
1951
1952 /* return 0 means link status changed, -1 means not changed */
1953 static int
1954 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1955 {
1956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1957         struct rte_eth_link link, old;
1958         ixgbe_link_speed link_speed;
1959         int link_up;
1960         int diag;
1961
1962         link.link_status = 0;
1963         link.link_speed = 0;
1964         link.link_duplex = 0;
1965         memset(&old, 0, sizeof(old));
1966         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1967
1968         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1969         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1970                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1971         else
1972                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1973         if (diag != 0) {
1974                 link.link_speed = ETH_LINK_SPEED_100;
1975                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1976                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1977                 if (link.link_status == old.link_status)
1978                         return -1;
1979                 return 0;
1980         }
1981
1982         if (link_up == 0) {
1983                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1984                 if (link.link_status == old.link_status)
1985                         return -1;
1986                 return 0;
1987         }
1988         link.link_status = 1;
1989         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1990
1991         switch (link_speed) {
1992         default:
1993         case IXGBE_LINK_SPEED_UNKNOWN:
1994                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1995                 link.link_speed = ETH_LINK_SPEED_100;
1996                 break;
1997
1998         case IXGBE_LINK_SPEED_100_FULL:
1999                 link.link_speed = ETH_LINK_SPEED_100;
2000                 break;
2001
2002         case IXGBE_LINK_SPEED_1GB_FULL:
2003                 link.link_speed = ETH_LINK_SPEED_1000;
2004                 break;
2005
2006         case IXGBE_LINK_SPEED_10GB_FULL:
2007                 link.link_speed = ETH_LINK_SPEED_10000;
2008                 break;
2009         }
2010         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2011
2012         if (link.link_status == old.link_status)
2013                 return -1;
2014
2015         return 0;
2016 }
2017
2018 static void
2019 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2020 {
2021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022         uint32_t fctrl;
2023
2024         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2025         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2026         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2027 }
2028
2029 static void
2030 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2031 {
2032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033         uint32_t fctrl;
2034
2035         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2036         fctrl &= (~IXGBE_FCTRL_UPE);
2037         if (dev->data->all_multicast == 1)
2038                 fctrl |= IXGBE_FCTRL_MPE;
2039         else
2040                 fctrl &= (~IXGBE_FCTRL_MPE);
2041         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2042 }
2043
2044 static void
2045 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2046 {
2047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048         uint32_t fctrl;
2049
2050         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2051         fctrl |= IXGBE_FCTRL_MPE;
2052         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2053 }
2054
2055 static void
2056 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2057 {
2058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059         uint32_t fctrl;
2060
2061         if (dev->data->promiscuous == 1)
2062                 return; /* must remain in all_multicast mode */
2063
2064         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2065         fctrl &= (~IXGBE_FCTRL_MPE);
2066         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2067 }
2068
2069 /**
2070  * It clears the interrupt causes and enables the interrupt.
2071  * It will be called once only during nic initialized.
2072  *
2073  * @param dev
2074  *  Pointer to struct rte_eth_dev.
2075  *
2076  * @return
2077  *  - On success, zero.
2078  *  - On failure, a negative value.
2079  */
2080 static int
2081 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2082 {
2083         struct ixgbe_interrupt *intr =
2084                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2085
2086         ixgbe_dev_link_status_print(dev);
2087         intr->mask |= IXGBE_EICR_LSC;
2088
2089         return 0;
2090 }
2091
2092 /*
2093  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2094  *
2095  * @param dev
2096  *  Pointer to struct rte_eth_dev.
2097  *
2098  * @return
2099  *  - On success, zero.
2100  *  - On failure, a negative value.
2101  */
2102 static int
2103 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2104 {
2105         uint32_t eicr;
2106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct ixgbe_interrupt *intr =
2108                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2109
2110         /* clear all cause mask */
2111         ixgbe_disable_intr(hw);
2112
2113         /* read-on-clear nic registers here */
2114         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2115         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2116
2117         intr->flags = 0;
2118         if (eicr & IXGBE_EICR_LSC) {
2119                 /* set flag for async link update */
2120                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2121         }
2122
2123         if (eicr & IXGBE_EICR_MAILBOX)
2124                 intr->flags |= IXGBE_FLAG_MAILBOX;
2125
2126         return 0;
2127 }
2128
2129 /**
2130  * It gets and then prints the link status.
2131  *
2132  * @param dev
2133  *  Pointer to struct rte_eth_dev.
2134  *
2135  * @return
2136  *  - On success, zero.
2137  *  - On failure, a negative value.
2138  */
2139 static void
2140 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2141 {
2142         struct rte_eth_link link;
2143
2144         memset(&link, 0, sizeof(link));
2145         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2146         if (link.link_status) {
2147                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2148                                         (int)(dev->data->port_id),
2149                                         (unsigned)link.link_speed,
2150                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2151                                         "full-duplex" : "half-duplex");
2152         } else {
2153                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2154                                 (int)(dev->data->port_id));
2155         }
2156         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2157                                 dev->pci_dev->addr.domain,
2158                                 dev->pci_dev->addr.bus,
2159                                 dev->pci_dev->addr.devid,
2160                                 dev->pci_dev->addr.function);
2161 }
2162
2163 /*
2164  * It executes link_update after knowing an interrupt occurred.
2165  *
2166  * @param dev
2167  *  Pointer to struct rte_eth_dev.
2168  *
2169  * @return
2170  *  - On success, zero.
2171  *  - On failure, a negative value.
2172  */
2173 static int
2174 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2175 {
2176         struct ixgbe_interrupt *intr =
2177                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2178         int64_t timeout;
2179         struct rte_eth_link link;
2180         int intr_enable_delay = false;
2181
2182         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
2183
2184         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2185                 ixgbe_pf_mbx_process(dev);
2186                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2187         }
2188
2189         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2190                 /* get the link status before link update, for predicting later */
2191                 memset(&link, 0, sizeof(link));
2192                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2193
2194                 ixgbe_dev_link_update(dev, 0);
2195
2196                 /* likely to up */
2197                 if (!link.link_status)
2198                         /* handle it 1 sec later, wait it being stable */
2199                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2200                 /* likely to down */
2201                 else
2202                         /* handle it 4 sec later, wait it being stable */
2203                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2204
2205                 ixgbe_dev_link_status_print(dev);
2206
2207                 intr_enable_delay = true;
2208         }
2209
2210         if (intr_enable_delay) {
2211                 if (rte_eal_alarm_set(timeout * 1000,
2212                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2213                         PMD_DRV_LOG(ERR, "Error setting alarm");
2214         } else {
2215                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2216                 ixgbe_enable_intr(dev);
2217                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2218         }
2219
2220
2221         return 0;
2222 }
2223
2224 /**
2225  * Interrupt handler which shall be registered for alarm callback for delayed
2226  * handling specific interrupt to wait for the stable nic state. As the
2227  * NIC interrupt state is not stable for ixgbe after link is just down,
2228  * it needs to wait 4 seconds to get the stable status.
2229  *
2230  * @param handle
2231  *  Pointer to interrupt handle.
2232  * @param param
2233  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2234  *
2235  * @return
2236  *  void
2237  */
2238 static void
2239 ixgbe_dev_interrupt_delayed_handler(void *param)
2240 {
2241         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2242         struct ixgbe_interrupt *intr =
2243                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2244         struct ixgbe_hw *hw =
2245                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246         uint32_t eicr;
2247
2248         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2249         if (eicr & IXGBE_EICR_MAILBOX)
2250                 ixgbe_pf_mbx_process(dev);
2251
2252         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2253                 ixgbe_dev_link_update(dev, 0);
2254                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2255                 ixgbe_dev_link_status_print(dev);
2256                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2257         }
2258
2259         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2260         ixgbe_enable_intr(dev);
2261         rte_intr_enable(&(dev->pci_dev->intr_handle));
2262 }
2263
2264 /**
2265  * Interrupt handler triggered by NIC  for handling
2266  * specific interrupt.
2267  *
2268  * @param handle
2269  *  Pointer to interrupt handle.
2270  * @param param
2271  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2272  *
2273  * @return
2274  *  void
2275  */
2276 static void
2277 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2278                                                         void *param)
2279 {
2280         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2281         ixgbe_dev_interrupt_get_status(dev);
2282         ixgbe_dev_interrupt_action(dev);
2283 }
2284
2285 static int
2286 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2287 {
2288         struct ixgbe_hw *hw;
2289
2290         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2292 }
2293
2294 static int
2295 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2296 {
2297         struct ixgbe_hw *hw;
2298
2299         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2301 }
2302
2303 static int
2304 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2305 {
2306         struct ixgbe_hw *hw;
2307         uint32_t mflcn_reg;
2308         uint32_t fccfg_reg;
2309         int rx_pause;
2310         int tx_pause;
2311
2312         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2313
2314         fc_conf->pause_time = hw->fc.pause_time;
2315         fc_conf->high_water = hw->fc.high_water[0];
2316         fc_conf->low_water = hw->fc.low_water[0];
2317         fc_conf->send_xon = hw->fc.send_xon;
2318         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2319
2320         /*
2321          * Return rx_pause status according to actual setting of
2322          * MFLCN register.
2323          */
2324         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2325         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2326                 rx_pause = 1;
2327         else
2328                 rx_pause = 0;
2329
2330         /*
2331          * Return tx_pause status according to actual setting of
2332          * FCCFG register.
2333          */
2334         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2335         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2336                 tx_pause = 1;
2337         else
2338                 tx_pause = 0;
2339
2340         if (rx_pause && tx_pause)
2341                 fc_conf->mode = RTE_FC_FULL;
2342         else if (rx_pause)
2343                 fc_conf->mode = RTE_FC_RX_PAUSE;
2344         else if (tx_pause)
2345                 fc_conf->mode = RTE_FC_TX_PAUSE;
2346         else
2347                 fc_conf->mode = RTE_FC_NONE;
2348
2349         return 0;
2350 }
2351
2352 static int
2353 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2354 {
2355         struct ixgbe_hw *hw;
2356         int err;
2357         uint32_t rx_buf_size;
2358         uint32_t max_high_water;
2359         uint32_t mflcn;
2360         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2361                 ixgbe_fc_none,
2362                 ixgbe_fc_rx_pause,
2363                 ixgbe_fc_tx_pause,
2364                 ixgbe_fc_full
2365         };
2366
2367         PMD_INIT_FUNC_TRACE();
2368
2369         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2370         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2371                 return -ENOTSUP;
2372         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2373         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2374
2375         /*
2376          * At least reserve one Ethernet frame for watermark
2377          * high_water/low_water in kilo bytes for ixgbe
2378          */
2379         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2380         if ((fc_conf->high_water > max_high_water) ||
2381                 (fc_conf->high_water < fc_conf->low_water)) {
2382                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2383                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2384                 return (-EINVAL);
2385         }
2386
2387         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2388         hw->fc.pause_time     = fc_conf->pause_time;
2389         hw->fc.high_water[0]  = fc_conf->high_water;
2390         hw->fc.low_water[0]   = fc_conf->low_water;
2391         hw->fc.send_xon       = fc_conf->send_xon;
2392
2393         err = ixgbe_fc_enable(hw);
2394
2395         /* Not negotiated is not an error case */
2396         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2397
2398                 /* check if we want to forward MAC frames - driver doesn't have native
2399                  * capability to do that, so we'll write the registers ourselves */
2400
2401                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2402
2403                 /* set or clear MFLCN.PMCF bit depending on configuration */
2404                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2405                         mflcn |= IXGBE_MFLCN_PMCF;
2406                 else
2407                         mflcn &= ~IXGBE_MFLCN_PMCF;
2408
2409                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2410                 IXGBE_WRITE_FLUSH(hw);
2411
2412                 return 0;
2413         }
2414
2415         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2416         return -EIO;
2417 }
2418
2419 /**
2420  *  ixgbe_pfc_enable_generic - Enable flow control
2421  *  @hw: pointer to hardware structure
2422  *  @tc_num: traffic class number
2423  *  Enable flow control according to the current settings.
2424  */
2425 static int
2426 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2427 {
2428         int ret_val = 0;
2429         uint32_t mflcn_reg, fccfg_reg;
2430         uint32_t reg;
2431         uint32_t fcrtl, fcrth;
2432         uint8_t i;
2433         uint8_t nb_rx_en;
2434
2435         /* Validate the water mark configuration */
2436         if (!hw->fc.pause_time) {
2437                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2438                 goto out;
2439         }
2440
2441         /* Low water mark of zero causes XOFF floods */
2442         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2443                  /* High/Low water can not be 0 */
2444                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2445                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2446                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2447                         goto out;
2448                 }
2449
2450                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2451                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2452                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2453                         goto out;
2454                 }
2455         }
2456         /* Negotiate the fc mode to use */
2457         ixgbe_fc_autoneg(hw);
2458
2459         /* Disable any previous flow control settings */
2460         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2461         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2462
2463         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2464         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2465
2466         switch (hw->fc.current_mode) {
2467         case ixgbe_fc_none:
2468                 /*
2469                  * If the count of enabled RX Priority Flow control >1,
2470                  * and the TX pause can not be disabled
2471                  */
2472                 nb_rx_en = 0;
2473                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2474                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2475                         if (reg & IXGBE_FCRTH_FCEN)
2476                                 nb_rx_en++;
2477                 }
2478                 if (nb_rx_en > 1)
2479                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2480                 break;
2481         case ixgbe_fc_rx_pause:
2482                 /*
2483                  * Rx Flow control is enabled and Tx Flow control is
2484                  * disabled by software override. Since there really
2485                  * isn't a way to advertise that we are capable of RX
2486                  * Pause ONLY, we will advertise that we support both
2487                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2488                  * disable the adapter's ability to send PAUSE frames.
2489                  */
2490                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2491                 /*
2492                  * If the count of enabled RX Priority Flow control >1,
2493                  * and the TX pause can not be disabled
2494                  */
2495                 nb_rx_en = 0;
2496                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2497                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2498                         if (reg & IXGBE_FCRTH_FCEN)
2499                                 nb_rx_en++;
2500                 }
2501                 if (nb_rx_en > 1)
2502                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2503                 break;
2504         case ixgbe_fc_tx_pause:
2505                 /*
2506                  * Tx Flow control is enabled, and Rx Flow control is
2507                  * disabled by software override.
2508                  */
2509                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2510                 break;
2511         case ixgbe_fc_full:
2512                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2513                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2514                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2515                 break;
2516         default:
2517                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2518                 ret_val = IXGBE_ERR_CONFIG;
2519                 goto out;
2520                 break;
2521         }
2522
2523         /* Set 802.3x based flow control settings. */
2524         mflcn_reg |= IXGBE_MFLCN_DPF;
2525         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2526         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2527
2528         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2529         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2530                 hw->fc.high_water[tc_num]) {
2531                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2532                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2533                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2534         } else {
2535                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2536                 /*
2537                  * In order to prevent Tx hangs when the internal Tx
2538                  * switch is enabled we must set the high water mark
2539                  * to the maximum FCRTH value.  This allows the Tx
2540                  * switch to function even under heavy Rx workloads.
2541                  */
2542                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2543         }
2544         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2545
2546         /* Configure pause time (2 TCs per register) */
2547         reg = hw->fc.pause_time * 0x00010001;
2548         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2549                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2550
2551         /* Configure flow control refresh threshold value */
2552         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2553
2554 out:
2555         return ret_val;
2556 }
2557
2558 static int
2559 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2560 {
2561         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2563
2564         if(hw->mac.type != ixgbe_mac_82598EB) {
2565                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2566         }
2567         return ret_val;
2568 }
2569
2570 static int
2571 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2572 {
2573         int err;
2574         uint32_t rx_buf_size;
2575         uint32_t max_high_water;
2576         uint8_t tc_num;
2577         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2578         struct ixgbe_hw *hw =
2579                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2580         struct ixgbe_dcb_config *dcb_config =
2581                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2582
2583         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2584                 ixgbe_fc_none,
2585                 ixgbe_fc_rx_pause,
2586                 ixgbe_fc_tx_pause,
2587                 ixgbe_fc_full
2588         };
2589
2590         PMD_INIT_FUNC_TRACE();
2591
2592         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2593         tc_num = map[pfc_conf->priority];
2594         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2595         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2596         /*
2597          * At least reserve one Ethernet frame for watermark
2598          * high_water/low_water in kilo bytes for ixgbe
2599          */
2600         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2601         if ((pfc_conf->fc.high_water > max_high_water) ||
2602                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2603                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2604                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2605                 return (-EINVAL);
2606         }
2607
2608         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2609         hw->fc.pause_time = pfc_conf->fc.pause_time;
2610         hw->fc.send_xon = pfc_conf->fc.send_xon;
2611         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2612         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2613
2614         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2615
2616         /* Not negotiated is not an error case */
2617         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2618                 return 0;
2619
2620         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2621         return -EIO;
2622 }
2623
2624 static int
2625 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2626                                 struct rte_eth_rss_reta *reta_conf)
2627 {
2628         uint8_t i,j,mask;
2629         uint32_t reta;
2630         struct ixgbe_hw *hw =
2631                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632
2633         PMD_INIT_FUNC_TRACE();
2634         /*
2635         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2636         * 128-entries in 32 registers
2637          */
2638         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2639                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2640                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2641                 else
2642                         mask = (uint8_t)((reta_conf->mask_hi >>
2643                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2644                 if (mask != 0) {
2645                         reta = 0;
2646                         if (mask != 0xF)
2647                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2648
2649                         for (j = 0; j < 4; j++) {
2650                                 if (mask & (0x1 << j)) {
2651                                         if (mask != 0xF)
2652                                                 reta &= ~(0xFF << 8 * j);
2653                                         reta |= reta_conf->reta[i + j] << 8*j;
2654                                 }
2655                         }
2656                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2657                 }
2658         }
2659
2660         return 0;
2661 }
2662
2663 static int
2664 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2665                                 struct rte_eth_rss_reta *reta_conf)
2666 {
2667         uint8_t i,j,mask;
2668         uint32_t reta;
2669         struct ixgbe_hw *hw =
2670                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671
2672         PMD_INIT_FUNC_TRACE();
2673         /*
2674          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2675          * 128-entries in 32 registers
2676          */
2677         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2678                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2679                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2680                 else
2681                         mask = (uint8_t)((reta_conf->mask_hi >>
2682                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2683
2684                 if (mask != 0) {
2685                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2686                         for (j = 0; j < 4; j++) {
2687                                 if (mask & (0x1 << j))
2688                                         reta_conf->reta[i + j] =
2689                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2690                         }
2691                 }
2692         }
2693
2694         return 0;
2695 }
2696
2697 static void
2698 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2699                                 uint32_t index, uint32_t pool)
2700 {
2701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2702         uint32_t enable_addr = 1;
2703
2704         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2705 }
2706
2707 static void
2708 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2709 {
2710         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2711
2712         ixgbe_clear_rar(hw, index);
2713 }
2714
2715 static int
2716 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2717 {
2718         uint32_t hlreg0;
2719         uint32_t maxfrs;
2720         struct ixgbe_hw *hw;
2721         struct rte_eth_dev_info dev_info;
2722         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2723
2724         ixgbe_dev_info_get(dev, &dev_info);
2725
2726         /* check that mtu is within the allowed range */
2727         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2728                 return -EINVAL;
2729
2730         /* refuse mtu that requires the support of scattered packets when this
2731          * feature has not been enabled before. */
2732         if (!dev->data->scattered_rx &&
2733             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2734              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2735                 return -EINVAL;
2736
2737         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2739
2740         /* switch to jumbo mode if needed */
2741         if (frame_size > ETHER_MAX_LEN) {
2742                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2743                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2744         } else {
2745                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2746                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2747         }
2748         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2749
2750         /* update max frame size */
2751         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2752
2753         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2754         maxfrs &= 0x0000FFFF;
2755         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2756         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2757
2758         return 0;
2759 }
2760
2761 /*
2762  * Virtual Function operations
2763  */
2764 static void
2765 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2766 {
2767         PMD_INIT_FUNC_TRACE();
2768
2769         /* Clear interrupt mask to stop from interrupts being generated */
2770         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2771
2772         IXGBE_WRITE_FLUSH(hw);
2773 }
2774
2775 static int
2776 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2777 {
2778         struct rte_eth_conf* conf = &dev->data->dev_conf;
2779
2780         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2781                 dev->data->port_id);
2782
2783         /*
2784          * VF has no ability to enable/disable HW CRC
2785          * Keep the persistent behavior the same as Host PF
2786          */
2787 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2788         if (!conf->rxmode.hw_strip_crc) {
2789                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2790                 conf->rxmode.hw_strip_crc = 1;
2791         }
2792 #else
2793         if (conf->rxmode.hw_strip_crc) {
2794                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2795                 conf->rxmode.hw_strip_crc = 0;
2796         }
2797 #endif
2798
2799         return 0;
2800 }
2801
2802 static int
2803 ixgbevf_dev_start(struct rte_eth_dev *dev)
2804 {
2805         struct ixgbe_hw *hw =
2806                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807         int err, mask = 0;
2808
2809         PMD_INIT_FUNC_TRACE();
2810
2811         hw->mac.ops.reset_hw(hw);
2812
2813         /* negotiate mailbox API version to use with the PF. */
2814         ixgbevf_negotiate_api(hw);
2815
2816         ixgbevf_dev_tx_init(dev);
2817
2818         /* This can fail when allocating mbufs for descriptor rings */
2819         err = ixgbevf_dev_rx_init(dev);
2820         if (err) {
2821                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2822                 ixgbe_dev_clear_queues(dev);
2823                 return err;
2824         }
2825
2826         /* Set vfta */
2827         ixgbevf_set_vfta_all(dev,1);
2828
2829         /* Set HW strip */
2830         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2831                 ETH_VLAN_EXTEND_MASK;
2832         ixgbevf_vlan_offload_set(dev, mask);
2833
2834         ixgbevf_dev_rxtx_start(dev);
2835
2836         return 0;
2837 }
2838
2839 static void
2840 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2841 {
2842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843
2844         PMD_INIT_FUNC_TRACE();
2845
2846         hw->adapter_stopped = TRUE;
2847         ixgbe_stop_adapter(hw);
2848
2849         /*
2850           * Clear what we set, but we still keep shadow_vfta to
2851           * restore after device starts
2852           */
2853         ixgbevf_set_vfta_all(dev,0);
2854
2855         ixgbe_dev_clear_queues(dev);
2856 }
2857
2858 static void
2859 ixgbevf_dev_close(struct rte_eth_dev *dev)
2860 {
2861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862
2863         PMD_INIT_FUNC_TRACE();
2864
2865         ixgbe_reset_hw(hw);
2866
2867         ixgbevf_dev_stop(dev);
2868
2869         /* reprogram the RAR[0] in case user changed it. */
2870         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2871 }
2872
2873 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2874 {
2875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         struct ixgbe_vfta * shadow_vfta =
2877                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2878         int i = 0, j = 0, vfta = 0, mask = 1;
2879
2880         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2881                 vfta = shadow_vfta->vfta[i];
2882                 if(vfta){
2883                         mask = 1;
2884                         for (j = 0; j < 32; j++){
2885                                 if(vfta & mask)
2886                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2887                                 mask<<=1;
2888                         }
2889                 }
2890         }
2891
2892 }
2893
2894 static int
2895 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2896 {
2897         struct ixgbe_hw *hw =
2898                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2899         struct ixgbe_vfta * shadow_vfta =
2900                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2901         uint32_t vid_idx = 0;
2902         uint32_t vid_bit = 0;
2903         int ret = 0;
2904
2905         PMD_INIT_FUNC_TRACE();
2906
2907         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2908         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2909         if(ret){
2910                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2911                 return ret;
2912         }
2913         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2914         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2915
2916         /* Save what we set and retore it after device reset */
2917         if (on)
2918                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2919         else
2920                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2921
2922         return 0;
2923 }
2924
2925 static void
2926 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2927 {
2928         struct ixgbe_hw *hw =
2929                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2930         uint32_t ctrl;
2931
2932         PMD_INIT_FUNC_TRACE();
2933
2934         if(queue >= hw->mac.max_rx_queues)
2935                 return;
2936
2937         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2938         if(on)
2939                 ctrl |= IXGBE_RXDCTL_VME;
2940         else
2941                 ctrl &= ~IXGBE_RXDCTL_VME;
2942         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2943
2944         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2945 }
2946
2947 static void
2948 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2949 {
2950         struct ixgbe_hw *hw =
2951                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         uint16_t i;
2953         int on = 0;
2954
2955         /* VF function only support hw strip feature, others are not support */
2956         if(mask & ETH_VLAN_STRIP_MASK){
2957                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2958
2959                 for(i=0; i < hw->mac.max_rx_queues; i++)
2960                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2961         }
2962 }
2963
2964 static int
2965 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2966 {
2967         uint32_t reg_val;
2968
2969         /* we only need to do this if VMDq is enabled */
2970         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2971         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2972                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2973                 return (-1);
2974         }
2975
2976         return 0;
2977 }
2978
2979 static uint32_t
2980 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2981 {
2982         uint32_t vector = 0;
2983         switch (hw->mac.mc_filter_type) {
2984         case 0:   /* use bits [47:36] of the address */
2985                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2986                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2987                 break;
2988         case 1:   /* use bits [46:35] of the address */
2989                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2990                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2991                 break;
2992         case 2:   /* use bits [45:34] of the address */
2993                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2994                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2995                 break;
2996         case 3:   /* use bits [43:32] of the address */
2997                 vector = ((uc_addr->addr_bytes[4]) |
2998                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2999                 break;
3000         default:  /* Invalid mc_filter_type */
3001                 break;
3002         }
3003
3004         /* vector can only be 12-bits or boundary will be exceeded */
3005         vector &= 0xFFF;
3006         return vector;
3007 }
3008
3009 static int
3010 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3011                                uint8_t on)
3012 {
3013         uint32_t vector;
3014         uint32_t uta_idx;
3015         uint32_t reg_val;
3016         uint32_t uta_shift;
3017         uint32_t rc;
3018         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3019         const uint32_t ixgbe_uta_bit_shift = 5;
3020         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3021         const uint32_t bit1 = 0x1;
3022
3023         struct ixgbe_hw *hw =
3024                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3025         struct ixgbe_uta_info *uta_info =
3026                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3027
3028         /* The UTA table only exists on 82599 hardware and newer */
3029         if (hw->mac.type < ixgbe_mac_82599EB)
3030                 return (-ENOTSUP);
3031
3032         vector = ixgbe_uta_vector(hw,mac_addr);
3033         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3034         uta_shift = vector & ixgbe_uta_bit_mask;
3035
3036         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3037         if(rc == on)
3038                 return 0;
3039
3040         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3041         if (on) {
3042                 uta_info->uta_in_use++;
3043                 reg_val |= (bit1 << uta_shift);
3044                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3045         } else {
3046                 uta_info->uta_in_use--;
3047                 reg_val &= ~(bit1 << uta_shift);
3048                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3049         }
3050
3051         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3052
3053         if (uta_info->uta_in_use > 0)
3054                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3055                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3056         else
3057                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3058
3059         return 0;
3060 }
3061
3062 static int
3063 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3064 {
3065         int i;
3066         struct ixgbe_hw *hw =
3067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         struct ixgbe_uta_info *uta_info =
3069                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3070
3071         /* The UTA table only exists on 82599 hardware and newer */
3072         if (hw->mac.type < ixgbe_mac_82599EB)
3073                 return (-ENOTSUP);
3074
3075         if(on) {
3076                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3077                         uta_info->uta_shadow[i] = ~0;
3078                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3079                 }
3080         } else {
3081                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3082                         uta_info->uta_shadow[i] = 0;
3083                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3084                 }
3085         }
3086         return 0;
3087
3088 }
3089 static int
3090 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3091                                uint16_t rx_mask, uint8_t on)
3092 {
3093         int val = 0;
3094
3095         struct ixgbe_hw *hw =
3096                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3097         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3098
3099         if (hw->mac.type == ixgbe_mac_82598EB) {
3100                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3101                         " on 82599 hardware and newer\n");
3102                 return (-ENOTSUP);
3103         }
3104         if (ixgbe_vmdq_mode_check(hw) < 0)
3105                 return (-ENOTSUP);
3106
3107         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
3108                 val |= IXGBE_VMOLR_AUPE;
3109         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
3110                 val |= IXGBE_VMOLR_ROMPE;
3111         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3112                 val |= IXGBE_VMOLR_ROPE;
3113         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3114                 val |= IXGBE_VMOLR_BAM;
3115         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3116                 val |= IXGBE_VMOLR_MPE;
3117
3118         if (on)
3119                 vmolr |= val;
3120         else
3121                 vmolr &= ~val;
3122
3123         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3124
3125         return 0;
3126 }
3127
3128 static int
3129 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3130 {
3131         uint32_t reg,addr;
3132         uint32_t val;
3133         const uint8_t bit1 = 0x1;
3134
3135         struct ixgbe_hw *hw =
3136                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137
3138         if (ixgbe_vmdq_mode_check(hw) < 0)
3139                 return (-ENOTSUP);
3140
3141         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3142         reg = IXGBE_READ_REG(hw, addr);
3143         val = bit1 << pool;
3144
3145         if (on)
3146                 reg |= val;
3147         else
3148                 reg &= ~val;
3149
3150         IXGBE_WRITE_REG(hw, addr,reg);
3151
3152         return 0;
3153 }
3154
3155 static int
3156 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3157 {
3158         uint32_t reg,addr;
3159         uint32_t val;
3160         const uint8_t bit1 = 0x1;
3161
3162         struct ixgbe_hw *hw =
3163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3164
3165         if (ixgbe_vmdq_mode_check(hw) < 0)
3166                 return (-ENOTSUP);
3167
3168         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3169         reg = IXGBE_READ_REG(hw, addr);
3170         val = bit1 << pool;
3171
3172         if (on)
3173                 reg |= val;
3174         else
3175                 reg &= ~val;
3176
3177         IXGBE_WRITE_REG(hw, addr,reg);
3178
3179         return 0;
3180 }
3181
3182 static int
3183 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3184                         uint64_t pool_mask, uint8_t vlan_on)
3185 {
3186         int ret = 0;
3187         uint16_t pool_idx;
3188         struct ixgbe_hw *hw =
3189                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190
3191         if (ixgbe_vmdq_mode_check(hw) < 0)
3192                 return (-ENOTSUP);
3193         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3194                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3195                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3196                         if (ret < 0)
3197                                 return ret;
3198         }
3199
3200         return ret;
3201 }
3202
3203 static int
3204 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3205                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3206                         uint8_t rule_id, uint8_t on)
3207 {
3208         uint32_t mr_ctl,vlvf;
3209         uint32_t mp_lsb = 0;
3210         uint32_t mv_msb = 0;
3211         uint32_t mv_lsb = 0;
3212         uint32_t mp_msb = 0;
3213         uint8_t i = 0;
3214         int reg_index = 0;
3215         uint64_t vlan_mask = 0;
3216
3217         const uint8_t pool_mask_offset = 32;
3218         const uint8_t vlan_mask_offset = 32;
3219         const uint8_t dst_pool_offset = 8;
3220         const uint8_t rule_mr_offset  = 4;
3221         const uint8_t mirror_rule_mask= 0x0F;
3222
3223         struct ixgbe_mirror_info *mr_info =
3224                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3225         struct ixgbe_hw *hw =
3226                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3227
3228         if (ixgbe_vmdq_mode_check(hw) < 0)
3229                 return (-ENOTSUP);
3230
3231         /* Check if vlan mask is valid */
3232         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3233                 if (mirror_conf->vlan.vlan_mask == 0)
3234                         return (-EINVAL);
3235         }
3236
3237         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3238         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3239                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3240                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3241                                 /* search vlan id related pool vlan filter index */
3242                                 reg_index = ixgbe_find_vlvf_slot(hw,
3243                                                 mirror_conf->vlan.vlan_id[i]);
3244                                 if(reg_index < 0)
3245                                         return (-EINVAL);
3246                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3247                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3248                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3249                                                 == mirror_conf->vlan.vlan_id[i]))
3250                                         vlan_mask |= (1ULL << reg_index);
3251                                 else
3252                                         return (-EINVAL);
3253                         }
3254                 }
3255
3256                 if (on) {
3257                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3258                         mv_msb = vlan_mask >> vlan_mask_offset;
3259
3260                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3261                                                 mirror_conf->vlan.vlan_mask;
3262                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3263                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3264                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3265                                                 mirror_conf->vlan.vlan_id[i];
3266                         }
3267                 } else {
3268                         mv_lsb = 0;
3269                         mv_msb = 0;
3270                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3271                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3272                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3273                 }
3274         }
3275
3276         /*
3277          * if enable pool mirror, write related pool mask register,if disable
3278          * pool mirror, clear PFMRVM register
3279          */
3280         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3281                 if (on) {
3282                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3283                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3284                         mr_info->mr_conf[rule_id].pool_mask =
3285                                         mirror_conf->pool_mask;
3286
3287                 } else {
3288                         mp_lsb = 0;
3289                         mp_msb = 0;
3290                         mr_info->mr_conf[rule_id].pool_mask = 0;
3291                 }
3292         }
3293
3294         /* read  mirror control register and recalculate it */
3295         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3296
3297         if (on) {
3298                 mr_ctl |= mirror_conf->rule_type_mask;
3299                 mr_ctl &= mirror_rule_mask;
3300                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3301         } else
3302                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3303
3304         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3305         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3306
3307         /* write mirrror control  register */
3308         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3309
3310         /* write pool mirrror control  register */
3311         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3312                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3313                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3314                                 mp_msb);
3315         }
3316         /* write VLAN mirrror control  register */
3317         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3318                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3319                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3320                                 mv_msb);
3321         }
3322
3323         return 0;
3324 }
3325
3326 static int
3327 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3328 {
3329         int mr_ctl = 0;
3330         uint32_t lsb_val = 0;
3331         uint32_t msb_val = 0;
3332         const uint8_t rule_mr_offset = 4;
3333
3334         struct ixgbe_hw *hw =
3335                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336         struct ixgbe_mirror_info *mr_info =
3337                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3338
3339         if (ixgbe_vmdq_mode_check(hw) < 0)
3340                 return (-ENOTSUP);
3341
3342         memset(&mr_info->mr_conf[rule_id], 0,
3343                 sizeof(struct rte_eth_vmdq_mirror_conf));
3344
3345         /* clear PFVMCTL register */
3346         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3347
3348         /* clear pool mask register */
3349         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3350         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3351
3352         /* clear vlan mask register */
3353         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3354         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3355
3356         return 0;
3357 }
3358
3359 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3360         uint16_t queue_idx, uint16_t tx_rate)
3361 {
3362         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363         uint32_t rf_dec, rf_int;
3364         uint32_t bcnrc_val;
3365         uint16_t link_speed = dev->data->dev_link.link_speed;
3366
3367         if (queue_idx >= hw->mac.max_tx_queues)
3368                 return -EINVAL;
3369
3370         if (tx_rate != 0) {
3371                 /* Calculate the rate factor values to set */
3372                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3373                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3374                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3375
3376                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3377                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3378                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3379                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3380         } else {
3381                 bcnrc_val = 0;
3382         }
3383
3384         /*
3385          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3386          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3387          * set as 0x4.
3388          */
3389         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3390                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3391                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3392                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3393                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3394         else
3395                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3396                         IXGBE_MMW_SIZE_DEFAULT);
3397
3398         /* Set RTTBCNRC of queue X */
3399         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3400         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3401         IXGBE_WRITE_FLUSH(hw);
3402
3403         return 0;
3404 }
3405
3406 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3407         uint16_t tx_rate, uint64_t q_msk)
3408 {
3409         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3410         struct ixgbe_vf_info *vfinfo =
3411                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3412         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3413         uint32_t queue_stride =
3414                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3415         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3416         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3417         uint16_t total_rate = 0;
3418
3419         if (queue_end >= hw->mac.max_tx_queues)
3420                 return -EINVAL;
3421
3422         if (vfinfo != NULL) {
3423                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3424                         if (vf_idx == vf)
3425                                 continue;
3426                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3427                                 idx++)
3428                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3429                 }
3430         } else
3431                 return -EINVAL;
3432
3433         /* Store tx_rate for this vf. */
3434         for (idx = 0; idx < nb_q_per_pool; idx++) {
3435                 if (((uint64_t)0x1 << idx) & q_msk) {
3436                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3437                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3438                         total_rate += tx_rate;
3439                 }
3440         }
3441
3442         if (total_rate > dev->data->dev_link.link_speed) {
3443                 /*
3444                  * Reset stored TX rate of the VF if it causes exceed
3445                  * link speed.
3446                  */
3447                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3448                 return -EINVAL;
3449         }
3450
3451         /* Set RTTBCNRC of each queue/pool for vf X  */
3452         for (; queue_idx <= queue_end; queue_idx++) {
3453                 if (0x1 & q_msk)
3454                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3455                 q_msk = q_msk >> 1;
3456         }
3457
3458         return 0;
3459 }
3460
3461 static void
3462 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3463                      __attribute__((unused)) uint32_t index,
3464                      __attribute__((unused)) uint32_t pool)
3465 {
3466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467         int diag;
3468
3469         /*
3470          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3471          * operation. Trap this case to avoid exhausting the [very limited]
3472          * set of PF resources used to store VF MAC addresses.
3473          */
3474         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3475                 return;
3476         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3477         if (diag == 0)
3478                 return;
3479         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3480 }
3481
3482 static void
3483 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3484 {
3485         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3487         struct ether_addr *mac_addr;
3488         uint32_t i;
3489         int diag;
3490
3491         /*
3492          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3493          * not support the deletion of a given MAC address.
3494          * Instead, it imposes to delete all MAC addresses, then to add again
3495          * all MAC addresses with the exception of the one to be deleted.
3496          */
3497         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3498
3499         /*
3500          * Add again all MAC addresses, with the exception of the deleted one
3501          * and of the permanent MAC address.
3502          */
3503         for (i = 0, mac_addr = dev->data->mac_addrs;
3504              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3505                 /* Skip the deleted MAC address */
3506                 if (i == index)
3507                         continue;
3508                 /* Skip NULL MAC addresses */
3509                 if (is_zero_ether_addr(mac_addr))
3510                         continue;
3511                 /* Skip the permanent MAC address */
3512                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3513                         continue;
3514                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3515                 if (diag != 0)
3516                         PMD_DRV_LOG(ERR,
3517                                     "Adding again MAC address "
3518                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3519                                     "diag=%d",
3520                                     mac_addr->addr_bytes[0],
3521                                     mac_addr->addr_bytes[1],
3522                                     mac_addr->addr_bytes[2],
3523                                     mac_addr->addr_bytes[3],
3524                                     mac_addr->addr_bytes[4],
3525                                     mac_addr->addr_bytes[5],
3526                                     diag);
3527         }
3528 }
3529
3530 /*
3531  * add syn filter
3532  *
3533  * @param
3534  * dev: Pointer to struct rte_eth_dev.
3535  * filter: ponter to the filter that will be added.
3536  * rx_queue: the queue id the filter assigned to.
3537  *
3538  * @return
3539  *    - On success, zero.
3540  *    - On failure, a negative value.
3541  */
3542 static int
3543 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3544                         struct rte_syn_filter *filter, uint16_t rx_queue)
3545 {
3546         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3547         uint32_t synqf;
3548
3549         if (hw->mac.type != ixgbe_mac_82599EB)
3550                 return -ENOSYS;
3551
3552         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3553                 return -EINVAL;
3554
3555         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3556
3557         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3558                 return -EINVAL;
3559
3560         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3561                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3562
3563         if (filter->hig_pri)
3564                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3565         else
3566                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3567
3568         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3569         return 0;
3570 }
3571
3572 /*
3573  * remove syn filter
3574  *
3575  * @param
3576  * dev: Pointer to struct rte_eth_dev.
3577  *
3578  * @return
3579  *    - On success, zero.
3580  *    - On failure, a negative value.
3581  */
3582 static int
3583 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3584 {
3585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586         uint32_t synqf;
3587
3588         if (hw->mac.type != ixgbe_mac_82599EB)
3589                 return -ENOSYS;
3590
3591         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3592
3593         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3594
3595         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3596         return 0;
3597 }
3598
3599 /*
3600  * get the syn filter's info
3601  *
3602  * @param
3603  * dev: Pointer to struct rte_eth_dev.
3604  * filter: ponter to the filter that returns.
3605  * *rx_queue: pointer to the queue id the filter assigned to.
3606  *
3607  * @return
3608  *    - On success, zero.
3609  *    - On failure, a negative value.
3610  */
3611 static int
3612 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3613                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3614
3615 {
3616         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617         uint32_t synqf;
3618
3619         if (hw->mac.type != ixgbe_mac_82599EB)
3620                 return -ENOSYS;
3621
3622         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3623         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3624                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3625                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3626                 return 0;
3627         }
3628         return -ENOENT;
3629 }
3630
3631 /*
3632  * add an ethertype filter
3633  *
3634  * @param
3635  * dev: Pointer to struct rte_eth_dev.
3636  * index: the index the filter allocates.
3637  * filter: ponter to the filter that will be added.
3638  * rx_queue: the queue id the filter assigned to.
3639  *
3640  * @return
3641  *    - On success, zero.
3642  *    - On failure, a negative value.
3643  */
3644 static int
3645 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3646                         uint16_t index, struct rte_ethertype_filter *filter,
3647                         uint16_t rx_queue)
3648 {
3649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3650         uint32_t etqf, etqs = 0;
3651
3652         if (hw->mac.type != ixgbe_mac_82599EB)
3653                 return -ENOSYS;
3654
3655         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3656                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3657                 return -EINVAL;
3658
3659         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3660         if (etqf & IXGBE_ETQF_FILTER_EN)
3661                 return -EINVAL;  /* filter index is in use. */
3662
3663         etqf = 0;
3664         etqf |= IXGBE_ETQF_FILTER_EN;
3665         etqf |= (uint32_t)filter->ethertype;
3666
3667         if (filter->priority_en) {
3668                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3669                         return -EINVAL;
3670                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3671                 etqf |= IXGBE_ETQF_UP_EN;
3672         }
3673         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3674         etqs |= IXGBE_ETQS_QUEUE_EN;
3675
3676         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3677         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3678         return 0;
3679 }
3680
3681 /*
3682  * remove an ethertype filter
3683  *
3684  * @param
3685  * dev: Pointer to struct rte_eth_dev.
3686  * index: the index the filter allocates.
3687  *
3688  * @return
3689  *    - On success, zero.
3690  *    - On failure, a negative value.
3691  */
3692 static int
3693 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3694                         uint16_t index)
3695 {
3696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3697
3698         if (hw->mac.type != ixgbe_mac_82599EB)
3699                 return -ENOSYS;
3700
3701         if (index >= IXGBE_MAX_ETQF_FILTERS)
3702                 return -EINVAL;
3703
3704         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3705         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3706
3707         return 0;
3708 }
3709
3710 /*
3711  * get an ethertype filter
3712  *
3713  * @param
3714  * dev: Pointer to struct rte_eth_dev.
3715  * index: the index the filter allocates.
3716  * filter: ponter to the filter that will be gotten.
3717  * *rx_queue: the ponited of the queue id the filter assigned to.
3718  *
3719  * @return
3720  *    - On success, zero.
3721  *    - On failure, a negative value.
3722  */
3723 static int
3724 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3725                         uint16_t index, struct rte_ethertype_filter *filter,
3726                         uint16_t *rx_queue)
3727 {
3728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729         uint32_t etqf, etqs;
3730
3731         if (hw->mac.type != ixgbe_mac_82599EB)
3732                 return -ENOSYS;
3733
3734         if (index >= IXGBE_MAX_ETQF_FILTERS)
3735                 return -EINVAL;
3736
3737         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3738         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3739         if (etqf & IXGBE_ETQF_FILTER_EN) {
3740                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3741                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3742                 if (filter->priority_en)
3743                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3744                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3745                 return 0;
3746         }
3747         return -ENOENT;
3748 }
3749
3750 static inline enum ixgbe_5tuple_protocol
3751 convert_protocol_type(uint8_t protocol_value)
3752 {
3753         if (protocol_value == IPPROTO_TCP)
3754                 return IXGBE_FILTER_PROTOCOL_TCP;
3755         else if (protocol_value == IPPROTO_UDP)
3756                 return IXGBE_FILTER_PROTOCOL_UDP;
3757         else if (protocol_value == IPPROTO_SCTP)
3758                 return IXGBE_FILTER_PROTOCOL_SCTP;
3759         else
3760                 return IXGBE_FILTER_PROTOCOL_NONE;
3761 }
3762
3763 static inline uint8_t
3764 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3765 {
3766         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3767                 return IPPROTO_TCP;
3768         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3769                 return IPPROTO_UDP;
3770         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3771                 return IPPROTO_SCTP;
3772         else
3773                 return 0;
3774 }
3775
3776 /*
3777  * add a 5tuple filter
3778  *
3779  * @param
3780  * dev: Pointer to struct rte_eth_dev.
3781  * index: the index the filter allocates.
3782  * filter: ponter to the filter that will be added.
3783  * rx_queue: the queue id the filter assigned to.
3784  *
3785  * @return
3786  *    - On success, zero.
3787  *    - On failure, a negative value.
3788  */
3789 static int
3790 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3791                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3792 {
3793         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3794         uint32_t ftqf, sdpqf = 0;
3795         uint32_t l34timir = 0;
3796         uint8_t mask = 0xff;
3797
3798         if (hw->mac.type != ixgbe_mac_82599EB)
3799                 return -ENOSYS;
3800
3801         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3802                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3803                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3804                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3805                 return -EINVAL;  /* filter index is out of range. */
3806
3807         if (filter->tcp_flags) {
3808                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3809                 return -EINVAL;
3810         }
3811
3812         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3813         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3814                 return -EINVAL;  /* filter index is in use. */
3815
3816         ftqf = 0;
3817         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3818         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3819
3820         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3821                 IXGBE_FTQF_PROTOCOL_MASK);
3822         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3823                 IXGBE_FTQF_PRIORITY_SHIFT);
3824         if (filter->src_ip_mask == 0) /* 0 means compare. */
3825                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3826         if (filter->dst_ip_mask == 0)
3827                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3828         if (filter->src_port_mask == 0)
3829                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3830         if (filter->dst_port_mask == 0)
3831                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3832         if (filter->protocol_mask == 0)
3833                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3834         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3835         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3836         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3837
3838         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3839         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3840         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3841         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3842
3843         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3844         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3845         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3846         return 0;
3847 }
3848
3849 /*
3850  * remove a 5tuple filter
3851  *
3852  * @param
3853  * dev: Pointer to struct rte_eth_dev.
3854  * index: the index the filter allocates.
3855  *
3856  * @return
3857  *    - On success, zero.
3858  *    - On failure, a negative value.
3859  */
3860 static int
3861 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3862                         uint16_t index)
3863 {
3864         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3865
3866         if (hw->mac.type != ixgbe_mac_82599EB)
3867                 return -ENOSYS;
3868
3869         if (index >= IXGBE_MAX_FTQF_FILTERS)
3870                 return -EINVAL;  /* filter index is out of range. */
3871
3872         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3873         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3874         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3875         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3876         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3877         return 0;
3878 }
3879
3880 /*
3881  * get a 5tuple filter
3882  *
3883  * @param
3884  * dev: Pointer to struct rte_eth_dev.
3885  * index: the index the filter allocates
3886  * filter: ponter to the filter that returns.
3887  * *rx_queue: pointer of the queue id the filter assigned to.
3888  *
3889  * @return
3890  *    - On success, zero.
3891  *    - On failure, a negative value.
3892  */
3893 static int
3894 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3895                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3896 {
3897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3898         uint32_t sdpqf, ftqf, l34timir;
3899         uint8_t mask;
3900         enum ixgbe_5tuple_protocol proto;
3901
3902         if (hw->mac.type != ixgbe_mac_82599EB)
3903                 return -ENOSYS;
3904
3905         if (index >= IXGBE_MAX_FTQF_FILTERS)
3906                 return -EINVAL;  /* filter index is out of range. */
3907
3908         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3909         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3910                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3911                 filter->protocol = revert_protocol_type(proto);
3912                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3913                                         IXGBE_FTQF_PRIORITY_MASK;
3914                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3915                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
3916                 filter->src_ip_mask =
3917                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3918                 filter->dst_ip_mask =
3919                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3920                 filter->src_port_mask =
3921                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3922                 filter->dst_port_mask =
3923                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3924                 filter->protocol_mask =
3925                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3926
3927                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3928                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3929                                         IXGBE_SDPQF_DSTPORT_SHIFT;
3930                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3931                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3932                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3933
3934                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3935                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3936                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
3937                 return 0;
3938         }
3939         return -ENOENT;
3940 }
3941
3942 static int
3943 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3944 {
3945         struct ixgbe_hw *hw;
3946         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3947
3948         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3949
3950         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3951                 return -EINVAL;
3952
3953         /* refuse mtu that requires the support of scattered packets when this
3954          * feature has not been enabled before. */
3955         if (!dev->data->scattered_rx &&
3956             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3957              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3958                 return -EINVAL;
3959
3960         /*
3961          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3962          * request of the version 2.0 of the mailbox API.
3963          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3964          * of the mailbox API.
3965          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3966          * prior to 3.11.33 which contains the following change:
3967          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3968          */
3969         ixgbevf_rlpml_set_vf(hw, max_frame);
3970
3971         /* update max frame size */
3972         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3973         return 0;
3974 }
3975
3976 static struct rte_driver rte_ixgbe_driver = {
3977         .type = PMD_PDEV,
3978         .init = rte_ixgbe_pmd_init,
3979 };
3980
3981 static struct rte_driver rte_ixgbevf_driver = {
3982         .type = PMD_PDEV,
3983         .init = rte_ixgbevf_pmd_init,
3984 };
3985
3986 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3987 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);