lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_tailq.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61
  62 #include "ixgbe_logs.h"
  63 #include "ixgbe/ixgbe_api.h"
  64 #include "ixgbe/ixgbe_vf.h"
  65 #include "ixgbe/ixgbe_common.h"
  66 #include "ixgbe_ethdev.h"
  67 #include "ixgbe_bypass.h"
  68
  69 /*
  70  * High threshold controlling when to start sending XOFF frames. Must be at
  71  * least 8 bytes less than receive packet buffer size. This value is in units
  72  * of 1024 bytes.
  73  */
  74 #define IXGBE_FC_HI    0x80
  75
  76 /*
  77  * Low threshold controlling when to start sending XON frames. This value is
  78  * in units of 1024 bytes.
  79  */
  80 #define IXGBE_FC_LO    0x40
  81
  82 /* Timer value included in XOFF frames. */
  83 #define IXGBE_FC_PAUSE 0x680
  84
  85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  86 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  87 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  88
  89
  90 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  91
  92 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  93
  94 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
  95                 struct rte_eth_dev *eth_dev);
  96 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
  97 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
  98 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
  99 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 100 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 101 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 102 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 104 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 105                                 int wait_to_complete);
 106 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_stats *stats);
 108 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 109 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 110                                              uint16_t queue_id,
 111                                              uint8_t stat_idx,
 112                                              uint8_t is_rx);
 113 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_dev_info *dev_info);
 115 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 116                 uint16_t vlan_id, int on);
 117 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 118 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 119                 uint16_t queue, bool on);
 120 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 121                 int on);
 122 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 123 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 124 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 125 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 126 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 127
 128 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 129 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 130 static int  ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 131                 struct rte_eth_fc_conf *fc_conf);
 132 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 133                 struct rte_eth_pfc_conf *pfc_conf);
 134 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 135                 struct rte_eth_rss_reta *reta_conf);
 136 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 137                 struct rte_eth_rss_reta *reta_conf);
 138 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 139 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 140 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 141 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 143                 void *param);
 144 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 145 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 146                 uint32_t index, uint32_t pool);
 147 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 148 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 149
 150 /* For Virtual Function support */
 151 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 152                 struct rte_eth_dev *eth_dev);
 153 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 154 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 155 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 156 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 157 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 158 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 159                 struct rte_eth_stats *stats);
 160 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 161 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 162                 uint16_t vlan_id, int on);
 163 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 164                 uint16_t queue, int on);
 165 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 166 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 167
 168 /* For Eth VMDQ APIs support */
 169 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 170                 ether_addr* mac_addr,uint8_t on);
 171 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 172 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 173                 uint16_t rx_mask, uint8_t on);
 174 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 175 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 176 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 177                 uint64_t pool_mask,uint8_t vlan_on);
 178 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 179                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 180                 uint8_t rule_id, uint8_t on);
 181 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 182                 uint8_t rule_id);
 183
 184 /*
 185  * Define VF Stats MACRO for Non "cleared on read" register
 186  */
 187 #define UPDATE_VF_STAT(reg, last, cur)                          \
 188 {                                                               \
 189         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 190         cur += latest - last;                                   \
 191         last = latest;                                          \
 192 }
 193
 194 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 195 {                                                                \
 196         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 197         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 198         u64 latest = ((new_msb << 32) | new_lsb);                \
 199         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 200         last = latest;                                           \
 201 }
 202
 203 #define IXGBE_SET_HWSTRIP(h, q) do{\
 204                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 205                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 206                 (h)->bitmap[idx] |= 1 << bit;\
 207         }while(0)
 208
 209 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 210                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 211                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 212                 (h)->bitmap[idx] &= ~(1 << bit);\
 213         }while(0)
 214
 215 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 216                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 217                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 218                 (r) = (h)->bitmap[idx] >> bit & 1;\
 219         }while(0)
 220
 221 /*
 222  * The set of PCI devices this driver supports
 223  */
 224 static struct rte_pci_id pci_id_ixgbe_map[] = {
 225
 226 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 227 #include "rte_pci_dev_ids.h"
 228
 229 { .vendor_id = 0, /* sentinel */ },
 230 };
 231
 232
 233 /*
 234  * The set of PCI devices this driver supports (for 82599 VF)
 235  */
 236 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 237
 238 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 239 #include "rte_pci_dev_ids.h"
 240 { .vendor_id = 0, /* sentinel */ },
 241
 242 };
 243
 244 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 245         .dev_configure        = ixgbe_dev_configure,
 246         .dev_start            = ixgbe_dev_start,
 247         .dev_stop             = ixgbe_dev_stop,
 248         .dev_close            = ixgbe_dev_close,
 249         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 250         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 251         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 252         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 253         .link_update          = ixgbe_dev_link_update,
 254         .stats_get            = ixgbe_dev_stats_get,
 255         .stats_reset          = ixgbe_dev_stats_reset,
 256         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 257         .dev_infos_get        = ixgbe_dev_info_get,
 258         .vlan_filter_set      = ixgbe_vlan_filter_set,
 259         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 260         .vlan_offload_set     = ixgbe_vlan_offload_set,
 261         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 262         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 263         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 264         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 265         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 266         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 267         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 268         .dev_led_on           = ixgbe_dev_led_on,
 269         .dev_led_off          = ixgbe_dev_led_off,
 270         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 271         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 272         .mac_addr_add         = ixgbe_add_rar,
 273         .mac_addr_remove      = ixgbe_remove_rar,
 274         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 275         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 276         .mirror_rule_set        = ixgbe_mirror_rule_set,
 277         .mirror_rule_reset      = ixgbe_mirror_rule_reset,
 278         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 279         .set_vf_rx            = ixgbe_set_pool_rx,
 280         .set_vf_tx            = ixgbe_set_pool_tx,
 281         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 282         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 283         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 284         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 285         .fdir_infos_get               = ixgbe_fdir_info_get,
 286         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 287         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 288         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 289         .fdir_set_masks               = ixgbe_fdir_set_masks,
 290         .reta_update          = ixgbe_dev_rss_reta_update,
 291         .reta_query           = ixgbe_dev_rss_reta_query,
 292 #ifdef RTE_NIC_BYPASS
 293         .bypass_init          = ixgbe_bypass_init,
 294         .bypass_state_set     = ixgbe_bypass_state_store,
 295         .bypass_state_show    = ixgbe_bypass_state_show,
 296         .bypass_event_set     = ixgbe_bypass_event_store,
 297         .bypass_event_show    = ixgbe_bypass_event_show,
 298         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 299         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 300         .bypass_ver_show      = ixgbe_bypass_ver_show,
 301         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 302 #endif /* RTE_NIC_BYPASS */
 303 };
 304
 305 /*
 306  * dev_ops for virtual function, bare necessities for basic vf
 307  * operation have been implemented
 308  */
 309 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 310
 311         .dev_configure        = ixgbevf_dev_configure,
 312         .dev_start            = ixgbevf_dev_start,
 313         .dev_stop             = ixgbevf_dev_stop,
 314         .link_update          = ixgbe_dev_link_update,
 315         .stats_get            = ixgbevf_dev_stats_get,
 316         .stats_reset          = ixgbevf_dev_stats_reset,
 317         .dev_close            = ixgbevf_dev_close,
 318         .dev_infos_get        = ixgbe_dev_info_get,
 319         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 320         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 321         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 322         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 323         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 324         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 325         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 326 };
 327
 328 /**
 329  * Atomically reads the link status information from global
 330  * structure rte_eth_dev.
 331  *
 332  * @param dev
 333  *   - Pointer to the structure rte_eth_dev to read from.
 334  *   - Pointer to the buffer to be saved with the link status.
 335  *
 336  * @return
 337  *   - On success, zero.
 338  *   - On failure, negative value.
 339  */
 340 static inline int
 341 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 342                                 struct rte_eth_link *link)
 343 {
 344         struct rte_eth_link *dst = link;
 345         struct rte_eth_link *src = &(dev->data->dev_link);
 346
 347         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 348                                         *(uint64_t *)src) == 0)
 349                 return -1;
 350
 351         return 0;
 352 }
 353
 354 /**
 355  * Atomically writes the link status information into global
 356  * structure rte_eth_dev.
 357  *
 358  * @param dev
 359  *   - Pointer to the structure rte_eth_dev to read from.
 360  *   - Pointer to the buffer to be saved with the link status.
 361  *
 362  * @return
 363  *   - On success, zero.
 364  *   - On failure, negative value.
 365  */
 366 static inline int
 367 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 368                                 struct rte_eth_link *link)
 369 {
 370         struct rte_eth_link *dst = &(dev->data->dev_link);
 371         struct rte_eth_link *src = link;
 372
 373         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 374                                         *(uint64_t *)src) == 0)
 375                 return -1;
 376
 377         return 0;
 378 }
 379
 380 /*
 381  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 382  */
 383 static inline int
 384 ixgbe_is_sfp(struct ixgbe_hw *hw)
 385 {
 386         switch (hw->phy.type) {
 387         case ixgbe_phy_sfp_avago:
 388         case ixgbe_phy_sfp_ftl:
 389         case ixgbe_phy_sfp_intel:
 390         case ixgbe_phy_sfp_unknown:
 391         case ixgbe_phy_sfp_passive_tyco:
 392         case ixgbe_phy_sfp_passive_unknown:
 393                 return 1;
 394         default:
 395                 return 0;
 396         }
 397 }
 398
 399 static inline int32_t
 400 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 401 {
 402         uint32_t ctrl_ext;
 403         int32_t status;
 404
 405         status = ixgbe_reset_hw(hw);
 406
 407         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 408         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 409         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 410         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 411         IXGBE_WRITE_FLUSH(hw);
 412
 413         return status;
 414 }
 415
 416 static inline void
 417 ixgbe_enable_intr(struct rte_eth_dev *dev)
 418 {
 419         struct ixgbe_interrupt *intr =
 420                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 421         struct ixgbe_hw *hw =
 422                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 423
 424         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 425         IXGBE_WRITE_FLUSH(hw);
 426 }
 427
 428 /*
 429  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 430  */
 431 static void
 432 ixgbe_disable_intr(struct ixgbe_hw *hw)
 433 {
 434         PMD_INIT_FUNC_TRACE();
 435
 436         if (hw->mac.type == ixgbe_mac_82598EB) {
 437                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 438         } else {
 439                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 440                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 441                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 442         }
 443         IXGBE_WRITE_FLUSH(hw);
 444 }
 445
 446 /*
 447  * This function resets queue statistics mapping registers.
 448  * From Niantic datasheet, Initialization of Statistics section:
 449  * "...if software requires the queue counters, the RQSMR and TQSM registers
 450  * must be re-programmed following a device reset.
 451  */
 452 static void
 453 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 454 {
 455         uint32_t i;
 456
 457         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 458                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 459                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 460         }
 461 }
 462
 463
 464 static int
 465 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 466                                   uint16_t queue_id,
 467                                   uint8_t stat_idx,
 468                                   uint8_t is_rx)
 469 {
 470 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 471 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 472 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 473
 474         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 475         struct ixgbe_stat_mapping_registers *stat_mappings =
 476                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 477         uint32_t qsmr_mask = 0;
 478         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 479         uint32_t q_map;
 480         uint8_t n, offset;
 481
 482         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 483                 return -ENOSYS;
 484
 485         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 486                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 487
 488         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 489         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 490                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 491                 return -EIO;
 492         }
 493         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 494
 495         /* Now clear any previous stat_idx set */
 496         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 497         if (!is_rx)
 498                 stat_mappings->tqsm[n] &= ~clearing_mask;
 499         else
 500                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 501
 502         q_map = (uint32_t)stat_idx;
 503         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 504         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 505         if (!is_rx)
 506                 stat_mappings->tqsm[n] |= qsmr_mask;
 507         else
 508                 stat_mappings->rqsmr[n] |= qsmr_mask;
 509
 510         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 511                      "%s[%d] = 0x%08x\n",
 512                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 513                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 514
 515         /* Now write the mapping in the appropriate register */
 516         if (is_rx) {
 517                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 518                              stat_mappings->rqsmr[n], n);
 519                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 520         }
 521         else {
 522                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 523                              stat_mappings->tqsm[n], n);
 524                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 525         }
 526         return 0;
 527 }
 528
 529 static void
 530 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 531 {
 532         struct ixgbe_stat_mapping_registers *stat_mappings =
 533                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 535         int i;
 536
 537         /* write whatever was in stat mapping table to the NIC */
 538         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 539                 /* rx */
 540                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 541
 542                 /* tx */
 543                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 544         }
 545 }
 546
 547 static void
 548 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 549 {
 550         uint8_t i;
 551         struct ixgbe_dcb_tc_config *tc;
 552         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 553
 554         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 555         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 556         for (i = 0; i < dcb_max_tc; i++) {
 557                 tc = &dcb_config->tc_config[i];
 558                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 559                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 560                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 561                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 562                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 563                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 564                 tc->pfc = ixgbe_dcb_pfc_disabled;
 565         }
 566
 567         /* Initialize default user to priority mapping, UPx->TC0 */
 568         tc = &dcb_config->tc_config[0];
 569         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 570         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 571         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 572                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 573                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 574         }
 575         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 576         dcb_config->pfc_mode_enable = false;
 577         dcb_config->vt_mode = true;
 578         dcb_config->round_robin_enable = false;
 579         /* support all DCB capabilities in 82599 */
 580         dcb_config->support.capabilities = 0xFF;
 581
 582         /*we only support 4 Tcs for X540*/
 583         if (hw->mac.type == ixgbe_mac_X540) {
 584                 dcb_config->num_tcs.pg_tcs = 4;
 585                 dcb_config->num_tcs.pfc_tcs = 4;
 586         }
 587 }
 588
 589 /*
 590  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 591  * It returns 0 on success.
 592  */
 593 static int
 594 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 595                      struct rte_eth_dev *eth_dev)
 596 {
 597         struct rte_pci_device *pci_dev;
 598         struct ixgbe_hw *hw =
 599                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 600         struct ixgbe_vfta * shadow_vfta =
 601                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 602         struct ixgbe_hwstrip *hwstrip =
 603                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 604         struct ixgbe_dcb_config *dcb_config =
 605                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 606         uint32_t ctrl_ext;
 607         uint16_t csum;
 608         int diag, i;
 609
 610         PMD_INIT_FUNC_TRACE();
 611
 612         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 613         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 614         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 615
 616         /* for secondary processes, we don't initialise any further as primary
 617          * has already done this work. Only check we don't need a different
 618          * RX function */
 619         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 620                 if (eth_dev->data->scattered_rx)
 621                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 622                 return 0;
 623         }
 624         pci_dev = eth_dev->pci_dev;
 625
 626         /* Vendor and Device ID need to be set before init of shared code */
 627         hw->device_id = pci_dev->id.device_id;
 628         hw->vendor_id = pci_dev->id.vendor_id;
 629         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 630 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 631         hw->allow_unsupported_sfp = 1;
 632 #endif
 633
 634         /* Initialize the shared code */
 635 #ifdef RTE_NIC_BYPASS
 636         diag = ixgbe_bypass_init_shared_code(hw);
 637 #else
 638         diag = ixgbe_init_shared_code(hw);
 639 #endif /* RTE_NIC_BYPASS */
 640
 641         if (diag != IXGBE_SUCCESS) {
 642                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 643                 return -EIO;
 644         }
 645
 646         /* Initialize DCB configuration*/
 647         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 648         ixgbe_dcb_init(hw,dcb_config);
 649         /* Get Hardware Flow Control setting */
 650         hw->fc.requested_mode = ixgbe_fc_full;
 651         hw->fc.current_mode = ixgbe_fc_full;
 652         hw->fc.pause_time = IXGBE_FC_PAUSE;
 653         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 654                 hw->fc.low_water[i] = IXGBE_FC_LO;
 655                 hw->fc.high_water[i] = IXGBE_FC_HI;
 656         }
 657         hw->fc.send_xon = 1;
 658
 659         /* Make sure we have a good EEPROM before we read from it */
 660         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 661         if (diag != IXGBE_SUCCESS) {
 662                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 663                 return -EIO;
 664         }
 665
 666 #ifdef RTE_NIC_BYPASS
 667         diag = ixgbe_bypass_init_hw(hw);
 668 #else
 669         diag = ixgbe_init_hw(hw);
 670 #endif /* RTE_NIC_BYPASS */
 671
 672         /*
 673          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 674          * is called too soon after the kernel driver unbinding/binding occurs.
 675          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 676          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 677          * also called. See ixgbe_identify_phy_82599(). The reason for the
 678          * failure is not known, and only occuts when virtualisation features
 679          * are disabled in the bios. A delay of 100ms  was found to be enough by
 680          * trial-and-error, and is doubled to be safe.
 681          */
 682         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 683                 rte_delay_ms(200);
 684                 diag = ixgbe_init_hw(hw);
 685         }
 686
 687         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 688                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 689                     "LOM.  Please be aware there may be issues associated "
 690                     "with your hardware.\n If you are experiencing problems "
 691                     "please contact your Intel or hardware representative "
 692                     "who provided you with this hardware.\n");
 693         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 694                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 695         if (diag) {
 696                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 697                 return -EIO;
 698         }
 699
 700         /* disable interrupt */
 701         ixgbe_disable_intr(hw);
 702
 703         /* pick up the PCI bus settings for reporting later */
 704         ixgbe_get_bus_info(hw);
 705
 706         /* reset mappings for queue statistics hw counters*/
 707         ixgbe_reset_qstat_mappings(hw);
 708
 709         /* Allocate memory for storing MAC addresses */
 710         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 711                         hw->mac.num_rar_entries, 0);
 712         if (eth_dev->data->mac_addrs == NULL) {
 713                 PMD_INIT_LOG(ERR,
 714                         "Failed to allocate %u bytes needed to store "
 715                         "MAC addresses",
 716                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 717                 return -ENOMEM;
 718         }
 719         /* Copy the permanent MAC address */
 720         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 721                         &eth_dev->data->mac_addrs[0]);
 722
 723         /* Allocate memory for storing hash filter MAC addresses */
 724         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 725                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 726         if (eth_dev->data->hash_mac_addrs == NULL) {
 727                 PMD_INIT_LOG(ERR,
 728                         "Failed to allocate %d bytes needed to store MAC addresses",
 729                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 730                 return -ENOMEM;
 731         }
 732
 733         /* initialize the vfta */
 734         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 735
 736         /* initialize the hw strip bitmap*/
 737         memset(hwstrip, 0, sizeof(*hwstrip));
 738
 739         /* initialize PF if max_vfs not zero */
 740         ixgbe_pf_host_init(eth_dev);
 741
 742         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 743         /* let hardware know driver is loaded */
 744         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 745         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 746         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 747         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 748         IXGBE_WRITE_FLUSH(hw);
 749
 750         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 751                 PMD_INIT_LOG(DEBUG,
 752                              "MAC: %d, PHY: %d, SFP+: %d<n",
 753                              (int) hw->mac.type, (int) hw->phy.type,
 754                              (int) hw->phy.sfp_type);
 755         else
 756                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 757                              (int) hw->mac.type, (int) hw->phy.type);
 758
 759         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 760                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 761                         pci_dev->id.device_id);
 762
 763         rte_intr_callback_register(&(pci_dev->intr_handle),
 764                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 765
 766         /* enable uio intr after callback register */
 767         rte_intr_enable(&(pci_dev->intr_handle));
 768
 769         /* enable support intr */
 770         ixgbe_enable_intr(eth_dev);
 771
 772         return 0;
 773 }
 774
 775 /*
 776  * Virtual Function device init
 777  */
 778 static int
 779 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 780                      struct rte_eth_dev *eth_dev)
 781 {
 782         struct rte_pci_device *pci_dev;
 783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 784         int diag;
 785         struct ixgbe_vfta * shadow_vfta =
 786                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 787         struct ixgbe_hwstrip *hwstrip =
 788                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 789
 790         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 791
 792         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 793         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 794         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 795
 796         /* for secondary processes, we don't initialise any further as primary
 797          * has already done this work. Only check we don't need a different
 798          * RX function */
 799         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 800                 if (eth_dev->data->scattered_rx)
 801                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 802                 return 0;
 803         }
 804
 805         pci_dev = eth_dev->pci_dev;
 806
 807         hw->device_id = pci_dev->id.device_id;
 808         hw->vendor_id = pci_dev->id.vendor_id;
 809         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 810
 811         /* initialize the vfta */
 812         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 813
 814         /* initialize the hw strip bitmap*/
 815         memset(hwstrip, 0, sizeof(*hwstrip));
 816
 817         /* Initialize the shared code */
 818         diag = ixgbe_init_shared_code(hw);
 819         if (diag != IXGBE_SUCCESS) {
 820                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 821                 return -EIO;
 822         }
 823
 824         /* init_mailbox_params */
 825         hw->mbx.ops.init_params(hw);
 826
 827         /* Disable the interrupts for VF */
 828         ixgbevf_intr_disable(hw);
 829
 830         hw->mac.num_rar_entries = hw->mac.max_rx_queues;
 831         diag = hw->mac.ops.reset_hw(hw);
 832
 833         if (diag != IXGBE_SUCCESS) {
 834                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 835                         RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
 836                                         "\tThe most likely cause of this error is that the VM host\n"
 837                                         "\thas not assigned a valid MAC address to this VF device.\n"
 838                                         "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
 839                                         "\ta possible solution to this problem.\n");
 840                 return (diag);
 841         }
 842
 843         /* Allocate memory for storing MAC addresses */
 844         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 845                         hw->mac.num_rar_entries, 0);
 846         if (eth_dev->data->mac_addrs == NULL) {
 847                 PMD_INIT_LOG(ERR,
 848                         "Failed to allocate %u bytes needed to store "
 849                         "MAC addresses",
 850                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 851                 return -ENOMEM;
 852         }
 853
 854         /* Copy the permanent MAC address */
 855         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 856                         &eth_dev->data->mac_addrs[0]);
 857
 858         /* reset the hardware with the new settings */
 859         diag = hw->mac.ops.start_hw(hw);
 860         switch (diag) {
 861                 case  0:
 862                         break;
 863
 864                 default:
 865                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 866                         return (-EIO);
 867         }
 868
 869         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
 870                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
 871                          "ixgbe_mac_82599_vf");
 872
 873         return 0;
 874 }
 875
 876 static struct eth_driver rte_ixgbe_pmd = {
 877         {
 878                 .name = "rte_ixgbe_pmd",
 879                 .id_table = pci_id_ixgbe_map,
 880 #ifdef RTE_EAL_UNBIND_PORTS
 881                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 882 #endif
 883         },
 884         .eth_dev_init = eth_ixgbe_dev_init,
 885         .dev_private_size = sizeof(struct ixgbe_adapter),
 886 };
 887
 888 /*
 889  * virtual function driver struct
 890  */
 891 static struct eth_driver rte_ixgbevf_pmd = {
 892         {
 893                 .name = "rte_ixgbevf_pmd",
 894                 .id_table = pci_id_ixgbevf_map,
 895 #ifdef RTE_EAL_UNBIND_PORTS
 896                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 897 #endif
 898         },
 899         .eth_dev_init = eth_ixgbevf_dev_init,
 900         .dev_private_size = sizeof(struct ixgbe_adapter),
 901 };
 902
 903 /*
 904  * Driver initialization routine.
 905  * Invoked once at EAL init time.
 906  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 907  */
 908 int
 909 rte_ixgbe_pmd_init(void)
 910 {
 911         PMD_INIT_FUNC_TRACE();
 912
 913         rte_eth_driver_register(&rte_ixgbe_pmd);
 914         return 0;
 915 }
 916
 917 /*
 918  * VF Driver initialization routine.
 919  * Invoked one at EAL init time.
 920  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
 921  */
 922 int
 923 rte_ixgbevf_pmd_init(void)
 924 {
 925         DEBUGFUNC("rte_ixgbevf_pmd_init");
 926
 927         rte_eth_driver_register(&rte_ixgbevf_pmd);
 928         return (0);
 929 }
 930
 931 static int
 932 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 933 {
 934         struct ixgbe_hw *hw =
 935                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936         struct ixgbe_vfta * shadow_vfta =
 937                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 938         uint32_t vfta;
 939         uint32_t vid_idx;
 940         uint32_t vid_bit;
 941
 942         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
 943         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
 944         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
 945         if (on)
 946                 vfta |= vid_bit;
 947         else
 948                 vfta &= ~vid_bit;
 949         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
 950
 951         /* update local VFTA copy */
 952         shadow_vfta->vfta[vid_idx] = vfta;
 953
 954         return 0;
 955 }
 956
 957 static void
 958 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 959 {
 960         if (on)
 961                 ixgbe_vlan_hw_strip_enable(dev, queue);
 962         else
 963                 ixgbe_vlan_hw_strip_disable(dev, queue);
 964 }
 965
 966 static void
 967 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
 968 {
 969         struct ixgbe_hw *hw =
 970                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 971
 972         /* Only the high 16-bits is valid */
 973         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
 974 }
 975
 976 void
 977 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
 978 {
 979         struct ixgbe_hw *hw =
 980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 981         uint32_t vlnctrl;
 982
 983         PMD_INIT_FUNC_TRACE();
 984
 985         /* Filter Table Disable */
 986         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 987         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
 988
 989         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
 990 }
 991
 992 void
 993 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 994 {
 995         struct ixgbe_hw *hw =
 996                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997         struct ixgbe_vfta * shadow_vfta =
 998                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 999         uint32_t vlnctrl;
1000         uint16_t i;
1001
1002         PMD_INIT_FUNC_TRACE();
1003
1004         /* Filter Table Enable */
1005         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1006         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1007         vlnctrl |= IXGBE_VLNCTRL_VFE;
1008
1009         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1010
1011         /* write whatever is in local vfta copy */
1012         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1013                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1014 }
1015
1016 static void
1017 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1018 {
1019         struct ixgbe_hwstrip *hwstrip =
1020                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1021
1022         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1023                 return;
1024
1025         if (on)
1026                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1027         else
1028                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1029 }
1030
1031 static void
1032 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1033 {
1034         struct ixgbe_hw *hw =
1035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036         uint32_t ctrl;
1037
1038         PMD_INIT_FUNC_TRACE();
1039
1040         if (hw->mac.type == ixgbe_mac_82598EB) {
1041                 /* No queue level support */
1042                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1043                 return;
1044         }
1045         else {
1046                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1047                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1048                 ctrl &= ~IXGBE_RXDCTL_VME;
1049                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1050         }
1051         /* record those setting for HW strip per queue */
1052         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1053 }
1054
1055 static void
1056 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1057 {
1058         struct ixgbe_hw *hw =
1059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060         uint32_t ctrl;
1061
1062         PMD_INIT_FUNC_TRACE();
1063
1064         if (hw->mac.type == ixgbe_mac_82598EB) {
1065                 /* No queue level supported */
1066                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1067                 return;
1068         }
1069         else {
1070                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1071                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1072                 ctrl |= IXGBE_RXDCTL_VME;
1073                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1074         }
1075         /* record those setting for HW strip per queue */
1076         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1077 }
1078
1079 void
1080 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1081 {
1082         struct ixgbe_hw *hw =
1083                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084         uint32_t ctrl;
1085         uint16_t i;
1086
1087         PMD_INIT_FUNC_TRACE();
1088
1089         if (hw->mac.type == ixgbe_mac_82598EB) {
1090                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1091                 ctrl &= ~IXGBE_VLNCTRL_VME;
1092                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1093         }
1094         else {
1095                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1096                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1097                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1098                         ctrl &= ~IXGBE_RXDCTL_VME;
1099                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1100
1101                         /* record those setting for HW strip per queue */
1102                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1103                 }
1104         }
1105 }
1106
1107 void
1108 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1109 {
1110         struct ixgbe_hw *hw =
1111                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112         uint32_t ctrl;
1113         uint16_t i;
1114
1115         PMD_INIT_FUNC_TRACE();
1116
1117         if (hw->mac.type == ixgbe_mac_82598EB) {
1118                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1119                 ctrl |= IXGBE_VLNCTRL_VME;
1120                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1121         }
1122         else {
1123                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1124                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1125                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1126                         ctrl |= IXGBE_RXDCTL_VME;
1127                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1128
1129                         /* record those setting for HW strip per queue */
1130                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1131                 }
1132         }
1133 }
1134
1135 static void
1136 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1137 {
1138         struct ixgbe_hw *hw =
1139                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1140         uint32_t ctrl;
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         /* DMATXCTRL: Geric Double VLAN Disable */
1145         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1146         ctrl &= ~IXGBE_DMATXCTL_GDV;
1147         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1148
1149         /* CTRL_EXT: Global Double VLAN Disable */
1150         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1151         ctrl &= ~IXGBE_EXTENDED_VLAN;
1152         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1153
1154 }
1155
1156 static void
1157 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1158 {
1159         struct ixgbe_hw *hw =
1160                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1161         uint32_t ctrl;
1162
1163         PMD_INIT_FUNC_TRACE();
1164
1165         /* DMATXCTRL: Geric Double VLAN Enable */
1166         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1167         ctrl |= IXGBE_DMATXCTL_GDV;
1168         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1169
1170         /* CTRL_EXT: Global Double VLAN Enable */
1171         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1172         ctrl |= IXGBE_EXTENDED_VLAN;
1173         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1174
1175         /*
1176          * VET EXT field in the EXVET register = 0x8100 by default
1177          * So no need to change. Same to VT field of DMATXCTL register
1178          */
1179 }
1180
1181 static void
1182 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1183 {
1184         if(mask & ETH_VLAN_STRIP_MASK){
1185                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1186                         ixgbe_vlan_hw_strip_enable_all(dev);
1187                 else
1188                         ixgbe_vlan_hw_strip_disable_all(dev);
1189         }
1190
1191         if(mask & ETH_VLAN_FILTER_MASK){
1192                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1193                         ixgbe_vlan_hw_filter_enable(dev);
1194                 else
1195                         ixgbe_vlan_hw_filter_disable(dev);
1196         }
1197
1198         if(mask & ETH_VLAN_EXTEND_MASK){
1199                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1200                         ixgbe_vlan_hw_extend_enable(dev);
1201                 else
1202                         ixgbe_vlan_hw_extend_disable(dev);
1203         }
1204 }
1205
1206 static void
1207 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1208 {
1209         struct ixgbe_hw *hw =
1210                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1212         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1213         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1214         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1215 }
1216
1217 static int
1218 ixgbe_dev_configure(struct rte_eth_dev *dev)
1219 {
1220         struct ixgbe_interrupt *intr =
1221                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1222
1223         PMD_INIT_FUNC_TRACE();
1224
1225         /* set flag to update link status after init */
1226         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1227
1228         return 0;
1229 }
1230
1231 /*
1232  * Configure device link speed and setup link.
1233  * It returns 0 on success.
1234  */
1235 static int
1236 ixgbe_dev_start(struct rte_eth_dev *dev)
1237 {
1238         struct ixgbe_hw *hw =
1239                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1240         int err, link_up = 0, negotiate = 0;
1241         uint32_t speed = 0;
1242         int mask = 0;
1243         int status;
1244
1245         PMD_INIT_FUNC_TRACE();
1246
1247         /* IXGBE devices don't support half duplex */
1248         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1249                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1250                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1251                                 dev->data->dev_conf.link_duplex,
1252                                 dev->data->port_id);
1253                 return -EINVAL;
1254         }
1255
1256         /* stop adapter */
1257         hw->adapter_stopped = FALSE;
1258         ixgbe_stop_adapter(hw);
1259
1260         /* reinitialize adapter
1261          * this calls reset and start */
1262         status = ixgbe_pf_reset_hw(hw);
1263         if (status != 0)
1264                 return -1;
1265         hw->mac.ops.start_hw(hw);
1266
1267         /* configure PF module if SRIOV enabled */
1268         ixgbe_pf_host_configure(dev);
1269
1270         /* initialize transmission unit */
1271         ixgbe_dev_tx_init(dev);
1272
1273         /* This can fail when allocating mbufs for descriptor rings */
1274         err = ixgbe_dev_rx_init(dev);
1275         if (err) {
1276                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1277                 goto error;
1278         }
1279
1280         ixgbe_dev_rxtx_start(dev);
1281
1282         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1283                 err = hw->mac.ops.setup_sfp(hw);
1284                 if (err)
1285                         goto error;
1286         }
1287
1288         /* Turn on the laser */
1289         ixgbe_enable_tx_laser(hw);
1290
1291         /* Skip link setup if loopback mode is enabled for 82599. */
1292         if (hw->mac.type == ixgbe_mac_82599EB &&
1293                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1294                 goto skip_link_setup;
1295
1296         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1297         if (err)
1298                 goto error;
1299         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1300         if (err)
1301                 goto error;
1302
1303         switch(dev->data->dev_conf.link_speed) {
1304         case ETH_LINK_SPEED_AUTONEG:
1305                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1306                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1307                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1308                 break;
1309         case ETH_LINK_SPEED_100:
1310                 /*
1311                  * Invalid for 82598 but error will be detected by
1312                  * ixgbe_setup_link()
1313                  */
1314                 speed = IXGBE_LINK_SPEED_100_FULL;
1315                 break;
1316         case ETH_LINK_SPEED_1000:
1317                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1318                 break;
1319         case ETH_LINK_SPEED_10000:
1320                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1321                 break;
1322         default:
1323                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1324                                 dev->data->dev_conf.link_speed,
1325                                 dev->data->port_id);
1326                 goto error;
1327         }
1328
1329         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1330         if (err)
1331                 goto error;
1332
1333 skip_link_setup:
1334
1335         /* check if lsc interrupt is enabled */
1336         if (dev->data->dev_conf.intr_conf.lsc != 0)
1337                 ixgbe_dev_lsc_interrupt_setup(dev);
1338
1339         /* resume enabled intr since hw reset */
1340         ixgbe_enable_intr(dev);
1341
1342         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1343                 ETH_VLAN_EXTEND_MASK;
1344         ixgbe_vlan_offload_set(dev, mask);
1345
1346         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1347                 /* Enable vlan filtering for VMDq */
1348                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1349         }
1350
1351         /* Configure DCB hw */
1352         ixgbe_configure_dcb(dev);
1353
1354         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1355                 err = ixgbe_fdir_configure(dev);
1356                 if (err)
1357                         goto error;
1358         }
1359
1360         ixgbe_restore_statistics_mapping(dev);
1361
1362         return (0);
1363
1364 error:
1365         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1366         ixgbe_dev_clear_queues(dev);
1367         return -EIO;
1368 }
1369
1370 /*
1371  * Stop device: disable rx and tx functions to allow for reconfiguring.
1372  */
1373 static void
1374 ixgbe_dev_stop(struct rte_eth_dev *dev)
1375 {
1376         struct rte_eth_link link;
1377         struct ixgbe_hw *hw =
1378                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1379
1380         PMD_INIT_FUNC_TRACE();
1381
1382         /* disable interrupts */
1383         ixgbe_disable_intr(hw);
1384
1385         /* reset the NIC */
1386         ixgbe_pf_reset_hw(hw);
1387         hw->adapter_stopped = FALSE;
1388
1389         /* stop adapter */
1390         ixgbe_stop_adapter(hw);
1391
1392         /* Turn off the laser */
1393         ixgbe_disable_tx_laser(hw);
1394
1395         ixgbe_dev_clear_queues(dev);
1396
1397         /* Clear recorded link status */
1398         memset(&link, 0, sizeof(link));
1399         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1400 }
1401
1402 /*
1403  * Reest and stop device.
1404  */
1405 static void
1406 ixgbe_dev_close(struct rte_eth_dev *dev)
1407 {
1408         struct ixgbe_hw *hw =
1409                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1410
1411         PMD_INIT_FUNC_TRACE();
1412
1413         ixgbe_pf_reset_hw(hw);
1414
1415         ixgbe_dev_stop(dev);
1416         hw->adapter_stopped = 1;
1417
1418         ixgbe_disable_pcie_master(hw);
1419
1420         /* reprogram the RAR[0] in case user changed it. */
1421         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1422 }
1423
1424 /*
1425  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1426  */
1427 static void
1428 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1429 {
1430         struct ixgbe_hw *hw =
1431                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1432         struct ixgbe_hw_stats *hw_stats =
1433                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1434         uint32_t bprc, lxon, lxoff, total;
1435         uint64_t total_missed_rx, total_qbrc, total_qprc;
1436         unsigned i;
1437
1438         total_missed_rx = 0;
1439         total_qbrc = 0;
1440         total_qprc = 0;
1441
1442         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1443         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1444         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1445         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1446
1447         for (i = 0; i < 8; i++) {
1448                 uint32_t mp;
1449                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1450                 /* global total per queue */
1451                 hw_stats->mpc[i] += mp;
1452                 /* Running comprehensive total for stats display */
1453                 total_missed_rx += hw_stats->mpc[i];
1454                 if (hw->mac.type == ixgbe_mac_82598EB)
1455                         hw_stats->rnbc[i] +=
1456                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1457                 hw_stats->pxontxc[i] +=
1458                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1459                 hw_stats->pxonrxc[i] +=
1460                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1461                 hw_stats->pxofftxc[i] +=
1462                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1463                 hw_stats->pxoffrxc[i] +=
1464                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1465                 hw_stats->pxon2offc[i] +=
1466                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1467         }
1468         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1469                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1470                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1471                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1472                 hw_stats->qbrc[i] +=
1473                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1474                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1475                 hw_stats->qbtc[i] +=
1476                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1477                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1478
1479                 total_qprc += hw_stats->qprc[i];
1480                 total_qbrc += hw_stats->qbrc[i];
1481         }
1482         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1483         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1484         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1485
1486         /* Note that gprc counts missed packets */
1487         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1488
1489         if (hw->mac.type != ixgbe_mac_82598EB) {
1490                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1491                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1492                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1493                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1494                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1495                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1496                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1497                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1498         } else {
1499                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1500                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1501                 /* 82598 only has a counter in the high register */
1502                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1503                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1504                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1505         }
1506
1507         /*
1508          * Workaround: mprc hardware is incorrectly counting
1509          * broadcasts, so for now we subtract those.
1510          */
1511         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1512         hw_stats->bprc += bprc;
1513         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1514         if (hw->mac.type == ixgbe_mac_82598EB)
1515                 hw_stats->mprc -= bprc;
1516
1517         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1518         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1519         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1520         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1521         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1522         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1523
1524         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1525         hw_stats->lxontxc += lxon;
1526         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1527         hw_stats->lxofftxc += lxoff;
1528         total = lxon + lxoff;
1529
1530         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1531         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1532         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1533         hw_stats->gptc -= total;
1534         hw_stats->mptc -= total;
1535         hw_stats->ptc64 -= total;
1536         hw_stats->gotc -= total * ETHER_MIN_LEN;
1537
1538         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1539         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1540         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1541         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1542         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1543         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1544         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1545         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1546         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1547         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1548         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1549         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1550         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1551         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1552         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1553         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1554         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1555         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1556         /* Only read FCOE on 82599 */
1557         if (hw->mac.type != ixgbe_mac_82598EB) {
1558                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1559                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1560                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1561                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1562                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1563         }
1564
1565         if (stats == NULL)
1566                 return;
1567
1568         /* Fill out the rte_eth_stats statistics structure */
1569         stats->ipackets = total_qprc;
1570         stats->ibytes = total_qbrc;
1571         stats->opackets = hw_stats->gptc;
1572         stats->obytes = hw_stats->gotc;
1573         stats->imcasts = hw_stats->mprc;
1574
1575         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1576                 stats->q_ipackets[i] = hw_stats->qprc[i];
1577                 stats->q_opackets[i] = hw_stats->qptc[i];
1578                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1579                 stats->q_obytes[i] = hw_stats->qbtc[i];
1580                 stats->q_errors[i] = hw_stats->qprdc[i];
1581         }
1582
1583         /* Rx Errors */
1584         stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1585                 hw_stats->rlec;
1586
1587         stats->oerrors  = 0;
1588
1589         /* Flow Director Stats registers */
1590         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1591         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1592         stats->fdirmatch = hw_stats->fdirmatch;
1593         stats->fdirmiss = hw_stats->fdirmiss;
1594 }
1595
1596 static void
1597 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1598 {
1599         struct ixgbe_hw_stats *stats =
1600                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1601
1602         /* HW registers are cleared on read */
1603         ixgbe_dev_stats_get(dev, NULL);
1604
1605         /* Reset software totals */
1606         memset(stats, 0, sizeof(*stats));
1607 }
1608
1609 static void
1610 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1611 {
1612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1614                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1615
1616         /* Good Rx packet, include VF loopback */
1617         UPDATE_VF_STAT(IXGBE_VFGPRC,
1618             hw_stats->last_vfgprc, hw_stats->vfgprc);
1619
1620         /* Good Rx octets, include VF loopback */
1621         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1622             hw_stats->last_vfgorc, hw_stats->vfgorc);
1623
1624         /* Good Tx packet, include VF loopback */
1625         UPDATE_VF_STAT(IXGBE_VFGPTC,
1626             hw_stats->last_vfgptc, hw_stats->vfgptc);
1627
1628         /* Good Tx octets, include VF loopback */
1629         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1630             hw_stats->last_vfgotc, hw_stats->vfgotc);
1631
1632         /* Rx Multicst Packet */
1633         UPDATE_VF_STAT(IXGBE_VFMPRC,
1634             hw_stats->last_vfmprc, hw_stats->vfmprc);
1635
1636         if (stats == NULL)
1637                 return;
1638
1639         memset(stats, 0, sizeof(*stats));
1640         stats->ipackets = hw_stats->vfgprc;
1641         stats->ibytes = hw_stats->vfgorc;
1642         stats->opackets = hw_stats->vfgptc;
1643         stats->obytes = hw_stats->vfgotc;
1644         stats->imcasts = hw_stats->vfmprc;
1645 }
1646
1647 static void
1648 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1649 {
1650         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1651                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1652
1653         /* Sync HW register to the last stats */
1654         ixgbevf_dev_stats_get(dev, NULL);
1655
1656         /* reset HW current stats*/
1657         hw_stats->vfgprc = 0;
1658         hw_stats->vfgorc = 0;
1659         hw_stats->vfgptc = 0;
1660         hw_stats->vfgotc = 0;
1661         hw_stats->vfmprc = 0;
1662
1663 }
1664
1665 static void
1666 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1667 {
1668         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1669
1670         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1671         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1672         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1673         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1674         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1675         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1676         dev_info->max_vfs = dev->pci_dev->max_vfs;
1677         if (hw->mac.type == ixgbe_mac_82598EB)
1678                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1679         else
1680                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1681 }
1682
1683 /* return 0 means link status changed, -1 means not changed */
1684 static int
1685 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1686 {
1687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1688         struct rte_eth_link link, old;
1689         ixgbe_link_speed link_speed;
1690         int link_up;
1691         int diag;
1692
1693         link.link_status = 0;
1694         link.link_speed = 0;
1695         link.link_duplex = 0;
1696         memset(&old, 0, sizeof(old));
1697         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1698
1699         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1700         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1701                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1702         else
1703                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1704         if (diag != 0) {
1705                 link.link_speed = ETH_LINK_SPEED_100;
1706                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1707                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1708                 if (link.link_status == old.link_status)
1709                         return -1;
1710                 return 0;
1711         }
1712
1713         if (link_up == 0) {
1714                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1715                 if (link.link_status == old.link_status)
1716                         return -1;
1717                 return 0;
1718         }
1719         link.link_status = 1;
1720         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1721
1722         switch (link_speed) {
1723         default:
1724         case IXGBE_LINK_SPEED_UNKNOWN:
1725                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1726                 link.link_speed = ETH_LINK_SPEED_100;
1727                 break;
1728
1729         case IXGBE_LINK_SPEED_100_FULL:
1730                 link.link_speed = ETH_LINK_SPEED_100;
1731                 break;
1732
1733         case IXGBE_LINK_SPEED_1GB_FULL:
1734                 link.link_speed = ETH_LINK_SPEED_1000;
1735                 break;
1736
1737         case IXGBE_LINK_SPEED_10GB_FULL:
1738                 link.link_speed = ETH_LINK_SPEED_10000;
1739                 break;
1740         }
1741         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1742
1743         if (link.link_status == old.link_status)
1744                 return -1;
1745
1746         return 0;
1747 }
1748
1749 static void
1750 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1751 {
1752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1753         uint32_t fctrl;
1754
1755         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1756         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1757         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1758 }
1759
1760 static void
1761 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1762 {
1763         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764         uint32_t fctrl;
1765
1766         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1767         fctrl &= (~IXGBE_FCTRL_UPE);
1768         if (dev->data->all_multicast == 1)
1769                 fctrl |= IXGBE_FCTRL_MPE;
1770         else
1771                 fctrl &= (~IXGBE_FCTRL_MPE);
1772         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1773 }
1774
1775 static void
1776 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1777 {
1778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1779         uint32_t fctrl;
1780
1781         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1782         fctrl |= IXGBE_FCTRL_MPE;
1783         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1784 }
1785
1786 static void
1787 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1788 {
1789         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1790         uint32_t fctrl;
1791
1792         if (dev->data->promiscuous == 1)
1793                 return; /* must remain in all_multicast mode */
1794
1795         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1796         fctrl &= (~IXGBE_FCTRL_MPE);
1797         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1798 }
1799
1800 /**
1801  * It clears the interrupt causes and enables the interrupt.
1802  * It will be called once only during nic initialized.
1803  *
1804  * @param dev
1805  *  Pointer to struct rte_eth_dev.
1806  *
1807  * @return
1808  *  - On success, zero.
1809  *  - On failure, a negative value.
1810  */
1811 static int
1812 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1813 {
1814         struct ixgbe_interrupt *intr =
1815                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1816
1817         ixgbe_dev_link_status_print(dev);
1818         intr->mask |= IXGBE_EICR_LSC;
1819
1820         return 0;
1821 }
1822
1823 /*
1824  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1825  *
1826  * @param dev
1827  *  Pointer to struct rte_eth_dev.
1828  *
1829  * @return
1830  *  - On success, zero.
1831  *  - On failure, a negative value.
1832  */
1833 static int
1834 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1835 {
1836         uint32_t eicr;
1837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838         struct ixgbe_interrupt *intr =
1839                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1840
1841         /* clear all cause mask */
1842         ixgbe_disable_intr(hw);
1843
1844         /* read-on-clear nic registers here */
1845         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1846         PMD_DRV_LOG(INFO, "eicr %x", eicr);
1847
1848         intr->flags = 0;
1849         if (eicr & IXGBE_EICR_LSC) {
1850                 /* set flag for async link update */
1851                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1852         }
1853
1854         if (eicr & IXGBE_EICR_MAILBOX)
1855                 intr->flags |= IXGBE_FLAG_MAILBOX;
1856
1857         return 0;
1858 }
1859
1860 /**
1861  * It gets and then prints the link status.
1862  *
1863  * @param dev
1864  *  Pointer to struct rte_eth_dev.
1865  *
1866  * @return
1867  *  - On success, zero.
1868  *  - On failure, a negative value.
1869  */
1870 static void
1871 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1872 {
1873         struct rte_eth_link link;
1874
1875         memset(&link, 0, sizeof(link));
1876         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1877         if (link.link_status) {
1878                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1879                                         (int)(dev->data->port_id),
1880                                         (unsigned)link.link_speed,
1881                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1882                                         "full-duplex" : "half-duplex");
1883         } else {
1884                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1885                                 (int)(dev->data->port_id));
1886         }
1887         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1888                                 dev->pci_dev->addr.domain,
1889                                 dev->pci_dev->addr.bus,
1890                                 dev->pci_dev->addr.devid,
1891                                 dev->pci_dev->addr.function);
1892 }
1893
1894 /*
1895  * It executes link_update after knowing an interrupt occured.
1896  *
1897  * @param dev
1898  *  Pointer to struct rte_eth_dev.
1899  *
1900  * @return
1901  *  - On success, zero.
1902  *  - On failure, a negative value.
1903  */
1904 static int
1905 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1906 {
1907         struct ixgbe_interrupt *intr =
1908                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1909         int64_t timeout;
1910         struct rte_eth_link link;
1911         int intr_enable_delay = false;
1912
1913         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1914
1915         if (intr->flags & IXGBE_FLAG_MAILBOX) {
1916                 ixgbe_pf_mbx_process(dev);
1917                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1918         }
1919
1920         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1921                 /* get the link status before link update, for predicting later */
1922                 memset(&link, 0, sizeof(link));
1923                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1924
1925                 ixgbe_dev_link_update(dev, 0);
1926
1927                 /* likely to up */
1928                 if (!link.link_status)
1929                         /* handle it 1 sec later, wait it being stable */
1930                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1931                 /* likely to down */
1932                 else
1933                         /* handle it 4 sec later, wait it being stable */
1934                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1935
1936                 ixgbe_dev_link_status_print(dev);
1937
1938                 intr_enable_delay = true;
1939         }
1940
1941         if (intr_enable_delay) {
1942                 if (rte_eal_alarm_set(timeout * 1000,
1943                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
1944                         PMD_DRV_LOG(ERR, "Error setting alarm");
1945         } else {
1946                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
1947                 ixgbe_enable_intr(dev);
1948                 rte_intr_enable(&(dev->pci_dev->intr_handle));
1949         }
1950
1951
1952         return 0;
1953 }
1954
1955 /**
1956  * Interrupt handler which shall be registered for alarm callback for delayed
1957  * handling specific interrupt to wait for the stable nic state. As the
1958  * NIC interrupt state is not stable for ixgbe after link is just down,
1959  * it needs to wait 4 seconds to get the stable status.
1960  *
1961  * @param handle
1962  *  Pointer to interrupt handle.
1963  * @param param
1964  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1965  *
1966  * @return
1967  *  void
1968  */
1969 static void
1970 ixgbe_dev_interrupt_delayed_handler(void *param)
1971 {
1972         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1973         struct ixgbe_interrupt *intr =
1974                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1975         struct ixgbe_hw *hw =
1976                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977         uint32_t eicr;
1978
1979         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1980         if (eicr & IXGBE_EICR_MAILBOX)
1981                 ixgbe_pf_mbx_process(dev);
1982
1983         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1984                 ixgbe_dev_link_update(dev, 0);
1985                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
1986                 ixgbe_dev_link_status_print(dev);
1987                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1988         }
1989
1990         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
1991         ixgbe_enable_intr(dev);
1992         rte_intr_enable(&(dev->pci_dev->intr_handle));
1993 }
1994
1995 /**
1996  * Interrupt handler triggered by NIC  for handling
1997  * specific interrupt.
1998  *
1999  * @param handle
2000  *  Pointer to interrupt handle.
2001  * @param param
2002  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2003  *
2004  * @return
2005  *  void
2006  */
2007 static void
2008 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2009                                                         void *param)
2010 {
2011         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2012         ixgbe_dev_interrupt_get_status(dev);
2013         ixgbe_dev_interrupt_action(dev);
2014 }
2015
2016 static int
2017 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2018 {
2019         struct ixgbe_hw *hw;
2020
2021         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2023 }
2024
2025 static int
2026 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2027 {
2028         struct ixgbe_hw *hw;
2029
2030         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2032 }
2033
2034 static int
2035 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2036 {
2037         struct ixgbe_hw *hw;
2038         int err;
2039         uint32_t rx_buf_size;
2040         uint32_t max_high_water;
2041         uint32_t mflcn;
2042         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2043                 ixgbe_fc_none,
2044                 ixgbe_fc_rx_pause,
2045                 ixgbe_fc_tx_pause,
2046                 ixgbe_fc_full
2047         };
2048
2049         PMD_INIT_FUNC_TRACE();
2050
2051         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2053         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2054
2055         /*
2056          * At least reserve one Ethernet frame for watermark
2057          * high_water/low_water in kilo bytes for ixgbe
2058          */
2059         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2060         if ((fc_conf->high_water > max_high_water) ||
2061                 (fc_conf->high_water < fc_conf->low_water)) {
2062                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2063                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2064                 return (-EINVAL);
2065         }
2066
2067         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2068         hw->fc.pause_time     = fc_conf->pause_time;
2069         hw->fc.high_water[0]  = fc_conf->high_water;
2070         hw->fc.low_water[0]   = fc_conf->low_water;
2071         hw->fc.send_xon       = fc_conf->send_xon;
2072
2073         err = ixgbe_fc_enable(hw);
2074
2075         /* Not negotiated is not an error case */
2076         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2077
2078                 /* check if we want to forward MAC frames - driver doesn't have native
2079                  * capability to do that, so we'll write the registers ourselves */
2080
2081                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2082
2083                 /* set or clear MFLCN.PMCF bit depending on configuration */
2084                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2085                         mflcn |= IXGBE_MFLCN_PMCF;
2086                 else
2087                         mflcn &= ~IXGBE_MFLCN_PMCF;
2088
2089                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2090                 IXGBE_WRITE_FLUSH(hw);
2091
2092                 return 0;
2093         }
2094
2095         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2096         return -EIO;
2097 }
2098
2099 /**
2100  *  ixgbe_pfc_enable_generic - Enable flow control
2101  *  @hw: pointer to hardware structure
2102  *  @tc_num: traffic class number
2103  *  Enable flow control according to the current settings.
2104  */
2105 static int
2106 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2107 {
2108         int ret_val = 0;
2109         uint32_t mflcn_reg, fccfg_reg;
2110         uint32_t reg;
2111         uint32_t fcrtl, fcrth;
2112         uint8_t i;
2113         uint8_t nb_rx_en;
2114
2115         /* Validate the water mark configuration */
2116         if (!hw->fc.pause_time) {
2117                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2118                 goto out;
2119         }
2120
2121         /* Low water mark of zero causes XOFF floods */
2122         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2123                  /* High/Low water can not be 0 */
2124                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2125                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2126                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2127                         goto out;
2128                 }
2129
2130                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2131                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2132                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2133                         goto out;
2134                 }
2135         }
2136         /* Negotiate the fc mode to use */
2137         ixgbe_fc_autoneg(hw);
2138
2139         /* Disable any previous flow control settings */
2140         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2141         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2142
2143         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2144         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2145
2146         switch (hw->fc.current_mode) {
2147         case ixgbe_fc_none:
2148                 /*
2149                  * If the count of enabled RX Priority Flow control >1,
2150                  * and the TX pause can not be disabled
2151                  */
2152                 nb_rx_en = 0;
2153                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2154                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2155                         if (reg & IXGBE_FCRTH_FCEN)
2156                                 nb_rx_en++;
2157                 }
2158                 if (nb_rx_en > 1)
2159                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2160                 break;
2161         case ixgbe_fc_rx_pause:
2162                 /*
2163                  * Rx Flow control is enabled and Tx Flow control is
2164                  * disabled by software override. Since there really
2165                  * isn't a way to advertise that we are capable of RX
2166                  * Pause ONLY, we will advertise that we support both
2167                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2168                  * disable the adapter's ability to send PAUSE frames.
2169                  */
2170                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2171                 /*
2172                  * If the count of enabled RX Priority Flow control >1,
2173                  * and the TX pause can not be disabled
2174                  */
2175                 nb_rx_en = 0;
2176                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2177                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2178                         if (reg & IXGBE_FCRTH_FCEN)
2179                                 nb_rx_en++;
2180                 }
2181                 if (nb_rx_en > 1)
2182                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2183                 break;
2184         case ixgbe_fc_tx_pause:
2185                 /*
2186                  * Tx Flow control is enabled, and Rx Flow control is
2187                  * disabled by software override.
2188                  */
2189                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2190                 break;
2191         case ixgbe_fc_full:
2192                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2193                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2194                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2195                 break;
2196         default:
2197                 DEBUGOUT("Flow control param set incorrectly\n");
2198                 ret_val = IXGBE_ERR_CONFIG;
2199                 goto out;
2200                 break;
2201         }
2202
2203         /* Set 802.3x based flow control settings. */
2204         mflcn_reg |= IXGBE_MFLCN_DPF;
2205         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2206         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2207
2208         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2209         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2210                 hw->fc.high_water[tc_num]) {
2211                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2212                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2213                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2214         } else {
2215                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2216                 /*
2217                  * In order to prevent Tx hangs when the internal Tx
2218                  * switch is enabled we must set the high water mark
2219                  * to the maximum FCRTH value.  This allows the Tx
2220                  * switch to function even under heavy Rx workloads.
2221                  */
2222                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2223         }
2224         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2225
2226         /* Configure pause time (2 TCs per register) */
2227         reg = hw->fc.pause_time * 0x00010001;
2228         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2229                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2230
2231         /* Configure flow control refresh threshold value */
2232         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2233
2234 out:
2235         return ret_val;
2236 }
2237
2238 static int
2239 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2240 {
2241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2243
2244         if(hw->mac.type != ixgbe_mac_82598EB) {
2245                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2246         }
2247         return ret_val;
2248 }
2249
2250 static int
2251 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2252 {
2253         int err;
2254         uint32_t rx_buf_size;
2255         uint32_t max_high_water;
2256         uint8_t tc_num;
2257         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2258         struct ixgbe_hw *hw =
2259                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2260         struct ixgbe_dcb_config *dcb_config =
2261                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2262
2263         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2264                 ixgbe_fc_none,
2265                 ixgbe_fc_rx_pause,
2266                 ixgbe_fc_tx_pause,
2267                 ixgbe_fc_full
2268         };
2269
2270         PMD_INIT_FUNC_TRACE();
2271
2272         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2273         tc_num = map[pfc_conf->priority];
2274         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2275         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2276         /*
2277          * At least reserve one Ethernet frame for watermark
2278          * high_water/low_water in kilo bytes for ixgbe
2279          */
2280         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2281         if ((pfc_conf->fc.high_water > max_high_water) ||
2282                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2283                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2284                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2285                 return (-EINVAL);
2286         }
2287
2288         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2289         hw->fc.pause_time = pfc_conf->fc.pause_time;
2290         hw->fc.send_xon = pfc_conf->fc.send_xon;
2291         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2292         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2293
2294         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2295
2296         /* Not negotiated is not an error case */
2297         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2298                 return 0;
2299
2300         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2301         return -EIO;
2302 }
2303
2304 static int
2305 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2306                                 struct rte_eth_rss_reta *reta_conf)
2307 {
2308         uint8_t i,j,mask;
2309         uint32_t reta;
2310         struct ixgbe_hw *hw =
2311                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2312
2313         PMD_INIT_FUNC_TRACE();
2314         /*
2315         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2316         * 128-entries in 32 registers
2317          */
2318         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2319                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2320                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2321                 else
2322                         mask = (uint8_t)((reta_conf->mask_hi >>
2323                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2324                 if (mask != 0) {
2325                         reta = 0;
2326                         if (mask != 0xF)
2327                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2328
2329                         for (j = 0; j < 4; j++) {
2330                                 if (mask & (0x1 << j)) {
2331                                         if (mask != 0xF)
2332                                                 reta &= ~(0xFF << 8 * j);
2333                                         reta |= reta_conf->reta[i + j] << 8*j;
2334                                 }
2335                         }
2336                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2337                 }
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int
2344 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2345                                 struct rte_eth_rss_reta *reta_conf)
2346 {
2347         uint8_t i,j,mask;
2348         uint32_t reta;
2349         struct ixgbe_hw *hw =
2350                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351
2352         PMD_INIT_FUNC_TRACE();
2353         /*
2354          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2355          * 128-entries in 32 registers
2356          */
2357         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2358                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2359                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2360                 else
2361                         mask = (uint8_t)((reta_conf->mask_hi >>
2362                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2363
2364                 if (mask != 0) {
2365                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2366                         for (j = 0; j < 4; j++) {
2367                                 if (mask & (0x1 << j))
2368                                         reta_conf->reta[i + j] =
2369                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2370                         }
2371                 }
2372         }
2373
2374         return 0;
2375 }
2376
2377 static void
2378 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2379                                 uint32_t index, uint32_t pool)
2380 {
2381         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2382         uint32_t enable_addr = 1;
2383
2384         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2385 }
2386
2387 static void
2388 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2389 {
2390         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391
2392         ixgbe_clear_rar(hw, index);
2393 }
2394
2395 /*
2396  * Virtual Function operations
2397  */
2398 static void
2399 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2400 {
2401         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2402
2403         /* Clear interrupt mask to stop from interrupts being generated */
2404         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2405
2406         IXGBE_WRITE_FLUSH(hw);
2407 }
2408
2409 static int
2410 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2411 {
2412         struct rte_eth_conf* conf = &dev->data->dev_conf;
2413
2414         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2415                 dev->data->port_id);
2416
2417         /*
2418          * VF has no ability to enable/disable HW CRC
2419          * Keep the persistent behavior the same as Host PF
2420          */
2421 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2422         if (!conf->rxmode.hw_strip_crc) {
2423                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2424                 conf->rxmode.hw_strip_crc = 1;
2425         }
2426 #else
2427         if (conf->rxmode.hw_strip_crc) {
2428                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2429                 conf->rxmode.hw_strip_crc = 0;
2430         }
2431 #endif
2432
2433         return 0;
2434 }
2435
2436 static int
2437 ixgbevf_dev_start(struct rte_eth_dev *dev)
2438 {
2439         struct ixgbe_hw *hw =
2440                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         int err, mask = 0;
2442
2443         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2444
2445         hw->mac.ops.reset_hw(hw);
2446
2447         ixgbevf_dev_tx_init(dev);
2448
2449         /* This can fail when allocating mbufs for descriptor rings */
2450         err = ixgbevf_dev_rx_init(dev);
2451         if (err) {
2452                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2453                 ixgbe_dev_clear_queues(dev);
2454                 return err;
2455         }
2456
2457         /* Set vfta */
2458         ixgbevf_set_vfta_all(dev,1);
2459
2460         /* Set HW strip */
2461         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2462                 ETH_VLAN_EXTEND_MASK;
2463         ixgbevf_vlan_offload_set(dev, mask);
2464
2465         ixgbevf_dev_rxtx_start(dev);
2466
2467         return 0;
2468 }
2469
2470 static void
2471 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2472 {
2473         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2474
2475         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2476
2477         hw->adapter_stopped = TRUE;
2478         ixgbe_stop_adapter(hw);
2479
2480         /*
2481           * Clear what we set, but we still keep shadow_vfta to
2482           * restore after device starts
2483           */
2484         ixgbevf_set_vfta_all(dev,0);
2485
2486         ixgbe_dev_clear_queues(dev);
2487 }
2488
2489 static void
2490 ixgbevf_dev_close(struct rte_eth_dev *dev)
2491 {
2492         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2493
2494         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2495
2496         ixgbe_reset_hw(hw);
2497
2498         ixgbevf_dev_stop(dev);
2499
2500         /* reprogram the RAR[0] in case user changed it. */
2501         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2502 }
2503
2504 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2505 {
2506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507         struct ixgbe_vfta * shadow_vfta =
2508                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2509         int i = 0, j = 0, vfta = 0, mask = 1;
2510
2511         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2512                 vfta = shadow_vfta->vfta[i];
2513                 if(vfta){
2514                         mask = 1;
2515                         for (j = 0; j < 32; j++){
2516                                 if(vfta & mask)
2517                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2518                                 mask<<=1;
2519                         }
2520                 }
2521         }
2522
2523 }
2524
2525 static int
2526 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2527 {
2528         struct ixgbe_hw *hw =
2529                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2530         struct ixgbe_vfta * shadow_vfta =
2531                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2532         uint32_t vid_idx = 0;
2533         uint32_t vid_bit = 0;
2534         int ret = 0;
2535
2536         PMD_INIT_FUNC_TRACE();
2537
2538         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2539         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2540         if(ret){
2541                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2542                 return ret;
2543         }
2544         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2545         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2546
2547         /* Save what we set and retore it after device reset */
2548         if (on)
2549                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2550         else
2551                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2552
2553         return 0;
2554 }
2555
2556 static void
2557 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2558 {
2559         struct ixgbe_hw *hw =
2560                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2561         uint32_t ctrl;
2562
2563         PMD_INIT_FUNC_TRACE();
2564
2565         if(queue >= hw->mac.max_rx_queues)
2566                 return;
2567
2568         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2569         if(on)
2570                 ctrl |= IXGBE_RXDCTL_VME;
2571         else
2572                 ctrl &= ~IXGBE_RXDCTL_VME;
2573         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2574
2575         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2576 }
2577
2578 static void
2579 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2580 {
2581         struct ixgbe_hw *hw =
2582                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2583         uint16_t i;
2584         int on = 0;
2585
2586         /* VF function only support hw strip feature, others are not support */
2587         if(mask & ETH_VLAN_STRIP_MASK){
2588                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2589
2590                 for(i=0; i < hw->mac.max_rx_queues; i++)
2591                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2592         }
2593 }
2594
2595 static int
2596 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2597 {
2598         uint32_t reg_val;
2599
2600         /* we only need to do this if VMDq is enabled */
2601         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2602         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2603                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2604                 return (-1);
2605         }
2606
2607         return 0;
2608 }
2609
2610 static uint32_t
2611 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2612 {
2613         uint32_t vector = 0;
2614         switch (hw->mac.mc_filter_type) {
2615         case 0:   /* use bits [47:36] of the address */
2616                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2617                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2618                 break;
2619         case 1:   /* use bits [46:35] of the address */
2620                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2621                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2622                 break;
2623         case 2:   /* use bits [45:34] of the address */
2624                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2625                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2626                 break;
2627         case 3:   /* use bits [43:32] of the address */
2628                 vector = ((uc_addr->addr_bytes[4]) |
2629                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2630                 break;
2631         default:  /* Invalid mc_filter_type */
2632                 break;
2633         }
2634
2635         /* vector can only be 12-bits or boundary will be exceeded */
2636         vector &= 0xFFF;
2637         return vector;
2638 }
2639
2640 static int
2641 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2642                                uint8_t on)
2643 {
2644         uint32_t vector;
2645         uint32_t uta_idx;
2646         uint32_t reg_val;
2647         uint32_t uta_shift;
2648         uint32_t rc;
2649         const uint32_t ixgbe_uta_idx_mask = 0x7F;
2650         const uint32_t ixgbe_uta_bit_shift = 5;
2651         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2652         const uint32_t bit1 = 0x1;
2653
2654         struct ixgbe_hw *hw =
2655                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656         struct ixgbe_uta_info *uta_info =
2657                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2658
2659         /* The UTA table only exists on 82599 hardware and newer */
2660         if (hw->mac.type < ixgbe_mac_82599EB)
2661                 return (-ENOTSUP);
2662
2663         vector = ixgbe_uta_vector(hw,mac_addr);
2664         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2665         uta_shift = vector & ixgbe_uta_bit_mask;
2666
2667         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2668         if(rc == on)
2669                 return 0;
2670
2671         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2672         if (on) {
2673                 uta_info->uta_in_use++;
2674                 reg_val |= (bit1 << uta_shift);
2675                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2676         } else {
2677                 uta_info->uta_in_use--;
2678                 reg_val &= ~(bit1 << uta_shift);
2679                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2680         }
2681
2682         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2683
2684         if (uta_info->uta_in_use > 0)
2685                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2686                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2687         else
2688                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2689
2690         return 0;
2691 }
2692
2693 static int
2694 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2695 {
2696         int i;
2697         struct ixgbe_hw *hw =
2698                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2699         struct ixgbe_uta_info *uta_info =
2700                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2701
2702         /* The UTA table only exists on 82599 hardware and newer */
2703         if (hw->mac.type < ixgbe_mac_82599EB)
2704                 return (-ENOTSUP);
2705
2706         if(on) {
2707                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2708                         uta_info->uta_shadow[i] = ~0;
2709                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2710                 }
2711         } else {
2712                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2713                         uta_info->uta_shadow[i] = 0;
2714                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2715                 }
2716         }
2717         return 0;
2718
2719 }
2720 static int
2721 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2722                                uint16_t rx_mask, uint8_t on)
2723 {
2724         int val = 0;
2725
2726         struct ixgbe_hw *hw =
2727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2728         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2729
2730         if (hw->mac.type == ixgbe_mac_82598EB) {
2731                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2732                         " on 82599 hardware and newer\n");
2733                 return (-ENOTSUP);
2734         }
2735         if (ixgbe_vmdq_mode_check(hw) < 0)
2736                 return (-ENOTSUP);
2737
2738         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2739                 val |= IXGBE_VMOLR_AUPE;
2740         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2741                 val |= IXGBE_VMOLR_ROMPE;
2742         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2743                 val |= IXGBE_VMOLR_ROPE;
2744         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2745                 val |= IXGBE_VMOLR_BAM;
2746         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2747                 val |= IXGBE_VMOLR_MPE;
2748
2749         if (on)
2750                 vmolr |= val;
2751         else
2752                 vmolr &= ~val;
2753
2754         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2755
2756         return 0;
2757 }
2758
2759 static int
2760 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2761 {
2762         uint32_t reg,addr;
2763         uint32_t val;
2764         const uint8_t bit1 = 0x1;
2765
2766         struct ixgbe_hw *hw =
2767                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2768
2769         if (ixgbe_vmdq_mode_check(hw) < 0)
2770                 return (-ENOTSUP);
2771
2772         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2773         reg = IXGBE_READ_REG(hw, addr);
2774         val = bit1 << pool;
2775
2776         if (on)
2777                 reg |= val;
2778         else
2779                 reg &= ~val;
2780
2781         IXGBE_WRITE_REG(hw, addr,reg);
2782
2783         return 0;
2784 }
2785
2786 static int
2787 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2788 {
2789         uint32_t reg,addr;
2790         uint32_t val;
2791         const uint8_t bit1 = 0x1;
2792
2793         struct ixgbe_hw *hw =
2794                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795
2796         if (ixgbe_vmdq_mode_check(hw) < 0)
2797                 return (-ENOTSUP);
2798
2799         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2800         reg = IXGBE_READ_REG(hw, addr);
2801         val = bit1 << pool;
2802
2803         if (on)
2804                 reg |= val;
2805         else
2806                 reg &= ~val;
2807
2808         IXGBE_WRITE_REG(hw, addr,reg);
2809
2810         return 0;
2811 }
2812
2813 static int
2814 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2815                         uint64_t pool_mask, uint8_t vlan_on)
2816 {
2817         int ret = 0;
2818         uint16_t pool_idx;
2819         struct ixgbe_hw *hw =
2820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2821
2822         if (ixgbe_vmdq_mode_check(hw) < 0)
2823                 return (-ENOTSUP);
2824         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2825                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2826                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2827                         if (ret < 0)
2828                                 return ret;
2829         }
2830
2831         return ret;
2832 }
2833
2834 static int
2835 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2836                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
2837                         uint8_t rule_id, uint8_t on)
2838 {
2839         uint32_t mr_ctl,vlvf;
2840         uint32_t mp_lsb = 0;
2841         uint32_t mv_msb = 0;
2842         uint32_t mv_lsb = 0;
2843         uint32_t mp_msb = 0;
2844         uint8_t i = 0;
2845         int reg_index = 0;
2846         uint64_t vlan_mask = 0;
2847
2848         const uint8_t pool_mask_offset = 32;
2849         const uint8_t vlan_mask_offset = 32;
2850         const uint8_t dst_pool_offset = 8;
2851         const uint8_t rule_mr_offset  = 4;
2852         const uint8_t mirror_rule_mask= 0x0F;
2853
2854         struct ixgbe_mirror_info *mr_info =
2855                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2856         struct ixgbe_hw *hw =
2857                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2858
2859         if (ixgbe_vmdq_mode_check(hw) < 0)
2860                 return (-ENOTSUP);
2861
2862         /* Check if vlan mask is valid */
2863         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2864                 if (mirror_conf->vlan.vlan_mask == 0)
2865                         return (-EINVAL);
2866         }
2867
2868         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2869         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2870                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2871                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2872                                 /* search vlan id related pool vlan filter index */
2873                                 reg_index = ixgbe_find_vlvf_slot(hw,
2874                                                 mirror_conf->vlan.vlan_id[i]);
2875                                 if(reg_index < 0)
2876                                         return (-EINVAL);
2877                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2878                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
2879                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
2880                                                 == mirror_conf->vlan.vlan_id[i]))
2881                                         vlan_mask |= (1ULL << reg_index);
2882                                 else
2883                                         return (-EINVAL);
2884                         }
2885                 }
2886
2887                 if (on) {
2888                         mv_lsb = vlan_mask & 0xFFFFFFFF;
2889                         mv_msb = vlan_mask >> vlan_mask_offset;
2890
2891                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
2892                                                 mirror_conf->vlan.vlan_mask;
2893                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2894                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2895                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2896                                                 mirror_conf->vlan.vlan_id[i];
2897                         }
2898                 } else {
2899                         mv_lsb = 0;
2900                         mv_msb = 0;
2901                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
2902                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
2903                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
2904                 }
2905         }
2906
2907         /*
2908          * if enable pool mirror, write related pool mask register,if disable
2909          * pool mirror, clear PFMRVM register
2910          */
2911         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2912                 if (on) {
2913                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
2914                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
2915                         mr_info->mr_conf[rule_id].pool_mask =
2916                                         mirror_conf->pool_mask;
2917
2918                 } else {
2919                         mp_lsb = 0;
2920                         mp_msb = 0;
2921                         mr_info->mr_conf[rule_id].pool_mask = 0;
2922                 }
2923         }
2924
2925         /* read  mirror control register and recalculate it */
2926         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
2927
2928         if (on) {
2929                 mr_ctl |= mirror_conf->rule_type_mask;
2930                 mr_ctl &= mirror_rule_mask;
2931                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
2932         } else
2933                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
2934
2935         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
2936         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
2937
2938         /* write mirrror control  register */
2939         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
2940
2941         /* write pool mirrror control  register */
2942         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2943                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
2944                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
2945                                 mp_msb);
2946         }
2947         /* write VLAN mirrror control  register */
2948         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2949                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
2950                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
2951                                 mv_msb);
2952         }
2953
2954         return 0;
2955 }
2956
2957 static int
2958 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
2959 {
2960         int mr_ctl = 0;
2961         uint32_t lsb_val = 0;
2962         uint32_t msb_val = 0;
2963         const uint8_t rule_mr_offset = 4;
2964
2965         struct ixgbe_hw *hw =
2966                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967         struct ixgbe_mirror_info *mr_info =
2968                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2969
2970         if (ixgbe_vmdq_mode_check(hw) < 0)
2971                 return (-ENOTSUP);
2972
2973         memset(&mr_info->mr_conf[rule_id], 0,
2974                 sizeof(struct rte_eth_vmdq_mirror_conf));
2975
2976         /* clear PFVMCTL register */
2977         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
2978
2979         /* clear pool mask register */
2980         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
2981         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
2982
2983         /* clear vlan mask register */
2984         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
2985         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
2986
2987         return 0;
2988 }