lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <string.h>
  40 #include <unistd.h>
  41 #include <stdarg.h>
  42 #include <inttypes.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62
  63 #include "ixgbe_logs.h"
  64 #include "ixgbe/ixgbe_api.h"
  65 #include "ixgbe/ixgbe_vf.h"
  66 #include "ixgbe/ixgbe_common.h"
  67 #include "ixgbe_ethdev.h"
  68
  69 /*
  70  * High threshold controlling when to start sending XOFF frames. Must be at
  71  * least 8 bytes less than receive packet buffer size. This value is in units
  72  * of 1024 bytes.
  73  */
  74 #define IXGBE_FC_HI    0x80
  75
  76 /*
  77  * Low threshold controlling when to start sending XON frames. This value is
  78  * in units of 1024 bytes.
  79  */
  80 #define IXGBE_FC_LO    0x40
  81
  82 /* Timer value included in XOFF frames. */
  83 #define IXGBE_FC_PAUSE 0x680
  84
  85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  86 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  87
  88 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  89
  90 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
  91                 struct rte_eth_dev *eth_dev);
  92 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
  93 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
  94 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
  95 static void ixgbe_dev_close(struct rte_eth_dev *dev);
  96 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
  97 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
  98 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
  99 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 100 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 101                                 int wait_to_complete);
 102 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 103                                 struct rte_eth_stats *stats);
 104 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 105 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 106                                              uint16_t queue_id,
 107                                              uint8_t stat_idx,
 108                                              uint8_t is_rx);
 109 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 110                                 struct rte_eth_dev_info *dev_info);
 111 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 112                 uint16_t vlan_id, int on);
 113 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 114 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 115                 uint16_t queue, bool on);
 116 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 117                 int on);
 118 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 119 static void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 120 static void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 121 static void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
 122 static void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
 123 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 124 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 125 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 126 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 127
 128 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 129 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 130 static int  ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 131                 struct rte_eth_fc_conf *fc_conf);
 132 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 133                 struct rte_eth_pfc_conf *pfc_conf);
 134 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 135                 struct rte_eth_rss_reta *reta_conf);
 136 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 137                 struct rte_eth_rss_reta *reta_conf);
 138 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 139 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 140 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 141 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 143                 void *param);
 144 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 145 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 146                 uint32_t index, uint32_t pool);
 147 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 148 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 149
 150 /* For Virtual Function support */
 151 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 152                 struct rte_eth_dev *eth_dev);
 153 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 154 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 155 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 156 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 157 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 158 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 159                 struct rte_eth_stats *stats);
 160 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 161 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 162                 uint16_t vlan_id, int on);
 163 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 164                 uint16_t queue, int on);
 165 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 166 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 167
 168
 169 /*
 170  * Define VF Stats MACRO for Non "cleared on read" register
 171  */
 172 #define UPDATE_VF_STAT(reg, last, cur)                          \
 173 {                                                               \
 174         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 175         cur += latest - last;                                   \
 176         last = latest;                                          \
 177 }
 178
 179 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 180 {                                                                \
 181         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 182         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 183         u64 latest = ((new_msb << 32) | new_lsb);                \
 184         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 185         last = latest;                                           \
 186 }
 187
 188 #define IXGBE_SET_HWSTRIP(h, q) do{\
 189                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 190                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 191                 (h)->bitmap[idx] |= 1 << bit;\
 192         }while(0)
 193
 194 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 195                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 196                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 197                 (h)->bitmap[idx] &= ~(1 << bit);\
 198         }while(0)
 199
 200 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 201                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 202                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 203                 (r) = (h)->bitmap[idx] >> bit & 1;\
 204         }while(0)
 205
 206 /*
 207  * The set of PCI devices this driver supports
 208  */
 209 static struct rte_pci_id pci_id_ixgbe_map[] = {
 210
 211 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 212 #include "rte_pci_dev_ids.h"
 213
 214 { .vendor_id = 0, /* sentinel */ },
 215 };
 216
 217
 218 /*
 219  * The set of PCI devices this driver supports (for 82599 VF)
 220  */
 221 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 222
 223 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 224 #include "rte_pci_dev_ids.h"
 225 { .vendor_id = 0, /* sentinel */ },
 226
 227 };
 228
 229 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 230         .dev_configure        = ixgbe_dev_configure,
 231         .dev_start            = ixgbe_dev_start,
 232         .dev_stop             = ixgbe_dev_stop,
 233         .dev_close            = ixgbe_dev_close,
 234         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 235         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 236         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 237         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 238         .link_update          = ixgbe_dev_link_update,
 239         .stats_get            = ixgbe_dev_stats_get,
 240         .stats_reset          = ixgbe_dev_stats_reset,
 241         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 242         .dev_infos_get        = ixgbe_dev_info_get,
 243         .vlan_filter_set      = ixgbe_vlan_filter_set,
 244         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 245         .vlan_offload_set     = ixgbe_vlan_offload_set,
 246         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 247         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 248         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 249         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 250         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 251         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 252         .dev_led_on           = ixgbe_dev_led_on,
 253         .dev_led_off          = ixgbe_dev_led_off,
 254         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 255         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 256         .mac_addr_add         = ixgbe_add_rar,
 257         .mac_addr_remove      = ixgbe_remove_rar,
 258         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 259         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 260         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 261         .fdir_infos_get               = ixgbe_fdir_info_get,
 262         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 263         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 264         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 265         .fdir_set_masks               = ixgbe_fdir_set_masks,
 266         .reta_update          = ixgbe_dev_rss_reta_update,
 267         .reta_query           = ixgbe_dev_rss_reta_query,
 268 };
 269
 270 /*
 271  * dev_ops for virtual function, bare necessities for basic vf
 272  * operation have been implemented
 273  */
 274 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 275
 276         .dev_configure        = ixgbevf_dev_configure,
 277         .dev_start            = ixgbevf_dev_start,
 278         .dev_stop             = ixgbevf_dev_stop,
 279         .link_update          = ixgbe_dev_link_update,
 280         .stats_get            = ixgbevf_dev_stats_get,
 281         .stats_reset          = ixgbevf_dev_stats_reset,
 282         .dev_close            = ixgbevf_dev_close,
 283         .dev_infos_get        = ixgbe_dev_info_get,
 284         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 285         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 286         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 287         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 288         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 289         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 290         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 291         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 292 };
 293
 294 /**
 295  * Atomically reads the link status information from global
 296  * structure rte_eth_dev.
 297  *
 298  * @param dev
 299  *   - Pointer to the structure rte_eth_dev to read from.
 300  *   - Pointer to the buffer to be saved with the link status.
 301  *
 302  * @return
 303  *   - On success, zero.
 304  *   - On failure, negative value.
 305  */
 306 static inline int
 307 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 308                                 struct rte_eth_link *link)
 309 {
 310         struct rte_eth_link *dst = link;
 311         struct rte_eth_link *src = &(dev->data->dev_link);
 312
 313         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 314                                         *(uint64_t *)src) == 0)
 315                 return -1;
 316
 317         return 0;
 318 }
 319
 320 /**
 321  * Atomically writes the link status information into global
 322  * structure rte_eth_dev.
 323  *
 324  * @param dev
 325  *   - Pointer to the structure rte_eth_dev to read from.
 326  *   - Pointer to the buffer to be saved with the link status.
 327  *
 328  * @return
 329  *   - On success, zero.
 330  *   - On failure, negative value.
 331  */
 332 static inline int
 333 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 334                                 struct rte_eth_link *link)
 335 {
 336         struct rte_eth_link *dst = &(dev->data->dev_link);
 337         struct rte_eth_link *src = link;
 338
 339         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 340                                         *(uint64_t *)src) == 0)
 341                 return -1;
 342
 343         return 0;
 344 }
 345
 346 /*
 347  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 348  */
 349 static inline int
 350 ixgbe_is_sfp(struct ixgbe_hw *hw)
 351 {
 352         switch (hw->phy.type) {
 353         case ixgbe_phy_sfp_avago:
 354         case ixgbe_phy_sfp_ftl:
 355         case ixgbe_phy_sfp_intel:
 356         case ixgbe_phy_sfp_unknown:
 357         case ixgbe_phy_sfp_passive_tyco:
 358         case ixgbe_phy_sfp_passive_unknown:
 359                 return 1;
 360         default:
 361                 return 0;
 362         }
 363 }
 364
 365 static inline void
 366 ixgbe_enable_intr(struct rte_eth_dev *dev)
 367 {
 368         struct ixgbe_interrupt *intr =
 369                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 370         struct ixgbe_hw *hw =
 371                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 372
 373         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 374         IXGBE_WRITE_FLUSH(hw);
 375 }
 376
 377 /*
 378  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 379  */
 380 static void
 381 ixgbe_disable_intr(struct ixgbe_hw *hw)
 382 {
 383         PMD_INIT_FUNC_TRACE();
 384
 385         if (hw->mac.type == ixgbe_mac_82598EB) {
 386                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 387         } else {
 388                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 389                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 390                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 391         }
 392         IXGBE_WRITE_FLUSH(hw);
 393 }
 394
 395 /*
 396  * This function resets queue statistics mapping registers.
 397  * From Niantic datasheet, Initialization of Statistics section:
 398  * "...if software requires the queue counters, the RQSMR and TQSM registers
 399  * must be re-programmed following a device reset.
 400  */
 401 static void
 402 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 403 {
 404         uint32_t i;
 405
 406         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 407                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 408                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 409         }
 410 }
 411
 412
 413 static int
 414 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 415                                   uint16_t queue_id,
 416                                   uint8_t stat_idx,
 417                                   uint8_t is_rx)
 418 {
 419 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 420 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 421 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 422
 423         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 424         struct ixgbe_stat_mapping_registers *stat_mappings =
 425                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 426         uint32_t qsmr_mask = 0;
 427         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 428         uint32_t q_map;
 429         uint8_t n, offset;
 430
 431         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 432                 return -ENOSYS;
 433
 434         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 435                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 436
 437         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 438         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 439                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 440                 return -EIO;
 441         }
 442         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 443
 444         /* Now clear any previous stat_idx set */
 445         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 446         if (!is_rx)
 447                 stat_mappings->tqsm[n] &= ~clearing_mask;
 448         else
 449                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 450
 451         q_map = (uint32_t)stat_idx;
 452         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 453         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 454         if (!is_rx)
 455                 stat_mappings->tqsm[n] |= qsmr_mask;
 456         else
 457                 stat_mappings->rqsmr[n] |= qsmr_mask;
 458
 459         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 460                      "%s[%d] = 0x%08x\n",
 461                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 462                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 463
 464         /* Now write the mapping in the appropriate register */
 465         if (is_rx) {
 466                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 467                              stat_mappings->rqsmr[n], n);
 468                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 469         }
 470         else {
 471                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 472                              stat_mappings->tqsm[n], n);
 473                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 474         }
 475         return 0;
 476 }
 477
 478 static void
 479 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 480 {
 481         struct ixgbe_stat_mapping_registers *stat_mappings =
 482                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 484         int i;
 485
 486         /* write whatever was in stat mapping table to the NIC */
 487         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 488                 /* rx */
 489                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 490
 491                 /* tx */
 492                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 493         }
 494 }
 495
 496 static void
 497 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 498 {
 499         uint8_t i;
 500         struct ixgbe_dcb_tc_config *tc;
 501         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 502
 503         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 504         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 505         for (i = 0; i < dcb_max_tc; i++) {
 506                 tc = &dcb_config->tc_config[i];
 507                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 508                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 509                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 510                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 511                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 512                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 513                 tc->pfc = ixgbe_dcb_pfc_disabled;
 514         }
 515
 516         /* Initialize default user to priority mapping, UPx->TC0 */
 517         tc = &dcb_config->tc_config[0];
 518         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 519         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 520         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 521                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 522                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 523         }
 524         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 525         dcb_config->pfc_mode_enable = false;
 526         dcb_config->vt_mode = true;
 527         dcb_config->round_robin_enable = false;
 528         /* support all DCB capabilities in 82599 */
 529         dcb_config->support.capabilities = 0xFF;
 530
 531         /*we only support 4 Tcs for X540*/
 532         if (hw->mac.type == ixgbe_mac_X540) {
 533                 dcb_config->num_tcs.pg_tcs = 4;
 534                 dcb_config->num_tcs.pfc_tcs = 4;
 535         }
 536 }
 537
 538 /*
 539  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 540  * It returns 0 on success.
 541  */
 542 static int
 543 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 544                      struct rte_eth_dev *eth_dev)
 545 {
 546         struct rte_pci_device *pci_dev;
 547         struct ixgbe_hw *hw =
 548                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 549         struct ixgbe_vfta * shadow_vfta =
 550                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 551         struct ixgbe_hwstrip *hwstrip =
 552                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 553         struct ixgbe_dcb_config *dcb_config =
 554                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 555         uint32_t ctrl_ext;
 556         uint16_t csum;
 557         int diag, i;
 558
 559         PMD_INIT_FUNC_TRACE();
 560
 561         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 562         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 563         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 564
 565         /* for secondary processes, we don't initialise any further as primary
 566          * has already done this work. Only check we don't need a different
 567          * RX function */
 568         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 569                 if (eth_dev->data->scattered_rx)
 570                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 571                 return 0;
 572         }
 573         pci_dev = eth_dev->pci_dev;
 574
 575         /* Vendor and Device ID need to be set before init of shared code */
 576         hw->device_id = pci_dev->id.device_id;
 577         hw->vendor_id = pci_dev->id.vendor_id;
 578         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 579 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 580         hw->allow_unsupported_sfp = 1;
 581 #endif
 582
 583         /* Initialize the shared code */
 584         diag = ixgbe_init_shared_code(hw);
 585         if (diag != IXGBE_SUCCESS) {
 586                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 587                 return -EIO;
 588         }
 589
 590         /* Initialize DCB configuration*/
 591         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 592         ixgbe_dcb_init(hw,dcb_config);
 593         /* Get Hardware Flow Control setting */
 594         hw->fc.requested_mode = ixgbe_fc_full;
 595         hw->fc.current_mode = ixgbe_fc_full;
 596         hw->fc.pause_time = IXGBE_FC_PAUSE;
 597         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 598                 hw->fc.low_water[i] = IXGBE_FC_LO;
 599                 hw->fc.high_water[i] = IXGBE_FC_HI;
 600         }
 601         hw->fc.send_xon = 1;
 602
 603         /* Make sure we have a good EEPROM before we read from it */
 604         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 605         if (diag != IXGBE_SUCCESS) {
 606                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 607                 return -EIO;
 608         }
 609
 610         diag = ixgbe_init_hw(hw);
 611
 612         /*
 613          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 614          * is called too soon after the kernel driver unbinding/binding occurs.
 615          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 616          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 617          * also called. See ixgbe_identify_phy_82599(). The reason for the
 618          * failure is not known, and only occuts when virtualisation features
 619          * are disabled in the bios. A delay of 100ms  was found to be enough by
 620          * trial-and-error, and is doubled to be safe.
 621          */
 622         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 623                 rte_delay_ms(200);
 624                 diag = ixgbe_init_hw(hw);
 625         }
 626
 627         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 628                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 629                     "LOM.  Please be aware there may be issues associated "
 630                     "with your hardware.\n If you are experiencing problems "
 631                     "please contact your Intel or hardware representative "
 632                     "who provided you with this hardware.\n");
 633         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 634                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 635         if (diag) {
 636                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 637                 return -EIO;
 638         }
 639
 640         /* disable interrupt */
 641         ixgbe_disable_intr(hw);
 642
 643         /* pick up the PCI bus settings for reporting later */
 644         ixgbe_get_bus_info(hw);
 645
 646         /* reset mappings for queue statistics hw counters*/
 647         ixgbe_reset_qstat_mappings(hw);
 648
 649         /* Allocate memory for storing MAC addresses */
 650         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 651                         hw->mac.num_rar_entries, 0);
 652         if (eth_dev->data->mac_addrs == NULL) {
 653                 PMD_INIT_LOG(ERR,
 654                         "Failed to allocate %d bytes needed to store MAC addresses",
 655                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 656                 return -ENOMEM;
 657         }
 658         /* Copy the permanent MAC address */
 659         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 660                         &eth_dev->data->mac_addrs[0]);
 661
 662         /* initialize the vfta */
 663         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 664
 665         /* initialize the hw strip bitmap*/
 666         memset(hwstrip, 0, sizeof(*hwstrip));
 667
 668         /* let hardware know driver is loaded */
 669         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 670         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 671         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 672
 673         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 674                 PMD_INIT_LOG(DEBUG,
 675                              "MAC: %d, PHY: %d, SFP+: %d<n",
 676                              (int) hw->mac.type, (int) hw->phy.type,
 677                              (int) hw->phy.sfp_type);
 678         else
 679                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 680                              (int) hw->mac.type, (int) hw->phy.type);
 681
 682         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 683                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 684                         pci_dev->id.device_id);
 685
 686         rte_intr_callback_register(&(pci_dev->intr_handle),
 687                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 688
 689         /* enable uio intr after callback register */
 690         rte_intr_enable(&(pci_dev->intr_handle));
 691
 692         /* enable support intr */
 693         ixgbe_enable_intr(eth_dev);
 694
 695         return 0;
 696 }
 697
 698 /*
 699  * Virtual Function device init
 700  */
 701 static int
 702 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 703                      struct rte_eth_dev *eth_dev)
 704 {
 705         struct rte_pci_device *pci_dev;
 706         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 707         int diag;
 708         struct ixgbe_vfta * shadow_vfta =
 709                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 710         struct ixgbe_hwstrip *hwstrip =
 711                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 712
 713         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 714
 715         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 716         pci_dev = eth_dev->pci_dev;
 717
 718         hw->device_id = pci_dev->id.device_id;
 719         hw->vendor_id = pci_dev->id.vendor_id;
 720         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 721
 722         /* initialize the vfta */
 723         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 724
 725         /* initialize the hw strip bitmap*/
 726         memset(hwstrip, 0, sizeof(*hwstrip));
 727
 728         /* Initialize the shared code */
 729         diag = ixgbe_init_shared_code(hw);
 730         if (diag != IXGBE_SUCCESS) {
 731                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 732                 return -EIO;
 733         }
 734
 735         /* init_mailbox_params */
 736         hw->mbx.ops.init_params(hw);
 737
 738         /* Disable the interrupts for VF */
 739         ixgbevf_intr_disable(hw);
 740
 741         hw->mac.num_rar_entries = hw->mac.max_rx_queues;
 742         diag = hw->mac.ops.reset_hw(hw);
 743         if (diag != IXGBE_SUCCESS) {
 744                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 745                 return (diag);
 746         }
 747
 748         /* Allocate memory for storing MAC addresses */
 749         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 750                         hw->mac.num_rar_entries, 0);
 751         if (eth_dev->data->mac_addrs == NULL) {
 752                 PMD_INIT_LOG(ERR,
 753                         "Failed to allocate %d bytes needed to store MAC addresses",
 754                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 755                 return -ENOMEM;
 756         }
 757         /* Copy the permanent MAC address */
 758         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 759                         &eth_dev->data->mac_addrs[0]);
 760
 761         /* reset the hardware with the new settings */
 762         diag = hw->mac.ops.start_hw(hw);
 763         switch (diag) {
 764                 case  0:
 765                         break;
 766
 767                 default:
 768                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 769                         return (-EIO);
 770         }
 771
 772         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
 773                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
 774                          "ixgbe_mac_82599_vf");
 775
 776         return 0;
 777 }
 778
 779 static struct eth_driver rte_ixgbe_pmd = {
 780         {
 781                 .name = "rte_ixgbe_pmd",
 782                 .id_table = pci_id_ixgbe_map,
 783 #ifdef RTE_EAL_UNBIND_PORTS
 784                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 785 #endif
 786         },
 787         .eth_dev_init = eth_ixgbe_dev_init,
 788         .dev_private_size = sizeof(struct ixgbe_adapter),
 789 };
 790
 791 /*
 792  * virtual function driver struct
 793  */
 794 static struct eth_driver rte_ixgbevf_pmd = {
 795         {
 796                 .name = "rte_ixgbevf_pmd",
 797                 .id_table = pci_id_ixgbevf_map,
 798 #ifdef RTE_EAL_UNBIND_PORTS
 799                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 800 #endif
 801         },
 802         .eth_dev_init = eth_ixgbevf_dev_init,
 803         .dev_private_size = sizeof(struct ixgbe_adapter),
 804 };
 805
 806 /*
 807  * Driver initialization routine.
 808  * Invoked once at EAL init time.
 809  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 810  */
 811 int
 812 rte_ixgbe_pmd_init(void)
 813 {
 814         PMD_INIT_FUNC_TRACE();
 815
 816         rte_eth_driver_register(&rte_ixgbe_pmd);
 817         return 0;
 818 }
 819
 820 /*
 821  * VF Driver initialization routine.
 822  * Invoked one at EAL init time.
 823  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
 824  */
 825 int
 826 rte_ixgbevf_pmd_init(void)
 827 {
 828         DEBUGFUNC("rte_ixgbevf_pmd_init");
 829
 830         rte_eth_driver_register(&rte_ixgbevf_pmd);
 831         return (0);
 832 }
 833
 834 static int
 835 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 836 {
 837         struct ixgbe_hw *hw =
 838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839         struct ixgbe_vfta * shadow_vfta =
 840                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 841         uint32_t vfta;
 842         uint32_t vid_idx;
 843         uint32_t vid_bit;
 844
 845         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
 846         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
 847         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
 848         if (on)
 849                 vfta |= vid_bit;
 850         else
 851                 vfta &= ~vid_bit;
 852         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
 853
 854         /* update local VFTA copy */
 855         shadow_vfta->vfta[vid_idx] = vfta;
 856
 857         return 0;
 858 }
 859
 860 static void
 861 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 862 {
 863         if (on)
 864                 ixgbe_vlan_hw_strip_enable(dev, queue);
 865         else
 866                 ixgbe_vlan_hw_strip_disable(dev, queue);
 867 }
 868
 869 static void
 870 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
 871 {
 872         struct ixgbe_hw *hw =
 873                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 874
 875         /* Only the high 16-bits is valid */
 876         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
 877 }
 878
 879 static void
 880 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
 881 {
 882         struct ixgbe_hw *hw =
 883                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 884         uint32_t vlnctrl;
 885
 886         PMD_INIT_FUNC_TRACE();
 887
 888         /* Filter Table Disable */
 889         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 890         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
 891
 892         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
 893 }
 894
 895 static void
 896 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 897 {
 898         struct ixgbe_hw *hw =
 899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 900         struct ixgbe_vfta * shadow_vfta =
 901                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 902         uint32_t vlnctrl;
 903         uint16_t i;
 904
 905         PMD_INIT_FUNC_TRACE();
 906
 907         /* Filter Table Enable */
 908         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 909         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
 910         vlnctrl |= IXGBE_VLNCTRL_VFE;
 911
 912         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
 913
 914         /* write whatever is in local vfta copy */
 915         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
 916                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
 917 }
 918
 919 static void
 920 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
 921 {
 922         struct ixgbe_hwstrip *hwstrip =
 923                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
 924
 925         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
 926                 return;
 927
 928         if (on)
 929                 IXGBE_SET_HWSTRIP(hwstrip, queue);
 930         else
 931                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
 932 }
 933
 934 static void
 935 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
 936 {
 937         struct ixgbe_hw *hw =
 938                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 939         uint32_t ctrl;
 940
 941         PMD_INIT_FUNC_TRACE();
 942
 943         if (hw->mac.type == ixgbe_mac_82598EB) {
 944                 /* No queue level support */
 945                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
 946                 return;
 947         }
 948         else {
 949                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
 950                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
 951                 ctrl &= ~IXGBE_RXDCTL_VME;
 952                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
 953         }
 954         /* record those setting for HW strip per queue */
 955         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
 956 }
 957
 958 static void
 959 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
 960 {
 961         struct ixgbe_hw *hw =
 962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 963         uint32_t ctrl;
 964
 965         PMD_INIT_FUNC_TRACE();
 966
 967         if (hw->mac.type == ixgbe_mac_82598EB) {
 968                 /* No queue level supported */
 969                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
 970                 return;
 971         }
 972         else {
 973                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
 974                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
 975                 ctrl |= IXGBE_RXDCTL_VME;
 976                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
 977         }
 978         /* record those setting for HW strip per queue */
 979         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
 980 }
 981
 982 static void
 983 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
 984 {
 985         struct ixgbe_hw *hw =
 986                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 987         uint32_t ctrl;
 988         uint16_t i;
 989
 990         PMD_INIT_FUNC_TRACE();
 991
 992         if (hw->mac.type == ixgbe_mac_82598EB) {
 993                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 994                 ctrl &= ~IXGBE_VLNCTRL_VME;
 995                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
 996         }
 997         else {
 998                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
 999                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1000                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1001                         ctrl &= ~IXGBE_RXDCTL_VME;
1002                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1003
1004                         /* record those setting for HW strip per queue */
1005                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1006                 }
1007         }
1008 }
1009
1010 static void
1011 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1012 {
1013         struct ixgbe_hw *hw =
1014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1015         uint32_t ctrl;
1016         uint16_t i;
1017
1018         PMD_INIT_FUNC_TRACE();
1019
1020         if (hw->mac.type == ixgbe_mac_82598EB) {
1021                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1022                 ctrl |= IXGBE_VLNCTRL_VME;
1023                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1024         }
1025         else {
1026                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1027                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1028                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1029                         ctrl |= IXGBE_RXDCTL_VME;
1030                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1031
1032                         /* record those setting for HW strip per queue */
1033                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1034                 }
1035         }
1036 }
1037
1038 static void
1039 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1040 {
1041         struct ixgbe_hw *hw =
1042                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043         uint32_t ctrl;
1044
1045         PMD_INIT_FUNC_TRACE();
1046
1047         /* DMATXCTRL: Geric Double VLAN Disable */
1048         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1049         ctrl &= ~IXGBE_DMATXCTL_GDV;
1050         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1051
1052         /* CTRL_EXT: Global Double VLAN Disable */
1053         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1054         ctrl &= ~IXGBE_EXTENDED_VLAN;
1055         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1056
1057 }
1058
1059 static void
1060 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1061 {
1062         struct ixgbe_hw *hw =
1063                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1064         uint32_t ctrl;
1065
1066         PMD_INIT_FUNC_TRACE();
1067
1068         /* DMATXCTRL: Geric Double VLAN Enable */
1069         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1070         ctrl |= IXGBE_DMATXCTL_GDV;
1071         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1072
1073         /* CTRL_EXT: Global Double VLAN Enable */
1074         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1075         ctrl |= IXGBE_EXTENDED_VLAN;
1076         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1077
1078         /*
1079          * VET EXT field in the EXVET register = 0x8100 by default
1080          * So no need to change. Same to VT field of DMATXCTL register
1081          */
1082 }
1083
1084 static void
1085 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1086 {
1087         if(mask & ETH_VLAN_STRIP_MASK){
1088                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1089                         ixgbe_vlan_hw_strip_enable_all(dev);
1090                 else
1091                         ixgbe_vlan_hw_strip_disable_all(dev);
1092         }
1093
1094         if(mask & ETH_VLAN_FILTER_MASK){
1095                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1096                         ixgbe_vlan_hw_filter_enable(dev);
1097                 else
1098                         ixgbe_vlan_hw_filter_disable(dev);
1099         }
1100
1101         if(mask & ETH_VLAN_EXTEND_MASK){
1102                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1103                         ixgbe_vlan_hw_extend_enable(dev);
1104                 else
1105                         ixgbe_vlan_hw_extend_disable(dev);
1106         }
1107 }
1108
1109 static int
1110 ixgbe_dev_configure(struct rte_eth_dev *dev)
1111 {
1112         struct ixgbe_interrupt *intr =
1113                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1114
1115         PMD_INIT_FUNC_TRACE();
1116
1117         /* set flag to update link status after init */
1118         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1119
1120         return 0;
1121 }
1122
1123 /*
1124  * Configure device link speed and setup link.
1125  * It returns 0 on success.
1126  */
1127 static int
1128 ixgbe_dev_start(struct rte_eth_dev *dev)
1129 {
1130         struct ixgbe_hw *hw =
1131                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1132         int err, link_up = 0, negotiate = 0;
1133         uint32_t speed = 0;
1134         int mask = 0;
1135
1136         PMD_INIT_FUNC_TRACE();
1137
1138         /* IXGBE devices don't support half duplex */
1139         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1140                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1141                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%u) for port %u\n",
1142                                 dev->data->dev_conf.link_duplex,
1143                                 dev->data->port_id);
1144                 return -EINVAL;
1145         }
1146
1147         /* stop adapter */
1148         hw->adapter_stopped = FALSE;
1149         ixgbe_stop_adapter(hw);
1150
1151         /* reinitialize adapter
1152          * this calls reset and start */
1153         ixgbe_init_hw(hw);
1154         hw->mac.ops.start_hw(hw);
1155
1156         /* initialize transmission unit */
1157         ixgbe_dev_tx_init(dev);
1158
1159         /* This can fail when allocating mbufs for descriptor rings */
1160         err = ixgbe_dev_rx_init(dev);
1161         if (err) {
1162                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1163                 goto error;
1164         }
1165
1166         ixgbe_dev_rxtx_start(dev);
1167
1168         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1169                 err = hw->mac.ops.setup_sfp(hw);
1170                 if (err)
1171                         goto error;
1172         }
1173
1174         /* Turn on the laser */
1175         if (hw->phy.multispeed_fiber)
1176                 ixgbe_enable_tx_laser(hw);
1177
1178         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1179         if (err)
1180                 goto error;
1181         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1182         if (err)
1183                 goto error;
1184
1185         switch(dev->data->dev_conf.link_speed) {
1186         case ETH_LINK_SPEED_AUTONEG:
1187                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1188                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1189                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1190                 break;
1191         case ETH_LINK_SPEED_100:
1192                 /*
1193                  * Invalid for 82598 but error will be detected by
1194                  * ixgbe_setup_link()
1195                  */
1196                 speed = IXGBE_LINK_SPEED_100_FULL;
1197                 break;
1198         case ETH_LINK_SPEED_1000:
1199                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1200                 break;
1201         case ETH_LINK_SPEED_10000:
1202                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1203                 break;
1204         default:
1205                 PMD_INIT_LOG(ERR, "Invalid link_speed (%u) for port %u\n",
1206                                 dev->data->dev_conf.link_speed, dev->data->port_id);
1207                 goto error;
1208         }
1209
1210         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1211         if (err)
1212                 goto error;
1213
1214         /* check if lsc interrupt is enabled */
1215         if (dev->data->dev_conf.intr_conf.lsc != 0)
1216                 ixgbe_dev_lsc_interrupt_setup(dev);
1217
1218         /* resume enabled intr since hw reset */
1219         ixgbe_enable_intr(dev);
1220
1221         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1222                 ETH_VLAN_EXTEND_MASK;
1223         ixgbe_vlan_offload_set(dev, mask);
1224
1225         /* Configure DCB hw */
1226         ixgbe_configure_dcb(dev);
1227
1228         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1229                 err = ixgbe_fdir_configure(dev);
1230                 if (err)
1231                         goto error;
1232         }
1233
1234         ixgbe_restore_statistics_mapping(dev);
1235
1236         return (0);
1237
1238 error:
1239         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1240         ixgbe_dev_clear_queues(dev);
1241         return -EIO;
1242 }
1243
1244 /*
1245  * Stop device: disable rx and tx functions to allow for reconfiguring.
1246  */
1247 static void
1248 ixgbe_dev_stop(struct rte_eth_dev *dev)
1249 {
1250         struct rte_eth_link link;
1251         struct ixgbe_hw *hw =
1252                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1253
1254         PMD_INIT_FUNC_TRACE();
1255
1256         /* disable interrupts */
1257         ixgbe_disable_intr(hw);
1258
1259         /* reset the NIC */
1260         ixgbe_reset_hw(hw);
1261         hw->adapter_stopped = FALSE;
1262
1263         /* stop adapter */
1264         ixgbe_stop_adapter(hw);
1265
1266         /* Turn off the laser */
1267         if (hw->phy.multispeed_fiber)
1268                 ixgbe_disable_tx_laser(hw);
1269
1270         ixgbe_dev_clear_queues(dev);
1271
1272         /* Clear recorded link status */
1273         memset(&link, 0, sizeof(link));
1274         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1275 }
1276
1277 /*
1278  * Reest and stop device.
1279  */
1280 static void
1281 ixgbe_dev_close(struct rte_eth_dev *dev)
1282 {
1283         struct ixgbe_hw *hw =
1284                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285
1286         PMD_INIT_FUNC_TRACE();
1287
1288         ixgbe_reset_hw(hw);
1289
1290
1291         ixgbe_dev_stop(dev);
1292         hw->adapter_stopped = 1;
1293
1294         ixgbe_disable_pcie_master(hw);
1295
1296         /* reprogram the RAR[0] in case user changed it. */
1297         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1298 }
1299
1300 /*
1301  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1302  */
1303 static void
1304 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1305 {
1306         struct ixgbe_hw *hw =
1307                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308         struct ixgbe_hw_stats *hw_stats =
1309                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1310         uint32_t bprc, lxon, lxoff, total;
1311         uint64_t total_missed_rx, total_qbrc, total_qprc;
1312         unsigned i;
1313
1314         total_missed_rx = 0;
1315         total_qbrc = 0;
1316         total_qprc = 0;
1317
1318         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1319         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1320         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1321         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1322
1323         for (i = 0; i < 8; i++) {
1324                 uint32_t mp;
1325                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1326                 /* global total per queue */
1327                 hw_stats->mpc[i] += mp;
1328                 /* Running comprehensive total for stats display */
1329                 total_missed_rx += hw_stats->mpc[i];
1330                 if (hw->mac.type == ixgbe_mac_82598EB)
1331                         hw_stats->rnbc[i] +=
1332                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1333                 hw_stats->pxontxc[i] +=
1334                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1335                 hw_stats->pxonrxc[i] +=
1336                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1337                 hw_stats->pxofftxc[i] +=
1338                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1339                 hw_stats->pxoffrxc[i] +=
1340                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1341                 hw_stats->pxon2offc[i] +=
1342                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1343         }
1344         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1345                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1346                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1347                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1348                 hw_stats->qbrc[i] +=
1349                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1350                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1351                 hw_stats->qbtc[i] +=
1352                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1353                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1354
1355                 total_qprc += hw_stats->qprc[i];
1356                 total_qbrc += hw_stats->qbrc[i];
1357         }
1358         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1359         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1360         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1361
1362         /* Note that gprc counts missed packets */
1363         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1364
1365         if (hw->mac.type != ixgbe_mac_82598EB) {
1366                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1367                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1368                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1369                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1370                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1371                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1372                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1373                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1374         } else {
1375                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1376                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1377                 /* 82598 only has a counter in the high register */
1378                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1379                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1380                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1381         }
1382
1383         /*
1384          * Workaround: mprc hardware is incorrectly counting
1385          * broadcasts, so for now we subtract those.
1386          */
1387         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1388         hw_stats->bprc += bprc;
1389         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1390         if (hw->mac.type == ixgbe_mac_82598EB)
1391                 hw_stats->mprc -= bprc;
1392
1393         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1394         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1395         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1396         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1397         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1398         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1399
1400         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1401         hw_stats->lxontxc += lxon;
1402         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1403         hw_stats->lxofftxc += lxoff;
1404         total = lxon + lxoff;
1405
1406         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1407         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1408         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1409         hw_stats->gptc -= total;
1410         hw_stats->mptc -= total;
1411         hw_stats->ptc64 -= total;
1412         hw_stats->gotc -= total * ETHER_MIN_LEN;
1413
1414         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1415         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1416         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1417         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1418         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1419         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1420         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1421         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1422         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1423         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1424         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1425         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1426         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1427         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1428         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1429         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1430         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1431         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1432         /* Only read FCOE on 82599 */
1433         if (hw->mac.type != ixgbe_mac_82598EB) {
1434                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1435                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1436                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1437                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1438                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1439         }
1440
1441         if (stats == NULL)
1442                 return;
1443
1444         /* Fill out the rte_eth_stats statistics structure */
1445         stats->ipackets = total_qprc;
1446         stats->ibytes = total_qbrc;
1447         stats->opackets = hw_stats->gptc;
1448         stats->obytes = hw_stats->gotc;
1449         stats->imcasts = hw_stats->mprc;
1450
1451         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1452                 stats->q_ipackets[i] = hw_stats->qprc[i];
1453                 stats->q_opackets[i] = hw_stats->qptc[i];
1454                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1455                 stats->q_obytes[i] = hw_stats->qbtc[i];
1456                 stats->q_errors[i] = hw_stats->qprdc[i];
1457         }
1458
1459         /* Rx Errors */
1460         stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1461                 hw_stats->rlec;
1462
1463         stats->oerrors  = 0;
1464
1465         /* Flow Director Stats registers */
1466         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1467         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1468         stats->fdirmatch = hw_stats->fdirmatch;
1469         stats->fdirmiss = hw_stats->fdirmiss;
1470 }
1471
1472 static void
1473 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1474 {
1475         struct ixgbe_hw_stats *stats =
1476                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1477
1478         /* HW registers are cleared on read */
1479         ixgbe_dev_stats_get(dev, NULL);
1480
1481         /* Reset software totals */
1482         memset(stats, 0, sizeof(*stats));
1483 }
1484
1485 static void
1486 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1487 {
1488         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1490                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1491
1492         /* Good Rx packet, include VF loopback */
1493         UPDATE_VF_STAT(IXGBE_VFGPRC,
1494             hw_stats->last_vfgprc, hw_stats->vfgprc);
1495
1496         /* Good Rx octets, include VF loopback */
1497         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1498             hw_stats->last_vfgorc, hw_stats->vfgorc);
1499
1500         /* Good Tx packet, include VF loopback */
1501         UPDATE_VF_STAT(IXGBE_VFGPTC,
1502             hw_stats->last_vfgptc, hw_stats->vfgptc);
1503
1504         /* Good Tx octets, include VF loopback */
1505         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1506             hw_stats->last_vfgotc, hw_stats->vfgotc);
1507
1508         /* Rx Multicst Packet */
1509         UPDATE_VF_STAT(IXGBE_VFMPRC,
1510             hw_stats->last_vfmprc, hw_stats->vfmprc);
1511
1512         if (stats == NULL)
1513                 return;
1514
1515         memset(stats, 0, sizeof(*stats));
1516         stats->ipackets = hw_stats->vfgprc;
1517         stats->ibytes = hw_stats->vfgorc;
1518         stats->opackets = hw_stats->vfgptc;
1519         stats->obytes = hw_stats->vfgotc;
1520         stats->imcasts = hw_stats->vfmprc;
1521 }
1522
1523 static void
1524 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1525 {
1526         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1527                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1528
1529         /* Sync HW register to the last stats */
1530         ixgbevf_dev_stats_get(dev, NULL);
1531
1532         /* reset HW current stats*/
1533         hw_stats->vfgprc = 0;
1534         hw_stats->vfgorc = 0;
1535         hw_stats->vfgptc = 0;
1536         hw_stats->vfgotc = 0;
1537         hw_stats->vfmprc = 0;
1538
1539 }
1540
1541 static void
1542 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1543 {
1544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1545
1546         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1547         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1548         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1549         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1550         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1551 }
1552
1553 /* return 0 means link status changed, -1 means not changed */
1554 static int
1555 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1556 {
1557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1558         struct rte_eth_link link, old;
1559         ixgbe_link_speed link_speed;
1560         int link_up;
1561         int diag;
1562
1563         link.link_status = 0;
1564         link.link_speed = 0;
1565         link.link_duplex = 0;
1566         memset(&old, 0, sizeof(old));
1567         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1568
1569         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1570         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1571                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1572         else
1573                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1574         if (diag != 0) {
1575                 link.link_speed = ETH_LINK_SPEED_100;
1576                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1577                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1578                 if (link.link_status == old.link_status)
1579                         return -1;
1580                 return 0;
1581         }
1582
1583         if (link_up == 0) {
1584                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1585                 if (link.link_status == old.link_status)
1586                         return -1;
1587                 return 0;
1588         }
1589         link.link_status = 1;
1590         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1591
1592         switch (link_speed) {
1593         default:
1594         case IXGBE_LINK_SPEED_UNKNOWN:
1595                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1596                 link.link_speed = ETH_LINK_SPEED_100;
1597                 break;
1598
1599         case IXGBE_LINK_SPEED_100_FULL:
1600                 link.link_speed = ETH_LINK_SPEED_100;
1601                 break;
1602
1603         case IXGBE_LINK_SPEED_1GB_FULL:
1604                 link.link_speed = ETH_LINK_SPEED_1000;
1605                 break;
1606
1607         case IXGBE_LINK_SPEED_10GB_FULL:
1608                 link.link_speed = ETH_LINK_SPEED_10000;
1609                 break;
1610         }
1611         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1612
1613         if (link.link_status == old.link_status)
1614                 return -1;
1615
1616         return 0;
1617 }
1618
1619 static void
1620 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1621 {
1622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         uint32_t fctrl;
1624
1625         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1626         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1627         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1628 }
1629
1630 static void
1631 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1632 {
1633         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634         uint32_t fctrl;
1635
1636         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1637         fctrl &= (~IXGBE_FCTRL_UPE);
1638         if (dev->data->all_multicast == 1)
1639                 fctrl |= IXGBE_FCTRL_MPE;
1640         else
1641                 fctrl &= (~IXGBE_FCTRL_MPE);
1642         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1643 }
1644
1645 static void
1646 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1647 {
1648         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649         uint32_t fctrl;
1650
1651         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1652         fctrl |= IXGBE_FCTRL_MPE;
1653         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1654 }
1655
1656 static void
1657 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1658 {
1659         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660         uint32_t fctrl;
1661
1662         if (dev->data->promiscuous == 1)
1663                 return; /* must remain in all_multicast mode */
1664
1665         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1666         fctrl &= (~IXGBE_FCTRL_MPE);
1667         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1668 }
1669
1670 /**
1671  * It clears the interrupt causes and enables the interrupt.
1672  * It will be called once only during nic initialized.
1673  *
1674  * @param dev
1675  *  Pointer to struct rte_eth_dev.
1676  *
1677  * @return
1678  *  - On success, zero.
1679  *  - On failure, a negative value.
1680  */
1681 static int
1682 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1683 {
1684         struct ixgbe_interrupt *intr =
1685                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1686
1687         ixgbe_dev_link_status_print(dev);
1688         intr->mask |= IXGBE_EICR_LSC;
1689
1690         return 0;
1691 }
1692
1693 /*
1694  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1695  *
1696  * @param dev
1697  *  Pointer to struct rte_eth_dev.
1698  *
1699  * @return
1700  *  - On success, zero.
1701  *  - On failure, a negative value.
1702  */
1703 static int
1704 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1705 {
1706         uint32_t eicr;
1707         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1708         struct ixgbe_interrupt *intr =
1709                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1710
1711         /* clear all cause mask */
1712         ixgbe_disable_intr(hw);
1713
1714         /* read-on-clear nic registers here */
1715         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1716         PMD_DRV_LOG(INFO, "eicr %x", eicr);
1717
1718         intr->flags = 0;
1719         if (eicr & IXGBE_EICR_LSC) {
1720                 /* set flag for async link update */
1721                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1722         }
1723
1724         return 0;
1725 }
1726
1727 /**
1728  * It gets and then prints the link status.
1729  *
1730  * @param dev
1731  *  Pointer to struct rte_eth_dev.
1732  *
1733  * @return
1734  *  - On success, zero.
1735  *  - On failure, a negative value.
1736  */
1737 static void
1738 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1739 {
1740         struct rte_eth_link link;
1741
1742         memset(&link, 0, sizeof(link));
1743         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1744         if (link.link_status) {
1745                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1746                                         (int)(dev->data->port_id),
1747                                         (unsigned)link.link_speed,
1748                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1749                                         "full-duplex" : "half-duplex");
1750         } else {
1751                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1752                                 (int)(dev->data->port_id));
1753         }
1754         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1755                                 dev->pci_dev->addr.domain,
1756                                 dev->pci_dev->addr.bus,
1757                                 dev->pci_dev->addr.devid,
1758                                 dev->pci_dev->addr.function);
1759 }
1760
1761 /*
1762  * It executes link_update after knowing an interrupt occured.
1763  *
1764  * @param dev
1765  *  Pointer to struct rte_eth_dev.
1766  *
1767  * @return
1768  *  - On success, zero.
1769  *  - On failure, a negative value.
1770  */
1771 static int
1772 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1773 {
1774         struct ixgbe_interrupt *intr =
1775                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1776         int64_t timeout;
1777         struct rte_eth_link link;
1778         int intr_enable_delay = false;
1779
1780         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1781
1782         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1783                 /* get the link status before link update, for predicting later */
1784                 memset(&link, 0, sizeof(link));
1785                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1786
1787                 ixgbe_dev_link_update(dev, 0);
1788
1789                 /* likely to up */
1790                 if (!link.link_status)
1791                         /* handle it 1 sec later, wait it being stable */
1792                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1793                 /* likely to down */
1794                 else
1795                         /* handle it 4 sec later, wait it being stable */
1796                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1797
1798                 ixgbe_dev_link_status_print(dev);
1799
1800                 intr_enable_delay = true;
1801         }
1802
1803         if (intr_enable_delay) {
1804                 if (rte_eal_alarm_set(timeout * 1000,
1805                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
1806                         PMD_DRV_LOG(ERR, "Error setting alarm");
1807         } else {
1808                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
1809                 ixgbe_enable_intr(dev);
1810                 rte_intr_enable(&(dev->pci_dev->intr_handle));
1811         }
1812
1813
1814         return 0;
1815 }
1816
1817 /**
1818  * Interrupt handler which shall be registered for alarm callback for delayed
1819  * handling specific interrupt to wait for the stable nic state. As the
1820  * NIC interrupt state is not stable for ixgbe after link is just down,
1821  * it needs to wait 4 seconds to get the stable status.
1822  *
1823  * @param handle
1824  *  Pointer to interrupt handle.
1825  * @param param
1826  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1827  *
1828  * @return
1829  *  void
1830  */
1831 static void
1832 ixgbe_dev_interrupt_delayed_handler(void *param)
1833 {
1834         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1835         struct ixgbe_interrupt *intr =
1836                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1837
1838         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1839                 ixgbe_dev_link_update(dev, 0);
1840                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
1841                 ixgbe_dev_link_status_print(dev);
1842                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1843         }
1844
1845         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler\n");
1846         ixgbe_enable_intr(dev);
1847         rte_intr_enable(&(dev->pci_dev->intr_handle));
1848 }
1849
1850 /**
1851  * Interrupt handler triggered by NIC  for handling
1852  * specific interrupt.
1853  *
1854  * @param handle
1855  *  Pointer to interrupt handle.
1856  * @param param
1857  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1858  *
1859  * @return
1860  *  void
1861  */
1862 static void
1863 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1864                                                         void *param)
1865 {
1866         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1867         ixgbe_dev_interrupt_get_status(dev);
1868         ixgbe_dev_interrupt_action(dev);
1869 }
1870
1871 static int
1872 ixgbe_dev_led_on(struct rte_eth_dev *dev)
1873 {
1874         struct ixgbe_hw *hw;
1875
1876         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1878 }
1879
1880 static int
1881 ixgbe_dev_led_off(struct rte_eth_dev *dev)
1882 {
1883         struct ixgbe_hw *hw;
1884
1885         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1886         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1887 }
1888
1889 static int
1890 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1891 {
1892         struct ixgbe_hw *hw;
1893         int err;
1894         uint32_t rx_buf_size;
1895         uint32_t max_high_water;
1896         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
1897                 ixgbe_fc_none,
1898                 ixgbe_fc_rx_pause,
1899                 ixgbe_fc_tx_pause,
1900                 ixgbe_fc_full
1901         };
1902
1903         PMD_INIT_FUNC_TRACE();
1904
1905         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1906         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
1907         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1908
1909         /*
1910          * At least reserve one Ethernet frame for watermark
1911          * high_water/low_water in kilo bytes for ixgbe
1912          */
1913         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
1914         if ((fc_conf->high_water > max_high_water) ||
1915                 (fc_conf->high_water < fc_conf->low_water)) {
1916                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
1917                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
1918                 return (-EINVAL);
1919         }
1920
1921         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
1922         hw->fc.pause_time     = fc_conf->pause_time;
1923         hw->fc.high_water[0]  = fc_conf->high_water;
1924         hw->fc.low_water[0]   = fc_conf->low_water;
1925         hw->fc.send_xon       = fc_conf->send_xon;
1926
1927         err = ixgbe_fc_enable(hw);
1928         /* Not negotiated is not an error case */
1929         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
1930                 return 0;
1931         }
1932
1933         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
1934         return -EIO;
1935 }
1936
1937 /**
1938  *  ixgbe_pfc_enable_generic - Enable flow control
1939  *  @hw: pointer to hardware structure
1940  *  @tc_num: traffic class number
1941  *  Enable flow control according to the current settings.
1942  */
1943 static int
1944 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
1945 {
1946         int ret_val = 0;
1947         uint32_t mflcn_reg, fccfg_reg;
1948         uint32_t reg;
1949         uint32_t fcrtl, fcrth;
1950         uint8_t i;
1951         uint8_t nb_rx_en;
1952
1953         /* Validate the water mark configuration */
1954         if (!hw->fc.pause_time) {
1955                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1956                 goto out;
1957         }
1958
1959         /* Low water mark of zero causes XOFF floods */
1960         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1961                  /* High/Low water can not be 0 */
1962                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
1963                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
1964                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1965                         goto out;
1966                 }
1967
1968                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
1969                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
1970                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1971                         goto out;
1972                 }
1973         }
1974         /* Negotiate the fc mode to use */
1975         ixgbe_fc_autoneg(hw);
1976
1977         /* Disable any previous flow control settings */
1978         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1979         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
1980
1981         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1982         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1983
1984         switch (hw->fc.current_mode) {
1985         case ixgbe_fc_none:
1986                 /*
1987                  * If the count of enabled RX Priority Flow control >1,
1988                  * and the TX pause can not be disabled
1989                  */
1990                 nb_rx_en = 0;
1991                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1992                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
1993                         if (reg & IXGBE_FCRTH_FCEN)
1994                                 nb_rx_en++;
1995                 }
1996                 if (nb_rx_en > 1)
1997                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
1998                 break;
1999         case ixgbe_fc_rx_pause:
2000                 /*
2001                  * Rx Flow control is enabled and Tx Flow control is
2002                  * disabled by software override. Since there really
2003                  * isn't a way to advertise that we are capable of RX
2004                  * Pause ONLY, we will advertise that we support both
2005                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2006                  * disable the adapter's ability to send PAUSE frames.
2007                  */
2008                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2009                 /*
2010                  * If the count of enabled RX Priority Flow control >1,
2011                  * and the TX pause can not be disabled
2012                  */
2013                 nb_rx_en = 0;
2014                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2015                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2016                         if (reg & IXGBE_FCRTH_FCEN)
2017                                 nb_rx_en++;
2018                 }
2019                 if (nb_rx_en > 1)
2020                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2021                 break;
2022         case ixgbe_fc_tx_pause:
2023                 /*
2024                  * Tx Flow control is enabled, and Rx Flow control is
2025                  * disabled by software override.
2026                  */
2027                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2028                 break;
2029         case ixgbe_fc_full:
2030                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2031                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2032                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2033                 break;
2034         default:
2035                 DEBUGOUT("Flow control param set incorrectly\n");
2036                 ret_val = IXGBE_ERR_CONFIG;
2037                 goto out;
2038                 break;
2039         }
2040
2041         /* Set 802.3x based flow control settings. */
2042         mflcn_reg |= IXGBE_MFLCN_DPF;
2043         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2044         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2045
2046         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2047         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2048                 hw->fc.high_water[tc_num]) {
2049                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2050                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2051                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2052         } else {
2053                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2054                 /*
2055                  * In order to prevent Tx hangs when the internal Tx
2056                  * switch is enabled we must set the high water mark
2057                  * to the maximum FCRTH value.  This allows the Tx
2058                  * switch to function even under heavy Rx workloads.
2059                  */
2060                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2061         }
2062         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2063
2064         /* Configure pause time (2 TCs per register) */
2065         reg = hw->fc.pause_time * 0x00010001;
2066         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2067                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2068
2069         /* Configure flow control refresh threshold value */
2070         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2071
2072 out:
2073         return ret_val;
2074 }
2075
2076 static int
2077 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2078 {
2079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2081
2082         if(hw->mac.type != ixgbe_mac_82598EB) {
2083                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2084         }
2085         return ret_val;
2086 }
2087
2088 static int
2089 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2090 {
2091         int err;
2092         uint32_t rx_buf_size;
2093         uint32_t max_high_water;
2094         uint8_t tc_num;
2095         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2096         struct ixgbe_hw *hw =
2097                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         struct ixgbe_dcb_config *dcb_config =
2099                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2100
2101         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2102                 ixgbe_fc_none,
2103                 ixgbe_fc_rx_pause,
2104                 ixgbe_fc_tx_pause,
2105                 ixgbe_fc_full
2106         };
2107
2108         PMD_INIT_FUNC_TRACE();
2109
2110         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2111         tc_num = map[pfc_conf->priority];
2112         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2113         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2114         /*
2115          * At least reserve one Ethernet frame for watermark
2116          * high_water/low_water in kilo bytes for ixgbe
2117          */
2118         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2119         if ((pfc_conf->fc.high_water > max_high_water) ||
2120                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2121                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2122                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2123                 return (-EINVAL);
2124         }
2125
2126         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2127         hw->fc.pause_time = pfc_conf->fc.pause_time;
2128         hw->fc.send_xon = pfc_conf->fc.send_xon;
2129         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2130         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2131
2132         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2133
2134         /* Not negotiated is not an error case */
2135         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2136                 return 0;
2137
2138         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2139         return -EIO;
2140 }
2141
2142 static int
2143 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2144                                 struct rte_eth_rss_reta *reta_conf)
2145 {
2146         uint8_t i,j,mask;
2147         uint32_t reta;
2148         struct ixgbe_hw *hw =
2149                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150
2151         PMD_INIT_FUNC_TRACE();
2152         /*
2153         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2154         * 128-entries in 32 registers
2155          */
2156         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2157                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2158                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2159                 else
2160                         mask = (uint8_t)((reta_conf->mask_hi >>
2161                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2162                 if (mask != 0) {
2163                         reta = 0;
2164                         if (mask != 0xF)
2165                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2166
2167                         for (j = 0; j < 4; j++) {
2168                                 if (mask & (0x1 << j)) {
2169                                         if (mask != 0xF)
2170                                                 reta &= ~(0xFF << 8 * j);
2171                                         reta |= reta_conf->reta[i + j] << 8*j;
2172                                 }
2173                         }
2174                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2175                 }
2176         }
2177
2178         return 0;
2179 }
2180
2181 static int
2182 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2183                                 struct rte_eth_rss_reta *reta_conf)
2184 {
2185         uint8_t i,j,mask;
2186         uint32_t reta;
2187         struct ixgbe_hw *hw =
2188                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189
2190         PMD_INIT_FUNC_TRACE();
2191         /*
2192          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2193          * 128-entries in 32 registers
2194          */
2195         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2196                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2197                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2198                 else
2199                         mask = (uint8_t)((reta_conf->mask_hi >>
2200                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2201
2202                 if (mask != 0) {
2203                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2204                         for (j = 0; j < 4; j++) {
2205                                 if (mask & (0x1 << j))
2206                                         reta_conf->reta[i + j] =
2207                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2208                         }
2209                 }
2210         }
2211
2212         return 0;
2213 }
2214
2215 static void
2216 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2217                                 uint32_t index, uint32_t pool)
2218 {
2219         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220         uint32_t enable_addr = 1;
2221
2222         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2223 }
2224
2225 static void
2226 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2227 {
2228         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2229
2230         ixgbe_clear_rar(hw, index);
2231 }
2232
2233 /*
2234  * Virtual Function operations
2235  */
2236 static void
2237 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2238 {
2239         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2240
2241         /* Clear interrupt mask to stop from interrupts being generated */
2242         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2243
2244         IXGBE_WRITE_FLUSH(hw);
2245 }
2246
2247 static int
2248 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2249 {
2250         struct rte_eth_conf* conf = &dev->data->dev_conf;
2251
2252         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2253                 dev->data->port_id);
2254
2255         /*
2256          * VF has no ability to enable/disable HW CRC
2257          * Keep the persistent behavior the same as Host PF
2258          */
2259 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2260         if (!conf->rxmode.hw_strip_crc) {
2261                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2262                 conf->rxmode.hw_strip_crc = 1;
2263         }
2264 #else
2265         if (conf->rxmode.hw_strip_crc) {
2266                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2267                 conf->rxmode.hw_strip_crc = 0;
2268         }
2269 #endif
2270
2271         return 0;
2272 }
2273
2274 static int
2275 ixgbevf_dev_start(struct rte_eth_dev *dev)
2276 {
2277         struct ixgbe_hw *hw =
2278                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2279         int err, mask = 0;
2280
2281         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2282
2283         hw->mac.ops.reset_hw(hw);
2284
2285         ixgbevf_dev_tx_init(dev);
2286
2287         /* This can fail when allocating mbufs for descriptor rings */
2288         err = ixgbevf_dev_rx_init(dev);
2289         if (err) {
2290                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2291                 ixgbe_dev_clear_queues(dev);
2292                 return err;
2293         }
2294
2295         /* Set vfta */
2296         ixgbevf_set_vfta_all(dev,1);
2297
2298         /* Set HW strip */
2299         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2300                 ETH_VLAN_EXTEND_MASK;
2301         ixgbevf_vlan_offload_set(dev, mask);
2302
2303         ixgbevf_dev_rxtx_start(dev);
2304
2305         return 0;
2306 }
2307
2308 static void
2309 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2310 {
2311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2312
2313         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2314
2315         hw->adapter_stopped = TRUE;
2316         ixgbe_stop_adapter(hw);
2317
2318         /*
2319           * Clear what we set, but we still keep shadow_vfta to
2320           * restore after device starts
2321           */
2322         ixgbevf_set_vfta_all(dev,0);
2323
2324         ixgbe_dev_clear_queues(dev);
2325 }
2326
2327 static void
2328 ixgbevf_dev_close(struct rte_eth_dev *dev)
2329 {
2330         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331
2332         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2333
2334         ixgbe_reset_hw(hw);
2335
2336         ixgbevf_dev_stop(dev);
2337
2338         /* reprogram the RAR[0] in case user changed it. */
2339         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2340 }
2341
2342 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2343 {
2344         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345         struct ixgbe_vfta * shadow_vfta =
2346                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2347         int i = 0, j = 0, vfta = 0, mask = 1;
2348
2349         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2350                 vfta = shadow_vfta->vfta[i];
2351                 if(vfta){
2352                         mask = 1;
2353                         for (j = 0; j < 32; j++){
2354                                 if(vfta & mask)
2355                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2356                                 mask<<=1;
2357                         }
2358                 }
2359         }
2360
2361 }
2362
2363 static int
2364 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2365 {
2366         struct ixgbe_hw *hw =
2367                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2368         struct ixgbe_vfta * shadow_vfta =
2369                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2370         uint32_t vid_idx = 0;
2371         uint32_t vid_bit = 0;
2372         int ret = 0;
2373
2374         PMD_INIT_FUNC_TRACE();
2375
2376         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2377         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2378         if(ret){
2379                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2380                 return ret;
2381         }
2382         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2383         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2384
2385         /* Save what we set and retore it after device reset */
2386         if (on)
2387                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2388         else
2389                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2390
2391         return 0;
2392 }
2393
2394 static void
2395 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2396 {
2397         struct ixgbe_hw *hw =
2398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399         uint32_t ctrl;
2400
2401         PMD_INIT_FUNC_TRACE();
2402
2403         if(queue >= hw->mac.max_rx_queues)
2404                 return;
2405
2406         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2407         if(on)
2408                 ctrl |= IXGBE_RXDCTL_VME;
2409         else
2410                 ctrl &= ~IXGBE_RXDCTL_VME;
2411         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2412
2413         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2414 }
2415
2416 static void
2417 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2418 {
2419         struct ixgbe_hw *hw =
2420                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2421         uint16_t i;
2422         int on = 0;
2423
2424         /* VF function only support hw strip feature, others are not support */
2425         if(mask & ETH_VLAN_STRIP_MASK){
2426                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2427
2428                 for(i=0; i < hw->mac.max_rx_queues; i++)
2429                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2430         }
2431 }